Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_watermark_cg

Group : uart_env_pkg::uart_env_cov::tx_watermark_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	2	5	71.43

Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_watermark_lvl	7	2	5	71.43	100	1	1	0

Summary for Variable cp_watermark_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	2	5	71.43

User Defined Bins for cp_watermark_lvl

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_levels[5]	0	1	1
all_levels[6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7517	1			T1	1		T2	1		T5	2
all_levels[1]	6022	1			T6	4		T12	2		T15	2
all_levels[2]	9081	1			T3	2		T12	1		T42	3
all_levels[3]	6107	1			T3	5		T6	26		T8	3
all_levels[4]	8863	1			T2	5		T4	7		T9	1