Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	724	1			T9	4		T18	11		T19	7
all_values[1]	724	1			T9	4		T18	11		T19	7
all_values[2]	724	1			T9	4		T18	11		T19	7
all_values[3]	724	1			T9	4		T18	11		T19	7
all_values[4]	724	1			T9	4		T18	11		T19	7
all_values[5]	724	1			T9	4		T18	11		T19	7
all_values[6]	724	1			T9	4		T18	11		T19	7
all_values[7]	724	1			T9	4		T18	11		T19	7
all_values[8]	724	1			T9	4		T18	11		T19	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3462

1

T9

27

T18

46

T19

33

auto[1]

3054

1

T9

9

T18

53

T19

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2148

1

T9

18

T18

30

T19

17

auto[1]

4368

1

T9

18

T18

69

T19

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3842

1

T9

26

T18

61

T19

36

auto[1]

2674

1

T9

10

T18

38

T19

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	209	1			T9	2		T18	5		T19	4
all_values[0]	auto[0]	auto[1]	auto[1]	219	1			T18	3		T20	3		T37	3
all_values[0]	auto[1]	auto[0]	auto[1]	152	1			T9	2		T18	1		T19	2
all_values[0]	auto[1]	auto[1]	auto[1]	144	1			T18	2		T19	1		T48	2
all_values[1]	auto[0]	auto[0]	auto[0]	200	1			T9	1		T18	3		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	218	1			T18	2		T19	3		T20	3
all_values[1]	auto[1]	auto[0]	auto[1]	166	1			T9	3		T18	4		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	140	1			T18	2		T19	1		T20	1
all_values[2]	auto[0]	auto[0]	auto[0]	140	1			T9	1		T18	2		T20	1
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T18	1		T19	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	118	1			T9	1		T18	2		T19	3
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T9	1		T18	3		T48	2
all_values[2]	auto[1]	auto[0]	auto[1]	174	1			T18	1		T19	3		T20	1
all_values[2]	auto[1]	auto[1]	auto[1]	132	1			T9	1		T18	2		T20	1
all_values[3]	auto[0]	auto[0]	auto[0]	163	1			T9	1		T18	2		T19	2
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T9	1		T18	1		T37	1
all_values[3]	auto[0]	auto[1]	auto[0]	147	1			T18	3		T19	1		T20	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T18	2		T19	1		T48	1
all_values[3]	auto[1]	auto[0]	auto[1]	155	1			T9	2		T19	2		T20	2
all_values[3]	auto[1]	auto[1]	auto[1]	123	1			T18	3		T19	1		T48	3
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T9	2		T18	2		T20	1
all_values[4]	auto[0]	auto[0]	auto[1]	58	1			T18	1		T19	3		T23	1
all_values[4]	auto[0]	auto[1]	auto[0]	142	1			T9	1		T18	1		T48	2
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T18	1		T19	1		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	171	1			T18	3		T19	2		T20	4
all_values[4]	auto[1]	auto[1]	auto[1]	121	1			T9	1		T18	3		T19	1
all_values[5]	auto[0]	auto[0]	auto[0]	151	1			T9	2		T18	1		T19	2
all_values[5]	auto[0]	auto[0]	auto[1]	64	1			T18	1		T20	1		T37	1
all_values[5]	auto[0]	auto[1]	auto[0]	126	1			T9	2		T18	3		T19	2
all_values[5]	auto[0]	auto[1]	auto[1]	74	1			T18	2		T19	1		T20	1
all_values[5]	auto[1]	auto[0]	auto[1]	173	1			T18	1		T19	1		T48	5
all_values[5]	auto[1]	auto[1]	auto[1]	136	1			T18	3		T19	1		T20	3
all_values[6]	auto[0]	auto[0]	auto[0]	158	1			T9	3		T18	2		T19	1
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T19	1		T20	3		T37	1
all_values[6]	auto[0]	auto[1]	auto[0]	122	1			T18	3		T48	3		T23	3
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T18	1		T19	1		T37	1
all_values[6]	auto[1]	auto[0]	auto[1]	162	1			T9	1		T18	3		T19	3
all_values[6]	auto[1]	auto[1]	auto[1]	134	1			T18	2		T19	1		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	156	1			T9	2		T18	1		T20	2
all_values[7]	auto[0]	auto[0]	auto[1]	64	1			T18	1		T19	1		T37	1
all_values[7]	auto[0]	auto[1]	auto[0]	151	1			T9	2		T18	3		T19	2
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T18	2		T20	1		T37	1
all_values[7]	auto[1]	auto[0]	auto[1]	158	1			T18	3		T20	1		T37	2
all_values[7]	auto[1]	auto[1]	auto[1]	130	1			T18	1		T19	4		T20	1
all_values[8]	auto[0]	auto[0]	auto[1]	231	1			T9	4		T18	4		T19	2
all_values[8]	auto[0]	auto[1]	auto[1]	190	1			T18	3		T19	3		T20	1
all_values[8]	auto[1]	auto[0]	auto[1]	164	1			T18	3		T20	1		T48	4
all_values[8]	auto[1]	auto[1]	auto[1]	139	1			T18	1		T19	2		T20	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal