Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1318
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T1258 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3805485728 Aug 16 04:55:56 PM PDT 24 Aug 16 04:55:57 PM PDT 24 29290467 ps
T1259 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1071578413 Aug 16 04:56:18 PM PDT 24 Aug 16 04:56:19 PM PDT 24 50007199 ps
T1260 /workspace/coverage/cover_reg_top/2.uart_intr_test.379507977 Aug 16 04:55:48 PM PDT 24 Aug 16 04:55:49 PM PDT 24 23723628 ps
T1261 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3606519500 Aug 16 04:56:09 PM PDT 24 Aug 16 04:56:10 PM PDT 24 49146147 ps
T1262 /workspace/coverage/cover_reg_top/5.uart_intr_test.3797523944 Aug 16 04:55:50 PM PDT 24 Aug 16 04:55:51 PM PDT 24 40213693 ps
T1263 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2676795116 Aug 16 04:55:49 PM PDT 24 Aug 16 04:55:50 PM PDT 24 20952790 ps
T1264 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1794310031 Aug 16 04:56:05 PM PDT 24 Aug 16 04:56:07 PM PDT 24 309107170 ps
T1265 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2756810350 Aug 16 04:55:49 PM PDT 24 Aug 16 04:55:52 PM PDT 24 101230384 ps
T1266 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2776451213 Aug 16 04:56:05 PM PDT 24 Aug 16 04:56:06 PM PDT 24 31034467 ps
T1267 /workspace/coverage/cover_reg_top/6.uart_intr_test.3476979428 Aug 16 04:55:52 PM PDT 24 Aug 16 04:55:53 PM PDT 24 29722678 ps
T1268 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1365212323 Aug 16 04:55:50 PM PDT 24 Aug 16 04:55:52 PM PDT 24 27859934 ps
T1269 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2804873499 Aug 16 04:55:46 PM PDT 24 Aug 16 04:55:48 PM PDT 24 999717569 ps
T56 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1729964591 Aug 16 04:55:51 PM PDT 24 Aug 16 04:55:53 PM PDT 24 32904930 ps
T1270 /workspace/coverage/cover_reg_top/16.uart_csr_rw.330348024 Aug 16 04:56:14 PM PDT 24 Aug 16 04:56:15 PM PDT 24 15584677 ps
T1271 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3369406320 Aug 16 04:55:51 PM PDT 24 Aug 16 04:55:52 PM PDT 24 71443918 ps
T1272 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1524136477 Aug 16 04:55:50 PM PDT 24 Aug 16 04:55:52 PM PDT 24 363275483 ps
T1273 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3060656127 Aug 16 04:55:56 PM PDT 24 Aug 16 04:55:57 PM PDT 24 16353630 ps
T1274 /workspace/coverage/cover_reg_top/18.uart_intr_test.3450188336 Aug 16 04:56:03 PM PDT 24 Aug 16 04:56:04 PM PDT 24 14545314 ps
T1275 /workspace/coverage/cover_reg_top/4.uart_intr_test.792944857 Aug 16 04:55:51 PM PDT 24 Aug 16 04:55:52 PM PDT 24 13351809 ps
T1276 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4184961995 Aug 16 04:56:02 PM PDT 24 Aug 16 04:56:03 PM PDT 24 50227742 ps
T1277 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1417439716 Aug 16 04:55:56 PM PDT 24 Aug 16 04:55:57 PM PDT 24 20100880 ps
T1278 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1237445447 Aug 16 04:55:50 PM PDT 24 Aug 16 04:55:52 PM PDT 24 52926072 ps
T1279 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4052973207 Aug 16 04:55:51 PM PDT 24 Aug 16 04:55:53 PM PDT 24 277156391 ps
T1280 /workspace/coverage/cover_reg_top/46.uart_intr_test.4192728383 Aug 16 04:56:09 PM PDT 24 Aug 16 04:56:10 PM PDT 24 22427711 ps
T1281 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3225757707 Aug 16 04:55:52 PM PDT 24 Aug 16 04:55:55 PM PDT 24 171801790 ps
T1282 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.385623027 Aug 16 04:56:08 PM PDT 24 Aug 16 04:56:09 PM PDT 24 76004552 ps
T1283 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1816620521 Aug 16 04:55:49 PM PDT 24 Aug 16 04:55:50 PM PDT 24 51658567 ps
T1284 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3494548084 Aug 16 04:55:50 PM PDT 24 Aug 16 04:55:51 PM PDT 24 60099480 ps
T1285 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1994809674 Aug 16 04:55:56 PM PDT 24 Aug 16 04:55:58 PM PDT 24 1059431933 ps
T1286 /workspace/coverage/cover_reg_top/12.uart_intr_test.721246812 Aug 16 04:56:14 PM PDT 24 Aug 16 04:56:14 PM PDT 24 12436846 ps
T1287 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.188638506 Aug 16 04:55:51 PM PDT 24 Aug 16 04:55:54 PM PDT 24 60655906 ps
T1288 /workspace/coverage/cover_reg_top/3.uart_intr_test.2612933689 Aug 16 04:55:50 PM PDT 24 Aug 16 04:55:51 PM PDT 24 46815225 ps
T1289 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2887390641 Aug 16 04:55:48 PM PDT 24 Aug 16 04:55:49 PM PDT 24 89464870 ps
T1290 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3312216810 Aug 16 04:56:01 PM PDT 24 Aug 16 04:56:02 PM PDT 24 17057924 ps
T1291 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3603548669 Aug 16 04:56:18 PM PDT 24 Aug 16 04:56:19 PM PDT 24 44314690 ps
T57 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1037783453 Aug 16 04:56:05 PM PDT 24 Aug 16 04:56:06 PM PDT 24 24199099 ps
T1292 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2232053034 Aug 16 04:56:21 PM PDT 24 Aug 16 04:56:23 PM PDT 24 120552887 ps
T1293 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2293540968 Aug 16 04:55:55 PM PDT 24 Aug 16 04:55:56 PM PDT 24 70952271 ps
T1294 /workspace/coverage/cover_reg_top/7.uart_intr_test.2548686165 Aug 16 04:56:01 PM PDT 24 Aug 16 04:56:02 PM PDT 24 14653271 ps
T1295 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.701857181 Aug 16 04:56:16 PM PDT 24 Aug 16 04:56:18 PM PDT 24 94797222 ps
T1296 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4158388624 Aug 16 04:56:03 PM PDT 24 Aug 16 04:56:03 PM PDT 24 97972144 ps
T1297 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3252887446 Aug 16 04:55:50 PM PDT 24 Aug 16 04:55:51 PM PDT 24 53508214 ps
T1298 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.35075900 Aug 16 04:55:55 PM PDT 24 Aug 16 04:55:56 PM PDT 24 27868916 ps
T1299 /workspace/coverage/cover_reg_top/47.uart_intr_test.2765141313 Aug 16 04:56:28 PM PDT 24 Aug 16 04:56:29 PM PDT 24 11871707 ps
T1300 /workspace/coverage/cover_reg_top/11.uart_intr_test.3386394236 Aug 16 04:55:55 PM PDT 24 Aug 16 04:55:56 PM PDT 24 31641677 ps
T1301 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2949390796 Aug 16 04:55:55 PM PDT 24 Aug 16 04:55:57 PM PDT 24 50628449 ps
T58 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1273979595 Aug 16 04:55:59 PM PDT 24 Aug 16 04:56:00 PM PDT 24 15345299 ps
T1302 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4093487889 Aug 16 04:55:46 PM PDT 24 Aug 16 04:55:47 PM PDT 24 21794459 ps
T59 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3227900990 Aug 16 04:55:50 PM PDT 24 Aug 16 04:55:51 PM PDT 24 26830850 ps
T60 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3635117707 Aug 16 04:56:01 PM PDT 24 Aug 16 04:56:02 PM PDT 24 15102976 ps
T1303 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3990433214 Aug 16 04:56:16 PM PDT 24 Aug 16 04:56:17 PM PDT 24 20320357 ps
T1304 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4285127068 Aug 16 04:55:52 PM PDT 24 Aug 16 04:55:53 PM PDT 24 354829909 ps
T1305 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1436336467 Aug 16 04:55:54 PM PDT 24 Aug 16 04:55:55 PM PDT 24 298556390 ps
T1306 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.596664611 Aug 16 04:56:05 PM PDT 24 Aug 16 04:56:06 PM PDT 24 57139166 ps
T1307 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1613449609 Aug 16 04:56:01 PM PDT 24 Aug 16 04:56:02 PM PDT 24 13672556 ps
T1308 /workspace/coverage/cover_reg_top/15.uart_intr_test.709563177 Aug 16 04:56:06 PM PDT 24 Aug 16 04:56:06 PM PDT 24 176309952 ps
T1309 /workspace/coverage/cover_reg_top/32.uart_intr_test.4124248977 Aug 16 04:56:18 PM PDT 24 Aug 16 04:56:19 PM PDT 24 25873455 ps
T105 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1397700165 Aug 16 04:56:04 PM PDT 24 Aug 16 04:56:05 PM PDT 24 123347763 ps
T61 /workspace/coverage/cover_reg_top/3.uart_csr_rw.664620459 Aug 16 04:55:52 PM PDT 24 Aug 16 04:55:53 PM PDT 24 11982339 ps
T1310 /workspace/coverage/cover_reg_top/11.uart_csr_rw.322610780 Aug 16 04:56:02 PM PDT 24 Aug 16 04:56:03 PM PDT 24 12380301 ps
T1311 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1502627718 Aug 16 04:55:56 PM PDT 24 Aug 16 04:55:57 PM PDT 24 27100655 ps
T1312 /workspace/coverage/cover_reg_top/33.uart_intr_test.549879412 Aug 16 04:56:19 PM PDT 24 Aug 16 04:56:20 PM PDT 24 113831870 ps
T1313 /workspace/coverage/cover_reg_top/10.uart_intr_test.153438291 Aug 16 04:56:16 PM PDT 24 Aug 16 04:56:17 PM PDT 24 29148218 ps
T1314 /workspace/coverage/cover_reg_top/20.uart_intr_test.166259649 Aug 16 04:56:09 PM PDT 24 Aug 16 04:56:10 PM PDT 24 12150079 ps
T1315 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.522754914 Aug 16 04:55:56 PM PDT 24 Aug 16 04:55:57 PM PDT 24 93819735 ps
T1316 /workspace/coverage/cover_reg_top/37.uart_intr_test.3128135299 Aug 16 04:56:26 PM PDT 24 Aug 16 04:56:27 PM PDT 24 64064217 ps
T1317 /workspace/coverage/cover_reg_top/12.uart_tl_errors.732849227 Aug 16 04:55:58 PM PDT 24 Aug 16 04:56:00 PM PDT 24 74633185 ps
T1318 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1427743813 Aug 16 04:56:00 PM PDT 24 Aug 16 04:56:01 PM PDT 24 29843002 ps

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.682718900
Short name T9
Test name
Test status
Simulation time 4805629647 ps
CPU time 17.74 seconds
Started Aug 16 05:02:31 PM PDT 24
Finished Aug 16 05:02:49 PM PDT 24
Peak memory 209364 kb
Host smart-fc5be10b-2f63-404a-8358-e700a664027c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682718900 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.682718900
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.57309026
Short name T91
Test name
Test status
Simulation time 179413751914 ps
CPU time 572.47 seconds
Started Aug 16 05:01:59 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 200896 kb
Host smart-91140633-b055-4876-a122-e09ef4a5ae65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57309026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.57309026
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3415742824
Short name T93
Test name
Test status
Simulation time 89252902156 ps
CPU time 31.04 seconds
Started Aug 16 05:02:52 PM PDT 24
Finished Aug 16 05:03:23 PM PDT 24
Peak memory 200792 kb
Host smart-04a70671-8f41-4921-8c55-6a393179ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415742824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3415742824
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_stress_all.1110271046
Short name T48
Test name
Test status
Simulation time 291247001477 ps
CPU time 881.33 seconds
Started Aug 16 05:05:03 PM PDT 24
Finished Aug 16 05:19:45 PM PDT 24
Peak memory 209424 kb
Host smart-138c3dac-883a-4c1c-aa4b-dc1584286917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110271046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1110271046
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3380866661
Short name T6
Test name
Test status
Simulation time 30525655185 ps
CPU time 73.08 seconds
Started Aug 16 05:07:02 PM PDT 24
Finished Aug 16 05:08:15 PM PDT 24
Peak memory 200820 kb
Host smart-84316b60-6300-472d-b9f9-2987da7d6416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380866661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3380866661
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all.4283802338
Short name T253
Test name
Test status
Simulation time 177524094904 ps
CPU time 472.4 seconds
Started Aug 16 05:05:30 PM PDT 24
Finished Aug 16 05:13:23 PM PDT 24
Peak memory 200896 kb
Host smart-323f8ba1-a8bb-421e-b8fe-76119e32245c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283802338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4283802338
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_intr.2078782313
Short name T24
Test name
Test status
Simulation time 60550816925 ps
CPU time 32.74 seconds
Started Aug 16 05:03:08 PM PDT 24
Finished Aug 16 05:03:41 PM PDT 24
Peak memory 200900 kb
Host smart-669a12d2-5a05-4cbf-9cbd-4f98866b062e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078782313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2078782313
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1558310927
Short name T251
Test name
Test status
Simulation time 87003176557 ps
CPU time 783.17 seconds
Started Aug 16 05:04:08 PM PDT 24
Finished Aug 16 05:17:11 PM PDT 24
Peak memory 200796 kb
Host smart-7e678687-5335-4ae3-a65c-d40aa94de969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558310927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1558310927
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2760346275
Short name T263
Test name
Test status
Simulation time 109295245496 ps
CPU time 235.57 seconds
Started Aug 16 05:04:41 PM PDT 24
Finished Aug 16 05:08:37 PM PDT 24
Peak memory 200912 kb
Host smart-a2e8119e-8591-4939-b172-1c3433c32cb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760346275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2760346275
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_stress_all.1443975423
Short name T280
Test name
Test status
Simulation time 212992740785 ps
CPU time 1245.6 seconds
Started Aug 16 05:04:54 PM PDT 24
Finished Aug 16 05:25:40 PM PDT 24
Peak memory 209128 kb
Host smart-a99207fb-6392-41a3-b578-78713f393b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443975423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1443975423
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4061101913
Short name T221
Test name
Test status
Simulation time 136788521808 ps
CPU time 71.79 seconds
Started Aug 16 05:06:26 PM PDT 24
Finished Aug 16 05:07:38 PM PDT 24
Peak memory 200820 kb
Host smart-99931c16-5d63-4508-93a8-052228a45051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061101913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4061101913
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.4094255909
Short name T12
Test name
Test status
Simulation time 9572679005 ps
CPU time 28.43 seconds
Started Aug 16 05:05:58 PM PDT 24
Finished Aug 16 05:06:26 PM PDT 24
Peak memory 217384 kb
Host smart-f5954e23-5eeb-4410-9e04-6af7f806824b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094255909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.4094255909
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3288795932
Short name T69
Test name
Test status
Simulation time 79059203 ps
CPU time 1.28 seconds
Started Aug 16 04:56:04 PM PDT 24
Finished Aug 16 04:56:05 PM PDT 24
Peak memory 199588 kb
Host smart-32b10d4c-3bbf-487f-81e7-334174e41b18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288795932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3288795932
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_stress_all.3256825977
Short name T138
Test name
Test status
Simulation time 194564019877 ps
CPU time 135.94 seconds
Started Aug 16 05:02:23 PM PDT 24
Finished Aug 16 05:04:39 PM PDT 24
Peak memory 217520 kb
Host smart-fcd23ff9-426f-45d2-81b5-d0beeaabf806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256825977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3256825977
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_alert_test.1111726769
Short name T10
Test name
Test status
Simulation time 12547700 ps
CPU time 0.55 seconds
Started Aug 16 05:03:38 PM PDT 24
Finished Aug 16 05:03:39 PM PDT 24
Peak memory 196212 kb
Host smart-1b96dd89-ed3f-49e4-9bb9-34e38d0c4569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111726769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1111726769
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1397888068
Short name T51
Test name
Test status
Simulation time 38855836 ps
CPU time 0.68 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 195472 kb
Host smart-0424835a-0b88-4164-9552-d6b7aa1b3ece
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397888068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1397888068
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.129190954
Short name T107
Test name
Test status
Simulation time 150115078192 ps
CPU time 255.73 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 200896 kb
Host smart-7b1d6c33-d24e-412e-8444-faa45c707119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129190954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.129190954
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2099900427
Short name T119
Test name
Test status
Simulation time 218975702317 ps
CPU time 326.86 seconds
Started Aug 16 05:05:40 PM PDT 24
Finished Aug 16 05:11:08 PM PDT 24
Peak memory 201020 kb
Host smart-0a1add85-0176-45de-8224-97c6e91c2986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099900427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2099900427
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1324332666
Short name T246
Test name
Test status
Simulation time 74822349692 ps
CPU time 75.6 seconds
Started Aug 16 05:06:43 PM PDT 24
Finished Aug 16 05:07:59 PM PDT 24
Peak memory 200884 kb
Host smart-3ed47f56-c77d-4d7b-89e2-749365e7b166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324332666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1324332666
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2865734580
Short name T15
Test name
Test status
Simulation time 577893839890 ps
CPU time 64.49 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:08:16 PM PDT 24
Peak memory 200880 kb
Host smart-6e49f37b-a9c0-485c-b834-a01b40a6fa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865734580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2865734580
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.4089079943
Short name T255
Test name
Test status
Simulation time 146168975994 ps
CPU time 114.06 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:05:33 PM PDT 24
Peak memory 200792 kb
Host smart-09422129-8e98-4cd0-981d-322507e441db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089079943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.4089079943
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2135611775
Short name T75
Test name
Test status
Simulation time 115572481 ps
CPU time 0.91 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:01:52 PM PDT 24
Peak memory 218928 kb
Host smart-f8b51e47-f613-451c-9b12-cac7389cc259
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135611775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2135611775
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3716014123
Short name T108
Test name
Test status
Simulation time 108959048046 ps
CPU time 100.56 seconds
Started Aug 16 05:03:40 PM PDT 24
Finished Aug 16 05:05:21 PM PDT 24
Peak memory 200840 kb
Host smart-91885550-3e08-4d6d-82cc-74fd0d886c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716014123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3716014123
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3192383316
Short name T175
Test name
Test status
Simulation time 136893946232 ps
CPU time 229.04 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:10:41 PM PDT 24
Peak memory 201024 kb
Host smart-3f5f0279-3f06-46b6-8da4-67ed3cc06abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192383316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3192383316
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4087151164
Short name T96
Test name
Test status
Simulation time 38285890985 ps
CPU time 18.53 seconds
Started Aug 16 05:03:30 PM PDT 24
Finished Aug 16 05:03:49 PM PDT 24
Peak memory 200920 kb
Host smart-a13365b1-6f3f-480b-ba9d-9dbafdbb07fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087151164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4087151164
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.425409275
Short name T326
Test name
Test status
Simulation time 197134028045 ps
CPU time 403.35 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:13:58 PM PDT 24
Peak memory 200908 kb
Host smart-9243df49-6b04-434c-bedf-2d33a22255cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425409275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.425409275
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.4233511805
Short name T163
Test name
Test status
Simulation time 113246579891 ps
CPU time 613.7 seconds
Started Aug 16 05:04:06 PM PDT 24
Finished Aug 16 05:14:20 PM PDT 24
Peak memory 209192 kb
Host smart-204c7943-7806-466d-821f-ff9895c8de7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233511805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4233511805
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.625059247
Short name T111
Test name
Test status
Simulation time 138388329490 ps
CPU time 226.65 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:06:11 PM PDT 24
Peak memory 200860 kb
Host smart-a5a95d38-161f-4042-aef2-ba899edad865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625059247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.625059247
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1481450732
Short name T157
Test name
Test status
Simulation time 38897241411 ps
CPU time 56.4 seconds
Started Aug 16 05:06:20 PM PDT 24
Finished Aug 16 05:07:16 PM PDT 24
Peak memory 200924 kb
Host smart-f7c4d46f-53cf-418f-990b-a0a87d2bff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481450732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1481450732
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2706580650
Short name T135
Test name
Test status
Simulation time 160597272109 ps
CPU time 114.68 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:08:46 PM PDT 24
Peak memory 200904 kb
Host smart-e88e3d7a-a82f-4aab-838e-9fc90f1fd13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706580650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2706580650
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3695652537
Short name T86
Test name
Test status
Simulation time 8101650805 ps
CPU time 22.61 seconds
Started Aug 16 05:02:22 PM PDT 24
Finished Aug 16 05:02:45 PM PDT 24
Peak memory 217528 kb
Host smart-0d6a5834-cfc1-49b6-946e-c8d349d1d02f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695652537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3695652537
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2202453912
Short name T67
Test name
Test status
Simulation time 17441800 ps
CPU time 0.63 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 195540 kb
Host smart-cd70503d-5382-452c-8854-572cc569ec3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202453912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2202453912
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/4.uart_stress_all.4040378905
Short name T329
Test name
Test status
Simulation time 194395218254 ps
CPU time 303.06 seconds
Started Aug 16 05:02:07 PM PDT 24
Finished Aug 16 05:07:10 PM PDT 24
Peak memory 200908 kb
Host smart-5ab25c9c-aa7c-4fe6-bf49-53b3e74bd778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040378905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4040378905
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all.1844842665
Short name T464
Test name
Test status
Simulation time 150986144817 ps
CPU time 2440.25 seconds
Started Aug 16 05:03:53 PM PDT 24
Finished Aug 16 05:44:34 PM PDT 24
Peak memory 200836 kb
Host smart-17835bd5-ca7b-4143-8c9f-129de98a866f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844842665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1844842665
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4063804349
Short name T114
Test name
Test status
Simulation time 205132035501 ps
CPU time 320.87 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 200856 kb
Host smart-6bd5f55f-24d4-4b90-95c1-57e0c17e49f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063804349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4063804349
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3487149669
Short name T116
Test name
Test status
Simulation time 33979813775 ps
CPU time 18.22 seconds
Started Aug 16 05:06:49 PM PDT 24
Finished Aug 16 05:07:08 PM PDT 24
Peak memory 200912 kb
Host smart-bb463feb-8922-4a5c-a31b-c536d6b7ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487149669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3487149669
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.1258070113
Short name T334
Test name
Test status
Simulation time 112639303142 ps
CPU time 243.05 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:06:31 PM PDT 24
Peak memory 200932 kb
Host smart-66797c5f-e988-4372-8f73-86e4742411b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258070113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1258070113
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all.147412616
Short name T588
Test name
Test status
Simulation time 611954059584 ps
CPU time 580.69 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:13:05 PM PDT 24
Peak memory 200740 kb
Host smart-5b66cb23-0c96-4f1b-8409-3a0b955add1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147412616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.147412616
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3418408578
Short name T45
Test name
Test status
Simulation time 247177358558 ps
CPU time 171.62 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:09:43 PM PDT 24
Peak memory 200644 kb
Host smart-051c320d-b2b4-4d35-ba32-be45f2e3fade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418408578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3418408578
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2017260936
Short name T229
Test name
Test status
Simulation time 79791786995 ps
CPU time 26.36 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:14 PM PDT 24
Peak memory 200912 kb
Host smart-1e70aa00-f95d-4ad0-958c-74a285f566e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017260936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2017260936
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_full.4055085139
Short name T134
Test name
Test status
Simulation time 77667011788 ps
CPU time 70.27 seconds
Started Aug 16 05:02:08 PM PDT 24
Finished Aug 16 05:03:18 PM PDT 24
Peak memory 200960 kb
Host smart-3fe153fb-379b-47ac-9dd1-85e579fe5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055085139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4055085139
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2318742296
Short name T231
Test name
Test status
Simulation time 30445285477 ps
CPU time 50.63 seconds
Started Aug 16 05:07:22 PM PDT 24
Finished Aug 16 05:08:12 PM PDT 24
Peak memory 200852 kb
Host smart-41c89ce0-6559-4296-bf40-4cec42d30766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318742296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2318742296
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.114796483
Short name T97
Test name
Test status
Simulation time 51450885085 ps
CPU time 19.91 seconds
Started Aug 16 05:01:58 PM PDT 24
Finished Aug 16 05:02:18 PM PDT 24
Peak memory 200704 kb
Host smart-04561ecb-8f2c-4984-a2f7-2455df8e5354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114796483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.114796483
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_stress_all.1684131520
Short name T99
Test name
Test status
Simulation time 694012359921 ps
CPU time 217.81 seconds
Started Aug 16 05:04:32 PM PDT 24
Finished Aug 16 05:08:10 PM PDT 24
Peak memory 200896 kb
Host smart-73e8eae3-6d16-4924-a8dd-b16e1e20b9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684131520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1684131520
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3320170971
Short name T143
Test name
Test status
Simulation time 78070899588 ps
CPU time 121.53 seconds
Started Aug 16 05:04:40 PM PDT 24
Finished Aug 16 05:06:42 PM PDT 24
Peak memory 200952 kb
Host smart-8c577830-61bf-4dc5-aa56-88b4098c74a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320170971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3320170971
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2972478231
Short name T152
Test name
Test status
Simulation time 65284768882 ps
CPU time 16.04 seconds
Started Aug 16 05:06:10 PM PDT 24
Finished Aug 16 05:06:26 PM PDT 24
Peak memory 200840 kb
Host smart-bc51f4dc-8d90-4593-9f50-4bda6aa2f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972478231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2972478231
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2639184739
Short name T314
Test name
Test status
Simulation time 116591441027 ps
CPU time 297.02 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:08:39 PM PDT 24
Peak memory 200548 kb
Host smart-ea5a2848-ee69-450c-bbc3-60b2cbb4e559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639184739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2639184739
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2876113409
Short name T188
Test name
Test status
Simulation time 172319235251 ps
CPU time 114.47 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:07:57 PM PDT 24
Peak memory 200924 kb
Host smart-df966449-3b6a-4a24-9044-9cce36d0ac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876113409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2876113409
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1126715803
Short name T966
Test name
Test status
Simulation time 94284368575 ps
CPU time 21.49 seconds
Started Aug 16 05:01:59 PM PDT 24
Finished Aug 16 05:02:20 PM PDT 24
Peak memory 200776 kb
Host smart-40fdceae-62cb-49ab-a161-65c198bf5c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126715803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1126715803
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_noise_filter.4245758823
Short name T278
Test name
Test status
Simulation time 76620040908 ps
CPU time 145.53 seconds
Started Aug 16 05:01:57 PM PDT 24
Finished Aug 16 05:04:22 PM PDT 24
Peak memory 201072 kb
Host smart-3b94e16d-e9c9-42ff-a807-0c60936e1cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245758823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4245758823
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.109598337
Short name T248
Test name
Test status
Simulation time 4033723143 ps
CPU time 14.02 seconds
Started Aug 16 05:02:43 PM PDT 24
Finished Aug 16 05:02:57 PM PDT 24
Peak memory 201060 kb
Host smart-e1287bfc-03c0-4326-a595-4129e2b454c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109598337 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.109598337
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3686613901
Short name T711
Test name
Test status
Simulation time 21707834902 ps
CPU time 30.13 seconds
Started Aug 16 05:06:49 PM PDT 24
Finished Aug 16 05:07:20 PM PDT 24
Peak memory 200836 kb
Host smart-a0a4a20a-6210-4133-8318-69799ac3a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686613901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3686613901
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2915514070
Short name T141
Test name
Test status
Simulation time 123486585115 ps
CPU time 43.53 seconds
Started Aug 16 05:07:04 PM PDT 24
Finished Aug 16 05:07:48 PM PDT 24
Peak memory 200824 kb
Host smart-b2a0488c-37b4-4824-87f7-952ccf2d473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915514070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2915514070
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1762259954
Short name T204
Test name
Test status
Simulation time 89809893624 ps
CPU time 66.09 seconds
Started Aug 16 05:07:13 PM PDT 24
Finished Aug 16 05:08:19 PM PDT 24
Peak memory 200940 kb
Host smart-209bc8a4-9c3c-4fc8-9244-ce05f2206dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762259954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1762259954
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3161068652
Short name T341
Test name
Test status
Simulation time 5575337811 ps
CPU time 19.1 seconds
Started Aug 16 05:05:50 PM PDT 24
Finished Aug 16 05:06:09 PM PDT 24
Peak memory 209304 kb
Host smart-5050af4a-0c34-4387-93cb-f119d41ab1b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161068652 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3161068652
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.92282231
Short name T216
Test name
Test status
Simulation time 198778820329 ps
CPU time 98.67 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:04:03 PM PDT 24
Peak memory 200860 kb
Host smart-bf535dd3-e528-44b9-8c7e-35f836b5e30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92282231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.92282231
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.361152920
Short name T179
Test name
Test status
Simulation time 51898844949 ps
CPU time 23.32 seconds
Started Aug 16 05:06:16 PM PDT 24
Finished Aug 16 05:06:40 PM PDT 24
Peak memory 200940 kb
Host smart-12eeabf3-9507-495e-a258-1d767062e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361152920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.361152920
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2114444392
Short name T169
Test name
Test status
Simulation time 29838884700 ps
CPU time 19.13 seconds
Started Aug 16 05:06:17 PM PDT 24
Finished Aug 16 05:06:36 PM PDT 24
Peak memory 200868 kb
Host smart-c95f4bba-9844-4681-9b03-47d8b6afb8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114444392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2114444392
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.754128978
Short name T990
Test name
Test status
Simulation time 50445931629 ps
CPU time 42.55 seconds
Started Aug 16 05:06:32 PM PDT 24
Finished Aug 16 05:07:15 PM PDT 24
Peak memory 200768 kb
Host smart-4451d9f3-d9a3-462e-bdb8-625638bc7c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754128978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.754128978
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.3330244952
Short name T317
Test name
Test status
Simulation time 336467508140 ps
CPU time 136.98 seconds
Started Aug 16 05:02:52 PM PDT 24
Finished Aug 16 05:05:09 PM PDT 24
Peak memory 210360 kb
Host smart-125d7e5b-6cfa-4e5d-8dd3-ca95f28e846a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330244952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3330244952
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2625227726
Short name T213
Test name
Test status
Simulation time 94922021130 ps
CPU time 43.74 seconds
Started Aug 16 05:06:42 PM PDT 24
Finished Aug 16 05:07:26 PM PDT 24
Peak memory 200868 kb
Host smart-6b2b8579-4bcf-4d15-a182-e4334f0bc66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625227726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2625227726
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2532807357
Short name T136
Test name
Test status
Simulation time 33221694601 ps
CPU time 30.34 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:07:42 PM PDT 24
Peak memory 200900 kb
Host smart-1f4de48a-372e-42ca-a59b-c437a6606cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532807357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2532807357
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1585810963
Short name T581
Test name
Test status
Simulation time 4761805349 ps
CPU time 12.68 seconds
Started Aug 16 05:04:59 PM PDT 24
Finished Aug 16 05:05:12 PM PDT 24
Peak memory 201124 kb
Host smart-c89e62ea-3da6-4cff-909a-f1ea00751602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585810963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1585810963
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.4124002417
Short name T710
Test name
Test status
Simulation time 713095413713 ps
CPU time 341.93 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:10:59 PM PDT 24
Peak memory 217320 kb
Host smart-0fc99bc0-7865-43b4-bf4a-02b0ed3cb8ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124002417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.4124002417
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1397700165
Short name T105
Test name
Test status
Simulation time 123347763 ps
CPU time 1.23 seconds
Started Aug 16 04:56:04 PM PDT 24
Finished Aug 16 04:56:05 PM PDT 24
Peak memory 199572 kb
Host smart-e6559455-d0b9-4196-99fa-98537f4d3af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397700165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1397700165
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.19815863
Short name T71
Test name
Test status
Simulation time 86463438 ps
CPU time 1.38 seconds
Started Aug 16 04:56:02 PM PDT 24
Finished Aug 16 04:56:04 PM PDT 24
Peak memory 199656 kb
Host smart-db558d97-5d89-4a6f-985c-cc6aa201d211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.19815863
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2260041857
Short name T738
Test name
Test status
Simulation time 16033893440 ps
CPU time 35.31 seconds
Started Aug 16 05:02:26 PM PDT 24
Finished Aug 16 05:03:01 PM PDT 24
Peak memory 210624 kb
Host smart-d6188f06-bd1f-48d1-9531-81deffc1b02a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260041857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2260041857
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.228991073
Short name T98
Test name
Test status
Simulation time 76270486824 ps
CPU time 51.7 seconds
Started Aug 16 05:06:10 PM PDT 24
Finished Aug 16 05:07:02 PM PDT 24
Peak memory 200924 kb
Host smart-62778dc2-1b00-474e-a54a-890335083e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228991073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.228991073
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1027060193
Short name T1162
Test name
Test status
Simulation time 58995038889 ps
CPU time 94.1 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:07:53 PM PDT 24
Peak memory 200856 kb
Host smart-2fae2ffc-5bd3-4619-a067-2a7aa8322bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027060193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1027060193
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.51654104
Short name T42
Test name
Test status
Simulation time 21676735743 ps
CPU time 43.41 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:07:01 PM PDT 24
Peak memory 200884 kb
Host smart-0198544f-0254-4afc-aa97-1b6fb918db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51654104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.51654104
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1755212545
Short name T3
Test name
Test status
Simulation time 29111832304 ps
CPU time 44.67 seconds
Started Aug 16 05:06:19 PM PDT 24
Finished Aug 16 05:07:04 PM PDT 24
Peak memory 200920 kb
Host smart-91afa3ad-7a36-4dfb-a8db-1e70f303c943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755212545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1755212545
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1913445440
Short name T186
Test name
Test status
Simulation time 28193226470 ps
CPU time 32.05 seconds
Started Aug 16 05:06:19 PM PDT 24
Finished Aug 16 05:06:52 PM PDT 24
Peak memory 200864 kb
Host smart-6556a6b1-6e0b-4629-a797-d09819da5d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913445440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1913445440
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1343348474
Short name T228
Test name
Test status
Simulation time 56136843428 ps
CPU time 47.77 seconds
Started Aug 16 05:06:21 PM PDT 24
Finished Aug 16 05:07:09 PM PDT 24
Peak memory 200892 kb
Host smart-39c67bfe-beda-4be8-bc99-c48d2efe2581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343348474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1343348474
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1383324497
Short name T234
Test name
Test status
Simulation time 184593423151 ps
CPU time 17.88 seconds
Started Aug 16 05:06:19 PM PDT 24
Finished Aug 16 05:06:37 PM PDT 24
Peak memory 200852 kb
Host smart-8e3bd12b-e5ac-4af2-b841-76d81b605eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383324497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1383324497
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3659910411
Short name T226
Test name
Test status
Simulation time 18241465633 ps
CPU time 29.71 seconds
Started Aug 16 05:06:25 PM PDT 24
Finished Aug 16 05:06:55 PM PDT 24
Peak memory 200836 kb
Host smart-5a7f436d-4beb-4225-bf1e-905edcb3a779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659910411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3659910411
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4291489918
Short name T869
Test name
Test status
Simulation time 87045373554 ps
CPU time 42.58 seconds
Started Aug 16 05:06:27 PM PDT 24
Finished Aug 16 05:07:10 PM PDT 24
Peak memory 200868 kb
Host smart-3ca0ef80-b2e3-4162-a4a0-71a64b141661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291489918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4291489918
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1792501493
Short name T241
Test name
Test status
Simulation time 72329808955 ps
CPU time 36.45 seconds
Started Aug 16 05:06:27 PM PDT 24
Finished Aug 16 05:07:04 PM PDT 24
Peak memory 200764 kb
Host smart-66143b78-b0a8-458e-9128-070228944187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792501493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1792501493
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.730297566
Short name T196
Test name
Test status
Simulation time 32980378300 ps
CPU time 49.68 seconds
Started Aug 16 05:06:35 PM PDT 24
Finished Aug 16 05:07:25 PM PDT 24
Peak memory 200848 kb
Host smart-0ec8f37a-b95f-4fa4-95f8-e20b5c9c619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730297566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.730297566
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.790599540
Short name T187
Test name
Test status
Simulation time 193015850395 ps
CPU time 320.53 seconds
Started Aug 16 05:02:51 PM PDT 24
Finished Aug 16 05:08:12 PM PDT 24
Peak memory 200892 kb
Host smart-bd558b24-4c93-4945-962c-493dd09215c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790599540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.790599540
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3319232456
Short name T888
Test name
Test status
Simulation time 164423759280 ps
CPU time 25.19 seconds
Started Aug 16 05:06:35 PM PDT 24
Finished Aug 16 05:07:00 PM PDT 24
Peak memory 200900 kb
Host smart-80207bb0-7ae2-4ce8-9e80-3aa4e29393f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319232456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3319232456
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1584077103
Short name T92
Test name
Test status
Simulation time 44377583023 ps
CPU time 67.67 seconds
Started Aug 16 05:06:36 PM PDT 24
Finished Aug 16 05:07:44 PM PDT 24
Peak memory 200828 kb
Host smart-aea3193b-c01d-43aa-bd13-c941fcf07d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584077103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1584077103
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.65863377
Short name T238
Test name
Test status
Simulation time 46704787777 ps
CPU time 49.23 seconds
Started Aug 16 05:02:54 PM PDT 24
Finished Aug 16 05:03:43 PM PDT 24
Peak memory 200876 kb
Host smart-1605d95e-be05-4c2a-96b5-88f70d1fa3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65863377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.65863377
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1514093327
Short name T243
Test name
Test status
Simulation time 21462888165 ps
CPU time 17.91 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:07:10 PM PDT 24
Peak memory 200824 kb
Host smart-573b6208-c9b6-4d0b-bee3-5f672078ad86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514093327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1514093327
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3395531329
Short name T223
Test name
Test status
Simulation time 108928056385 ps
CPU time 83.32 seconds
Started Aug 16 05:06:49 PM PDT 24
Finished Aug 16 05:08:12 PM PDT 24
Peak memory 200628 kb
Host smart-0234b1c5-b2e8-4acd-abb1-58b8d1f7a74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395531329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3395531329
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.816042497
Short name T220
Test name
Test status
Simulation time 319670107160 ps
CPU time 135.18 seconds
Started Aug 16 05:03:25 PM PDT 24
Finished Aug 16 05:05:40 PM PDT 24
Peak memory 200936 kb
Host smart-4f78a968-6d2b-427f-85bd-577e9423d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816042497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.816042497
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3210342946
Short name T156
Test name
Test status
Simulation time 56454515809 ps
CPU time 20.17 seconds
Started Aug 16 05:07:09 PM PDT 24
Finished Aug 16 05:07:29 PM PDT 24
Peak memory 200688 kb
Host smart-3b1f44f8-69c1-4cf5-88b0-914d3afe6985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210342946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3210342946
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3867260321
Short name T198
Test name
Test status
Simulation time 58605509232 ps
CPU time 88.8 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:08:39 PM PDT 24
Peak memory 200820 kb
Host smart-2640561a-1cb2-4f33-917d-2f4958b1a5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867260321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3867260321
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1803137494
Short name T245
Test name
Test status
Simulation time 59899409480 ps
CPU time 11.52 seconds
Started Aug 16 05:07:12 PM PDT 24
Finished Aug 16 05:07:24 PM PDT 24
Peak memory 200756 kb
Host smart-34d8d611-6aee-46cc-ba34-23d569e73aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803137494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1803137494
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.776463769
Short name T227
Test name
Test status
Simulation time 57169618178 ps
CPU time 16.25 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:07:26 PM PDT 24
Peak memory 200852 kb
Host smart-3cd063a6-906a-441f-b0cb-799320ee57b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776463769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.776463769
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3461836405
Short name T240
Test name
Test status
Simulation time 13755261446 ps
CPU time 5.86 seconds
Started Aug 16 05:03:57 PM PDT 24
Finished Aug 16 05:04:03 PM PDT 24
Peak memory 200880 kb
Host smart-062e3841-bfa4-43ca-958b-ffcab4a98569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461836405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3461836405
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.323624540
Short name T239
Test name
Test status
Simulation time 8356794345 ps
CPU time 16.06 seconds
Started Aug 16 05:04:11 PM PDT 24
Finished Aug 16 05:04:27 PM PDT 24
Peak memory 200840 kb
Host smart-acdd8ac1-e8e0-4386-bbd8-2fe7baa715e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323624540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.323624540
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.500321953
Short name T230
Test name
Test status
Simulation time 149253168495 ps
CPU time 63.2 seconds
Started Aug 16 05:06:03 PM PDT 24
Finished Aug 16 05:07:07 PM PDT 24
Peak memory 200908 kb
Host smart-555cc43b-c9b0-45e3-9bc4-9b5abbbfcef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500321953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.500321953
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2706564156
Short name T1223
Test name
Test status
Simulation time 20726213 ps
CPU time 0.68 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:54 PM PDT 24
Peak memory 195492 kb
Host smart-bd0a63d2-5b76-4c30-bbf4-fc3b5b910b23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706564156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2706564156
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1524136477
Short name T1272
Test name
Test status
Simulation time 363275483 ps
CPU time 1.5 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 198200 kb
Host smart-eb3075ba-97a9-4cb4-a367-2b72b199df8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524136477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1524136477
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3252887446
Short name T1297
Test name
Test status
Simulation time 53508214 ps
CPU time 0.64 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 195452 kb
Host smart-bff74076-4997-4281-94f7-62647ab7ef64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252887446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3252887446
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1365212323
Short name T1268
Test name
Test status
Simulation time 27859934 ps
CPU time 1.25 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 200236 kb
Host smart-0e209739-422a-44a9-bc60-a07192489d49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365212323 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1365212323
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.167780540
Short name T1195
Test name
Test status
Simulation time 27287521 ps
CPU time 0.57 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:49 PM PDT 24
Peak memory 194496 kb
Host smart-f96c33ce-4a9a-4947-87ee-08b21f427521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167780540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.167780540
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3939871329
Short name T62
Test name
Test status
Simulation time 19540573 ps
CPU time 0.62 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 195544 kb
Host smart-4438ff51-bba2-4e24-927f-0af69a314493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939871329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3939871329
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2804873499
Short name T1269
Test name
Test status
Simulation time 999717569 ps
CPU time 2.03 seconds
Started Aug 16 04:55:46 PM PDT 24
Finished Aug 16 04:55:48 PM PDT 24
Peak memory 200216 kb
Host smart-b7178bcc-e6e6-4c61-8d6d-5e5968b859c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804873499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2804873499
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1816620521
Short name T1283
Test name
Test status
Simulation time 51658567 ps
CPU time 1.02 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 199328 kb
Host smart-47567c97-a89e-4a36-a885-ccc4dc23b353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816620521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1816620521
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.909340695
Short name T1215
Test name
Test status
Simulation time 533499293 ps
CPU time 1.61 seconds
Started Aug 16 04:55:46 PM PDT 24
Finished Aug 16 04:55:48 PM PDT 24
Peak memory 197740 kb
Host smart-6ea39170-89ba-4939-ae47-03e169b03184
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909340695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.909340695
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1709286620
Short name T1183
Test name
Test status
Simulation time 39528320 ps
CPU time 0.56 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:54 PM PDT 24
Peak memory 195440 kb
Host smart-44c42802-9528-40ce-a4e2-96651707cbf0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709286620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1709286620
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.595124924
Short name T1188
Test name
Test status
Simulation time 89864158 ps
CPU time 0.8 seconds
Started Aug 16 04:55:47 PM PDT 24
Finished Aug 16 04:55:48 PM PDT 24
Peak memory 199996 kb
Host smart-cbbc006a-7c77-4b21-ab5c-e36bb4739a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595124924 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.595124924
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3982912125
Short name T53
Test name
Test status
Simulation time 31365307 ps
CPU time 0.58 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:49 PM PDT 24
Peak memory 195532 kb
Host smart-638336c3-244f-4c79-b7c2-c2428d19f1c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982912125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3982912125
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4061885409
Short name T1235
Test name
Test status
Simulation time 14365965 ps
CPU time 0.58 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 194536 kb
Host smart-b2883b7c-bdd8-4847-b1ed-6542ed1e1bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061885409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4061885409
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2676795116
Short name T1263
Test name
Test status
Simulation time 20952790 ps
CPU time 0.65 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 195480 kb
Host smart-e70bd95f-3651-4bee-adf2-dd50a174bffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676795116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2676795116
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3064007030
Short name T1194
Test name
Test status
Simulation time 150912161 ps
CPU time 1.97 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:58 PM PDT 24
Peak memory 200112 kb
Host smart-7f2e71fe-e6d3-4dce-a19f-f64be1d2cd6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064007030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3064007030
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2887390641
Short name T1289
Test name
Test status
Simulation time 89464870 ps
CPU time 1.32 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:49 PM PDT 24
Peak memory 199728 kb
Host smart-01f2f5ec-edac-413f-b71a-7677f963961b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887390641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2887390641
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3805485728
Short name T1258
Test name
Test status
Simulation time 29290467 ps
CPU time 0.76 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 198680 kb
Host smart-870b9dfc-eedd-4b6c-8c33-31a298c6117e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805485728 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3805485728
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.555239034
Short name T63
Test name
Test status
Simulation time 19736096 ps
CPU time 0.53 seconds
Started Aug 16 04:55:54 PM PDT 24
Finished Aug 16 04:55:55 PM PDT 24
Peak memory 195512 kb
Host smart-8007bc00-448f-4e07-94fa-43f4bfae3467
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555239034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.555239034
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.153438291
Short name T1313
Test name
Test status
Simulation time 29148218 ps
CPU time 0.57 seconds
Started Aug 16 04:56:16 PM PDT 24
Finished Aug 16 04:56:17 PM PDT 24
Peak memory 194536 kb
Host smart-72fdcc2f-11ec-4e92-9276-3ec9334f6817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153438291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.153438291
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3060656127
Short name T1273
Test name
Test status
Simulation time 16353630 ps
CPU time 0.76 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 197300 kb
Host smart-b132b258-c512-46e5-972f-fe82d117149e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060656127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3060656127
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4114309070
Short name T1189
Test name
Test status
Simulation time 389309814 ps
CPU time 2.13 seconds
Started Aug 16 04:56:00 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 200036 kb
Host smart-8f399dc8-29be-469c-a23e-846d8a7f093b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114309070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4114309070
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3606519500
Short name T1261
Test name
Test status
Simulation time 49146147 ps
CPU time 0.92 seconds
Started Aug 16 04:56:09 PM PDT 24
Finished Aug 16 04:56:10 PM PDT 24
Peak memory 199072 kb
Host smart-316012bc-e1bc-4bec-b78e-32e423d55463
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606519500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3606519500
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2949390796
Short name T1301
Test name
Test status
Simulation time 50628449 ps
CPU time 1.25 seconds
Started Aug 16 04:55:55 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 200236 kb
Host smart-05b4f629-1712-41b9-ad31-6f025fa14554
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949390796 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2949390796
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.322610780
Short name T1310
Test name
Test status
Simulation time 12380301 ps
CPU time 0.61 seconds
Started Aug 16 04:56:02 PM PDT 24
Finished Aug 16 04:56:03 PM PDT 24
Peak memory 195532 kb
Host smart-13cbc920-7036-4b7d-9a69-44bf0c380dc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322610780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.322610780
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3386394236
Short name T1300
Test name
Test status
Simulation time 31641677 ps
CPU time 0.53 seconds
Started Aug 16 04:55:55 PM PDT 24
Finished Aug 16 04:55:56 PM PDT 24
Peak memory 194552 kb
Host smart-20b23ddb-8b7b-4ab6-8e55-abc43776793d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386394236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3386394236
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.35075900
Short name T1298
Test name
Test status
Simulation time 27868916 ps
CPU time 0.77 seconds
Started Aug 16 04:55:55 PM PDT 24
Finished Aug 16 04:55:56 PM PDT 24
Peak memory 196000 kb
Host smart-8cdf9c4d-a517-4970-8dbe-a6fa28e4a332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35075900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_
outstanding.35075900
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.563330751
Short name T1239
Test name
Test status
Simulation time 80084421 ps
CPU time 1.93 seconds
Started Aug 16 04:56:19 PM PDT 24
Finished Aug 16 04:56:21 PM PDT 24
Peak memory 200204 kb
Host smart-efeb0982-0e62-4a34-9b52-0ce15ae6968d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563330751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.563330751
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.522754914
Short name T1315
Test name
Test status
Simulation time 93819735 ps
CPU time 1.27 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 199340 kb
Host smart-db50c3da-73e9-4571-813d-b4293b7ff7e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522754914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.522754914
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1542336686
Short name T1182
Test name
Test status
Simulation time 19632038 ps
CPU time 0.67 seconds
Started Aug 16 04:55:55 PM PDT 24
Finished Aug 16 04:55:56 PM PDT 24
Peak memory 197644 kb
Host smart-53605ff0-4f58-4323-b7c4-96e2df9b0136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542336686 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1542336686
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.580006098
Short name T68
Test name
Test status
Simulation time 43362678 ps
CPU time 0.59 seconds
Started Aug 16 04:55:58 PM PDT 24
Finished Aug 16 04:55:59 PM PDT 24
Peak memory 195472 kb
Host smart-643178c9-e39d-4b50-8ef7-6d61e701f863
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580006098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.580006098
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.721246812
Short name T1286
Test name
Test status
Simulation time 12436846 ps
CPU time 0.54 seconds
Started Aug 16 04:56:14 PM PDT 24
Finished Aug 16 04:56:14 PM PDT 24
Peak memory 194536 kb
Host smart-f36351b4-37c7-4c99-adb9-6bc80d4dbb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721246812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.721246812
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.266521054
Short name T66
Test name
Test status
Simulation time 53592364 ps
CPU time 0.64 seconds
Started Aug 16 04:56:01 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 195796 kb
Host smart-d9129bf6-6935-4911-8f0e-5ab83d7ae822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266521054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.266521054
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.732849227
Short name T1317
Test name
Test status
Simulation time 74633185 ps
CPU time 2.01 seconds
Started Aug 16 04:55:58 PM PDT 24
Finished Aug 16 04:56:00 PM PDT 24
Peak memory 200212 kb
Host smart-e41f3210-d142-48cd-ad3f-2317082b4f07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732849227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.732849227
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1071578413
Short name T1259
Test name
Test status
Simulation time 50007199 ps
CPU time 0.74 seconds
Started Aug 16 04:56:18 PM PDT 24
Finished Aug 16 04:56:19 PM PDT 24
Peak memory 198740 kb
Host smart-43e4dd95-58b0-495b-b6ae-ecfdcc328604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071578413 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1071578413
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1915424490
Short name T55
Test name
Test status
Simulation time 63800457 ps
CPU time 0.63 seconds
Started Aug 16 04:56:01 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 195628 kb
Host smart-34a5a696-0b11-4a97-ad77-57188f2ee829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915424490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1915424490
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2425264316
Short name T1245
Test name
Test status
Simulation time 16128067 ps
CPU time 0.6 seconds
Started Aug 16 04:56:02 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 194540 kb
Host smart-f968adec-ebe7-4afe-a713-67ddacdb88fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425264316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2425264316
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2183591495
Short name T1241
Test name
Test status
Simulation time 56614681 ps
CPU time 0.65 seconds
Started Aug 16 04:56:13 PM PDT 24
Finished Aug 16 04:56:14 PM PDT 24
Peak memory 195820 kb
Host smart-b4fff695-11c9-43f1-8ace-503152ff9191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183591495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2183591495
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1994809674
Short name T1285
Test name
Test status
Simulation time 1059431933 ps
CPU time 2.03 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:58 PM PDT 24
Peak memory 200148 kb
Host smart-ed7e12b9-3bab-48f9-b308-d957ff1d7bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994809674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1994809674
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1661006829
Short name T1232
Test name
Test status
Simulation time 42056373 ps
CPU time 0.93 seconds
Started Aug 16 04:55:54 PM PDT 24
Finished Aug 16 04:55:55 PM PDT 24
Peak memory 199224 kb
Host smart-4a04e3f4-e74b-4119-b3f6-212df0d94111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661006829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1661006829
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4184961995
Short name T1276
Test name
Test status
Simulation time 50227742 ps
CPU time 0.72 seconds
Started Aug 16 04:56:02 PM PDT 24
Finished Aug 16 04:56:03 PM PDT 24
Peak memory 198396 kb
Host smart-bd443b76-6ebf-4ef8-aa73-1e3c76185bb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184961995 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4184961995
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2776451213
Short name T1266
Test name
Test status
Simulation time 31034467 ps
CPU time 0.61 seconds
Started Aug 16 04:56:05 PM PDT 24
Finished Aug 16 04:56:06 PM PDT 24
Peak memory 195800 kb
Host smart-6dbd6c28-10e0-43b2-ac13-a17b11c3d90a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776451213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2776451213
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.602218183
Short name T1185
Test name
Test status
Simulation time 22181716 ps
CPU time 0.57 seconds
Started Aug 16 04:56:17 PM PDT 24
Finished Aug 16 04:56:18 PM PDT 24
Peak memory 194544 kb
Host smart-69943b6b-642b-4b20-bf7c-16b7115829c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602218183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.602218183
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4158388624
Short name T1296
Test name
Test status
Simulation time 97972144 ps
CPU time 0.72 seconds
Started Aug 16 04:56:03 PM PDT 24
Finished Aug 16 04:56:03 PM PDT 24
Peak memory 197304 kb
Host smart-9682a0bf-c98f-44dd-ae00-4c50a193833f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158388624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4158388624
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.974960351
Short name T1198
Test name
Test status
Simulation time 498062937 ps
CPU time 1.84 seconds
Started Aug 16 04:56:02 PM PDT 24
Finished Aug 16 04:56:04 PM PDT 24
Peak memory 200200 kb
Host smart-d6ddd269-3570-404f-b981-f9332bf137dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974960351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.974960351
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.701857181
Short name T1295
Test name
Test status
Simulation time 94797222 ps
CPU time 1.37 seconds
Started Aug 16 04:56:16 PM PDT 24
Finished Aug 16 04:56:18 PM PDT 24
Peak memory 199732 kb
Host smart-e45b4793-fb33-45aa-8b01-adb8abc00ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701857181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.701857181
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.596664611
Short name T1306
Test name
Test status
Simulation time 57139166 ps
CPU time 1.01 seconds
Started Aug 16 04:56:05 PM PDT 24
Finished Aug 16 04:56:06 PM PDT 24
Peak memory 199776 kb
Host smart-a8bab25a-97c2-4eed-9b89-c69ce3ccdbb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596664611 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.596664611
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2965312720
Short name T1252
Test name
Test status
Simulation time 28885276 ps
CPU time 0.65 seconds
Started Aug 16 04:56:32 PM PDT 24
Finished Aug 16 04:56:33 PM PDT 24
Peak memory 195436 kb
Host smart-ae0f96cd-e625-4d3f-98c7-fcc0e3cc5aa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965312720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2965312720
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.709563177
Short name T1308
Test name
Test status
Simulation time 176309952 ps
CPU time 0.61 seconds
Started Aug 16 04:56:06 PM PDT 24
Finished Aug 16 04:56:06 PM PDT 24
Peak memory 194536 kb
Host smart-ab03a58f-b456-45ab-a86b-27dac24367ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709563177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.709563177
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1613449609
Short name T1307
Test name
Test status
Simulation time 13672556 ps
CPU time 0.68 seconds
Started Aug 16 04:56:01 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 194964 kb
Host smart-bda559bb-bf7a-4bcc-8b7c-76e55e4ff1ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613449609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1613449609
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2232053034
Short name T1292
Test name
Test status
Simulation time 120552887 ps
CPU time 1.68 seconds
Started Aug 16 04:56:21 PM PDT 24
Finished Aug 16 04:56:23 PM PDT 24
Peak memory 200084 kb
Host smart-78db2b18-6185-4137-be2b-ad7fd55fac13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232053034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2232053034
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1457243988
Short name T1243
Test name
Test status
Simulation time 149332202 ps
CPU time 0.97 seconds
Started Aug 16 04:56:00 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 199980 kb
Host smart-6ae96857-53f1-48f8-8afb-ea701974c083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457243988 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1457243988
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.330348024
Short name T1270
Test name
Test status
Simulation time 15584677 ps
CPU time 0.57 seconds
Started Aug 16 04:56:14 PM PDT 24
Finished Aug 16 04:56:15 PM PDT 24
Peak memory 195444 kb
Host smart-b44d2c78-77a7-4095-8f92-1f0f06f8b07c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330348024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.330348024
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.143896402
Short name T1190
Test name
Test status
Simulation time 18095993 ps
CPU time 0.58 seconds
Started Aug 16 04:56:24 PM PDT 24
Finished Aug 16 04:56:25 PM PDT 24
Peak memory 194580 kb
Host smart-23ecd83a-eaa6-4bf0-bd63-95c7a76de862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143896402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.143896402
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1605512535
Short name T1249
Test name
Test status
Simulation time 29049151 ps
CPU time 0.63 seconds
Started Aug 16 04:56:03 PM PDT 24
Finished Aug 16 04:56:04 PM PDT 24
Peak memory 195812 kb
Host smart-cc5ad11b-1e35-4b5f-a32e-6f3f16a49e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605512535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1605512535
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1794310031
Short name T1264
Test name
Test status
Simulation time 309107170 ps
CPU time 2.51 seconds
Started Aug 16 04:56:05 PM PDT 24
Finished Aug 16 04:56:07 PM PDT 24
Peak memory 200092 kb
Host smart-494ed162-718a-4880-94e7-acdd6fe5d900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794310031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1794310031
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3737086776
Short name T1251
Test name
Test status
Simulation time 54780565 ps
CPU time 1.01 seconds
Started Aug 16 04:56:17 PM PDT 24
Finished Aug 16 04:56:18 PM PDT 24
Peak memory 199168 kb
Host smart-3008cf38-dcb3-42f5-9227-82230d5bb544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737086776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3737086776
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3312216810
Short name T1290
Test name
Test status
Simulation time 17057924 ps
CPU time 0.91 seconds
Started Aug 16 04:56:01 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 199928 kb
Host smart-49bb7863-0eff-4706-802e-6d7cdf3140e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312216810 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3312216810
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1273979595
Short name T58
Test name
Test status
Simulation time 15345299 ps
CPU time 0.6 seconds
Started Aug 16 04:55:59 PM PDT 24
Finished Aug 16 04:56:00 PM PDT 24
Peak memory 195564 kb
Host smart-e2ed0593-250b-4c31-bafe-808b56ae89df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273979595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1273979595
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1532835020
Short name T1240
Test name
Test status
Simulation time 29625275 ps
CPU time 0.59 seconds
Started Aug 16 04:56:17 PM PDT 24
Finished Aug 16 04:56:18 PM PDT 24
Peak memory 194544 kb
Host smart-c7f15366-30b1-4067-99c8-ccec9d38f93e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532835020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1532835020
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1296235062
Short name T1254
Test name
Test status
Simulation time 22416170 ps
CPU time 0.65 seconds
Started Aug 16 04:56:29 PM PDT 24
Finished Aug 16 04:56:30 PM PDT 24
Peak memory 196732 kb
Host smart-42a50988-d659-4992-8a69-c3ede5fd4004
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296235062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1296235062
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.255885583
Short name T1210
Test name
Test status
Simulation time 455775111 ps
CPU time 2.43 seconds
Started Aug 16 04:56:04 PM PDT 24
Finished Aug 16 04:56:06 PM PDT 24
Peak memory 200280 kb
Host smart-17d8416b-3614-4cdd-a4f7-de532fedbf55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255885583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.255885583
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2970370035
Short name T1221
Test name
Test status
Simulation time 347138542 ps
CPU time 0.85 seconds
Started Aug 16 04:56:16 PM PDT 24
Finished Aug 16 04:56:17 PM PDT 24
Peak memory 199844 kb
Host smart-73da4da8-6b72-49d6-825f-854a86f49515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970370035 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2970370035
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3635117707
Short name T60
Test name
Test status
Simulation time 15102976 ps
CPU time 0.64 seconds
Started Aug 16 04:56:01 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 195468 kb
Host smart-5dfc6437-f3ba-4398-893d-b26dec8f0da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635117707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3635117707
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3450188336
Short name T1274
Test name
Test status
Simulation time 14545314 ps
CPU time 0.56 seconds
Started Aug 16 04:56:03 PM PDT 24
Finished Aug 16 04:56:04 PM PDT 24
Peak memory 194620 kb
Host smart-9d70512e-96e1-4150-85ba-8c398f2b1fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450188336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3450188336
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3990433214
Short name T1303
Test name
Test status
Simulation time 20320357 ps
CPU time 0.7 seconds
Started Aug 16 04:56:16 PM PDT 24
Finished Aug 16 04:56:17 PM PDT 24
Peak memory 196076 kb
Host smart-fa5d15c7-6734-49b3-8485-f1cfd31c876f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990433214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3990433214
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2493629276
Short name T1236
Test name
Test status
Simulation time 442629659 ps
CPU time 2.5 seconds
Started Aug 16 04:56:01 PM PDT 24
Finished Aug 16 04:56:03 PM PDT 24
Peak memory 200196 kb
Host smart-821a9689-76f8-4096-b889-ba53f24062f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493629276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2493629276
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1602946435
Short name T103
Test name
Test status
Simulation time 270321674 ps
CPU time 1.32 seconds
Started Aug 16 04:56:06 PM PDT 24
Finished Aug 16 04:56:07 PM PDT 24
Peak memory 199544 kb
Host smart-bd5c4653-d60c-41de-9d44-e9c62a1f1155
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602946435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1602946435
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.385623027
Short name T1282
Test name
Test status
Simulation time 76004552 ps
CPU time 0.91 seconds
Started Aug 16 04:56:08 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 200008 kb
Host smart-c932d5b3-c327-4327-8155-72ec6c90a7d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385623027 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.385623027
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3603548669
Short name T1291
Test name
Test status
Simulation time 44314690 ps
CPU time 0.58 seconds
Started Aug 16 04:56:18 PM PDT 24
Finished Aug 16 04:56:19 PM PDT 24
Peak memory 195500 kb
Host smart-6bcb8d2d-e499-4b7d-96f5-a766804fb841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603548669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3603548669
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3860889531
Short name T1217
Test name
Test status
Simulation time 14256300 ps
CPU time 0.54 seconds
Started Aug 16 04:56:32 PM PDT 24
Finished Aug 16 04:56:33 PM PDT 24
Peak memory 194552 kb
Host smart-80221884-1e59-44cd-8445-1811d5ff7df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860889531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3860889531
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1965415578
Short name T64
Test name
Test status
Simulation time 114574615 ps
CPU time 0.84 seconds
Started Aug 16 04:56:24 PM PDT 24
Finished Aug 16 04:56:24 PM PDT 24
Peak memory 197240 kb
Host smart-3697360e-9457-4021-a62c-e8f1f442b325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965415578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1965415578
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.4244963046
Short name T1212
Test name
Test status
Simulation time 382530604 ps
CPU time 2.09 seconds
Started Aug 16 04:56:07 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 200204 kb
Host smart-495b2a73-370d-49e1-a83e-c6e05f072733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244963046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.4244963046
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1517381433
Short name T104
Test name
Test status
Simulation time 90346675 ps
CPU time 1.31 seconds
Started Aug 16 04:56:27 PM PDT 24
Finished Aug 16 04:56:29 PM PDT 24
Peak memory 199580 kb
Host smart-6ee39dea-4d77-4d72-a0f4-a4577efbe999
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517381433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1517381433
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.594987188
Short name T1255
Test name
Test status
Simulation time 15021718 ps
CPU time 0.68 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 194860 kb
Host smart-50ff6b26-0266-41bf-8750-524397e5e11f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594987188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.594987188
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.188638506
Short name T1287
Test name
Test status
Simulation time 60655906 ps
CPU time 2.23 seconds
Started Aug 16 04:55:51 PM PDT 24
Finished Aug 16 04:55:54 PM PDT 24
Peak memory 198224 kb
Host smart-d0e86bd1-c1ef-4790-9c23-376efe85b40b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188638506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.188638506
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2711167840
Short name T1224
Test name
Test status
Simulation time 20426921 ps
CPU time 0.59 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 195492 kb
Host smart-d709f6f4-398e-45ad-81d8-6baac72b3899
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711167840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2711167840
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3477026529
Short name T1199
Test name
Test status
Simulation time 83045108 ps
CPU time 0.82 seconds
Started Aug 16 04:55:51 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 199024 kb
Host smart-778ffdb2-9c11-4c5b-889a-42ab4dbbd9b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477026529 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3477026529
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1089591597
Short name T1231
Test name
Test status
Simulation time 39844038 ps
CPU time 0.57 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:49 PM PDT 24
Peak memory 195496 kb
Host smart-d385fc22-0b46-4bf6-aa39-1bb7e83faf83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089591597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1089591597
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.379507977
Short name T1260
Test name
Test status
Simulation time 23723628 ps
CPU time 0.58 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:49 PM PDT 24
Peak memory 194572 kb
Host smart-f2e961bd-490f-4b38-92fe-fdcd2e5d9b20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379507977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.379507977
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3494548084
Short name T1284
Test name
Test status
Simulation time 60099480 ps
CPU time 0.74 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 196168 kb
Host smart-f403e18c-63f4-4760-8fcc-0a42a72257ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494548084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3494548084
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.326161929
Short name T1214
Test name
Test status
Simulation time 58295708 ps
CPU time 1.34 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:49 PM PDT 24
Peak memory 200160 kb
Host smart-3fda730d-245e-4867-895e-6b97d2f5a7f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326161929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.326161929
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3369406320
Short name T1271
Test name
Test status
Simulation time 71443918 ps
CPU time 1.18 seconds
Started Aug 16 04:55:51 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 199364 kb
Host smart-98451efa-9669-4ddd-b062-37cc61d02a54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369406320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3369406320
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.166259649
Short name T1314
Test name
Test status
Simulation time 12150079 ps
CPU time 0.58 seconds
Started Aug 16 04:56:09 PM PDT 24
Finished Aug 16 04:56:10 PM PDT 24
Peak memory 194444 kb
Host smart-45818bda-1df8-454e-a535-b407b7b0b7d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166259649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.166259649
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4207867342
Short name T1234
Test name
Test status
Simulation time 24185735 ps
CPU time 0.59 seconds
Started Aug 16 04:56:25 PM PDT 24
Finished Aug 16 04:56:25 PM PDT 24
Peak memory 194540 kb
Host smart-d81610a6-9bc1-415c-9397-fd6ed3606ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207867342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4207867342
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2867916145
Short name T1230
Test name
Test status
Simulation time 11880105 ps
CPU time 0.55 seconds
Started Aug 16 04:56:14 PM PDT 24
Finished Aug 16 04:56:14 PM PDT 24
Peak memory 194448 kb
Host smart-ccc32e55-36c4-4ebb-b806-e9829b73b6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867916145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2867916145
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2576553685
Short name T1237
Test name
Test status
Simulation time 45051380 ps
CPU time 0.58 seconds
Started Aug 16 04:56:20 PM PDT 24
Finished Aug 16 04:56:21 PM PDT 24
Peak memory 194428 kb
Host smart-e56ee79a-7943-4068-a486-fd9642cc02ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576553685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2576553685
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1426861500
Short name T1222
Test name
Test status
Simulation time 29978484 ps
CPU time 0.57 seconds
Started Aug 16 04:56:08 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 194604 kb
Host smart-d9e29728-24ea-4601-ad82-ddc3c76f1e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426861500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1426861500
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3066055280
Short name T1244
Test name
Test status
Simulation time 25621126 ps
CPU time 0.58 seconds
Started Aug 16 04:56:16 PM PDT 24
Finished Aug 16 04:56:17 PM PDT 24
Peak memory 194540 kb
Host smart-81746a53-399b-430d-89ff-ab56ef8b2ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066055280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3066055280
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.336748044
Short name T1226
Test name
Test status
Simulation time 25650023 ps
CPU time 0.57 seconds
Started Aug 16 04:56:08 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 194548 kb
Host smart-bc30089f-a3e2-4475-a748-f8b1b5f2299e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336748044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.336748044
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1169717155
Short name T1250
Test name
Test status
Simulation time 12262322 ps
CPU time 0.57 seconds
Started Aug 16 04:56:09 PM PDT 24
Finished Aug 16 04:56:10 PM PDT 24
Peak memory 194528 kb
Host smart-330302ad-09a6-4b10-af97-f5d87419f4f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169717155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1169717155
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.4109793237
Short name T1233
Test name
Test status
Simulation time 10855206 ps
CPU time 0.59 seconds
Started Aug 16 04:56:20 PM PDT 24
Finished Aug 16 04:56:21 PM PDT 24
Peak memory 194552 kb
Host smart-60ba0028-a604-47bb-92e7-d25813b538e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109793237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4109793237
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2682302450
Short name T1203
Test name
Test status
Simulation time 14499491 ps
CPU time 0.62 seconds
Started Aug 16 04:56:07 PM PDT 24
Finished Aug 16 04:56:08 PM PDT 24
Peak memory 194488 kb
Host smart-ec1773ed-dd97-4a71-8fa5-b1561a93571c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682302450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2682302450
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1729964591
Short name T56
Test name
Test status
Simulation time 32904930 ps
CPU time 0.8 seconds
Started Aug 16 04:55:51 PM PDT 24
Finished Aug 16 04:55:53 PM PDT 24
Peak memory 196352 kb
Host smart-d22c0e11-95a2-4bc2-9aca-dc6497c4df79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729964591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1729964591
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3225757707
Short name T1281
Test name
Test status
Simulation time 171801790 ps
CPU time 2.35 seconds
Started Aug 16 04:55:52 PM PDT 24
Finished Aug 16 04:55:55 PM PDT 24
Peak memory 197876 kb
Host smart-0f969823-825e-4dde-9f1e-6dd7461be8ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225757707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3225757707
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1914093551
Short name T1206
Test name
Test status
Simulation time 30480848 ps
CPU time 0.56 seconds
Started Aug 16 04:55:46 PM PDT 24
Finished Aug 16 04:55:47 PM PDT 24
Peak memory 195468 kb
Host smart-4b31d7b5-b122-456b-8d21-9f710f17a204
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914093551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1914093551
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.153388787
Short name T1202
Test name
Test status
Simulation time 114736635 ps
CPU time 1.07 seconds
Started Aug 16 04:55:51 PM PDT 24
Finished Aug 16 04:55:53 PM PDT 24
Peak memory 200208 kb
Host smart-ef58da2f-2503-4e95-b63c-926dc89625b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153388787 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.153388787
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.664620459
Short name T61
Test name
Test status
Simulation time 11982339 ps
CPU time 0.6 seconds
Started Aug 16 04:55:52 PM PDT 24
Finished Aug 16 04:55:53 PM PDT 24
Peak memory 195584 kb
Host smart-49829d50-41db-45f7-986f-38bf8eb68730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664620459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.664620459
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2612933689
Short name T1288
Test name
Test status
Simulation time 46815225 ps
CPU time 0.57 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 194536 kb
Host smart-6490df22-ea9f-44f0-be82-74ec7718c181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612933689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2612933689
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3267354932
Short name T1247
Test name
Test status
Simulation time 21444225 ps
CPU time 0.68 seconds
Started Aug 16 04:55:51 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 195724 kb
Host smart-62ee59a3-dc25-4048-87b1-8335afe3da75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267354932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3267354932
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2756810350
Short name T1265
Test name
Test status
Simulation time 101230384 ps
CPU time 2.11 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 200080 kb
Host smart-f488f981-d115-4fb6-99bf-e46a8817d2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756810350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2756810350
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2246584212
Short name T73
Test name
Test status
Simulation time 95893871 ps
CPU time 0.99 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 199204 kb
Host smart-11148fde-d20b-4248-98de-1444c66bc205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246584212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2246584212
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1204279994
Short name T1204
Test name
Test status
Simulation time 12732724 ps
CPU time 0.58 seconds
Started Aug 16 04:56:10 PM PDT 24
Finished Aug 16 04:56:11 PM PDT 24
Peak memory 194528 kb
Host smart-571b4dcf-45bf-4cfa-a817-52e746525bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204279994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1204279994
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.243294765
Short name T1192
Test name
Test status
Simulation time 141283189 ps
CPU time 0.59 seconds
Started Aug 16 04:56:07 PM PDT 24
Finished Aug 16 04:56:08 PM PDT 24
Peak memory 194548 kb
Host smart-2255f65e-60c3-4fbb-856e-4b1cbdaea599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243294765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.243294765
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4124248977
Short name T1309
Test name
Test status
Simulation time 25873455 ps
CPU time 0.55 seconds
Started Aug 16 04:56:18 PM PDT 24
Finished Aug 16 04:56:19 PM PDT 24
Peak memory 194468 kb
Host smart-6f6c32e9-ecac-4b8a-a5c0-531cee7dc9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124248977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4124248977
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.549879412
Short name T1312
Test name
Test status
Simulation time 113831870 ps
CPU time 0.59 seconds
Started Aug 16 04:56:19 PM PDT 24
Finished Aug 16 04:56:20 PM PDT 24
Peak memory 194540 kb
Host smart-ed139a6f-94d6-4357-9914-0f19a45cd9f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549879412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.549879412
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2018394245
Short name T1211
Test name
Test status
Simulation time 24096350 ps
CPU time 0.6 seconds
Started Aug 16 04:56:08 PM PDT 24
Finished Aug 16 04:56:08 PM PDT 24
Peak memory 194508 kb
Host smart-74aff200-819e-473e-9617-ed12cee7d2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018394245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2018394245
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2972043149
Short name T1257
Test name
Test status
Simulation time 49130590 ps
CPU time 0.6 seconds
Started Aug 16 04:56:07 PM PDT 24
Finished Aug 16 04:56:08 PM PDT 24
Peak memory 194524 kb
Host smart-02a058be-a9da-4b15-9447-bc25e017f648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972043149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2972043149
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.4222299600
Short name T1228
Test name
Test status
Simulation time 14589553 ps
CPU time 0.6 seconds
Started Aug 16 04:56:08 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 194552 kb
Host smart-c7ed6c07-4c2f-4d74-a5e1-2d60f4de5f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222299600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4222299600
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3128135299
Short name T1316
Test name
Test status
Simulation time 64064217 ps
CPU time 0.57 seconds
Started Aug 16 04:56:26 PM PDT 24
Finished Aug 16 04:56:27 PM PDT 24
Peak memory 194540 kb
Host smart-424deedb-a55d-4954-8557-d0a272bf7613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128135299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3128135299
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.625361039
Short name T1187
Test name
Test status
Simulation time 50915484 ps
CPU time 0.57 seconds
Started Aug 16 04:56:08 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 194548 kb
Host smart-055d81ce-20a3-4afc-800b-8ba026957ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625361039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.625361039
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2094824437
Short name T1208
Test name
Test status
Simulation time 49764755 ps
CPU time 0.6 seconds
Started Aug 16 04:56:07 PM PDT 24
Finished Aug 16 04:56:08 PM PDT 24
Peak memory 194592 kb
Host smart-e636e132-549e-4e98-8d27-a98051b9cb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094824437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2094824437
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2439402519
Short name T1196
Test name
Test status
Simulation time 16122170 ps
CPU time 0.63 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:49 PM PDT 24
Peak memory 194948 kb
Host smart-3c6873e3-9d0b-4b49-a23e-c67146b92489
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439402519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2439402519
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3604742252
Short name T1186
Test name
Test status
Simulation time 217708549 ps
CPU time 1.6 seconds
Started Aug 16 04:55:46 PM PDT 24
Finished Aug 16 04:55:48 PM PDT 24
Peak memory 197900 kb
Host smart-a68d0d89-0518-45af-86b8-568d5eb37a07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604742252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3604742252
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3251300698
Short name T1205
Test name
Test status
Simulation time 34095707 ps
CPU time 0.61 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 195432 kb
Host smart-78ec7eca-7d54-42e8-9d29-fdc50a20763a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251300698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3251300698
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1237445447
Short name T1278
Test name
Test status
Simulation time 52926072 ps
CPU time 1.4 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 200188 kb
Host smart-632fdb53-7c49-4475-a392-64746aa2422d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237445447 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1237445447
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3107067908
Short name T52
Test name
Test status
Simulation time 22783484 ps
CPU time 0.63 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 195540 kb
Host smart-1fa4b62f-2107-4fe7-8cf2-51eba537d9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107067908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3107067908
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.792944857
Short name T1275
Test name
Test status
Simulation time 13351809 ps
CPU time 0.57 seconds
Started Aug 16 04:55:51 PM PDT 24
Finished Aug 16 04:55:52 PM PDT 24
Peak memory 194536 kb
Host smart-d77540d1-48f4-4983-a99b-47475870b510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792944857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.792944857
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3190457126
Short name T65
Test name
Test status
Simulation time 82839518 ps
CPU time 0.68 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 195948 kb
Host smart-723b656d-acac-4ece-9357-bc54bbcd3842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190457126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3190457126
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1332148978
Short name T1201
Test name
Test status
Simulation time 70841823 ps
CPU time 1.64 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 200216 kb
Host smart-e7948e63-e0ba-4e23-af25-89d0e43932ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332148978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1332148978
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4052973207
Short name T1279
Test name
Test status
Simulation time 277156391 ps
CPU time 0.99 seconds
Started Aug 16 04:55:51 PM PDT 24
Finished Aug 16 04:55:53 PM PDT 24
Peak memory 199480 kb
Host smart-00d77baa-b862-49ef-b987-22efcb1fe4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052973207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4052973207
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.4017788402
Short name T1225
Test name
Test status
Simulation time 27011626 ps
CPU time 0.57 seconds
Started Aug 16 04:56:10 PM PDT 24
Finished Aug 16 04:56:11 PM PDT 24
Peak memory 194560 kb
Host smart-3f731572-dde8-44de-8c6e-ff39053aaebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017788402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.4017788402
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.828436958
Short name T1227
Test name
Test status
Simulation time 22531499 ps
CPU time 0.57 seconds
Started Aug 16 04:56:10 PM PDT 24
Finished Aug 16 04:56:10 PM PDT 24
Peak memory 194548 kb
Host smart-f41685fe-7a46-4292-8d49-e48f9c6c6d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828436958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.828436958
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.434049071
Short name T1256
Test name
Test status
Simulation time 23214751 ps
CPU time 0.59 seconds
Started Aug 16 04:56:17 PM PDT 24
Finished Aug 16 04:56:17 PM PDT 24
Peak memory 194624 kb
Host smart-d8a9a5b4-a01c-4921-a87f-5f3c822a652f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434049071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.434049071
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3337496546
Short name T1246
Test name
Test status
Simulation time 98769603 ps
CPU time 0.58 seconds
Started Aug 16 04:56:09 PM PDT 24
Finished Aug 16 04:56:09 PM PDT 24
Peak memory 194548 kb
Host smart-a22d8590-3342-4ad8-925c-9970813fe4d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337496546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3337496546
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1730252479
Short name T1181
Test name
Test status
Simulation time 37203557 ps
CPU time 0.57 seconds
Started Aug 16 04:56:10 PM PDT 24
Finished Aug 16 04:56:11 PM PDT 24
Peak memory 194536 kb
Host smart-b22bffee-abdc-44cb-8449-71b883b5145c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730252479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1730252479
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3103232820
Short name T1184
Test name
Test status
Simulation time 41430215 ps
CPU time 0.55 seconds
Started Aug 16 04:56:24 PM PDT 24
Finished Aug 16 04:56:24 PM PDT 24
Peak memory 194468 kb
Host smart-f5d3cfe7-5a23-4e34-a201-71c80acd02cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103232820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3103232820
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.4192728383
Short name T1280
Test name
Test status
Simulation time 22427711 ps
CPU time 0.59 seconds
Started Aug 16 04:56:09 PM PDT 24
Finished Aug 16 04:56:10 PM PDT 24
Peak memory 194512 kb
Host smart-80ef47c4-9469-41d8-8d8b-f6ea5350100d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192728383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4192728383
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2765141313
Short name T1299
Test name
Test status
Simulation time 11871707 ps
CPU time 0.62 seconds
Started Aug 16 04:56:28 PM PDT 24
Finished Aug 16 04:56:29 PM PDT 24
Peak memory 194464 kb
Host smart-d17b1f3e-f4d8-4add-b1ec-d2036678f202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765141313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2765141313
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1396282790
Short name T1180
Test name
Test status
Simulation time 103626615 ps
CPU time 0.61 seconds
Started Aug 16 04:56:10 PM PDT 24
Finished Aug 16 04:56:10 PM PDT 24
Peak memory 194588 kb
Host smart-de474d87-2cdc-473c-9815-617815b8b966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396282790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1396282790
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3410939484
Short name T1209
Test name
Test status
Simulation time 48982937 ps
CPU time 0.57 seconds
Started Aug 16 04:56:28 PM PDT 24
Finished Aug 16 04:56:28 PM PDT 24
Peak memory 194540 kb
Host smart-1ebabc34-1510-4b85-885f-1f9d81d25633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410939484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3410939484
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.758605858
Short name T1191
Test name
Test status
Simulation time 119426218 ps
CPU time 0.9 seconds
Started Aug 16 04:55:46 PM PDT 24
Finished Aug 16 04:55:47 PM PDT 24
Peak memory 199984 kb
Host smart-646c8e46-f8bf-4bd8-9f10-3aa5b0844bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758605858 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.758605858
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3227900990
Short name T59
Test name
Test status
Simulation time 26830850 ps
CPU time 0.61 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 195652 kb
Host smart-1e4c220d-90d6-4555-b503-f48d6a8610d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227900990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3227900990
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3797523944
Short name T1262
Test name
Test status
Simulation time 40213693 ps
CPU time 0.54 seconds
Started Aug 16 04:55:50 PM PDT 24
Finished Aug 16 04:55:51 PM PDT 24
Peak memory 194476 kb
Host smart-bbcac4e9-dd87-4722-93f4-39a9ddc753b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797523944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3797523944
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4093487889
Short name T1302
Test name
Test status
Simulation time 21794459 ps
CPU time 0.66 seconds
Started Aug 16 04:55:46 PM PDT 24
Finished Aug 16 04:55:47 PM PDT 24
Peak memory 195900 kb
Host smart-34f5f6c6-f2c7-4f9a-b7e2-e0066cb3a3aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093487889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4093487889
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4285456508
Short name T1213
Test name
Test status
Simulation time 329773265 ps
CPU time 1.42 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 200244 kb
Host smart-bcd790f5-be5c-4c0b-9989-b2c855dd2f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285456508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4285456508
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3215604209
Short name T70
Test name
Test status
Simulation time 52904825 ps
CPU time 1.01 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 199208 kb
Host smart-1fac129b-94e6-4095-ad13-72b89f77c31c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215604209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3215604209
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2348234260
Short name T1248
Test name
Test status
Simulation time 53849306 ps
CPU time 0.87 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 199876 kb
Host smart-e295a377-29f4-4d9d-adaf-1bbaa3df535b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348234260 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2348234260
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.172890909
Short name T54
Test name
Test status
Simulation time 18054633 ps
CPU time 0.66 seconds
Started Aug 16 04:55:49 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 195484 kb
Host smart-4e07166d-7d80-4b82-8393-6d6391a0b430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172890909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.172890909
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3476979428
Short name T1267
Test name
Test status
Simulation time 29722678 ps
CPU time 0.58 seconds
Started Aug 16 04:55:52 PM PDT 24
Finished Aug 16 04:55:53 PM PDT 24
Peak memory 194544 kb
Host smart-b01678d3-9b72-419c-8c55-25bf9b7a7b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476979428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3476979428
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2293540968
Short name T1293
Test name
Test status
Simulation time 70952271 ps
CPU time 0.66 seconds
Started Aug 16 04:55:55 PM PDT 24
Finished Aug 16 04:55:56 PM PDT 24
Peak memory 194892 kb
Host smart-3c5e2158-2a2f-4ff0-a460-1ac5139ab642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293540968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2293540968
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3059048816
Short name T1229
Test name
Test status
Simulation time 34674842 ps
CPU time 0.88 seconds
Started Aug 16 04:55:52 PM PDT 24
Finished Aug 16 04:55:53 PM PDT 24
Peak memory 199316 kb
Host smart-9fd43ed8-2c08-4dd3-974e-383d8dd7de28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059048816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3059048816
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4285127068
Short name T1304
Test name
Test status
Simulation time 354829909 ps
CPU time 1.35 seconds
Started Aug 16 04:55:52 PM PDT 24
Finished Aug 16 04:55:53 PM PDT 24
Peak memory 199536 kb
Host smart-9b8bd113-ff7c-4e66-a7cd-2ac390ee9381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285127068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4285127068
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2888175229
Short name T1197
Test name
Test status
Simulation time 184821280 ps
CPU time 0.98 seconds
Started Aug 16 04:56:12 PM PDT 24
Finished Aug 16 04:56:13 PM PDT 24
Peak memory 199976 kb
Host smart-ded65a0e-3db2-405f-b312-13035650f27c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888175229 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2888175229
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3252235269
Short name T1219
Test name
Test status
Simulation time 71467996 ps
CPU time 0.58 seconds
Started Aug 16 04:55:58 PM PDT 24
Finished Aug 16 04:55:58 PM PDT 24
Peak memory 195492 kb
Host smart-f3fd176d-cd5d-48d3-b8ee-395ff21d3a7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252235269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3252235269
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2548686165
Short name T1294
Test name
Test status
Simulation time 14653271 ps
CPU time 0.58 seconds
Started Aug 16 04:56:01 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 194448 kb
Host smart-7b7ad052-fe46-480d-98af-0cb2ee5b4017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548686165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2548686165
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1417439716
Short name T1277
Test name
Test status
Simulation time 20100880 ps
CPU time 0.65 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 194692 kb
Host smart-d0981cda-0a0c-452e-91a7-479fd7b13ac8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417439716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1417439716
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1384607292
Short name T1193
Test name
Test status
Simulation time 79778102 ps
CPU time 2.18 seconds
Started Aug 16 04:55:48 PM PDT 24
Finished Aug 16 04:55:50 PM PDT 24
Peak memory 200236 kb
Host smart-2860fe2d-5989-485b-97b6-947dc27fea6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384607292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1384607292
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.820729568
Short name T1242
Test name
Test status
Simulation time 343789034 ps
CPU time 1.32 seconds
Started Aug 16 04:56:02 PM PDT 24
Finished Aug 16 04:56:03 PM PDT 24
Peak memory 199348 kb
Host smart-99487c1f-f64f-4456-8a60-4280a5dc9a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820729568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.820729568
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1436336467
Short name T1305
Test name
Test status
Simulation time 298556390 ps
CPU time 0.84 seconds
Started Aug 16 04:55:54 PM PDT 24
Finished Aug 16 04:55:55 PM PDT 24
Peak memory 199976 kb
Host smart-745b418b-1804-475b-bbcb-cece3da88114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436336467 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1436336467
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1037783453
Short name T57
Test name
Test status
Simulation time 24199099 ps
CPU time 0.57 seconds
Started Aug 16 04:56:05 PM PDT 24
Finished Aug 16 04:56:06 PM PDT 24
Peak memory 195516 kb
Host smart-898cc624-7428-43db-b8a7-c182c0189b05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037783453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1037783453
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.34943155
Short name T1207
Test name
Test status
Simulation time 51676664 ps
CPU time 0.58 seconds
Started Aug 16 04:56:18 PM PDT 24
Finished Aug 16 04:56:19 PM PDT 24
Peak memory 194556 kb
Host smart-98ffc3b7-587c-457b-9533-26c29ca9ea09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34943155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.34943155
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1502627718
Short name T1311
Test name
Test status
Simulation time 27100655 ps
CPU time 0.69 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 195972 kb
Host smart-8a9928a6-2024-415f-a006-db19e41a4e8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502627718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1502627718
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2079653791
Short name T1218
Test name
Test status
Simulation time 314322930 ps
CPU time 1.97 seconds
Started Aug 16 04:55:57 PM PDT 24
Finished Aug 16 04:55:59 PM PDT 24
Peak memory 200212 kb
Host smart-c3da7ffc-14e9-446c-978b-18c60555e821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079653791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2079653791
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3100315795
Short name T1216
Test name
Test status
Simulation time 50463247 ps
CPU time 0.93 seconds
Started Aug 16 04:55:54 PM PDT 24
Finished Aug 16 04:55:56 PM PDT 24
Peak memory 199068 kb
Host smart-a4911332-413e-42ba-831d-50afbd819916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100315795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3100315795
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.113560680
Short name T1238
Test name
Test status
Simulation time 23605514 ps
CPU time 0.72 seconds
Started Aug 16 04:56:01 PM PDT 24
Finished Aug 16 04:56:02 PM PDT 24
Peak memory 198824 kb
Host smart-b55917d8-b9a9-4c6b-a8f0-8ad56da112a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113560680 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.113560680
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1796662941
Short name T1253
Test name
Test status
Simulation time 59206909 ps
CPU time 0.62 seconds
Started Aug 16 04:55:59 PM PDT 24
Finished Aug 16 04:56:00 PM PDT 24
Peak memory 195544 kb
Host smart-50fc887c-bb2f-4fc9-a736-565f5f592572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796662941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1796662941
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1051471047
Short name T1200
Test name
Test status
Simulation time 14464265 ps
CPU time 0.59 seconds
Started Aug 16 04:55:59 PM PDT 24
Finished Aug 16 04:56:00 PM PDT 24
Peak memory 194444 kb
Host smart-3cceb8ff-6f4f-4d45-a098-f872dfd4f8f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051471047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1051471047
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1427743813
Short name T1318
Test name
Test status
Simulation time 29843002 ps
CPU time 0.74 seconds
Started Aug 16 04:56:00 PM PDT 24
Finished Aug 16 04:56:01 PM PDT 24
Peak memory 197144 kb
Host smart-f8e59beb-9e85-4bca-9486-3afb080838be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427743813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1427743813
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3059169577
Short name T1220
Test name
Test status
Simulation time 160431492 ps
CPU time 2.67 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:59 PM PDT 24
Peak memory 200200 kb
Host smart-416b3e9d-0f42-4cec-9607-eaf50a43196e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059169577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3059169577
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2177891101
Short name T72
Test name
Test status
Simulation time 146238912 ps
CPU time 0.95 seconds
Started Aug 16 04:55:56 PM PDT 24
Finished Aug 16 04:55:57 PM PDT 24
Peak memory 198980 kb
Host smart-9930871d-b57f-4761-bfb1-56653102bda1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177891101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2177891101
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2326199107
Short name T571
Test name
Test status
Simulation time 45274273 ps
CPU time 0.56 seconds
Started Aug 16 05:01:56 PM PDT 24
Finished Aug 16 05:01:57 PM PDT 24
Peak memory 196132 kb
Host smart-4cfed5d9-f205-428f-bc42-6329e9b05d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326199107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2326199107
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.112253153
Short name T901
Test name
Test status
Simulation time 13789624665 ps
CPU time 20.92 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:02:12 PM PDT 24
Peak memory 200856 kb
Host smart-5f34191a-7737-4485-a8fa-569ee70a5a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112253153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.112253153
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1911401601
Short name T161
Test name
Test status
Simulation time 119686546185 ps
CPU time 48.1 seconds
Started Aug 16 05:01:52 PM PDT 24
Finished Aug 16 05:02:40 PM PDT 24
Peak memory 200860 kb
Host smart-75353054-682a-46ca-aede-cb12ef3af1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911401601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1911401601
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3140310733
Short name T214
Test name
Test status
Simulation time 91563995559 ps
CPU time 54.35 seconds
Started Aug 16 05:01:50 PM PDT 24
Finished Aug 16 05:02:45 PM PDT 24
Peak memory 200880 kb
Host smart-6583e25e-591f-4858-b778-2d725a555a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140310733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3140310733
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.174436535
Short name T755
Test name
Test status
Simulation time 120003328991 ps
CPU time 34.25 seconds
Started Aug 16 05:01:57 PM PDT 24
Finished Aug 16 05:02:31 PM PDT 24
Peak memory 200912 kb
Host smart-ff1eaa46-25c0-4b60-9c81-5631be9310a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174436535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.174436535
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.821423684
Short name T542
Test name
Test status
Simulation time 55118051805 ps
CPU time 158.79 seconds
Started Aug 16 05:01:53 PM PDT 24
Finished Aug 16 05:04:32 PM PDT 24
Peak memory 200892 kb
Host smart-02c39247-7528-46f4-b0d9-c953afec5743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821423684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.821423684
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2648122098
Short name T420
Test name
Test status
Simulation time 1730208877 ps
CPU time 2.17 seconds
Started Aug 16 05:01:52 PM PDT 24
Finished Aug 16 05:01:54 PM PDT 24
Peak memory 198116 kb
Host smart-a9f19629-1ac8-4547-a56d-5df90e5b144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648122098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2648122098
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.532951709
Short name T456
Test name
Test status
Simulation time 9971832547 ps
CPU time 129.71 seconds
Started Aug 16 05:01:49 PM PDT 24
Finished Aug 16 05:03:59 PM PDT 24
Peak memory 200892 kb
Host smart-fb2c73bd-2394-46e5-b8c0-c3e2e6a3953b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532951709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.532951709
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.146306105
Short name T496
Test name
Test status
Simulation time 2576709979 ps
CPU time 4.49 seconds
Started Aug 16 05:01:57 PM PDT 24
Finished Aug 16 05:02:02 PM PDT 24
Peak memory 199944 kb
Host smart-6d3b5aec-23d9-4421-9638-8bc76463c27d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146306105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.146306105
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.158504682
Short name T592
Test name
Test status
Simulation time 1577645493 ps
CPU time 2.87 seconds
Started Aug 16 05:01:56 PM PDT 24
Finished Aug 16 05:01:59 PM PDT 24
Peak memory 196304 kb
Host smart-76ffbc98-36e0-4cfa-b97c-d40764e89329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158504682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.158504682
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.2539279103
Short name T613
Test name
Test status
Simulation time 5433522143 ps
CPU time 22.93 seconds
Started Aug 16 05:02:16 PM PDT 24
Finished Aug 16 05:02:39 PM PDT 24
Peak memory 200848 kb
Host smart-7156d5fb-b3b3-4412-b536-d2b041bc9a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539279103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2539279103
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3365546355
Short name T943
Test name
Test status
Simulation time 309159574774 ps
CPU time 1642.2 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:29:13 PM PDT 24
Peak memory 200928 kb
Host smart-7f80463e-14d2-46ba-ae21-78e29e7ed234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365546355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3365546355
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3926966768
Short name T1147
Test name
Test status
Simulation time 2410589649 ps
CPU time 12.73 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:02:04 PM PDT 24
Peak memory 200964 kb
Host smart-03796141-af2b-4190-a423-4ee5f18b5b80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926966768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3926966768
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3738317405
Short name T697
Test name
Test status
Simulation time 1473249874 ps
CPU time 1.97 seconds
Started Aug 16 05:01:59 PM PDT 24
Finished Aug 16 05:02:01 PM PDT 24
Peak memory 199148 kb
Host smart-ad3a846e-4214-4f08-8ee6-64572c8bf4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738317405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3738317405
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2091757171
Short name T899
Test name
Test status
Simulation time 28234189284 ps
CPU time 10.13 seconds
Started Aug 16 05:01:57 PM PDT 24
Finished Aug 16 05:02:07 PM PDT 24
Peak memory 200780 kb
Host smart-25506a1c-346b-41e8-8f9d-9cf5ca21a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091757171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2091757171
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3257984047
Short name T894
Test name
Test status
Simulation time 14223565 ps
CPU time 0.55 seconds
Started Aug 16 05:01:52 PM PDT 24
Finished Aug 16 05:01:53 PM PDT 24
Peak memory 196176 kb
Host smart-d4cb6969-f449-476d-a651-4388c57324cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257984047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3257984047
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2929220968
Short name T44
Test name
Test status
Simulation time 102395052599 ps
CPU time 17.98 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:02:09 PM PDT 24
Peak memory 200904 kb
Host smart-de9c51d9-fdc9-4c08-a512-ad2d912187b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929220968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2929220968
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1446036906
Short name T720
Test name
Test status
Simulation time 248226259856 ps
CPU time 221.96 seconds
Started Aug 16 05:01:57 PM PDT 24
Finished Aug 16 05:05:39 PM PDT 24
Peak memory 200884 kb
Host smart-bb422fe5-2cb7-4a09-8793-bcc8e1e31256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446036906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1446036906
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2468794221
Short name T259
Test name
Test status
Simulation time 30155726188 ps
CPU time 12.05 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:02:03 PM PDT 24
Peak memory 200676 kb
Host smart-16e20124-5a5d-48cd-879a-6f3c7a92438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468794221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2468794221
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2203034730
Short name T614
Test name
Test status
Simulation time 233762798156 ps
CPU time 349.01 seconds
Started Aug 16 05:01:55 PM PDT 24
Finished Aug 16 05:07:44 PM PDT 24
Peak memory 198492 kb
Host smart-296f5051-52fa-4773-8651-f97ead4ebd75
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203034730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2203034730
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2554133760
Short name T1062
Test name
Test status
Simulation time 132078317864 ps
CPU time 762.5 seconds
Started Aug 16 05:01:59 PM PDT 24
Finished Aug 16 05:14:42 PM PDT 24
Peak memory 200844 kb
Host smart-81ecf075-f88d-4cd3-a2e3-65e64b06bcef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554133760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2554133760
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2484675383
Short name T1126
Test name
Test status
Simulation time 6056052229 ps
CPU time 10.86 seconds
Started Aug 16 05:01:52 PM PDT 24
Finished Aug 16 05:02:03 PM PDT 24
Peak memory 200552 kb
Host smart-0fbd09e6-a0dd-471a-82d6-039f128621fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484675383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2484675383
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3141848644
Short name T249
Test name
Test status
Simulation time 82930145677 ps
CPU time 141.27 seconds
Started Aug 16 05:01:54 PM PDT 24
Finished Aug 16 05:04:15 PM PDT 24
Peak memory 200432 kb
Host smart-3d10bf3a-e231-427c-af14-e6d56c949112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141848644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3141848644
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3629654805
Short name T1157
Test name
Test status
Simulation time 12297940223 ps
CPU time 516.96 seconds
Started Aug 16 05:01:49 PM PDT 24
Finished Aug 16 05:10:26 PM PDT 24
Peak memory 200908 kb
Host smart-17f5afcf-6cbf-460a-8096-8c2be001c1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629654805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3629654805
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.508192074
Short name T993
Test name
Test status
Simulation time 7010169344 ps
CPU time 62.67 seconds
Started Aug 16 05:01:56 PM PDT 24
Finished Aug 16 05:02:59 PM PDT 24
Peak memory 198980 kb
Host smart-cec31e63-18d0-4bb3-a5ad-dc3c28e927a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508192074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.508192074
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2300046295
Short name T549
Test name
Test status
Simulation time 77047330457 ps
CPU time 33.91 seconds
Started Aug 16 05:01:58 PM PDT 24
Finished Aug 16 05:02:32 PM PDT 24
Peak memory 200844 kb
Host smart-dd28c9eb-902b-47aa-be09-ee1f93bece23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300046295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2300046295
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3272914280
Short name T1037
Test name
Test status
Simulation time 4979552194 ps
CPU time 2.59 seconds
Started Aug 16 05:01:57 PM PDT 24
Finished Aug 16 05:02:00 PM PDT 24
Peak memory 197372 kb
Host smart-e3139094-0867-42ea-8db5-57fde40a6173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272914280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3272914280
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2361630470
Short name T33
Test name
Test status
Simulation time 124167614 ps
CPU time 0.78 seconds
Started Aug 16 05:01:52 PM PDT 24
Finished Aug 16 05:01:53 PM PDT 24
Peak memory 218780 kb
Host smart-fbc01530-38b7-4285-af95-c6de93d9ab67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361630470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2361630470
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3295671064
Short name T968
Test name
Test status
Simulation time 763800543 ps
CPU time 1.21 seconds
Started Aug 16 05:01:50 PM PDT 24
Finished Aug 16 05:01:51 PM PDT 24
Peak memory 200784 kb
Host smart-52f14b5a-e74b-49d7-ac1c-832ad95d3920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295671064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3295671064
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3617664120
Short name T115
Test name
Test status
Simulation time 172993229787 ps
CPU time 28.54 seconds
Started Aug 16 05:01:49 PM PDT 24
Finished Aug 16 05:02:18 PM PDT 24
Peak memory 200864 kb
Host smart-1df12512-0aa0-45fb-9d8d-8dd395a0d330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617664120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3617664120
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2015993667
Short name T772
Test name
Test status
Simulation time 10866465541 ps
CPU time 41.17 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:02:33 PM PDT 24
Peak memory 216512 kb
Host smart-069c5b2b-da5b-404a-91b9-dc44ddd03171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015993667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2015993667
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2859550448
Short name T687
Test name
Test status
Simulation time 969617262 ps
CPU time 2.16 seconds
Started Aug 16 05:01:50 PM PDT 24
Finished Aug 16 05:01:53 PM PDT 24
Peak memory 200560 kb
Host smart-ef56a423-74b2-423f-a262-5e2e34e16a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859550448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2859550448
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.445077705
Short name T1150
Test name
Test status
Simulation time 58724874115 ps
CPU time 73.29 seconds
Started Aug 16 05:01:52 PM PDT 24
Finished Aug 16 05:03:05 PM PDT 24
Peak memory 200840 kb
Host smart-d243c36e-b185-476d-804c-12017d1782f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445077705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.445077705
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.43361638
Short name T682
Test name
Test status
Simulation time 65594629 ps
CPU time 0.54 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:28 PM PDT 24
Peak memory 195472 kb
Host smart-aa44a004-6301-4681-b2fa-f36b2799abf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43361638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.43361638
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3425688262
Short name T853
Test name
Test status
Simulation time 52402003698 ps
CPU time 51.07 seconds
Started Aug 16 05:02:20 PM PDT 24
Finished Aug 16 05:03:11 PM PDT 24
Peak memory 200896 kb
Host smart-1d503eef-2ef4-4ab7-9df2-0e1f602c685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425688262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3425688262
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4105874490
Short name T953
Test name
Test status
Simulation time 120899057544 ps
CPU time 318.89 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:07:43 PM PDT 24
Peak memory 200856 kb
Host smart-b62eb22d-0530-4950-8175-7233f9dfaf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105874490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4105874490
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2644871950
Short name T110
Test name
Test status
Simulation time 23881614705 ps
CPU time 9.7 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:36 PM PDT 24
Peak memory 200828 kb
Host smart-19570aa2-7dab-4dc1-8c15-bf5f948d194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644871950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2644871950
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.685802267
Short name T585
Test name
Test status
Simulation time 8038405500 ps
CPU time 3.75 seconds
Started Aug 16 05:02:21 PM PDT 24
Finished Aug 16 05:02:25 PM PDT 24
Peak memory 197616 kb
Host smart-2969f1a4-e57d-40a1-b5e7-eca53ac57f18
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685802267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.685802267
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3453461289
Short name T250
Test name
Test status
Simulation time 184977519927 ps
CPU time 1198.27 seconds
Started Aug 16 05:02:26 PM PDT 24
Finished Aug 16 05:22:25 PM PDT 24
Peak memory 200828 kb
Host smart-6b1bb5ce-4845-4def-a5e6-11a9788f80e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453461289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3453461289
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3848892555
Short name T681
Test name
Test status
Simulation time 6875685030 ps
CPU time 4.06 seconds
Started Aug 16 05:02:21 PM PDT 24
Finished Aug 16 05:02:25 PM PDT 24
Peak memory 199424 kb
Host smart-3570f5a3-b2a5-412c-867a-1389199cf80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848892555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3848892555
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3152747962
Short name T792
Test name
Test status
Simulation time 18808432263 ps
CPU time 89.75 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:03:54 PM PDT 24
Peak memory 201036 kb
Host smart-293afffb-65db-4a9f-b9eb-5f589fc069c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152747962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3152747962
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2629445172
Short name T247
Test name
Test status
Simulation time 13919174290 ps
CPU time 653.51 seconds
Started Aug 16 05:02:23 PM PDT 24
Finished Aug 16 05:13:16 PM PDT 24
Peak memory 200916 kb
Host smart-acbc5551-cf54-4b4f-833c-38fe8ce1f064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2629445172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2629445172
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.4013604971
Short name T17
Test name
Test status
Simulation time 6692213921 ps
CPU time 65.83 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:03:33 PM PDT 24
Peak memory 200108 kb
Host smart-bc8a581a-d63b-4b43-85d6-10ccdac5b2d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013604971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4013604971
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.222327754
Short name T411
Test name
Test status
Simulation time 28156610475 ps
CPU time 16.83 seconds
Started Aug 16 05:02:21 PM PDT 24
Finished Aug 16 05:02:38 PM PDT 24
Peak memory 200844 kb
Host smart-d796ed95-76fe-4e09-b73e-6746beac8476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222327754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.222327754
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1248866672
Short name T520
Test name
Test status
Simulation time 3677992600 ps
CPU time 5.83 seconds
Started Aug 16 05:02:22 PM PDT 24
Finished Aug 16 05:02:28 PM PDT 24
Peak memory 197064 kb
Host smart-39cc2c79-cba6-4f8a-95bf-06ebfd9ef0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248866672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1248866672
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2331836573
Short name T876
Test name
Test status
Simulation time 6041474131 ps
CPU time 9.86 seconds
Started Aug 16 05:02:23 PM PDT 24
Finished Aug 16 05:02:33 PM PDT 24
Peak memory 200836 kb
Host smart-ad4ce7fc-f6de-4538-a857-4d73912f9d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331836573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2331836573
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2484418755
Short name T803
Test name
Test status
Simulation time 839220810 ps
CPU time 2.64 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:02:26 PM PDT 24
Peak memory 200648 kb
Host smart-7630f82d-1278-4169-aa11-2eb955528584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484418755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2484418755
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2094903721
Short name T620
Test name
Test status
Simulation time 86076651214 ps
CPU time 38.6 seconds
Started Aug 16 05:02:31 PM PDT 24
Finished Aug 16 05:03:10 PM PDT 24
Peak memory 200904 kb
Host smart-23d6ca68-e346-4879-b84d-4ed458415292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094903721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2094903721
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1519408678
Short name T951
Test name
Test status
Simulation time 62393656550 ps
CPU time 93.02 seconds
Started Aug 16 05:06:13 PM PDT 24
Finished Aug 16 05:07:46 PM PDT 24
Peak memory 200912 kb
Host smart-22873b94-55b7-4f3f-899d-3f3894a3fba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519408678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1519408678
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2125372939
Short name T181
Test name
Test status
Simulation time 54164872901 ps
CPU time 139.73 seconds
Started Aug 16 05:06:13 PM PDT 24
Finished Aug 16 05:08:33 PM PDT 24
Peak memory 200888 kb
Host smart-571aca7f-4460-415a-a274-06941592feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125372939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2125372939
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.711773121
Short name T287
Test name
Test status
Simulation time 24107859653 ps
CPU time 43.41 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:06:55 PM PDT 24
Peak memory 200928 kb
Host smart-47758a0b-5ec9-49a9-bedf-e3ce54a42a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711773121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.711773121
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1051909224
Short name T1003
Test name
Test status
Simulation time 6789548770 ps
CPU time 10.63 seconds
Started Aug 16 05:06:10 PM PDT 24
Finished Aug 16 05:06:21 PM PDT 24
Peak memory 200384 kb
Host smart-b59de189-41eb-4cf5-a5c7-b87c1788e664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051909224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1051909224
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2689819277
Short name T192
Test name
Test status
Simulation time 18552197330 ps
CPU time 41.55 seconds
Started Aug 16 05:06:13 PM PDT 24
Finished Aug 16 05:06:54 PM PDT 24
Peak memory 200888 kb
Host smart-ca131db8-369a-4c33-b4c3-a0fd98180698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689819277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2689819277
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.271165311
Short name T928
Test name
Test status
Simulation time 124021236351 ps
CPU time 51.21 seconds
Started Aug 16 05:06:10 PM PDT 24
Finished Aug 16 05:07:01 PM PDT 24
Peak memory 200916 kb
Host smart-0d7cff38-8030-49fa-a120-50d0e3a8360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271165311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.271165311
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1785229533
Short name T872
Test name
Test status
Simulation time 251930412994 ps
CPU time 96.6 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:07:55 PM PDT 24
Peak memory 200844 kb
Host smart-046a428a-24a5-44b7-a69d-49bb0d626de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785229533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1785229533
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.1308077709
Short name T825
Test name
Test status
Simulation time 13462677 ps
CPU time 0.57 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:27 PM PDT 24
Peak memory 196128 kb
Host smart-6ac21ded-8829-413c-902b-72b907742df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308077709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1308077709
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3568282858
Short name T318
Test name
Test status
Simulation time 55627594561 ps
CPU time 48.36 seconds
Started Aug 16 05:02:21 PM PDT 24
Finished Aug 16 05:03:10 PM PDT 24
Peak memory 200816 kb
Host smart-2f433aa5-8d73-450d-8214-3c3960b9f10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568282858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3568282858
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.4162015760
Short name T838
Test name
Test status
Simulation time 102773086406 ps
CPU time 92.28 seconds
Started Aug 16 05:02:23 PM PDT 24
Finished Aug 16 05:03:55 PM PDT 24
Peak memory 200952 kb
Host smart-edf4f1bf-7435-4742-bf89-7f6e3169b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162015760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4162015760
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.2496690569
Short name T352
Test name
Test status
Simulation time 276140648870 ps
CPU time 41.13 seconds
Started Aug 16 05:02:23 PM PDT 24
Finished Aug 16 05:03:05 PM PDT 24
Peak memory 197860 kb
Host smart-41dc93fa-272d-49fc-9f02-10c9b569c66a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496690569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2496690569
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2188222400
Short name T673
Test name
Test status
Simulation time 82761783805 ps
CPU time 224.41 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:06:08 PM PDT 24
Peak memory 200892 kb
Host smart-c64f2ec6-599e-498b-a0b7-a384dd415d12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188222400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2188222400
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.141336432
Short name T610
Test name
Test status
Simulation time 4261941047 ps
CPU time 7.43 seconds
Started Aug 16 05:02:22 PM PDT 24
Finished Aug 16 05:02:30 PM PDT 24
Peak memory 199588 kb
Host smart-408fcf28-c3a2-4a81-971e-503b99646297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141336432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.141336432
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3657624348
Short name T465
Test name
Test status
Simulation time 8182942228 ps
CPU time 18.61 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:02:42 PM PDT 24
Peak memory 201076 kb
Host smart-0fc95b99-765d-412d-aae1-38005fd276f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657624348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3657624348
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3951810079
Short name T403
Test name
Test status
Simulation time 8060358503 ps
CPU time 264.24 seconds
Started Aug 16 05:02:26 PM PDT 24
Finished Aug 16 05:06:51 PM PDT 24
Peak memory 200892 kb
Host smart-b573807b-9b36-4b4b-b4c8-e91d4c73fe0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951810079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3951810079
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3345338977
Short name T694
Test name
Test status
Simulation time 1433619912 ps
CPU time 1.15 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:28 PM PDT 24
Peak memory 197864 kb
Host smart-6cecf44c-6d12-4586-af95-1cfaa35c6362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345338977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3345338977
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4141560775
Short name T325
Test name
Test status
Simulation time 2892628330 ps
CPU time 2.86 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:02:27 PM PDT 24
Peak memory 196688 kb
Host smart-c05dd5f5-cf1c-456d-a4ae-cc0a5d39398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141560775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4141560775
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3454526159
Short name T541
Test name
Test status
Simulation time 521744054 ps
CPU time 1.28 seconds
Started Aug 16 05:02:20 PM PDT 24
Finished Aug 16 05:02:21 PM PDT 24
Peak memory 199604 kb
Host smart-7195828b-1aae-4a86-b2ca-313b406701a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454526159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3454526159
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3621201296
Short name T1152
Test name
Test status
Simulation time 243852188545 ps
CPU time 2299 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:40:46 PM PDT 24
Peak memory 200868 kb
Host smart-4bef9dd0-8b64-4458-b885-1e1abd8aa2b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621201296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3621201296
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3110102584
Short name T833
Test name
Test status
Simulation time 5809465636 ps
CPU time 12.47 seconds
Started Aug 16 05:02:22 PM PDT 24
Finished Aug 16 05:02:35 PM PDT 24
Peak memory 200912 kb
Host smart-126dd990-3ccb-4cdf-9620-7143ad94bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110102584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3110102584
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.599558432
Short name T831
Test name
Test status
Simulation time 43805056034 ps
CPU time 20.87 seconds
Started Aug 16 05:02:24 PM PDT 24
Finished Aug 16 05:02:45 PM PDT 24
Peak memory 200784 kb
Host smart-37d64b69-6ce9-413c-bdf7-bac3082bda13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599558432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.599558432
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1863622588
Short name T363
Test name
Test status
Simulation time 140760153699 ps
CPU time 59.41 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:07:17 PM PDT 24
Peak memory 200836 kb
Host smart-7d0218aa-4b87-40b8-ab89-1eb83515f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863622588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1863622588
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1931694254
Short name T418
Test name
Test status
Simulation time 23503722988 ps
CPU time 39.32 seconds
Started Aug 16 05:06:20 PM PDT 24
Finished Aug 16 05:06:59 PM PDT 24
Peak memory 200620 kb
Host smart-82f9cae2-639f-48dc-8657-7b79707cb12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931694254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1931694254
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2613352500
Short name T349
Test name
Test status
Simulation time 34980739555 ps
CPU time 9.21 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:06:28 PM PDT 24
Peak memory 200804 kb
Host smart-36d39638-58f8-43ea-b370-16abb900cede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613352500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2613352500
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.585284482
Short name T765
Test name
Test status
Simulation time 62202828940 ps
CPU time 27.59 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:06:45 PM PDT 24
Peak memory 200844 kb
Host smart-22fe3724-0ded-4aba-a1c0-3651b7751bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585284482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.585284482
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2976805055
Short name T1153
Test name
Test status
Simulation time 13315338379 ps
CPU time 5.64 seconds
Started Aug 16 05:06:21 PM PDT 24
Finished Aug 16 05:06:27 PM PDT 24
Peak memory 200900 kb
Host smart-5332e1b4-2688-431f-a127-471bf18b63c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976805055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2976805055
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.118018050
Short name T915
Test name
Test status
Simulation time 88670407 ps
CPU time 0.57 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:28 PM PDT 24
Peak memory 196212 kb
Host smart-ca503397-ad99-45da-8c46-86cba9538a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118018050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.118018050
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1733885786
Short name T898
Test name
Test status
Simulation time 122231384732 ps
CPU time 326.33 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:07:54 PM PDT 24
Peak memory 200824 kb
Host smart-9d8719ed-90df-44f7-b9c8-2e41e09afb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733885786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1733885786
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2709767556
Short name T832
Test name
Test status
Simulation time 69718460543 ps
CPU time 36.92 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:03:05 PM PDT 24
Peak memory 200780 kb
Host smart-5b4024f4-5d49-4e27-8f05-0ac2fdbd8449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709767556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2709767556
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.74713103
Short name T450
Test name
Test status
Simulation time 139632510648 ps
CPU time 77.04 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:03:45 PM PDT 24
Peak memory 200880 kb
Host smart-21199a69-f467-4092-b6b1-38cf43b0bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74713103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.74713103
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1811582977
Short name T300
Test name
Test status
Simulation time 54320730857 ps
CPU time 118.99 seconds
Started Aug 16 05:02:33 PM PDT 24
Finished Aug 16 05:04:32 PM PDT 24
Peak memory 200896 kb
Host smart-736aeb4d-2832-4d42-9306-1fc2031d0185
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811582977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1811582977
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3369487643
Short name T1133
Test name
Test status
Simulation time 320188945267 ps
CPU time 393.25 seconds
Started Aug 16 05:02:33 PM PDT 24
Finished Aug 16 05:09:07 PM PDT 24
Peak memory 200828 kb
Host smart-075d6f16-d5aa-4df9-9692-a49ef63eca8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369487643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3369487643
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3968281173
Short name T1013
Test name
Test status
Simulation time 8504229366 ps
CPU time 6.81 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:34 PM PDT 24
Peak memory 200852 kb
Host smart-487dae2c-7883-4436-b965-9fe1e098142b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968281173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3968281173
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1819293032
Short name T290
Test name
Test status
Simulation time 29555214809 ps
CPU time 63.08 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:03:31 PM PDT 24
Peak memory 200300 kb
Host smart-054570fb-e172-4b64-b016-1d98d0794155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819293032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1819293032
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2684126787
Short name T563
Test name
Test status
Simulation time 28505838225 ps
CPU time 191.41 seconds
Started Aug 16 05:02:34 PM PDT 24
Finished Aug 16 05:05:45 PM PDT 24
Peak memory 200896 kb
Host smart-9f468480-e7e8-4ea7-a88b-109be0f48575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684126787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2684126787
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4048672943
Short name T1006
Test name
Test status
Simulation time 1412983629 ps
CPU time 0.97 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:29 PM PDT 24
Peak memory 196568 kb
Host smart-adfe91df-3efa-41d7-a1d6-78dbed05a49b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048672943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4048672943
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1110202015
Short name T133
Test name
Test status
Simulation time 27521818339 ps
CPU time 18.67 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:46 PM PDT 24
Peak memory 200932 kb
Host smart-4e96eb8d-d952-4d0e-9369-c77891adea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110202015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1110202015
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2680038074
Short name T780
Test name
Test status
Simulation time 923371366 ps
CPU time 1.02 seconds
Started Aug 16 05:02:29 PM PDT 24
Finished Aug 16 05:02:30 PM PDT 24
Peak memory 196264 kb
Host smart-7a9e06a5-e084-49c2-a454-1be5d2e0f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680038074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2680038074
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.4288305194
Short name T762
Test name
Test status
Simulation time 492684795 ps
CPU time 1.47 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:02:29 PM PDT 24
Peak memory 200324 kb
Host smart-4aea274a-2f9d-4487-84b8-29003093bba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288305194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4288305194
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.803272891
Short name T922
Test name
Test status
Simulation time 968526011381 ps
CPU time 343.05 seconds
Started Aug 16 05:02:31 PM PDT 24
Finished Aug 16 05:08:14 PM PDT 24
Peak memory 209304 kb
Host smart-9bbe9672-08a9-4fe1-ae62-c38ad4964625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803272891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.803272891
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1333841484
Short name T997
Test name
Test status
Simulation time 994289212 ps
CPU time 8.84 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:36 PM PDT 24
Peak memory 200912 kb
Host smart-637a5d7b-8dd1-41a9-90fa-c28bcab47b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333841484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1333841484
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.4246860972
Short name T586
Test name
Test status
Simulation time 1062578350 ps
CPU time 4.41 seconds
Started Aug 16 05:02:26 PM PDT 24
Finished Aug 16 05:02:31 PM PDT 24
Peak memory 199360 kb
Host smart-4f76eb62-17be-4110-af84-4fa1e99d75fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246860972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4246860972
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2771613844
Short name T1121
Test name
Test status
Simulation time 18958052027 ps
CPU time 8.07 seconds
Started Aug 16 05:02:26 PM PDT 24
Finished Aug 16 05:02:34 PM PDT 24
Peak memory 200680 kb
Host smart-66fc0dac-2b07-4961-aded-e53f338f890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771613844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2771613844
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1836949036
Short name T583
Test name
Test status
Simulation time 190551659009 ps
CPU time 32.19 seconds
Started Aug 16 05:06:17 PM PDT 24
Finished Aug 16 05:06:49 PM PDT 24
Peak memory 200912 kb
Host smart-44a09da9-8239-4f28-ba24-067e7a062bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836949036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1836949036
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3510308514
Short name T1163
Test name
Test status
Simulation time 23623510059 ps
CPU time 14.78 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:06:33 PM PDT 24
Peak memory 200776 kb
Host smart-5e8a99c9-8d23-435a-9c00-587c9dc42d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510308514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3510308514
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1981993947
Short name T120
Test name
Test status
Simulation time 26878413569 ps
CPU time 91.16 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:07:50 PM PDT 24
Peak memory 200796 kb
Host smart-98399ba2-5eb7-4021-aefe-49ea984f0551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981993947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1981993947
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1846170229
Short name T244
Test name
Test status
Simulation time 97903790021 ps
CPU time 38.04 seconds
Started Aug 16 05:06:19 PM PDT 24
Finished Aug 16 05:06:57 PM PDT 24
Peak memory 200904 kb
Host smart-9c389cac-7882-4b37-8155-5d9cc21bb323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846170229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1846170229
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2934110257
Short name T1114
Test name
Test status
Simulation time 100177943000 ps
CPU time 43.58 seconds
Started Aug 16 05:06:19 PM PDT 24
Finished Aug 16 05:07:03 PM PDT 24
Peak memory 200900 kb
Host smart-ca868330-b600-444b-8247-820a1b3c24f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934110257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2934110257
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3885016078
Short name T494
Test name
Test status
Simulation time 65711676228 ps
CPU time 46.45 seconds
Started Aug 16 05:06:20 PM PDT 24
Finished Aug 16 05:07:06 PM PDT 24
Peak memory 200848 kb
Host smart-9e145279-d26f-4d04-a3a0-0872bb4a37da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885016078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3885016078
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1421457912
Short name T731
Test name
Test status
Simulation time 152388775 ps
CPU time 0.59 seconds
Started Aug 16 05:02:30 PM PDT 24
Finished Aug 16 05:02:31 PM PDT 24
Peak memory 196212 kb
Host smart-26e72fd0-2c4b-47af-9b1c-cfdcce6d2b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421457912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1421457912
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1241470371
Short name T1035
Test name
Test status
Simulation time 10208230755 ps
CPU time 22.24 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:02:50 PM PDT 24
Peak memory 200924 kb
Host smart-d5f4b9aa-87c6-4993-9b66-911c4494f08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241470371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1241470371
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3184380586
Short name T142
Test name
Test status
Simulation time 28217233997 ps
CPU time 42.71 seconds
Started Aug 16 05:02:34 PM PDT 24
Finished Aug 16 05:03:17 PM PDT 24
Peak memory 200896 kb
Host smart-a6c5791d-ece8-48a4-989a-c74ad220a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184380586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3184380586
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1224568754
Short name T127
Test name
Test status
Simulation time 98154795706 ps
CPU time 42.3 seconds
Started Aug 16 05:02:31 PM PDT 24
Finished Aug 16 05:03:13 PM PDT 24
Peak memory 200916 kb
Host smart-9881c4be-228a-4bbc-a178-c2928e85de2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224568754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1224568754
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2940550331
Short name T1064
Test name
Test status
Simulation time 14199342090 ps
CPU time 13.68 seconds
Started Aug 16 05:02:44 PM PDT 24
Finished Aug 16 05:02:58 PM PDT 24
Peak memory 200860 kb
Host smart-9e4f2f19-c92b-4890-9dbb-53c2509e5638
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940550331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2940550331
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4109156286
Short name T413
Test name
Test status
Simulation time 103330424663 ps
CPU time 167.29 seconds
Started Aug 16 05:02:29 PM PDT 24
Finished Aug 16 05:05:16 PM PDT 24
Peak memory 200712 kb
Host smart-6666e5a8-5338-4252-bd21-e8af83199843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109156286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4109156286
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1672345630
Short name T525
Test name
Test status
Simulation time 1516246965 ps
CPU time 1.24 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:02:30 PM PDT 24
Peak memory 196984 kb
Host smart-a7f3a42f-35f0-49eb-af96-452746ff2143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672345630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1672345630
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2624923392
Short name T776
Test name
Test status
Simulation time 151353102314 ps
CPU time 48.65 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:03:17 PM PDT 24
Peak memory 201028 kb
Host smart-42e28541-c2e2-42b5-ad99-03bda548e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624923392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2624923392
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.755470955
Short name T1098
Test name
Test status
Simulation time 10274953883 ps
CPU time 62.88 seconds
Started Aug 16 05:02:31 PM PDT 24
Finished Aug 16 05:03:34 PM PDT 24
Peak memory 200908 kb
Host smart-bee312d3-8344-4d63-9c46-0a3c1c97243e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755470955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.755470955
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.325276209
Short name T1109
Test name
Test status
Simulation time 5673763532 ps
CPU time 15.31 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:02:43 PM PDT 24
Peak memory 199092 kb
Host smart-0213816a-0a9c-43ad-b686-f4065ea39f30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325276209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.325276209
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1701149447
Short name T279
Test name
Test status
Simulation time 34879775866 ps
CPU time 44.11 seconds
Started Aug 16 05:02:28 PM PDT 24
Finished Aug 16 05:03:12 PM PDT 24
Peak memory 200608 kb
Host smart-998d7c9c-1016-46c8-b24f-dc6bc0d73635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701149447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1701149447
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3673780187
Short name T331
Test name
Test status
Simulation time 3322749934 ps
CPU time 2.08 seconds
Started Aug 16 05:02:30 PM PDT 24
Finished Aug 16 05:02:32 PM PDT 24
Peak memory 197400 kb
Host smart-4213a60b-f9c2-465c-a0a9-3d11a34522f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673780187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3673780187
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.756292790
Short name T535
Test name
Test status
Simulation time 5912917202 ps
CPU time 14.08 seconds
Started Aug 16 05:02:27 PM PDT 24
Finished Aug 16 05:02:41 PM PDT 24
Peak memory 200712 kb
Host smart-65a186e1-ee58-40be-a301-c121b95e5ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756292790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.756292790
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3164534735
Short name T288
Test name
Test status
Simulation time 1439028056 ps
CPU time 2.76 seconds
Started Aug 16 05:02:29 PM PDT 24
Finished Aug 16 05:02:32 PM PDT 24
Peak memory 200808 kb
Host smart-81bbf763-d798-431b-8a32-1a93914f9f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164534735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3164534735
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3376495228
Short name T601
Test name
Test status
Simulation time 35447660541 ps
CPU time 50.17 seconds
Started Aug 16 05:02:29 PM PDT 24
Finished Aug 16 05:03:20 PM PDT 24
Peak memory 200796 kb
Host smart-3b2d127e-e836-4156-bdde-641ed227654b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376495228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3376495228
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2208799709
Short name T903
Test name
Test status
Simulation time 17097199667 ps
CPU time 32.99 seconds
Started Aug 16 05:06:20 PM PDT 24
Finished Aug 16 05:06:53 PM PDT 24
Peak memory 200876 kb
Host smart-ec3ba9d3-dfc9-49a1-acbd-18e54288d3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208799709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2208799709
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1715598053
Short name T422
Test name
Test status
Simulation time 55373563708 ps
CPU time 30.16 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:06:48 PM PDT 24
Peak memory 200868 kb
Host smart-78b329cc-f4d7-4d41-a1e7-e5e4cedaac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715598053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1715598053
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.827437547
Short name T551
Test name
Test status
Simulation time 26401556911 ps
CPU time 53.53 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:07:11 PM PDT 24
Peak memory 200904 kb
Host smart-fb292940-d823-40d0-b535-5a1c0edb6577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827437547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.827437547
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3435616010
Short name T1047
Test name
Test status
Simulation time 65697060470 ps
CPU time 27.64 seconds
Started Aug 16 05:06:18 PM PDT 24
Finished Aug 16 05:06:46 PM PDT 24
Peak memory 200848 kb
Host smart-e2637cd8-e201-4c15-8bbb-a762d5f1b082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435616010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3435616010
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1223066893
Short name T971
Test name
Test status
Simulation time 27544087359 ps
CPU time 50.82 seconds
Started Aug 16 05:06:26 PM PDT 24
Finished Aug 16 05:07:17 PM PDT 24
Peak memory 200888 kb
Host smart-7bdca5e2-ac90-4fd1-8338-192994ec278a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223066893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1223066893
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.564443439
Short name T508
Test name
Test status
Simulation time 37317004668 ps
CPU time 35.22 seconds
Started Aug 16 05:06:27 PM PDT 24
Finished Aug 16 05:07:02 PM PDT 24
Peak memory 200940 kb
Host smart-3354ef22-26b2-41bb-bd33-211211355164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564443439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.564443439
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3063706032
Short name T319
Test name
Test status
Simulation time 73305110203 ps
CPU time 33.97 seconds
Started Aug 16 05:06:30 PM PDT 24
Finished Aug 16 05:07:04 PM PDT 24
Peak memory 200764 kb
Host smart-3d62a9d2-5b22-4785-a16e-d1900f598b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063706032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3063706032
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2671658282
Short name T132
Test name
Test status
Simulation time 15340136360 ps
CPU time 22.86 seconds
Started Aug 16 05:06:27 PM PDT 24
Finished Aug 16 05:06:50 PM PDT 24
Peak memory 200892 kb
Host smart-eac6d6ae-0015-419c-95e5-569070dbee3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671658282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2671658282
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1686382561
Short name T165
Test name
Test status
Simulation time 156682523978 ps
CPU time 952.21 seconds
Started Aug 16 05:06:27 PM PDT 24
Finished Aug 16 05:22:19 PM PDT 24
Peak memory 200912 kb
Host smart-1d39ec86-6f01-499f-8dfe-f5f3c9f5265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686382561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1686382561
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4185715597
Short name T441
Test name
Test status
Simulation time 24512290 ps
CPU time 0.57 seconds
Started Aug 16 05:02:43 PM PDT 24
Finished Aug 16 05:02:44 PM PDT 24
Peak memory 196520 kb
Host smart-0c7b8c49-2087-4aa9-bead-443bf917858c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185715597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4185715597
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3058224619
Short name T1136
Test name
Test status
Simulation time 80982492916 ps
CPU time 33.8 seconds
Started Aug 16 05:02:36 PM PDT 24
Finished Aug 16 05:03:10 PM PDT 24
Peak memory 200740 kb
Host smart-26a9477a-e066-4784-9ae2-f42c7113befa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058224619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3058224619
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.458395384
Short name T1018
Test name
Test status
Simulation time 193652230530 ps
CPU time 40.24 seconds
Started Aug 16 05:02:36 PM PDT 24
Finished Aug 16 05:03:16 PM PDT 24
Peak memory 200844 kb
Host smart-6632ba1f-a31a-4fe7-a729-d382b94e4c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458395384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.458395384
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1758485019
Short name T177
Test name
Test status
Simulation time 24592173714 ps
CPU time 54.76 seconds
Started Aug 16 05:02:34 PM PDT 24
Finished Aug 16 05:03:29 PM PDT 24
Peak memory 200900 kb
Host smart-ef11b3e4-4604-4f93-a71c-1e5c5c6a3e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758485019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1758485019
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.142249661
Short name T407
Test name
Test status
Simulation time 149674584583 ps
CPU time 207.01 seconds
Started Aug 16 05:02:37 PM PDT 24
Finished Aug 16 05:06:04 PM PDT 24
Peak memory 200848 kb
Host smart-05b04fbc-19bc-420f-8c74-67f0ab7a70a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142249661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.142249661
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.85924244
Short name T544
Test name
Test status
Simulation time 90848871156 ps
CPU time 231.44 seconds
Started Aug 16 05:02:48 PM PDT 24
Finished Aug 16 05:06:39 PM PDT 24
Peak memory 200864 kb
Host smart-06f94c9c-9b11-4c27-bd2f-765e246f5039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85924244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.85924244
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2111390833
Short name T390
Test name
Test status
Simulation time 2011699581 ps
CPU time 3.51 seconds
Started Aug 16 05:02:36 PM PDT 24
Finished Aug 16 05:02:39 PM PDT 24
Peak memory 199444 kb
Host smart-770a02e0-c6b1-4c21-8640-a4c804c4f874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111390833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2111390833
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.186248033
Short name T1048
Test name
Test status
Simulation time 3548782701 ps
CPU time 6.88 seconds
Started Aug 16 05:02:37 PM PDT 24
Finished Aug 16 05:02:44 PM PDT 24
Peak memory 198980 kb
Host smart-2da55036-2c0a-4296-8345-91d2a369e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186248033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.186248033
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3403776815
Short name T886
Test name
Test status
Simulation time 21339553043 ps
CPU time 324.87 seconds
Started Aug 16 05:02:42 PM PDT 24
Finished Aug 16 05:08:07 PM PDT 24
Peak memory 200868 kb
Host smart-f9d2760a-175f-4cdd-8e2b-ee5093a1606e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403776815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3403776815
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2905191654
Short name T1038
Test name
Test status
Simulation time 2121216131 ps
CPU time 6.16 seconds
Started Aug 16 05:02:38 PM PDT 24
Finished Aug 16 05:02:44 PM PDT 24
Peak memory 199036 kb
Host smart-278eda8f-9705-4d5e-a026-d2d47ea83e76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2905191654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2905191654
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1680751598
Short name T556
Test name
Test status
Simulation time 116524514116 ps
CPU time 116 seconds
Started Aug 16 05:02:35 PM PDT 24
Finished Aug 16 05:04:31 PM PDT 24
Peak memory 200968 kb
Host smart-f6d94b49-823b-4af8-a39f-4fb2f730fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680751598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1680751598
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3652795022
Short name T837
Test name
Test status
Simulation time 1923687050 ps
CPU time 3.72 seconds
Started Aug 16 05:02:34 PM PDT 24
Finished Aug 16 05:02:37 PM PDT 24
Peak memory 196548 kb
Host smart-baa4cc67-27f4-4eb1-b9f4-b046ece17d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652795022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3652795022
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4086698937
Short name T1097
Test name
Test status
Simulation time 6060753879 ps
CPU time 16.59 seconds
Started Aug 16 05:02:45 PM PDT 24
Finished Aug 16 05:03:02 PM PDT 24
Peak memory 199740 kb
Host smart-8cd50335-2dac-4781-b887-0f8cda595b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086698937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4086698937
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1661585734
Short name T307
Test name
Test status
Simulation time 243165730315 ps
CPU time 1286.59 seconds
Started Aug 16 05:02:45 PM PDT 24
Finished Aug 16 05:24:12 PM PDT 24
Peak memory 200912 kb
Host smart-55a665e6-37f3-44bd-b0bd-0cadf478a067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661585734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1661585734
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4239561543
Short name T276
Test name
Test status
Simulation time 1099438495 ps
CPU time 2.47 seconds
Started Aug 16 05:02:39 PM PDT 24
Finished Aug 16 05:02:42 PM PDT 24
Peak memory 199880 kb
Host smart-38c051c8-bc8a-4472-b381-48d545048cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239561543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4239561543
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1674415847
Short name T719
Test name
Test status
Simulation time 16527874117 ps
CPU time 24.97 seconds
Started Aug 16 05:02:35 PM PDT 24
Finished Aug 16 05:03:00 PM PDT 24
Peak memory 200860 kb
Host smart-061f21f1-7aea-4590-ad5c-659ed09e2716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674415847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1674415847
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2096155336
Short name T574
Test name
Test status
Simulation time 152390032225 ps
CPU time 59.15 seconds
Started Aug 16 05:06:26 PM PDT 24
Finished Aug 16 05:07:25 PM PDT 24
Peak memory 200772 kb
Host smart-4e6a97bb-a5fb-4d41-a614-ad4bdcfe95c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096155336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2096155336
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.467554084
Short name T580
Test name
Test status
Simulation time 16764214860 ps
CPU time 28.59 seconds
Started Aug 16 05:06:32 PM PDT 24
Finished Aug 16 05:07:01 PM PDT 24
Peak memory 200736 kb
Host smart-74f1e25f-7ce6-4304-8d23-d483c272583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467554084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.467554084
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2431096539
Short name T146
Test name
Test status
Simulation time 56366076338 ps
CPU time 98.65 seconds
Started Aug 16 05:06:27 PM PDT 24
Finished Aug 16 05:08:06 PM PDT 24
Peak memory 200868 kb
Host smart-afb866be-c82c-465d-a22e-46a9cf0a0b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431096539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2431096539
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1305335498
Short name T676
Test name
Test status
Simulation time 111462804665 ps
CPU time 46.11 seconds
Started Aug 16 05:06:26 PM PDT 24
Finished Aug 16 05:07:13 PM PDT 24
Peak memory 200796 kb
Host smart-3e5b3e2f-0fe5-4ae7-b568-46c11c4181e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305335498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1305335498
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4290137618
Short name T1021
Test name
Test status
Simulation time 105220358951 ps
CPU time 25.03 seconds
Started Aug 16 05:06:28 PM PDT 24
Finished Aug 16 05:06:54 PM PDT 24
Peak memory 200848 kb
Host smart-c093b9c1-eab8-49d7-a7ac-4bd53a45b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290137618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4290137618
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3076671997
Short name T493
Test name
Test status
Simulation time 20110111180 ps
CPU time 16.95 seconds
Started Aug 16 05:06:26 PM PDT 24
Finished Aug 16 05:06:43 PM PDT 24
Peak memory 200864 kb
Host smart-e0ea4ae3-3f90-4c48-98dc-257350b97ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076671997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3076671997
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3176408553
Short name T703
Test name
Test status
Simulation time 31705663957 ps
CPU time 44.31 seconds
Started Aug 16 05:06:27 PM PDT 24
Finished Aug 16 05:07:12 PM PDT 24
Peak memory 200896 kb
Host smart-ea3d89aa-99a6-4101-bd5b-b9f90cf038da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176408553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3176408553
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2979930115
Short name T1174
Test name
Test status
Simulation time 72084287239 ps
CPU time 52.54 seconds
Started Aug 16 05:06:32 PM PDT 24
Finished Aug 16 05:07:24 PM PDT 24
Peak memory 200660 kb
Host smart-050a3a69-b0f9-427f-a6c4-8dbf8aea6f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979930115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2979930115
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1788407885
Short name T113
Test name
Test status
Simulation time 68381433779 ps
CPU time 110.8 seconds
Started Aug 16 05:06:26 PM PDT 24
Finished Aug 16 05:08:17 PM PDT 24
Peak memory 200896 kb
Host smart-9cc0973d-a64b-4e37-ac80-83633cdc4213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788407885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1788407885
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1434063493
Short name T721
Test name
Test status
Simulation time 21929494 ps
CPU time 0.56 seconds
Started Aug 16 05:02:43 PM PDT 24
Finished Aug 16 05:02:44 PM PDT 24
Peak memory 195188 kb
Host smart-4e182bef-7a33-4b13-a16e-b84848c3e3eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434063493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1434063493
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2159212165
Short name T292
Test name
Test status
Simulation time 31872786811 ps
CPU time 50.32 seconds
Started Aug 16 05:02:44 PM PDT 24
Finished Aug 16 05:03:34 PM PDT 24
Peak memory 200852 kb
Host smart-07b04258-ece8-49bf-8880-7a2c23f3c823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159212165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2159212165
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3950795862
Short name T624
Test name
Test status
Simulation time 36935088085 ps
CPU time 16.46 seconds
Started Aug 16 05:02:48 PM PDT 24
Finished Aug 16 05:03:04 PM PDT 24
Peak memory 200584 kb
Host smart-e894f412-2ed2-4ae1-aae2-2e52281fca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950795862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3950795862
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2255117779
Short name T530
Test name
Test status
Simulation time 60326544065 ps
CPU time 77.61 seconds
Started Aug 16 05:02:45 PM PDT 24
Finished Aug 16 05:04:02 PM PDT 24
Peak memory 199312 kb
Host smart-6c5e00dd-6640-4231-87b5-2513c997caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255117779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2255117779
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.4272612637
Short name T1086
Test name
Test status
Simulation time 31776959741 ps
CPU time 11.68 seconds
Started Aug 16 05:02:44 PM PDT 24
Finished Aug 16 05:02:56 PM PDT 24
Peak memory 198088 kb
Host smart-286db013-dd60-4a45-bc63-b84f3270cea5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272612637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4272612637
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.727652242
Short name T295
Test name
Test status
Simulation time 76717129386 ps
CPU time 195.31 seconds
Started Aug 16 05:02:45 PM PDT 24
Finished Aug 16 05:06:01 PM PDT 24
Peak memory 200924 kb
Host smart-614d3707-64ee-4d92-b201-b83690a8ed4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727652242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.727652242
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1706074332
Short name T800
Test name
Test status
Simulation time 4674970256 ps
CPU time 2.23 seconds
Started Aug 16 05:02:45 PM PDT 24
Finished Aug 16 05:02:48 PM PDT 24
Peak memory 199272 kb
Host smart-17ee9c54-b359-4bf0-b73e-59e7a23a1bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706074332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1706074332
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2280625776
Short name T560
Test name
Test status
Simulation time 44792568526 ps
CPU time 77.73 seconds
Started Aug 16 05:02:45 PM PDT 24
Finished Aug 16 05:04:03 PM PDT 24
Peak memory 201096 kb
Host smart-6225477d-4f1b-40c9-9607-72108f5e61d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280625776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2280625776
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3626172013
Short name T1079
Test name
Test status
Simulation time 29164538767 ps
CPU time 414.01 seconds
Started Aug 16 05:02:42 PM PDT 24
Finished Aug 16 05:09:36 PM PDT 24
Peak memory 200832 kb
Host smart-2156c28d-e9a4-43d9-879f-dc140ce03b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626172013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3626172013
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3321628075
Short name T847
Test name
Test status
Simulation time 1804163800 ps
CPU time 8.98 seconds
Started Aug 16 05:02:43 PM PDT 24
Finished Aug 16 05:02:52 PM PDT 24
Peak memory 198844 kb
Host smart-23d709fc-176c-43e6-b6bf-881f97d82706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321628075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3321628075
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1371678259
Short name T766
Test name
Test status
Simulation time 86780706790 ps
CPU time 232.5 seconds
Started Aug 16 05:02:47 PM PDT 24
Finished Aug 16 05:06:39 PM PDT 24
Peak memory 200908 kb
Host smart-4a368f6a-d0f2-4c0b-83bb-00f36d4e53ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371678259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1371678259
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.957121462
Short name T452
Test name
Test status
Simulation time 2810537267 ps
CPU time 5.17 seconds
Started Aug 16 05:02:45 PM PDT 24
Finished Aug 16 05:02:51 PM PDT 24
Peak memory 195972 kb
Host smart-ad6a8330-0722-4225-8a32-895974fe0c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957121462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.957121462
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1208747366
Short name T1138
Test name
Test status
Simulation time 534374963 ps
CPU time 2.29 seconds
Started Aug 16 05:02:48 PM PDT 24
Finished Aug 16 05:02:50 PM PDT 24
Peak memory 200400 kb
Host smart-267efa55-4421-4ab3-95b6-e44a15f8217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208747366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1208747366
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.4138812362
Short name T78
Test name
Test status
Simulation time 456945566767 ps
CPU time 606.11 seconds
Started Aug 16 05:02:48 PM PDT 24
Finished Aug 16 05:12:55 PM PDT 24
Peak memory 200836 kb
Host smart-4863a39b-1dbc-4859-a313-9bf7c70dd9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138812362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.4138812362
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3442689320
Short name T1085
Test name
Test status
Simulation time 985990267 ps
CPU time 17.39 seconds
Started Aug 16 05:02:43 PM PDT 24
Finished Aug 16 05:03:00 PM PDT 24
Peak memory 200828 kb
Host smart-f6452957-e7b6-412d-9e51-50bb46bb6e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442689320 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3442689320
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2187269972
Short name T437
Test name
Test status
Simulation time 608474608 ps
CPU time 1.5 seconds
Started Aug 16 05:02:45 PM PDT 24
Finished Aug 16 05:02:46 PM PDT 24
Peak memory 200484 kb
Host smart-19b14c3a-deba-4635-a9ea-fe92d69d3815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187269972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2187269972
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.696197811
Short name T559
Test name
Test status
Simulation time 50220672219 ps
CPU time 10.66 seconds
Started Aug 16 05:02:43 PM PDT 24
Finished Aug 16 05:02:54 PM PDT 24
Peak memory 200888 kb
Host smart-cbd01a91-df24-4580-9ab7-c724ecfff5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696197811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.696197811
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3193325177
Short name T203
Test name
Test status
Simulation time 81635900759 ps
CPU time 27.11 seconds
Started Aug 16 05:06:26 PM PDT 24
Finished Aug 16 05:06:53 PM PDT 24
Peak memory 200952 kb
Host smart-667a1dfc-09d9-4277-a006-5c061f8a2a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193325177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3193325177
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2955785083
Short name T644
Test name
Test status
Simulation time 57415689094 ps
CPU time 25.59 seconds
Started Aug 16 05:06:32 PM PDT 24
Finished Aug 16 05:06:58 PM PDT 24
Peak memory 200908 kb
Host smart-f41627fd-ad28-465b-9fd1-cec2da71ed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955785083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2955785083
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1681612339
Short name T1165
Test name
Test status
Simulation time 220080471378 ps
CPU time 89.33 seconds
Started Aug 16 05:06:26 PM PDT 24
Finished Aug 16 05:07:55 PM PDT 24
Peak memory 200524 kb
Host smart-aa689854-633b-42ba-87bd-3d976928bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681612339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1681612339
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3890449549
Short name T476
Test name
Test status
Simulation time 374497532262 ps
CPU time 154.05 seconds
Started Aug 16 05:06:31 PM PDT 24
Finished Aug 16 05:09:05 PM PDT 24
Peak memory 200796 kb
Host smart-e6a16847-683d-441b-80ec-f24f09608427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890449549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3890449549
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1710769809
Short name T193
Test name
Test status
Simulation time 82317085816 ps
CPU time 226.03 seconds
Started Aug 16 05:06:28 PM PDT 24
Finished Aug 16 05:10:14 PM PDT 24
Peak memory 200852 kb
Host smart-085c5579-6c97-4d30-a33a-a911afb6490d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710769809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1710769809
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3532508087
Short name T950
Test name
Test status
Simulation time 218596579988 ps
CPU time 315.03 seconds
Started Aug 16 05:06:34 PM PDT 24
Finished Aug 16 05:11:49 PM PDT 24
Peak memory 200896 kb
Host smart-7a0153fa-f3dc-4989-b829-68312a30a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532508087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3532508087
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.642560254
Short name T978
Test name
Test status
Simulation time 20314671 ps
CPU time 0.55 seconds
Started Aug 16 05:02:52 PM PDT 24
Finished Aug 16 05:02:53 PM PDT 24
Peak memory 196220 kb
Host smart-e1e7661c-613e-4da8-ad09-f328f041db0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642560254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.642560254
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.166188694
Short name T1089
Test name
Test status
Simulation time 273248235061 ps
CPU time 76.55 seconds
Started Aug 16 05:02:54 PM PDT 24
Finished Aug 16 05:04:10 PM PDT 24
Peak memory 200848 kb
Host smart-25d37b7c-e2dd-4cc2-bfd9-0485804e38e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166188694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.166188694
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3210907105
Short name T160
Test name
Test status
Simulation time 67211694019 ps
CPU time 44.13 seconds
Started Aug 16 05:02:57 PM PDT 24
Finished Aug 16 05:03:41 PM PDT 24
Peak memory 200840 kb
Host smart-20b923bf-118c-4082-b0dd-7ae2467bbcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210907105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3210907105
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.826644202
Short name T477
Test name
Test status
Simulation time 90870925166 ps
CPU time 51.87 seconds
Started Aug 16 05:02:51 PM PDT 24
Finished Aug 16 05:03:43 PM PDT 24
Peak memory 200940 kb
Host smart-ccf180aa-5043-4ae2-bbfd-ba9895348011
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826644202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.826644202
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1378181575
Short name T1076
Test name
Test status
Simulation time 127806451200 ps
CPU time 402.98 seconds
Started Aug 16 05:02:57 PM PDT 24
Finished Aug 16 05:09:40 PM PDT 24
Peak memory 200940 kb
Host smart-ea600807-78c6-4ab3-9f99-45d1933d3da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378181575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1378181575
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.846931667
Short name T546
Test name
Test status
Simulation time 9345717626 ps
CPU time 4.53 seconds
Started Aug 16 05:02:51 PM PDT 24
Finished Aug 16 05:02:55 PM PDT 24
Peak memory 199580 kb
Host smart-72477f18-26eb-4711-a038-825151bd5774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846931667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.846931667
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.391378509
Short name T435
Test name
Test status
Simulation time 36424380167 ps
CPU time 15.62 seconds
Started Aug 16 05:02:56 PM PDT 24
Finished Aug 16 05:03:12 PM PDT 24
Peak memory 201084 kb
Host smart-6c2e8fea-5001-4b28-a169-434c00ac2fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391378509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.391378509
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3672720846
Short name T753
Test name
Test status
Simulation time 25544466689 ps
CPU time 365.2 seconds
Started Aug 16 05:02:57 PM PDT 24
Finished Aug 16 05:09:02 PM PDT 24
Peak memory 200848 kb
Host smart-fad9557a-50a7-4b3b-a9a0-2ac521167257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672720846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3672720846
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2534155113
Short name T1034
Test name
Test status
Simulation time 6477474270 ps
CPU time 14.47 seconds
Started Aug 16 05:02:57 PM PDT 24
Finished Aug 16 05:03:12 PM PDT 24
Peak memory 200176 kb
Host smart-de1c39a2-eb0e-497a-afea-fa765d6802ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534155113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2534155113
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2011115099
Short name T518
Test name
Test status
Simulation time 1830475670 ps
CPU time 3.47 seconds
Started Aug 16 05:02:52 PM PDT 24
Finished Aug 16 05:02:56 PM PDT 24
Peak memory 196468 kb
Host smart-6125eef0-4b41-4914-83bf-8f87e415cc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011115099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2011115099
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1327570710
Short name T305
Test name
Test status
Simulation time 716265761 ps
CPU time 3.04 seconds
Started Aug 16 05:02:48 PM PDT 24
Finished Aug 16 05:02:51 PM PDT 24
Peak memory 200440 kb
Host smart-8c5d6bd1-44f9-4b27-a60d-54a6ca76754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327570710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1327570710
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2818397417
Short name T529
Test name
Test status
Simulation time 2253786720 ps
CPU time 42.75 seconds
Started Aug 16 05:02:52 PM PDT 24
Finished Aug 16 05:03:35 PM PDT 24
Peak memory 209372 kb
Host smart-84ca27b4-4196-4a29-bb3e-6a731c290ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818397417 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2818397417
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.51032388
Short name T283
Test name
Test status
Simulation time 2361324513 ps
CPU time 2.1 seconds
Started Aug 16 05:02:56 PM PDT 24
Finished Aug 16 05:02:59 PM PDT 24
Peak memory 199668 kb
Host smart-0d703ab5-10b5-45c6-91fc-d185958f6b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51032388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.51032388
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.954145488
Short name T1092
Test name
Test status
Simulation time 81228048603 ps
CPU time 155.11 seconds
Started Aug 16 05:02:51 PM PDT 24
Finished Aug 16 05:05:26 PM PDT 24
Peak memory 200900 kb
Host smart-62220bb3-be6a-43cb-ae3f-7463342523ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954145488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.954145488
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1994726921
Short name T827
Test name
Test status
Simulation time 148248106590 ps
CPU time 114.9 seconds
Started Aug 16 05:06:34 PM PDT 24
Finished Aug 16 05:08:29 PM PDT 24
Peak memory 200888 kb
Host smart-3676bd2f-bbf2-4319-85de-33121a88afb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994726921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1994726921
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.4057228577
Short name T1139
Test name
Test status
Simulation time 14009574146 ps
CPU time 10.91 seconds
Started Aug 16 05:06:38 PM PDT 24
Finished Aug 16 05:06:49 PM PDT 24
Peak memory 200800 kb
Host smart-974b1d23-d2f8-49d9-a5cb-4d211e98b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057228577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.4057228577
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3662589901
Short name T547
Test name
Test status
Simulation time 94435840776 ps
CPU time 153.75 seconds
Started Aug 16 05:06:36 PM PDT 24
Finished Aug 16 05:09:10 PM PDT 24
Peak memory 200896 kb
Host smart-d827300b-a60b-4ec7-ae00-93a6937d89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662589901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3662589901
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.511065248
Short name T693
Test name
Test status
Simulation time 21585024205 ps
CPU time 30.28 seconds
Started Aug 16 05:06:37 PM PDT 24
Finished Aug 16 05:07:07 PM PDT 24
Peak memory 200648 kb
Host smart-49ba188b-1ad1-4e8e-8f8a-7b3c5f5d1b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511065248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.511065248
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2501517067
Short name T764
Test name
Test status
Simulation time 38045047128 ps
CPU time 23.13 seconds
Started Aug 16 05:06:38 PM PDT 24
Finished Aug 16 05:07:01 PM PDT 24
Peak memory 200796 kb
Host smart-2b0a154d-1194-4938-86b0-2bb55e011f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501517067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2501517067
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1919888979
Short name T1142
Test name
Test status
Simulation time 106732790587 ps
CPU time 45.23 seconds
Started Aug 16 05:06:37 PM PDT 24
Finished Aug 16 05:07:23 PM PDT 24
Peak memory 200848 kb
Host smart-0b7c6f09-fb1b-4da8-8191-92320031ed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919888979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1919888979
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.412166633
Short name T273
Test name
Test status
Simulation time 26484865269 ps
CPU time 45.82 seconds
Started Aug 16 05:06:39 PM PDT 24
Finished Aug 16 05:07:25 PM PDT 24
Peak memory 200808 kb
Host smart-74685985-e4c6-4652-991f-dac122a0f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412166633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.412166633
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2678449035
Short name T729
Test name
Test status
Simulation time 37332221573 ps
CPU time 17.78 seconds
Started Aug 16 05:06:35 PM PDT 24
Finished Aug 16 05:06:53 PM PDT 24
Peak memory 200936 kb
Host smart-8d52aa5d-aa67-4720-ac84-6615a2b5df60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678449035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2678449035
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1035774931
Short name T913
Test name
Test status
Simulation time 23472655 ps
CPU time 0.61 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:01 PM PDT 24
Peak memory 196232 kb
Host smart-d4b418f9-79ac-46c2-a853-1ce433f2102f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035774931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1035774931
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1070649797
Short name T686
Test name
Test status
Simulation time 144634354313 ps
CPU time 114.52 seconds
Started Aug 16 05:02:51 PM PDT 24
Finished Aug 16 05:04:46 PM PDT 24
Peak memory 200864 kb
Host smart-4defa368-527f-4f3b-9d45-d50f49ea0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070649797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1070649797
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3627806102
Short name T813
Test name
Test status
Simulation time 99953197098 ps
CPU time 162.64 seconds
Started Aug 16 05:02:54 PM PDT 24
Finished Aug 16 05:05:37 PM PDT 24
Peak memory 200876 kb
Host smart-c3afd21e-e118-407f-97be-4ef4d03e89f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627806102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3627806102
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.930740066
Short name T354
Test name
Test status
Simulation time 23071551411 ps
CPU time 37.52 seconds
Started Aug 16 05:02:57 PM PDT 24
Finished Aug 16 05:03:35 PM PDT 24
Peak memory 199276 kb
Host smart-28dd2ebb-25fd-4e0f-af29-b43404ac8959
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930740066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.930740066
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1757773324
Short name T430
Test name
Test status
Simulation time 71943658450 ps
CPU time 350.25 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:08:51 PM PDT 24
Peak memory 200888 kb
Host smart-8d0a4b2b-c892-4bed-9ef7-8dfa90edb851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757773324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1757773324
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2363532960
Short name T461
Test name
Test status
Simulation time 105313392 ps
CPU time 1.3 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:03:01 PM PDT 24
Peak memory 199476 kb
Host smart-211ea5a5-6fc0-4e46-9544-8b7d303143c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363532960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2363532960
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1257555381
Short name T1014
Test name
Test status
Simulation time 64919305532 ps
CPU time 138.91 seconds
Started Aug 16 05:02:54 PM PDT 24
Finished Aug 16 05:05:13 PM PDT 24
Peak memory 201068 kb
Host smart-7a329f06-c7cf-4d59-a849-0afb1e0e7ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257555381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1257555381
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.354461306
Short name T885
Test name
Test status
Simulation time 24159427122 ps
CPU time 1442.17 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:27:02 PM PDT 24
Peak memory 200940 kb
Host smart-22ff5b39-e2de-432b-86b4-321dc3001d40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354461306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.354461306
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2492369420
Short name T410
Test name
Test status
Simulation time 6718284850 ps
CPU time 16.2 seconds
Started Aug 16 05:02:53 PM PDT 24
Finished Aug 16 05:03:09 PM PDT 24
Peak memory 200128 kb
Host smart-d8617493-2ba2-4905-8ccb-8f40553550e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492369420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2492369420
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.976243226
Short name T722
Test name
Test status
Simulation time 41175373131 ps
CPU time 17.78 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:18 PM PDT 24
Peak memory 200928 kb
Host smart-a564ee63-2cdb-4d9f-88f7-5e23a03c0623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976243226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.976243226
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1557894562
Short name T5
Test name
Test status
Simulation time 2915995882 ps
CPU time 2.89 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:03 PM PDT 24
Peak memory 196976 kb
Host smart-5c47b996-478b-4955-a4cf-f45d73089073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557894562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1557894562
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3719242401
Short name T1117
Test name
Test status
Simulation time 6279022135 ps
CPU time 8.54 seconds
Started Aug 16 05:02:52 PM PDT 24
Finished Aug 16 05:03:01 PM PDT 24
Peak memory 200900 kb
Host smart-08cc3778-6da0-4379-815a-bc7c05403237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719242401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3719242401
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.370323936
Short name T982
Test name
Test status
Simulation time 233285833150 ps
CPU time 100.89 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:04:40 PM PDT 24
Peak memory 200896 kb
Host smart-17ad63a4-20de-4982-b73c-f45cd178c5c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370323936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.370323936
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.565889147
Short name T849
Test name
Test status
Simulation time 19101033040 ps
CPU time 84.7 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:04:25 PM PDT 24
Peak memory 216388 kb
Host smart-792cb37d-66d5-4793-ab00-2dcc72868ba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565889147 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.565889147
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2667812605
Short name T854
Test name
Test status
Simulation time 813564780 ps
CPU time 2.75 seconds
Started Aug 16 05:03:01 PM PDT 24
Finished Aug 16 05:03:04 PM PDT 24
Peak memory 199840 kb
Host smart-3cf77915-4be5-4dc7-b1eb-35d27f47793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667812605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2667812605
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1362690539
Short name T40
Test name
Test status
Simulation time 13721014949 ps
CPU time 29.27 seconds
Started Aug 16 05:02:52 PM PDT 24
Finished Aug 16 05:03:21 PM PDT 24
Peak memory 200860 kb
Host smart-b4ec52f1-97be-4b05-b9df-3784a51f4734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362690539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1362690539
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.9638166
Short name T371
Test name
Test status
Simulation time 111823574148 ps
CPU time 154.83 seconds
Started Aug 16 05:06:36 PM PDT 24
Finished Aug 16 05:09:11 PM PDT 24
Peak memory 200852 kb
Host smart-ef74b5f9-46bf-46b4-8a91-f962d4349b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9638166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.9638166
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2638306979
Short name T155
Test name
Test status
Simulation time 158762330865 ps
CPU time 19.52 seconds
Started Aug 16 05:06:43 PM PDT 24
Finished Aug 16 05:07:03 PM PDT 24
Peak memory 200828 kb
Host smart-dc9f3671-c380-47fc-b6c3-2319ec89d0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638306979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2638306979
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2724490280
Short name T1065
Test name
Test status
Simulation time 102094666023 ps
CPU time 171.21 seconds
Started Aug 16 05:06:41 PM PDT 24
Finished Aug 16 05:09:32 PM PDT 24
Peak memory 200828 kb
Host smart-01fede91-5bf0-4491-a0b2-ce7ca45ea825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724490280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2724490280
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2155198758
Short name T150
Test name
Test status
Simulation time 30426829254 ps
CPU time 29.83 seconds
Started Aug 16 05:06:44 PM PDT 24
Finished Aug 16 05:07:14 PM PDT 24
Peak memory 200844 kb
Host smart-e8d71def-9dbb-4382-8e81-3fc350cf6fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155198758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2155198758
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3746620957
Short name T343
Test name
Test status
Simulation time 113564288147 ps
CPU time 95.8 seconds
Started Aug 16 05:06:43 PM PDT 24
Finished Aug 16 05:08:19 PM PDT 24
Peak memory 200892 kb
Host smart-3d1a08a3-ddf1-4a2c-9000-fe44888bfa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746620957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3746620957
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.4208122148
Short name T364
Test name
Test status
Simulation time 119631813952 ps
CPU time 192.32 seconds
Started Aug 16 05:06:42 PM PDT 24
Finished Aug 16 05:09:55 PM PDT 24
Peak memory 200632 kb
Host smart-9028862a-10fd-484f-9ea7-6810569025f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208122148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4208122148
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1425490347
Short name T201
Test name
Test status
Simulation time 175894403046 ps
CPU time 278.97 seconds
Started Aug 16 05:06:44 PM PDT 24
Finished Aug 16 05:11:23 PM PDT 24
Peak memory 200928 kb
Host smart-88fb0168-79e5-4447-95e6-47a2ad861a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425490347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1425490347
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4162503119
Short name T4
Test name
Test status
Simulation time 30361117232 ps
CPU time 56.05 seconds
Started Aug 16 05:06:41 PM PDT 24
Finished Aug 16 05:07:37 PM PDT 24
Peak memory 200836 kb
Host smart-95876944-e1d9-450b-9d9a-682f35110101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162503119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4162503119
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1027767760
Short name T905
Test name
Test status
Simulation time 118876873996 ps
CPU time 144.06 seconds
Started Aug 16 05:06:41 PM PDT 24
Finished Aug 16 05:09:05 PM PDT 24
Peak memory 200848 kb
Host smart-939c483b-4f19-4dcf-97ce-43ca25be755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027767760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1027767760
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1797520775
Short name T408
Test name
Test status
Simulation time 52117949 ps
CPU time 0.57 seconds
Started Aug 16 05:03:01 PM PDT 24
Finished Aug 16 05:03:02 PM PDT 24
Peak memory 196224 kb
Host smart-e00a3e64-228e-44c9-8912-6fbb33b09317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797520775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1797520775
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3813570523
Short name T649
Test name
Test status
Simulation time 24553593995 ps
CPU time 9.34 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:03:09 PM PDT 24
Peak memory 200852 kb
Host smart-ca8a5b5e-ecbe-4a4d-8684-3694bf1f1d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813570523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3813570523
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3546475855
Short name T154
Test name
Test status
Simulation time 164866595304 ps
CPU time 96.82 seconds
Started Aug 16 05:03:01 PM PDT 24
Finished Aug 16 05:04:38 PM PDT 24
Peak memory 201040 kb
Host smart-2bbf3cff-2413-48f7-bb99-3660ef6d6448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546475855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3546475855
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.195778999
Short name T182
Test name
Test status
Simulation time 111559809382 ps
CPU time 34.02 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:34 PM PDT 24
Peak memory 200904 kb
Host smart-57234299-a346-4191-a22d-96b893b4c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195778999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.195778999
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1909165053
Short name T1053
Test name
Test status
Simulation time 19114361665 ps
CPU time 24.05 seconds
Started Aug 16 05:03:01 PM PDT 24
Finished Aug 16 05:03:25 PM PDT 24
Peak memory 200844 kb
Host smart-f6e37738-3bcc-4410-a844-f576cbbd1bfb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909165053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1909165053
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4101008969
Short name T405
Test name
Test status
Simulation time 146624069713 ps
CPU time 499.75 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:11:19 PM PDT 24
Peak memory 200832 kb
Host smart-678e4d65-1cb4-4a20-9019-0d91071b2a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101008969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4101008969
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.4176761440
Short name T562
Test name
Test status
Simulation time 9191946401 ps
CPU time 17.66 seconds
Started Aug 16 05:02:58 PM PDT 24
Finished Aug 16 05:03:16 PM PDT 24
Peak memory 199584 kb
Host smart-0c5f9809-12c6-451f-9bdb-e1da03f46585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176761440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.4176761440
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2822656623
Short name T891
Test name
Test status
Simulation time 35114233602 ps
CPU time 47.99 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:03:47 PM PDT 24
Peak memory 201060 kb
Host smart-0b83af39-ac89-4ecf-a351-3778e63e3266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822656623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2822656623
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3886266941
Short name T1039
Test name
Test status
Simulation time 11528769800 ps
CPU time 318.93 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:08:20 PM PDT 24
Peak memory 200904 kb
Host smart-93937f1a-bab1-455c-a63d-804400dbdb28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886266941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3886266941
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3826294255
Short name T483
Test name
Test status
Simulation time 2324181595 ps
CPU time 9.83 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:10 PM PDT 24
Peak memory 199884 kb
Host smart-014424fe-7c66-4d77-97e8-07892a5a90f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826294255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3826294255
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1634634294
Short name T139
Test name
Test status
Simulation time 128833849437 ps
CPU time 41.07 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:42 PM PDT 24
Peak memory 200896 kb
Host smart-865d5e5d-16fe-480f-8a53-24314c5978a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634634294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1634634294
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2162241960
Short name T469
Test name
Test status
Simulation time 7099524664 ps
CPU time 12.03 seconds
Started Aug 16 05:02:58 PM PDT 24
Finished Aug 16 05:03:10 PM PDT 24
Peak memory 197056 kb
Host smart-80944f9d-4529-4ef8-af3b-394d4621d36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162241960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2162241960
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.954823410
Short name T1103
Test name
Test status
Simulation time 498902718 ps
CPU time 1.94 seconds
Started Aug 16 05:03:01 PM PDT 24
Finished Aug 16 05:03:03 PM PDT 24
Peak memory 199780 kb
Host smart-f73372e7-bf42-40b3-b282-827a4f411901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954823410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.954823410
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3664179005
Short name T1057
Test name
Test status
Simulation time 293937466907 ps
CPU time 703.34 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:14:43 PM PDT 24
Peak memory 200892 kb
Host smart-f9d40211-6e17-49f4-8c25-5c2c56edb6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664179005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3664179005
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.4242973781
Short name T819
Test name
Test status
Simulation time 2770490179 ps
CPU time 24.71 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:03:24 PM PDT 24
Peak memory 215736 kb
Host smart-272a434f-1f4e-458f-905f-48bad040dcf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242973781 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.4242973781
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.617909282
Short name T919
Test name
Test status
Simulation time 2229824532 ps
CPU time 2.22 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:02 PM PDT 24
Peak memory 200820 kb
Host smart-93e3e053-12d6-4e0e-a3c1-7eebddb09493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617909282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.617909282
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3036839217
Short name T471
Test name
Test status
Simulation time 45827761810 ps
CPU time 58.14 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:03:57 PM PDT 24
Peak memory 200892 kb
Host smart-2ab71678-ce26-4335-a088-2470bed171f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036839217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3036839217
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1116443041
Short name T323
Test name
Test status
Simulation time 50903501411 ps
CPU time 40.18 seconds
Started Aug 16 05:06:40 PM PDT 24
Finished Aug 16 05:07:21 PM PDT 24
Peak memory 200868 kb
Host smart-76f1c6bc-bd51-4cf9-a339-4bd79141c33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116443041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1116443041
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3738901472
Short name T842
Test name
Test status
Simulation time 6332041522 ps
CPU time 10.96 seconds
Started Aug 16 05:06:44 PM PDT 24
Finished Aug 16 05:06:55 PM PDT 24
Peak memory 199652 kb
Host smart-72994237-63cf-4a41-8cf9-1b2687ee53ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738901472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3738901472
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.877844103
Short name T14
Test name
Test status
Simulation time 83223960664 ps
CPU time 30.3 seconds
Started Aug 16 05:06:44 PM PDT 24
Finished Aug 16 05:07:14 PM PDT 24
Peak memory 200920 kb
Host smart-da0a2b21-1e08-40c5-b371-38dc1ca17798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877844103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.877844103
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3956386555
Short name T232
Test name
Test status
Simulation time 75679150039 ps
CPU time 28.29 seconds
Started Aug 16 05:06:45 PM PDT 24
Finished Aug 16 05:07:14 PM PDT 24
Peak memory 200924 kb
Host smart-d951639a-cbdc-4582-be92-346d807070d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956386555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3956386555
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2248581906
Short name T293
Test name
Test status
Simulation time 152759310196 ps
CPU time 72.25 seconds
Started Aug 16 05:06:42 PM PDT 24
Finished Aug 16 05:07:55 PM PDT 24
Peak memory 200896 kb
Host smart-1184d32e-9441-4f3f-b53f-19cdc64e560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248581906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2248581906
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3323185380
Short name T587
Test name
Test status
Simulation time 50335344446 ps
CPU time 27.13 seconds
Started Aug 16 05:06:47 PM PDT 24
Finished Aug 16 05:07:14 PM PDT 24
Peak memory 200792 kb
Host smart-d524b171-5e26-4aa2-a1cf-e1336e1eb564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323185380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3323185380
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3371101635
Short name T677
Test name
Test status
Simulation time 116968350663 ps
CPU time 33.54 seconds
Started Aug 16 05:06:43 PM PDT 24
Finished Aug 16 05:07:16 PM PDT 24
Peak memory 200776 kb
Host smart-288778ea-47c8-44a1-b7b3-730fd57e81ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371101635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3371101635
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3352075140
Short name T189
Test name
Test status
Simulation time 129820183062 ps
CPU time 42.64 seconds
Started Aug 16 05:06:44 PM PDT 24
Finished Aug 16 05:07:27 PM PDT 24
Peak memory 200824 kb
Host smart-2777e6ff-97b1-4c65-8848-b3369195c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352075140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3352075140
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.70108944
Short name T130
Test name
Test status
Simulation time 36029863566 ps
CPU time 31.16 seconds
Started Aug 16 05:06:43 PM PDT 24
Finished Aug 16 05:07:15 PM PDT 24
Peak memory 199632 kb
Host smart-a11f2c7c-c7ef-41a7-82e3-8b57fe0c5007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70108944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.70108944
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3540788470
Short name T564
Test name
Test status
Simulation time 37514015 ps
CPU time 0.57 seconds
Started Aug 16 05:03:06 PM PDT 24
Finished Aug 16 05:03:07 PM PDT 24
Peak memory 196132 kb
Host smart-c6bbfcf4-6bb7-41d0-9247-c321ac4df045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540788470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3540788470
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2688685195
Short name T989
Test name
Test status
Simulation time 127469466936 ps
CPU time 28.36 seconds
Started Aug 16 05:03:01 PM PDT 24
Finished Aug 16 05:03:29 PM PDT 24
Peak memory 200904 kb
Host smart-48e56b01-b668-4b52-8960-4a8898c6619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688685195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2688685195
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3331013300
Short name T861
Test name
Test status
Simulation time 54724619901 ps
CPU time 101.84 seconds
Started Aug 16 05:02:59 PM PDT 24
Finished Aug 16 05:04:41 PM PDT 24
Peak memory 200856 kb
Host smart-0ad38655-e01f-4222-a7ee-6492e0029cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331013300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3331013300
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1862615784
Short name T589
Test name
Test status
Simulation time 19723090731 ps
CPU time 31.01 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:31 PM PDT 24
Peak memory 200704 kb
Host smart-eaa05ac5-d2d1-47d3-9333-a0f648174ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862615784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1862615784
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3614989335
Short name T415
Test name
Test status
Simulation time 67625216083 ps
CPU time 304.63 seconds
Started Aug 16 05:03:11 PM PDT 24
Finished Aug 16 05:08:15 PM PDT 24
Peak memory 200892 kb
Host smart-b60667d4-0dd5-4719-afd7-c37266d66c89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614989335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3614989335
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4048932376
Short name T1063
Test name
Test status
Simulation time 8203703020 ps
CPU time 8.13 seconds
Started Aug 16 05:03:09 PM PDT 24
Finished Aug 16 05:03:18 PM PDT 24
Peak memory 199740 kb
Host smart-943c2f2e-03da-4082-8328-6980fdea4011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048932376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4048932376
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1673079053
Short name T426
Test name
Test status
Simulation time 57469715907 ps
CPU time 39.07 seconds
Started Aug 16 05:03:05 PM PDT 24
Finished Aug 16 05:03:44 PM PDT 24
Peak memory 200416 kb
Host smart-b9404d11-69a2-4661-82fc-032ac77cbc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673079053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1673079053
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2789274930
Short name T723
Test name
Test status
Simulation time 8486149238 ps
CPU time 94.25 seconds
Started Aug 16 05:03:06 PM PDT 24
Finished Aug 16 05:04:41 PM PDT 24
Peak memory 200904 kb
Host smart-8212a0be-1a5d-4a5b-8a29-60a44a0ed583
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789274930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2789274930
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.533620960
Short name T578
Test name
Test status
Simulation time 3613127417 ps
CPU time 7.51 seconds
Started Aug 16 05:03:08 PM PDT 24
Finished Aug 16 05:03:16 PM PDT 24
Peak memory 199108 kb
Host smart-455ff000-728b-4301-98a6-a6fd2dbec670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533620960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.533620960
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.726852855
Short name T572
Test name
Test status
Simulation time 92408184965 ps
CPU time 118.35 seconds
Started Aug 16 05:03:07 PM PDT 24
Finished Aug 16 05:05:06 PM PDT 24
Peak memory 200876 kb
Host smart-ab953fc8-b46e-4379-b657-250e1d3edc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726852855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.726852855
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2358347630
Short name T916
Test name
Test status
Simulation time 2557184609 ps
CPU time 1.68 seconds
Started Aug 16 05:03:08 PM PDT 24
Finished Aug 16 05:03:09 PM PDT 24
Peak memory 197320 kb
Host smart-e0643510-ca90-4d0b-a0fa-3484a53aec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358347630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2358347630
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2415958363
Short name T1005
Test name
Test status
Simulation time 947761256 ps
CPU time 1.81 seconds
Started Aug 16 05:03:03 PM PDT 24
Finished Aug 16 05:03:05 PM PDT 24
Peak memory 200608 kb
Host smart-38d67954-a5bb-4744-ab44-86c2b0e61186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415958363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2415958363
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1293720226
Short name T145
Test name
Test status
Simulation time 23658868293 ps
CPU time 44.4 seconds
Started Aug 16 05:03:06 PM PDT 24
Finished Aug 16 05:03:51 PM PDT 24
Peak memory 200844 kb
Host smart-56c080be-afd4-4a17-bb64-f03d5ae40c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293720226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1293720226
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.906839725
Short name T1161
Test name
Test status
Simulation time 1819980910 ps
CPU time 19.71 seconds
Started Aug 16 05:03:07 PM PDT 24
Finished Aug 16 05:03:27 PM PDT 24
Peak memory 201104 kb
Host smart-7035d5c9-dc6b-4aa5-bc68-741943de5e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906839725 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.906839725
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.12251400
Short name T757
Test name
Test status
Simulation time 7318136368 ps
CPU time 8.07 seconds
Started Aug 16 05:03:09 PM PDT 24
Finished Aug 16 05:03:18 PM PDT 24
Peak memory 200828 kb
Host smart-435dcdaa-73f8-47ca-ae7d-52b26d473487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12251400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.12251400
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.221879998
Short name T949
Test name
Test status
Simulation time 85853096362 ps
CPU time 53.2 seconds
Started Aug 16 05:03:00 PM PDT 24
Finished Aug 16 05:03:53 PM PDT 24
Peak memory 200916 kb
Host smart-f2e6fdc6-fef0-4e69-8ad9-f20c680bd3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221879998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.221879998
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.756196125
Short name T159
Test name
Test status
Simulation time 130780947383 ps
CPU time 46.61 seconds
Started Aug 16 05:06:46 PM PDT 24
Finished Aug 16 05:07:33 PM PDT 24
Peak memory 200860 kb
Host smart-e694e716-8a1d-4b2a-a74c-695bd30d1124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756196125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.756196125
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3195351622
Short name T750
Test name
Test status
Simulation time 66452402411 ps
CPU time 30.61 seconds
Started Aug 16 05:06:50 PM PDT 24
Finished Aug 16 05:07:21 PM PDT 24
Peak memory 200916 kb
Host smart-af0612f9-15b6-4111-8740-80c25de049d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195351622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3195351622
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3350525292
Short name T178
Test name
Test status
Simulation time 50916888474 ps
CPU time 39.55 seconds
Started Aug 16 05:06:51 PM PDT 24
Finished Aug 16 05:07:31 PM PDT 24
Peak memory 200820 kb
Host smart-b0bc324b-8735-4c3e-b132-9e4b14cb380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350525292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3350525292
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1850648810
Short name T623
Test name
Test status
Simulation time 36911860607 ps
CPU time 20.99 seconds
Started Aug 16 05:06:50 PM PDT 24
Finished Aug 16 05:07:11 PM PDT 24
Peak memory 200872 kb
Host smart-cd480b0a-5382-4957-9be0-b7c105ef6d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850648810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1850648810
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4249678995
Short name T173
Test name
Test status
Simulation time 103204302351 ps
CPU time 164.89 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:09:37 PM PDT 24
Peak memory 200776 kb
Host smart-131e2a0a-ffbc-46b9-8e5e-8290e294fadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249678995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4249678995
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2737290018
Short name T117
Test name
Test status
Simulation time 15136262298 ps
CPU time 8.49 seconds
Started Aug 16 05:06:49 PM PDT 24
Finished Aug 16 05:06:58 PM PDT 24
Peak memory 200884 kb
Host smart-9db79fbd-fe1f-473e-b5d6-f2310320bc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737290018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2737290018
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.626564978
Short name T914
Test name
Test status
Simulation time 46567292523 ps
CPU time 57.48 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:07:50 PM PDT 24
Peak memory 200836 kb
Host smart-9e2bdf4e-4eb9-4abe-8d28-a7e1841a3306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626564978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.626564978
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1668989849
Short name T375
Test name
Test status
Simulation time 35859704 ps
CPU time 0.56 seconds
Started Aug 16 05:02:05 PM PDT 24
Finished Aug 16 05:02:05 PM PDT 24
Peak memory 195380 kb
Host smart-509102bd-f66d-49af-8766-c3e58773b5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668989849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1668989849
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3845489754
Short name T992
Test name
Test status
Simulation time 28002671187 ps
CPU time 9.24 seconds
Started Aug 16 05:01:54 PM PDT 24
Finished Aug 16 05:02:04 PM PDT 24
Peak memory 200844 kb
Host smart-398d799c-2bb3-4be6-aa1d-98f971df03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845489754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3845489754
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.735561881
Short name T577
Test name
Test status
Simulation time 90925528890 ps
CPU time 118.96 seconds
Started Aug 16 05:02:03 PM PDT 24
Finished Aug 16 05:04:02 PM PDT 24
Peak memory 200892 kb
Host smart-b59d9079-20e0-485d-8c4b-7be61998f477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735561881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.735561881
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1032811378
Short name T1132
Test name
Test status
Simulation time 139844607724 ps
CPU time 102.84 seconds
Started Aug 16 05:02:00 PM PDT 24
Finished Aug 16 05:03:43 PM PDT 24
Peak memory 200916 kb
Host smart-05e78810-7bdb-4520-9148-bb7c469f2b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032811378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1032811378
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2700578488
Short name T857
Test name
Test status
Simulation time 32467390334 ps
CPU time 14.85 seconds
Started Aug 16 05:02:05 PM PDT 24
Finished Aug 16 05:02:20 PM PDT 24
Peak memory 200908 kb
Host smart-00447824-6141-4727-b105-2e219c882adf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700578488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2700578488
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1627154457
Short name T584
Test name
Test status
Simulation time 102243778708 ps
CPU time 791.1 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:15:15 PM PDT 24
Peak memory 200920 kb
Host smart-507255c4-585a-4679-ac23-98f904acecc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627154457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1627154457
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.349657892
Short name T81
Test name
Test status
Simulation time 8403695009 ps
CPU time 6.64 seconds
Started Aug 16 05:02:03 PM PDT 24
Finished Aug 16 05:02:10 PM PDT 24
Peak memory 200008 kb
Host smart-869a472d-ed67-49d5-ad7f-5a438f74a7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349657892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.349657892
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1306622150
Short name T603
Test name
Test status
Simulation time 78754360336 ps
CPU time 195.99 seconds
Started Aug 16 05:02:01 PM PDT 24
Finished Aug 16 05:05:17 PM PDT 24
Peak memory 200988 kb
Host smart-1322ec17-211b-466a-a06a-c023feaee0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306622150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1306622150
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2520030973
Short name T362
Test name
Test status
Simulation time 12542653466 ps
CPU time 718.37 seconds
Started Aug 16 05:02:06 PM PDT 24
Finished Aug 16 05:14:05 PM PDT 24
Peak memory 200800 kb
Host smart-8854a70e-09f5-4b09-bf62-5aecf85317c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520030973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2520030973
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3065859595
Short name T381
Test name
Test status
Simulation time 2300833005 ps
CPU time 2.1 seconds
Started Aug 16 05:02:07 PM PDT 24
Finished Aug 16 05:02:09 PM PDT 24
Peak memory 199108 kb
Host smart-a2c284b7-3698-4f46-89e6-4d22abbffa39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065859595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3065859595
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4099244336
Short name T289
Test name
Test status
Simulation time 125704457116 ps
CPU time 51.9 seconds
Started Aug 16 05:02:00 PM PDT 24
Finished Aug 16 05:02:52 PM PDT 24
Peak memory 200992 kb
Host smart-f263ec34-f93b-4578-a0e1-9cd9dac1df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099244336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4099244336
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2886091287
Short name T443
Test name
Test status
Simulation time 27293648685 ps
CPU time 10.33 seconds
Started Aug 16 05:01:58 PM PDT 24
Finished Aug 16 05:02:08 PM PDT 24
Peak memory 196960 kb
Host smart-5e77d603-6696-43ad-8bca-57add64b7d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886091287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2886091287
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.745419713
Short name T74
Test name
Test status
Simulation time 130166847 ps
CPU time 0.78 seconds
Started Aug 16 05:02:05 PM PDT 24
Finished Aug 16 05:02:06 PM PDT 24
Peak memory 218768 kb
Host smart-f11e74af-898e-4eba-9aa3-bd65de89529f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745419713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.745419713
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1343662447
Short name T348
Test name
Test status
Simulation time 5368599179 ps
CPU time 22.91 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:02:14 PM PDT 24
Peak memory 200696 kb
Host smart-36552284-27f0-4c92-bbc8-15d679b7b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343662447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1343662447
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.999486945
Short name T1083
Test name
Test status
Simulation time 22753770701 ps
CPU time 33.33 seconds
Started Aug 16 05:02:05 PM PDT 24
Finished Aug 16 05:02:39 PM PDT 24
Peak memory 216500 kb
Host smart-8dd5629e-953e-4011-a7fc-e8a0735ee779
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999486945 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.999486945
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.659167644
Short name T1146
Test name
Test status
Simulation time 5652987029 ps
CPU time 1.66 seconds
Started Aug 16 05:01:59 PM PDT 24
Finished Aug 16 05:02:01 PM PDT 24
Peak memory 200768 kb
Host smart-4a2e976b-c91d-4b30-89bf-443da4df99ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659167644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.659167644
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2619602114
Short name T522
Test name
Test status
Simulation time 73935534275 ps
CPU time 99.06 seconds
Started Aug 16 05:01:52 PM PDT 24
Finished Aug 16 05:03:31 PM PDT 24
Peak memory 200852 kb
Host smart-d0f0b7f6-0a1e-4dfc-a029-cbd4a5d303ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619602114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2619602114
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3434474637
Short name T553
Test name
Test status
Simulation time 13946005 ps
CPU time 0.54 seconds
Started Aug 16 05:03:11 PM PDT 24
Finished Aug 16 05:03:11 PM PDT 24
Peak memory 196560 kb
Host smart-9d63315f-ff85-4ddc-a187-e067f20c9891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434474637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3434474637
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1549319824
Short name T543
Test name
Test status
Simulation time 22629667580 ps
CPU time 9.85 seconds
Started Aug 16 05:03:09 PM PDT 24
Finished Aug 16 05:03:19 PM PDT 24
Peak memory 200876 kb
Host smart-524a4cbf-f0c5-4044-b993-2d2e2e7c22d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549319824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1549319824
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1835242391
Short name T782
Test name
Test status
Simulation time 17120189324 ps
CPU time 29.86 seconds
Started Aug 16 05:03:09 PM PDT 24
Finished Aug 16 05:03:39 PM PDT 24
Peak memory 200896 kb
Host smart-eb394936-a01f-4151-a74f-70e1acd04326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835242391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1835242391
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2812889733
Short name T202
Test name
Test status
Simulation time 281276712958 ps
CPU time 68.15 seconds
Started Aug 16 05:03:09 PM PDT 24
Finished Aug 16 05:04:17 PM PDT 24
Peak memory 200824 kb
Host smart-affd0375-d5ec-48db-9659-330cc6d61d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812889733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2812889733
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1846097837
Short name T360
Test name
Test status
Simulation time 66520656600 ps
CPU time 11.94 seconds
Started Aug 16 05:03:11 PM PDT 24
Finished Aug 16 05:03:23 PM PDT 24
Peak memory 197080 kb
Host smart-5e518cb2-04b8-46bc-a911-4de51ed8dc46
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846097837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1846097837
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1916352879
Short name T1111
Test name
Test status
Simulation time 164551745625 ps
CPU time 132.72 seconds
Started Aug 16 05:03:05 PM PDT 24
Finished Aug 16 05:05:18 PM PDT 24
Peak memory 200904 kb
Host smart-2b0796b3-57f1-41ba-aea5-fcaf5e8e4c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916352879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1916352879
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1981075977
Short name T527
Test name
Test status
Simulation time 6988176382 ps
CPU time 7.23 seconds
Started Aug 16 05:03:06 PM PDT 24
Finished Aug 16 05:03:13 PM PDT 24
Peak memory 200788 kb
Host smart-dbbf56c1-4da9-4131-a82e-451dd37f7d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981075977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1981075977
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.622853168
Short name T600
Test name
Test status
Simulation time 58776339311 ps
CPU time 88.95 seconds
Started Aug 16 05:03:06 PM PDT 24
Finished Aug 16 05:04:36 PM PDT 24
Peak memory 200504 kb
Host smart-5f620fec-fd45-4343-b0c5-9c52f9bac0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622853168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.622853168
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1616272353
Short name T799
Test name
Test status
Simulation time 14677050480 ps
CPU time 835.91 seconds
Started Aug 16 05:03:07 PM PDT 24
Finished Aug 16 05:17:03 PM PDT 24
Peak memory 200920 kb
Host smart-4e47dd11-a976-488f-af85-8156da3ec923
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616272353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1616272353
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1169431915
Short name T1071
Test name
Test status
Simulation time 5389688743 ps
CPU time 23.2 seconds
Started Aug 16 05:03:05 PM PDT 24
Finished Aug 16 05:03:28 PM PDT 24
Peak memory 200076 kb
Host smart-2f711772-f47c-4cd7-9cf1-a8dbb724563b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169431915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1169431915
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2587240977
Short name T510
Test name
Test status
Simulation time 87673101433 ps
CPU time 143.42 seconds
Started Aug 16 05:03:11 PM PDT 24
Finished Aug 16 05:05:34 PM PDT 24
Peak memory 200968 kb
Host smart-37dcea28-918c-4a93-8036-2c115f5c40db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587240977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2587240977
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4163417256
Short name T431
Test name
Test status
Simulation time 3558304927 ps
CPU time 1.19 seconds
Started Aug 16 05:03:10 PM PDT 24
Finished Aug 16 05:03:12 PM PDT 24
Peak memory 197376 kb
Host smart-c25e95cc-c2b2-4410-8315-a9d404a55130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163417256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4163417256
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2390563860
Short name T1068
Test name
Test status
Simulation time 5591372173 ps
CPU time 5.37 seconds
Started Aug 16 05:03:06 PM PDT 24
Finished Aug 16 05:03:11 PM PDT 24
Peak memory 200116 kb
Host smart-c7e0d216-525a-45da-bf3e-1753f1cb24c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390563860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2390563860
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.163457186
Short name T691
Test name
Test status
Simulation time 107247345511 ps
CPU time 63.56 seconds
Started Aug 16 05:03:07 PM PDT 24
Finished Aug 16 05:04:11 PM PDT 24
Peak memory 200836 kb
Host smart-196b2002-2ed9-44c9-8ca6-4f9546fd7c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163457186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.163457186
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2957704295
Short name T642
Test name
Test status
Simulation time 4587996385 ps
CPU time 29.49 seconds
Started Aug 16 05:03:08 PM PDT 24
Finished Aug 16 05:03:38 PM PDT 24
Peak memory 217536 kb
Host smart-58f92ff3-de43-4e26-9c5e-29f36a570191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957704295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2957704295
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.4137267903
Short name T995
Test name
Test status
Simulation time 6966583967 ps
CPU time 24.92 seconds
Started Aug 16 05:03:05 PM PDT 24
Finished Aug 16 05:03:31 PM PDT 24
Peak memory 200672 kb
Host smart-f15466c3-3a4d-4706-bf3c-5c45afdbbb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137267903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.4137267903
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1766294909
Short name T906
Test name
Test status
Simulation time 81024236048 ps
CPU time 47.71 seconds
Started Aug 16 05:03:06 PM PDT 24
Finished Aug 16 05:03:54 PM PDT 24
Peak memory 200868 kb
Host smart-fd4edc5a-4587-47da-a598-18b98b6583fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766294909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1766294909
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.782264524
Short name T972
Test name
Test status
Simulation time 19994160650 ps
CPU time 28.5 seconds
Started Aug 16 05:06:53 PM PDT 24
Finished Aug 16 05:07:21 PM PDT 24
Peak memory 200912 kb
Host smart-667690db-46e0-4e46-b248-8707701ccef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782264524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.782264524
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2070926529
Short name T129
Test name
Test status
Simulation time 169229487187 ps
CPU time 70.66 seconds
Started Aug 16 05:06:50 PM PDT 24
Finished Aug 16 05:08:01 PM PDT 24
Peak memory 200912 kb
Host smart-a23b3bb9-9a97-45e9-99f5-a616fd598167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070926529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2070926529
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.619309137
Short name T222
Test name
Test status
Simulation time 46383234428 ps
CPU time 36.83 seconds
Started Aug 16 05:06:50 PM PDT 24
Finished Aug 16 05:07:27 PM PDT 24
Peak memory 200896 kb
Host smart-be2eddac-0f9d-4078-adb7-09f4ec8dbe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619309137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.619309137
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2698388387
Short name T137
Test name
Test status
Simulation time 35001066618 ps
CPU time 31.89 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:07:24 PM PDT 24
Peak memory 200828 kb
Host smart-3ed40bcb-82f0-4448-adfe-728fa2bf8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698388387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2698388387
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.78844022
Short name T195
Test name
Test status
Simulation time 52225299129 ps
CPU time 25.69 seconds
Started Aug 16 05:06:51 PM PDT 24
Finished Aug 16 05:07:17 PM PDT 24
Peak memory 200836 kb
Host smart-7b575abd-8740-404e-8773-ef105b49e10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78844022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.78844022
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.704950894
Short name T191
Test name
Test status
Simulation time 63304982817 ps
CPU time 94.72 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:08:26 PM PDT 24
Peak memory 200888 kb
Host smart-5ef117ce-ce91-49ea-a00e-7752d13c303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704950894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.704950894
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.941460711
Short name T342
Test name
Test status
Simulation time 24597923455 ps
CPU time 40.9 seconds
Started Aug 16 05:06:51 PM PDT 24
Finished Aug 16 05:07:32 PM PDT 24
Peak memory 200860 kb
Host smart-9ad66507-593a-4220-b8f6-da8e572afadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941460711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.941460711
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1051221083
Short name T172
Test name
Test status
Simulation time 90805933429 ps
CPU time 128.96 seconds
Started Aug 16 05:06:53 PM PDT 24
Finished Aug 16 05:09:02 PM PDT 24
Peak memory 200916 kb
Host smart-6f0d48e2-77a7-4ee5-8f32-4207e3474aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051221083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1051221083
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.688772020
Short name T500
Test name
Test status
Simulation time 26782825 ps
CPU time 0.58 seconds
Started Aug 16 05:03:22 PM PDT 24
Finished Aug 16 05:03:23 PM PDT 24
Peak memory 196476 kb
Host smart-399324fe-b87d-4ba5-b767-90fb617f5ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688772020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.688772020
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1330011720
Short name T315
Test name
Test status
Simulation time 133304721175 ps
CPU time 368.97 seconds
Started Aug 16 05:03:15 PM PDT 24
Finished Aug 16 05:09:24 PM PDT 24
Peak memory 200792 kb
Host smart-852e97a2-f607-4592-8289-41d852472f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330011720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1330011720
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2999427907
Short name T131
Test name
Test status
Simulation time 122971717012 ps
CPU time 228.8 seconds
Started Aug 16 05:03:15 PM PDT 24
Finished Aug 16 05:07:04 PM PDT 24
Peak memory 200932 kb
Host smart-1ad66832-f46c-448d-b02e-878d4c00a5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999427907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2999427907
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3255683819
Short name T788
Test name
Test status
Simulation time 245089275603 ps
CPU time 42.18 seconds
Started Aug 16 05:03:17 PM PDT 24
Finished Aug 16 05:03:59 PM PDT 24
Peak memory 200924 kb
Host smart-9cacfb9c-f319-4cdc-8002-6f2898032bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255683819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3255683819
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1066653320
Short name T896
Test name
Test status
Simulation time 44417703679 ps
CPU time 15.78 seconds
Started Aug 16 05:03:13 PM PDT 24
Finished Aug 16 05:03:29 PM PDT 24
Peak memory 200640 kb
Host smart-88cfbdfe-55e1-441d-9ac2-868f98d14b99
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066653320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1066653320
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.4247270456
Short name T83
Test name
Test status
Simulation time 84675652550 ps
CPU time 281.87 seconds
Started Aug 16 05:03:14 PM PDT 24
Finished Aug 16 05:07:56 PM PDT 24
Peak memory 200852 kb
Host smart-f92105d4-f68c-4aad-b454-88002931a7ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247270456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.4247270456
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2121174933
Short name T398
Test name
Test status
Simulation time 11228965464 ps
CPU time 8.56 seconds
Started Aug 16 05:03:17 PM PDT 24
Finished Aug 16 05:03:25 PM PDT 24
Peak memory 200876 kb
Host smart-9e28dd93-4d03-4be3-a0c0-ede26ac4ee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121174933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2121174933
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1644631179
Short name T492
Test name
Test status
Simulation time 74902765372 ps
CPU time 34.65 seconds
Started Aug 16 05:03:17 PM PDT 24
Finished Aug 16 05:03:51 PM PDT 24
Peak memory 198660 kb
Host smart-5151b168-2aec-494b-bad6-cc9ef1dbb345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644631179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1644631179
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.4235200579
Short name T647
Test name
Test status
Simulation time 10027259668 ps
CPU time 560.78 seconds
Started Aug 16 05:03:18 PM PDT 24
Finished Aug 16 05:12:39 PM PDT 24
Peak memory 200900 kb
Host smart-f5dfc878-9182-4be1-9afe-fdfcc136405a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235200579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.4235200579
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1132381573
Short name T462
Test name
Test status
Simulation time 4431116996 ps
CPU time 9.71 seconds
Started Aug 16 05:03:18 PM PDT 24
Finished Aug 16 05:03:27 PM PDT 24
Peak memory 199996 kb
Host smart-5bcea30f-7a5c-497f-94af-60aed577ce0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132381573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1132381573
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.992981349
Short name T151
Test name
Test status
Simulation time 142024396004 ps
CPU time 61.9 seconds
Started Aug 16 05:03:16 PM PDT 24
Finished Aug 16 05:04:18 PM PDT 24
Peak memory 200852 kb
Host smart-e7218874-8ed3-4058-9ae7-bd5ea4c87087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992981349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.992981349
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.4019350447
Short name T775
Test name
Test status
Simulation time 4355467382 ps
CPU time 7.45 seconds
Started Aug 16 05:03:18 PM PDT 24
Finished Aug 16 05:03:26 PM PDT 24
Peak memory 197380 kb
Host smart-9371191e-8bdd-43a0-a926-85c646866679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019350447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.4019350447
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1558776034
Short name T594
Test name
Test status
Simulation time 6011988568 ps
CPU time 33.34 seconds
Started Aug 16 05:03:14 PM PDT 24
Finished Aug 16 05:03:48 PM PDT 24
Peak memory 200796 kb
Host smart-fffe7026-a231-4577-b590-17e3ebb15b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558776034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1558776034
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2595914208
Short name T545
Test name
Test status
Simulation time 142090770033 ps
CPU time 941.64 seconds
Started Aug 16 05:03:21 PM PDT 24
Finished Aug 16 05:19:02 PM PDT 24
Peak memory 209276 kb
Host smart-6ab7124a-ccda-4e84-ba16-be0a82d400ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595914208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2595914208
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.921339576
Short name T734
Test name
Test status
Simulation time 16186593596 ps
CPU time 25.9 seconds
Started Aug 16 05:03:16 PM PDT 24
Finished Aug 16 05:03:42 PM PDT 24
Peak memory 216744 kb
Host smart-31d0639d-f178-40cf-bbe6-7a0e4d0998d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921339576 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.921339576
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4048730951
Short name T379
Test name
Test status
Simulation time 1091855538 ps
CPU time 4.19 seconds
Started Aug 16 05:03:21 PM PDT 24
Finished Aug 16 05:03:26 PM PDT 24
Peak memory 200748 kb
Host smart-0b61367f-7fe5-4275-893c-c3a0e587bda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048730951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4048730951
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2826465781
Short name T1072
Test name
Test status
Simulation time 5585381183 ps
CPU time 9.83 seconds
Started Aug 16 05:03:17 PM PDT 24
Finished Aug 16 05:03:27 PM PDT 24
Peak memory 200676 kb
Host smart-bb482506-33be-426a-adb6-28bfe89688b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826465781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2826465781
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2075362649
Short name T1043
Test name
Test status
Simulation time 97457188276 ps
CPU time 62.29 seconds
Started Aug 16 05:06:51 PM PDT 24
Finished Aug 16 05:07:54 PM PDT 24
Peak memory 200888 kb
Host smart-75db9681-c36a-4acb-b66c-e8c7249da5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075362649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2075362649
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2724270457
Short name T1176
Test name
Test status
Simulation time 185909628170 ps
CPU time 63.55 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:07:56 PM PDT 24
Peak memory 200796 kb
Host smart-c5ffac14-4bfb-43ff-a87b-41ae9bdd0241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724270457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2724270457
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2759839467
Short name T2
Test name
Test status
Simulation time 123749966621 ps
CPU time 47.72 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:07:40 PM PDT 24
Peak memory 200888 kb
Host smart-e1b12f42-d1eb-4db7-bf27-14601ec1ee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759839467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2759839467
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2063574849
Short name T211
Test name
Test status
Simulation time 19688246943 ps
CPU time 9.04 seconds
Started Aug 16 05:06:49 PM PDT 24
Finished Aug 16 05:06:59 PM PDT 24
Peak memory 200872 kb
Host smart-3b9086c4-5f35-4ea6-be04-1bcd8550249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063574849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2063574849
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.4088198305
Short name T826
Test name
Test status
Simulation time 35333162458 ps
CPU time 13.11 seconds
Started Aug 16 05:06:51 PM PDT 24
Finished Aug 16 05:07:04 PM PDT 24
Peak memory 200852 kb
Host smart-7eebbb09-534d-4e85-af46-458bb08192fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088198305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.4088198305
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.4077656127
Short name T170
Test name
Test status
Simulation time 27180253088 ps
CPU time 43.19 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:07:35 PM PDT 24
Peak memory 200924 kb
Host smart-2dbe21bd-f1cb-4157-bc76-f4aaf6557876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077656127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.4077656127
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3280000833
Short name T184
Test name
Test status
Simulation time 120004961427 ps
CPU time 48.78 seconds
Started Aug 16 05:06:51 PM PDT 24
Finished Aug 16 05:07:40 PM PDT 24
Peak memory 200908 kb
Host smart-0335617d-76e8-4536-a7b5-1251483d9689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280000833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3280000833
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4229852638
Short name T874
Test name
Test status
Simulation time 29988754503 ps
CPU time 42.72 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:07:35 PM PDT 24
Peak memory 200716 kb
Host smart-4ad096eb-2c23-4b39-a37e-77416facc022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229852638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4229852638
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2129484361
Short name T1022
Test name
Test status
Simulation time 34020788 ps
CPU time 0.56 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:03:25 PM PDT 24
Peak memory 196212 kb
Host smart-a9d6598b-8835-462b-8452-df604a8e5c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129484361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2129484361
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2831407341
Short name T168
Test name
Test status
Simulation time 234933409122 ps
CPU time 115.42 seconds
Started Aug 16 05:03:15 PM PDT 24
Finished Aug 16 05:05:11 PM PDT 24
Peak memory 201016 kb
Host smart-dbf57649-a95e-4b2b-b677-1719152aa8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831407341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2831407341
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1006517055
Short name T767
Test name
Test status
Simulation time 27692959317 ps
CPU time 36.73 seconds
Started Aug 16 05:03:15 PM PDT 24
Finished Aug 16 05:03:52 PM PDT 24
Peak memory 200692 kb
Host smart-d0e54a5b-b70f-4968-8335-7308163a0847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006517055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1006517055
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.484602775
Short name T712
Test name
Test status
Simulation time 77802771050 ps
CPU time 188.91 seconds
Started Aug 16 05:03:15 PM PDT 24
Finished Aug 16 05:06:24 PM PDT 24
Peak memory 200840 kb
Host smart-8ae848ee-a0df-4f4c-a864-ea5caa4c5aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484602775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.484602775
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3968074279
Short name T1113
Test name
Test status
Simulation time 10707568901 ps
CPU time 3.55 seconds
Started Aug 16 05:03:18 PM PDT 24
Finished Aug 16 05:03:22 PM PDT 24
Peak memory 200832 kb
Host smart-4fbaa7fe-ca4c-4c94-87fa-9b462c40d883
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968074279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3968074279
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3605106455
Short name T609
Test name
Test status
Simulation time 95507579508 ps
CPU time 188.22 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:06:31 PM PDT 24
Peak memory 200816 kb
Host smart-9d964449-bf24-4a56-9a93-531e92d5dce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605106455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3605106455
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2977474051
Short name T774
Test name
Test status
Simulation time 20288126 ps
CPU time 0.58 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:03:23 PM PDT 24
Peak memory 196556 kb
Host smart-0982d755-7744-41e2-924b-39094106bff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977474051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2977474051
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1184476338
Short name T301
Test name
Test status
Simulation time 51868991666 ps
CPU time 46.7 seconds
Started Aug 16 05:03:15 PM PDT 24
Finished Aug 16 05:04:02 PM PDT 24
Peak memory 200748 kb
Host smart-e7400a49-66e2-47df-b3a2-afd1082b1884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184476338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1184476338
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.796545105
Short name T653
Test name
Test status
Simulation time 11947478849 ps
CPU time 39.08 seconds
Started Aug 16 05:03:25 PM PDT 24
Finished Aug 16 05:04:04 PM PDT 24
Peak memory 200856 kb
Host smart-070de842-16ce-4231-8e14-44c0b6e3f0f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796545105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.796545105
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.4170783453
Short name T573
Test name
Test status
Simulation time 3711662495 ps
CPU time 33.54 seconds
Started Aug 16 05:03:20 PM PDT 24
Finished Aug 16 05:03:54 PM PDT 24
Peak memory 199424 kb
Host smart-56efb4cf-bbf9-4762-8701-f8224a1dbcc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170783453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4170783453
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1517960976
Short name T807
Test name
Test status
Simulation time 78462319560 ps
CPU time 111.83 seconds
Started Aug 16 05:03:25 PM PDT 24
Finished Aug 16 05:05:17 PM PDT 24
Peak memory 200908 kb
Host smart-87d75abf-07c8-475a-8fad-19135da7c675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517960976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1517960976
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3677706435
Short name T473
Test name
Test status
Simulation time 7372409073 ps
CPU time 3.66 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:03:28 PM PDT 24
Peak memory 197028 kb
Host smart-e73ef8ac-227e-40a3-81e7-8807f465cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677706435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3677706435
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2355895890
Short name T513
Test name
Test status
Simulation time 304041527 ps
CPU time 1.44 seconds
Started Aug 16 05:03:15 PM PDT 24
Finished Aug 16 05:03:16 PM PDT 24
Peak memory 200752 kb
Host smart-c3a15e89-4bfd-41a6-9839-3da1cdf42783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355895890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2355895890
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4248372119
Short name T347
Test name
Test status
Simulation time 156581468534 ps
CPU time 238.4 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:07:21 PM PDT 24
Peak memory 200860 kb
Host smart-56085f9c-dcea-4747-9dc6-1d6f47f4b3fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248372119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4248372119
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3566915698
Short name T1127
Test name
Test status
Simulation time 16313738898 ps
CPU time 64.92 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:04:28 PM PDT 24
Peak memory 217568 kb
Host smart-0c6d0b96-8ff2-4bdc-90cc-7c9600859ff3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566915698 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3566915698
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2984210945
Short name T927
Test name
Test status
Simulation time 1019653639 ps
CPU time 1.61 seconds
Started Aug 16 05:03:25 PM PDT 24
Finished Aug 16 05:03:27 PM PDT 24
Peak memory 199416 kb
Host smart-8646feda-a47b-4631-998d-04c3453a6f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984210945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2984210945
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4286258646
Short name T427
Test name
Test status
Simulation time 22508095110 ps
CPU time 32.69 seconds
Started Aug 16 05:03:20 PM PDT 24
Finished Aug 16 05:03:53 PM PDT 24
Peak memory 200888 kb
Host smart-b7fa5ea3-8486-4b8b-8eba-c36434463db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286258646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4286258646
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1424093914
Short name T741
Test name
Test status
Simulation time 70003477822 ps
CPU time 119.37 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:08:51 PM PDT 24
Peak memory 200868 kb
Host smart-a1ce062f-a011-4aa2-9fdf-f0fa9090a45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424093914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1424093914
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2628938518
Short name T684
Test name
Test status
Simulation time 115606956134 ps
CPU time 84.17 seconds
Started Aug 16 05:06:52 PM PDT 24
Finished Aug 16 05:08:16 PM PDT 24
Peak memory 200884 kb
Host smart-0e05b3f3-39ae-4b92-8ce5-af4a87108765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628938518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2628938518
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.52305158
Short name T333
Test name
Test status
Simulation time 129528025557 ps
CPU time 195.39 seconds
Started Aug 16 05:06:54 PM PDT 24
Finished Aug 16 05:10:10 PM PDT 24
Peak memory 200816 kb
Host smart-f629fc5d-fa43-47a4-8ebd-1c457c87ee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52305158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.52305158
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4043751502
Short name T212
Test name
Test status
Simulation time 40861629583 ps
CPU time 63.94 seconds
Started Aug 16 05:07:01 PM PDT 24
Finished Aug 16 05:08:06 PM PDT 24
Peak memory 200980 kb
Host smart-6a4245ca-eeb8-47e7-9e08-99e5dcad2243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043751502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4043751502
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3210568705
Short name T94
Test name
Test status
Simulation time 47503227716 ps
CPU time 22.55 seconds
Started Aug 16 05:07:09 PM PDT 24
Finished Aug 16 05:07:32 PM PDT 24
Peak memory 200896 kb
Host smart-659ca92d-0b24-4d4c-937a-f3615bd5c042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210568705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3210568705
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1814471359
Short name T1041
Test name
Test status
Simulation time 8721809002 ps
CPU time 14.91 seconds
Started Aug 16 05:07:04 PM PDT 24
Finished Aug 16 05:07:19 PM PDT 24
Peak memory 200688 kb
Host smart-5a72a5f2-789f-42f0-8448-3b84346878a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814471359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1814471359
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3859109039
Short name T615
Test name
Test status
Simulation time 49696083125 ps
CPU time 154.28 seconds
Started Aug 16 05:07:04 PM PDT 24
Finished Aug 16 05:09:38 PM PDT 24
Peak memory 200916 kb
Host smart-fccd6a91-bf42-452d-99ca-fc8b29511930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859109039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3859109039
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.233286746
Short name T626
Test name
Test status
Simulation time 24995613305 ps
CPU time 18.2 seconds
Started Aug 16 05:07:02 PM PDT 24
Finished Aug 16 05:07:21 PM PDT 24
Peak memory 200828 kb
Host smart-35aed0bc-10c7-4b45-afc2-7d393a5e51b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233286746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.233286746
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2461445450
Short name T190
Test name
Test status
Simulation time 33809800223 ps
CPU time 20.47 seconds
Started Aug 16 05:07:03 PM PDT 24
Finished Aug 16 05:07:24 PM PDT 24
Peak memory 200284 kb
Host smart-cf769e78-de6f-4868-8406-1d8d2152532b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461445450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2461445450
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.851783943
Short name T823
Test name
Test status
Simulation time 270743687172 ps
CPU time 168.08 seconds
Started Aug 16 05:07:03 PM PDT 24
Finished Aug 16 05:09:51 PM PDT 24
Peak memory 200184 kb
Host smart-2c962a0a-8256-472a-926d-8ff62ea31661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851783943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.851783943
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3501367705
Short name T436
Test name
Test status
Simulation time 12246252 ps
CPU time 0.58 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:03:24 PM PDT 24
Peak memory 196228 kb
Host smart-4f3b2d5a-1ba0-4268-96ab-d396a7491f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501367705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3501367705
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2614335203
Short name T699
Test name
Test status
Simulation time 176373471586 ps
CPU time 276.33 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:08:01 PM PDT 24
Peak memory 200824 kb
Host smart-98f029a8-1dcf-4e09-a960-77b2b9ba9273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614335203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2614335203
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1878753237
Short name T1066
Test name
Test status
Simulation time 34439038946 ps
CPU time 53.83 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:04:18 PM PDT 24
Peak memory 200836 kb
Host smart-1ea4b50c-9219-4c6f-a422-2952ecead407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878753237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1878753237
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.3315506469
Short name T1010
Test name
Test status
Simulation time 31809749669 ps
CPU time 55.49 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:04:19 PM PDT 24
Peak memory 200872 kb
Host smart-d2b70674-a38f-418e-8a21-4070aa9b3411
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315506469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3315506469
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.923705028
Short name T763
Test name
Test status
Simulation time 126604520357 ps
CPU time 372.45 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:09:36 PM PDT 24
Peak memory 200884 kb
Host smart-07d87ca9-c960-4699-a0ed-978d453bdb3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923705028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.923705028
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1646721873
Short name T769
Test name
Test status
Simulation time 7405748247 ps
CPU time 10.78 seconds
Started Aug 16 05:03:26 PM PDT 24
Finished Aug 16 05:03:37 PM PDT 24
Peak memory 200752 kb
Host smart-da2862ad-5663-4098-b0d8-564164c33c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646721873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1646721873
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3143905913
Short name T999
Test name
Test status
Simulation time 115788128947 ps
CPU time 99.2 seconds
Started Aug 16 05:03:22 PM PDT 24
Finished Aug 16 05:05:02 PM PDT 24
Peak memory 201180 kb
Host smart-e054431b-d477-492d-9c9d-020cc95642c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143905913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3143905913
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2134695076
Short name T1106
Test name
Test status
Simulation time 14275381181 ps
CPU time 481.59 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 200828 kb
Host smart-e6f5e48d-a952-4cf0-93e1-80da5f1dbf24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134695076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2134695076
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4129562543
Short name T1025
Test name
Test status
Simulation time 2026947253 ps
CPU time 6.34 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:03:31 PM PDT 24
Peak memory 199876 kb
Host smart-8cc1664c-157d-44f4-b98e-14e164222fcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129562543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4129562543
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1317701789
Short name T608
Test name
Test status
Simulation time 70804193117 ps
CPU time 24.37 seconds
Started Aug 16 05:03:25 PM PDT 24
Finished Aug 16 05:03:50 PM PDT 24
Peak memory 200836 kb
Host smart-307bc2ce-9553-49f9-9175-f7a73e26b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317701789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1317701789
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3421431724
Short name T479
Test name
Test status
Simulation time 2582402920 ps
CPU time 2.66 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:03:26 PM PDT 24
Peak memory 196896 kb
Host smart-6a4bba3b-dbae-411c-b130-c580e528e07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421431724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3421431724
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.124321396
Short name T286
Test name
Test status
Simulation time 512201214 ps
CPU time 1.7 seconds
Started Aug 16 05:03:25 PM PDT 24
Finished Aug 16 05:03:26 PM PDT 24
Peak memory 200496 kb
Host smart-46cb57b8-e09a-4e42-9e58-5d1c722c5038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124321396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.124321396
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2584203554
Short name T344
Test name
Test status
Simulation time 6058723735 ps
CPU time 6.52 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:03:30 PM PDT 24
Peak memory 200884 kb
Host smart-31bbff41-2bcc-4155-ab98-49ba230249a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584203554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2584203554
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1397700786
Short name T867
Test name
Test status
Simulation time 40272960864 ps
CPU time 23.48 seconds
Started Aug 16 05:03:27 PM PDT 24
Finished Aug 16 05:03:50 PM PDT 24
Peak memory 200904 kb
Host smart-d6e54a76-642c-4e43-b627-645c4ad374d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397700786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1397700786
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1086087628
Short name T180
Test name
Test status
Simulation time 46633405702 ps
CPU time 156.2 seconds
Started Aug 16 05:07:02 PM PDT 24
Finished Aug 16 05:09:39 PM PDT 24
Peak memory 200916 kb
Host smart-7765adb7-d38d-4d54-97ee-ea748e3f32ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086087628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1086087628
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2414652380
Short name T749
Test name
Test status
Simulation time 40873105733 ps
CPU time 38.92 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:07:49 PM PDT 24
Peak memory 200888 kb
Host smart-b0b8a7cd-2117-4751-b943-b6e791c2e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414652380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2414652380
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2464583929
Short name T969
Test name
Test status
Simulation time 25834250804 ps
CPU time 61.68 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:08:11 PM PDT 24
Peak memory 200828 kb
Host smart-98f81e14-899f-4ba5-ae9d-99e93bf316eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464583929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2464583929
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.920259385
Short name T785
Test name
Test status
Simulation time 81349081471 ps
CPU time 25.98 seconds
Started Aug 16 05:07:04 PM PDT 24
Finished Aug 16 05:07:30 PM PDT 24
Peak memory 200868 kb
Host smart-f66d7460-b44d-42d7-8750-248827e3d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920259385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.920259385
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1943851787
Short name T324
Test name
Test status
Simulation time 8168142635 ps
CPU time 13.07 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:07:23 PM PDT 24
Peak memory 200912 kb
Host smart-f516926d-b278-454b-b0b7-cba570ef6294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943851787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1943851787
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2369320877
Short name T512
Test name
Test status
Simulation time 131242892667 ps
CPU time 81.4 seconds
Started Aug 16 05:07:03 PM PDT 24
Finished Aug 16 05:08:25 PM PDT 24
Peak memory 200908 kb
Host smart-2fda5520-024e-44fd-a1d1-8f85aa7b859e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369320877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2369320877
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2225253688
Short name T629
Test name
Test status
Simulation time 149517837651 ps
CPU time 62.39 seconds
Started Aug 16 05:07:01 PM PDT 24
Finished Aug 16 05:08:04 PM PDT 24
Peak memory 200896 kb
Host smart-c7adbf28-2a60-4c02-a439-6775ca868b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225253688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2225253688
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1965710446
Short name T126
Test name
Test status
Simulation time 13437240392 ps
CPU time 21.2 seconds
Started Aug 16 05:07:03 PM PDT 24
Finished Aug 16 05:07:24 PM PDT 24
Peak memory 200952 kb
Host smart-50f138ea-7b7d-42bb-8ab6-415fc3332435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965710446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1965710446
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4140601975
Short name T595
Test name
Test status
Simulation time 10638520 ps
CPU time 0.55 seconds
Started Aug 16 05:03:29 PM PDT 24
Finished Aug 16 05:03:30 PM PDT 24
Peak memory 195176 kb
Host smart-4678e7bd-ec24-496f-a6bf-c116c33888a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140601975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4140601975
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1378905113
Short name T900
Test name
Test status
Simulation time 40830651970 ps
CPU time 65.56 seconds
Started Aug 16 05:03:25 PM PDT 24
Finished Aug 16 05:04:31 PM PDT 24
Peak memory 200856 kb
Host smart-c6a8c013-4a54-461f-bf75-6a07c6e80d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378905113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1378905113
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2283059234
Short name T1055
Test name
Test status
Simulation time 23883871630 ps
CPU time 34.61 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:03:58 PM PDT 24
Peak memory 200892 kb
Host smart-f1c50d12-33de-4a83-931f-4290524d7b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283059234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2283059234
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2770971840
Short name T1135
Test name
Test status
Simulation time 69754598008 ps
CPU time 32.14 seconds
Started Aug 16 05:03:25 PM PDT 24
Finished Aug 16 05:03:57 PM PDT 24
Peak memory 200908 kb
Host smart-d5f4dd5b-ac9b-414a-abe2-b227c924c647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770971840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2770971840
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1434152804
Short name T690
Test name
Test status
Simulation time 107039053158 ps
CPU time 436.6 seconds
Started Aug 16 05:03:29 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 200864 kb
Host smart-45a8bf75-42e0-4475-90c4-d98cc800b740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434152804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1434152804
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1768251139
Short name T377
Test name
Test status
Simulation time 10506842254 ps
CPU time 17.28 seconds
Started Aug 16 05:03:30 PM PDT 24
Finished Aug 16 05:03:48 PM PDT 24
Peak memory 200792 kb
Host smart-44adac85-544d-4dcd-8c45-3b81a634075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768251139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1768251139
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3174633752
Short name T567
Test name
Test status
Simulation time 29692463527 ps
CPU time 49.46 seconds
Started Aug 16 05:03:31 PM PDT 24
Finished Aug 16 05:04:21 PM PDT 24
Peak memory 199920 kb
Host smart-f40aadb4-48b9-41a8-9d42-b92a16d0141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174633752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3174633752
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3468991351
Short name T332
Test name
Test status
Simulation time 19900002827 ps
CPU time 228.49 seconds
Started Aug 16 05:03:30 PM PDT 24
Finished Aug 16 05:07:19 PM PDT 24
Peak memory 200900 kb
Host smart-37e28686-09d8-4fa2-ba63-a124a77dae2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3468991351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3468991351
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1864878759
Short name T1093
Test name
Test status
Simulation time 4011161251 ps
CPU time 28.16 seconds
Started Aug 16 05:03:23 PM PDT 24
Finished Aug 16 05:03:51 PM PDT 24
Peak memory 198984 kb
Host smart-9031d5d4-ce36-4346-89ab-60711e81ab79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864878759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1864878759
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2214371051
Short name T1104
Test name
Test status
Simulation time 106101057016 ps
CPU time 151.63 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:06:13 PM PDT 24
Peak memory 200916 kb
Host smart-7584aa33-7f5f-4d9a-a0d1-6e7eb199130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214371051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2214371051
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1422008816
Short name T855
Test name
Test status
Simulation time 52347857316 ps
CPU time 19.62 seconds
Started Aug 16 05:03:31 PM PDT 24
Finished Aug 16 05:03:51 PM PDT 24
Peak memory 195784 kb
Host smart-a9c43b10-c349-4971-ba04-64cb97e2e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422008816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1422008816
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2730567020
Short name T864
Test name
Test status
Simulation time 247785609 ps
CPU time 1.41 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:03:26 PM PDT 24
Peak memory 199124 kb
Host smart-d9962b1c-04b2-4953-8c3c-de573f4ae600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730567020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2730567020
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.4273557976
Short name T911
Test name
Test status
Simulation time 75800596003 ps
CPU time 143.18 seconds
Started Aug 16 05:03:41 PM PDT 24
Finished Aug 16 05:06:04 PM PDT 24
Peak memory 200904 kb
Host smart-2863c897-9777-4533-8cfe-e50c1b599357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273557976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.4273557976
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3182431147
Short name T917
Test name
Test status
Simulation time 13023224553 ps
CPU time 36.46 seconds
Started Aug 16 05:03:32 PM PDT 24
Finished Aug 16 05:04:08 PM PDT 24
Peak memory 209348 kb
Host smart-a3dc1b23-1919-4ba4-86a6-07e87b089ac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182431147 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3182431147
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.540042784
Short name T1084
Test name
Test status
Simulation time 697718264 ps
CPU time 1.47 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:03:44 PM PDT 24
Peak memory 199808 kb
Host smart-c5600e69-3844-4251-8c92-3e274071f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540042784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.540042784
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3842861747
Short name T457
Test name
Test status
Simulation time 95929494066 ps
CPU time 16.56 seconds
Started Aug 16 05:03:24 PM PDT 24
Finished Aug 16 05:03:41 PM PDT 24
Peak memory 200896 kb
Host smart-2b893680-437b-4abd-bd5b-3a8318a04693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842861747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3842861747
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3501253044
Short name T233
Test name
Test status
Simulation time 154374613195 ps
CPU time 67.51 seconds
Started Aug 16 05:07:03 PM PDT 24
Finished Aug 16 05:08:10 PM PDT 24
Peak memory 200828 kb
Host smart-ab2dadf2-ae60-4035-a476-709dba93f1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501253044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3501253044
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.588872166
Short name T617
Test name
Test status
Simulation time 30299672437 ps
CPU time 11.8 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:07:22 PM PDT 24
Peak memory 200920 kb
Host smart-d27835da-1053-4722-b8ea-45f0ebec2e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588872166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.588872166
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1916601287
Short name T1001
Test name
Test status
Simulation time 166351455917 ps
CPU time 66.21 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:08:21 PM PDT 24
Peak memory 200820 kb
Host smart-d44b2755-6fc1-44a2-9588-ca7f11313985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916601287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1916601287
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3650527982
Short name T1164
Test name
Test status
Simulation time 53507747603 ps
CPU time 22.4 seconds
Started Aug 16 05:07:03 PM PDT 24
Finished Aug 16 05:07:25 PM PDT 24
Peak memory 201024 kb
Host smart-e3053016-42aa-4522-a7ce-ea839e4a0a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650527982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3650527982
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1655348959
Short name T746
Test name
Test status
Simulation time 121752902227 ps
CPU time 42.22 seconds
Started Aug 16 05:07:01 PM PDT 24
Finished Aug 16 05:07:44 PM PDT 24
Peak memory 200912 kb
Host smart-a450da20-2c01-4c89-85ad-2f1749bc3040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655348959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1655348959
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1239539832
Short name T812
Test name
Test status
Simulation time 164638324448 ps
CPU time 136.99 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:09:27 PM PDT 24
Peak memory 200956 kb
Host smart-bebddf09-3b0a-4123-96ba-0b27ea56847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239539832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1239539832
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.4277203024
Short name T1129
Test name
Test status
Simulation time 23295606785 ps
CPU time 13.74 seconds
Started Aug 16 05:07:03 PM PDT 24
Finished Aug 16 05:07:17 PM PDT 24
Peak memory 200976 kb
Host smart-7be92dd4-7bb5-4018-b206-d032bc075891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277203024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.4277203024
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2453676881
Short name T532
Test name
Test status
Simulation time 8942812288 ps
CPU time 4.84 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:07:15 PM PDT 24
Peak memory 199880 kb
Host smart-9be20b26-083e-473a-b1a4-9149b2461c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453676881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2453676881
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2998342990
Short name T162
Test name
Test status
Simulation time 14723998602 ps
CPU time 24.35 seconds
Started Aug 16 05:07:04 PM PDT 24
Finished Aug 16 05:07:29 PM PDT 24
Peak memory 200908 kb
Host smart-3f6d601e-a344-4d15-ba8c-373a93313978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998342990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2998342990
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_full.303947799
Short name T550
Test name
Test status
Simulation time 25485337997 ps
CPU time 24.08 seconds
Started Aug 16 05:03:30 PM PDT 24
Finished Aug 16 05:03:55 PM PDT 24
Peak memory 200908 kb
Host smart-5e663f21-384e-47c8-93ce-0ce3c9874128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303947799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.303947799
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.462969506
Short name T158
Test name
Test status
Simulation time 115694792124 ps
CPU time 17.8 seconds
Started Aug 16 05:03:31 PM PDT 24
Finished Aug 16 05:03:50 PM PDT 24
Peak memory 200804 kb
Host smart-db79865f-4421-4b18-9470-7f19e398775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462969506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.462969506
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.495357545
Short name T735
Test name
Test status
Simulation time 9652861165 ps
CPU time 12.8 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:03:55 PM PDT 24
Peak memory 200840 kb
Host smart-a06d56b3-cffc-4a31-911d-9fe443e83769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495357545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.495357545
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2904894392
Short name T1102
Test name
Test status
Simulation time 28440881306 ps
CPU time 8.77 seconds
Started Aug 16 05:03:31 PM PDT 24
Finished Aug 16 05:03:40 PM PDT 24
Peak memory 198860 kb
Host smart-4c6598e6-105a-4446-a9be-b739ee829bd7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904894392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2904894392
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3080425692
Short name T458
Test name
Test status
Simulation time 108814171186 ps
CPU time 287.26 seconds
Started Aug 16 05:03:40 PM PDT 24
Finished Aug 16 05:08:27 PM PDT 24
Peak memory 200912 kb
Host smart-dffd5b35-ce46-4cbb-aa4f-470f7e1f1761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080425692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3080425692
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2990231893
Short name T965
Test name
Test status
Simulation time 4807777611 ps
CPU time 7.79 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:03:47 PM PDT 24
Peak memory 198760 kb
Host smart-c6fc55bf-2a56-40e0-a34c-f195b018fbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990231893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2990231893
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.2194580749
Short name T858
Test name
Test status
Simulation time 1692972990 ps
CPU time 22.24 seconds
Started Aug 16 05:03:40 PM PDT 24
Finished Aug 16 05:04:02 PM PDT 24
Peak memory 200852 kb
Host smart-07bb19ea-1ebc-42d4-9659-925b29d77e38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194580749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2194580749
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3732892589
Short name T21
Test name
Test status
Simulation time 3590141520 ps
CPU time 13.78 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:03:56 PM PDT 24
Peak memory 199060 kb
Host smart-53b8140f-8aa2-4a8d-a819-e6eca227518f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732892589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3732892589
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2820714379
Short name T873
Test name
Test status
Simulation time 56521967910 ps
CPU time 53.62 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:04:33 PM PDT 24
Peak memory 200908 kb
Host smart-e5367e08-c81b-4469-8e52-6843a254b2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820714379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2820714379
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3752838348
Short name T1050
Test name
Test status
Simulation time 4734687701 ps
CPU time 7.54 seconds
Started Aug 16 05:03:38 PM PDT 24
Finished Aug 16 05:03:46 PM PDT 24
Peak memory 197400 kb
Host smart-2576755d-3f57-4af0-afa8-14d072a668a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752838348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3752838348
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2959046919
Short name T998
Test name
Test status
Simulation time 5545140923 ps
CPU time 7.67 seconds
Started Aug 16 05:03:43 PM PDT 24
Finished Aug 16 05:03:51 PM PDT 24
Peak memory 200780 kb
Host smart-9db62418-d66f-4a64-b570-b0b3ff5d41ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959046919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2959046919
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.155088666
Short name T783
Test name
Test status
Simulation time 301460765223 ps
CPU time 196.26 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:06:56 PM PDT 24
Peak memory 200944 kb
Host smart-11f40f5b-fd69-41e9-b0ab-62993d90f3e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155088666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.155088666
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.860467163
Short name T936
Test name
Test status
Simulation time 3625874653 ps
CPU time 27.33 seconds
Started Aug 16 05:03:38 PM PDT 24
Finished Aug 16 05:04:06 PM PDT 24
Peak memory 200824 kb
Host smart-b575b28c-d781-443e-9f74-6231dcf37a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860467163 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.860467163
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2528069440
Short name T1131
Test name
Test status
Simulation time 776003578 ps
CPU time 1.74 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:03:41 PM PDT 24
Peak memory 199660 kb
Host smart-ab91f4f7-9b71-4d4e-817a-a17090fe8c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528069440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2528069440
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2521088000
Short name T683
Test name
Test status
Simulation time 57846020308 ps
CPU time 80.71 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:05:02 PM PDT 24
Peak memory 200904 kb
Host smart-d16c929d-a95f-4c4e-8020-2567e5162f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521088000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2521088000
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2852157745
Short name T830
Test name
Test status
Simulation time 116475281479 ps
CPU time 33.78 seconds
Started Aug 16 05:07:03 PM PDT 24
Finished Aug 16 05:07:37 PM PDT 24
Peak memory 200828 kb
Host smart-2a34b19c-6e92-4031-94da-e07e112f3ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852157745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2852157745
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2931290840
Short name T877
Test name
Test status
Simulation time 27131916852 ps
CPU time 14.97 seconds
Started Aug 16 05:07:02 PM PDT 24
Finished Aug 16 05:07:18 PM PDT 24
Peak memory 200904 kb
Host smart-159b2775-c113-498e-a8cc-45bdbe95f4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931290840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2931290840
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2456846894
Short name T771
Test name
Test status
Simulation time 32329325087 ps
CPU time 53.6 seconds
Started Aug 16 05:07:12 PM PDT 24
Finished Aug 16 05:08:06 PM PDT 24
Peak memory 200644 kb
Host smart-8e0df116-2ec2-4a11-adbd-6c951b3904ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456846894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2456846894
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.468495253
Short name T524
Test name
Test status
Simulation time 144756662172 ps
CPU time 57.09 seconds
Started Aug 16 05:07:16 PM PDT 24
Finished Aug 16 05:08:13 PM PDT 24
Peak memory 200904 kb
Host smart-561fce1d-18cc-43f2-a73f-527bc14a9600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468495253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.468495253
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.250742714
Short name T200
Test name
Test status
Simulation time 91644274229 ps
CPU time 26.86 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:07:38 PM PDT 24
Peak memory 200676 kb
Host smart-06bb17cf-cb28-4559-b553-c6f52b1e6e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250742714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.250742714
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2896649005
Short name T199
Test name
Test status
Simulation time 22021022491 ps
CPU time 34.78 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:07:45 PM PDT 24
Peak memory 200840 kb
Host smart-b8b3d350-5b95-41d8-997e-d6a85dabef48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896649005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2896649005
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2332832765
Short name T631
Test name
Test status
Simulation time 94244436650 ps
CPU time 136.62 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:09:30 PM PDT 24
Peak memory 200900 kb
Host smart-8ac064fa-f9ae-4b3e-b53a-b787d107491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332832765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2332832765
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1991283879
Short name T811
Test name
Test status
Simulation time 50530575405 ps
CPU time 62.94 seconds
Started Aug 16 05:07:17 PM PDT 24
Finished Aug 16 05:08:20 PM PDT 24
Peak memory 200876 kb
Host smart-bd9f19a0-c59a-4427-b99e-b26cfd5e5bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991283879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1991283879
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4224257602
Short name T531
Test name
Test status
Simulation time 17895625 ps
CPU time 0.53 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:03:40 PM PDT 24
Peak memory 196212 kb
Host smart-db0b737a-4b55-4759-820d-eedcbddf9813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224257602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4224257602
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2458177451
Short name T822
Test name
Test status
Simulation time 48299400990 ps
CPU time 71.32 seconds
Started Aug 16 05:03:40 PM PDT 24
Finished Aug 16 05:04:52 PM PDT 24
Peak memory 200852 kb
Host smart-5bc562c3-ba9b-422f-8f79-28f8a9267b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458177451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2458177451
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3379458493
Short name T713
Test name
Test status
Simulation time 110277163233 ps
CPU time 136.31 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:05:56 PM PDT 24
Peak memory 200892 kb
Host smart-dfeea10a-3a09-48ab-957c-0ff97d538785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379458493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3379458493
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.285881031
Short name T1143
Test name
Test status
Simulation time 115260993169 ps
CPU time 530.55 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:12:32 PM PDT 24
Peak memory 200844 kb
Host smart-1ab10c21-38c2-45cc-9238-349e4e6c66af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285881031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.285881031
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2508241986
Short name T262
Test name
Test status
Simulation time 37519157225 ps
CPU time 59.85 seconds
Started Aug 16 05:03:43 PM PDT 24
Finished Aug 16 05:04:43 PM PDT 24
Peak memory 200916 kb
Host smart-8e426e3f-50b6-4a6e-9ecc-01a567a5180a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508241986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2508241986
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3344815054
Short name T1051
Test name
Test status
Simulation time 121213023766 ps
CPU time 926.16 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:19:08 PM PDT 24
Peak memory 200888 kb
Host smart-54fcc064-98b7-43e1-a304-5b201f661d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344815054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3344815054
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1234611466
Short name T752
Test name
Test status
Simulation time 4928372039 ps
CPU time 10.09 seconds
Started Aug 16 05:03:41 PM PDT 24
Finished Aug 16 05:03:51 PM PDT 24
Peak memory 200100 kb
Host smart-07af0390-2f23-4f5a-945a-c5e13f380061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234611466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1234611466
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3542748067
Short name T727
Test name
Test status
Simulation time 67183929574 ps
CPU time 25.37 seconds
Started Aug 16 05:03:37 PM PDT 24
Finished Aug 16 05:04:02 PM PDT 24
Peak memory 199600 kb
Host smart-d6a2a69f-9cc6-41b6-afd2-b6212e1051f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542748067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3542748067
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1518446347
Short name T1081
Test name
Test status
Simulation time 14469665958 ps
CPU time 212.46 seconds
Started Aug 16 05:03:41 PM PDT 24
Finished Aug 16 05:07:13 PM PDT 24
Peak memory 200840 kb
Host smart-1bcd5e75-76fd-4047-987c-609d834c4023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518446347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1518446347
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2829713603
Short name T372
Test name
Test status
Simulation time 1696579054 ps
CPU time 6.75 seconds
Started Aug 16 05:03:38 PM PDT 24
Finished Aug 16 05:03:44 PM PDT 24
Peak memory 198952 kb
Host smart-9f5cde53-6c4b-4d15-8cf8-d106262d8395
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829713603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2829713603
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.305138249
Short name T848
Test name
Test status
Simulation time 1595705471 ps
CPU time 1.32 seconds
Started Aug 16 05:03:38 PM PDT 24
Finished Aug 16 05:03:40 PM PDT 24
Peak memory 196352 kb
Host smart-b487972d-e26c-40be-8452-95223f9e2d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305138249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.305138249
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.384869697
Short name T328
Test name
Test status
Simulation time 5804794812 ps
CPU time 9.23 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:03:48 PM PDT 24
Peak memory 200808 kb
Host smart-d6897e90-a05f-4700-a087-ab24c04d4abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384869697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.384869697
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1114340128
Short name T164
Test name
Test status
Simulation time 155687586876 ps
CPU time 68.49 seconds
Started Aug 16 05:03:38 PM PDT 24
Finished Aug 16 05:04:47 PM PDT 24
Peak memory 200888 kb
Host smart-01418553-6a92-4e22-81cf-ecf895ac8adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114340128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1114340128
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.50460861
Short name T1002
Test name
Test status
Simulation time 15000429713 ps
CPU time 62.86 seconds
Started Aug 16 05:03:38 PM PDT 24
Finished Aug 16 05:04:41 PM PDT 24
Peak memory 217296 kb
Host smart-e02ecc57-ba69-4a29-9dec-6bbbb93ce54d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50460861 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.50460861
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2731177777
Short name T701
Test name
Test status
Simulation time 8776031394 ps
CPU time 12.3 seconds
Started Aug 16 05:03:40 PM PDT 24
Finished Aug 16 05:03:53 PM PDT 24
Peak memory 200340 kb
Host smart-47db1bc0-0c7c-4253-8945-16f1b734ca55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731177777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2731177777
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3583156478
Short name T236
Test name
Test status
Simulation time 80995619605 ps
CPU time 35.4 seconds
Started Aug 16 05:07:09 PM PDT 24
Finished Aug 16 05:07:45 PM PDT 24
Peak memory 200864 kb
Host smart-a5a0bc20-a0d4-4144-a4df-ae4d5c5e65b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583156478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3583156478
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.410591917
Short name T336
Test name
Test status
Simulation time 12285482774 ps
CPU time 17.29 seconds
Started Aug 16 05:07:13 PM PDT 24
Finished Aug 16 05:07:31 PM PDT 24
Peak memory 200664 kb
Host smart-43786c94-7c66-4b46-b940-7e41f135e822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410591917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.410591917
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.224580560
Short name T739
Test name
Test status
Simulation time 14048342414 ps
CPU time 23.66 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:07:35 PM PDT 24
Peak memory 200848 kb
Host smart-297ddcf3-c96c-4be9-8f0e-404e09bde0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224580560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.224580560
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.284647972
Short name T242
Test name
Test status
Simulation time 50760844275 ps
CPU time 25.3 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:07:36 PM PDT 24
Peak memory 200864 kb
Host smart-2dfe1c0d-4ca7-4da1-aef6-42f739d15ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284647972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.284647972
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3280262942
Short name T194
Test name
Test status
Simulation time 149310702013 ps
CPU time 203.34 seconds
Started Aug 16 05:07:13 PM PDT 24
Finished Aug 16 05:10:37 PM PDT 24
Peak memory 200908 kb
Host smart-cd3d082b-c8b8-4826-a966-63dd047cb892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280262942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3280262942
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1005944191
Short name T862
Test name
Test status
Simulation time 8465085018 ps
CPU time 16.84 seconds
Started Aug 16 05:07:12 PM PDT 24
Finished Aug 16 05:07:29 PM PDT 24
Peak memory 200928 kb
Host smart-6824bc19-e06c-4734-a960-8c9ef8b24b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005944191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1005944191
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2999976030
Short name T835
Test name
Test status
Simulation time 18557499866 ps
CPU time 15.92 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:07:30 PM PDT 24
Peak memory 199896 kb
Host smart-b42a8c0b-2ae2-4b10-91f6-1ad4217fe35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999976030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2999976030
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1309937640
Short name T964
Test name
Test status
Simulation time 131756998823 ps
CPU time 113.13 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:09:05 PM PDT 24
Peak memory 200912 kb
Host smart-a09ce942-9276-4142-abbb-5652ec6f8778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309937640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1309937640
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.593361188
Short name T959
Test name
Test status
Simulation time 11457823816 ps
CPU time 17.05 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:07:31 PM PDT 24
Peak memory 200912 kb
Host smart-d09fdfaa-43ae-4827-ad68-33558adc246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593361188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.593361188
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1954325977
Short name T606
Test name
Test status
Simulation time 50109746808 ps
CPU time 41.19 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:07:51 PM PDT 24
Peak memory 200900 kb
Host smart-0360d8c8-a1ae-41b9-9efc-d7c401c04d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954325977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1954325977
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3021025459
Short name T1045
Test name
Test status
Simulation time 13505879 ps
CPU time 0.58 seconds
Started Aug 16 05:03:45 PM PDT 24
Finished Aug 16 05:03:46 PM PDT 24
Peak memory 196132 kb
Host smart-a72b422a-c628-4b83-803d-eec9c7084eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021025459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3021025459
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1695085774
Short name T1167
Test name
Test status
Simulation time 126675018531 ps
CPU time 75.75 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:04:55 PM PDT 24
Peak memory 200940 kb
Host smart-6de96f12-fc5f-4208-b699-c968a2bb13b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695085774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1695085774
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3249959490
Short name T46
Test name
Test status
Simulation time 16839340924 ps
CPU time 28.8 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:04:08 PM PDT 24
Peak memory 200888 kb
Host smart-db695ee4-a7b9-479a-ab2a-2db77f45a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249959490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3249959490
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4055063071
Short name T1094
Test name
Test status
Simulation time 73962746163 ps
CPU time 109.57 seconds
Started Aug 16 05:03:42 PM PDT 24
Finished Aug 16 05:05:32 PM PDT 24
Peak memory 200832 kb
Host smart-3faeb74c-877a-4643-a1a3-e508a5b2bcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055063071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4055063071
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1686059085
Short name T1115
Test name
Test status
Simulation time 22454048390 ps
CPU time 34.96 seconds
Started Aug 16 05:03:45 PM PDT 24
Finished Aug 16 05:04:20 PM PDT 24
Peak memory 199768 kb
Host smart-31743ce6-950c-4711-9c35-4722d73dd34f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686059085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1686059085
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.953409269
Short name T282
Test name
Test status
Simulation time 146991389826 ps
CPU time 465.66 seconds
Started Aug 16 05:03:47 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 200844 kb
Host smart-3dc8036d-55bf-4959-9799-5eb25671070c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953409269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.953409269
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3211199513
Short name T373
Test name
Test status
Simulation time 6302526755 ps
CPU time 6.3 seconds
Started Aug 16 05:03:48 PM PDT 24
Finished Aug 16 05:03:54 PM PDT 24
Peak memory 199508 kb
Host smart-5d1211c4-23ec-490c-a683-973d080084a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211199513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3211199513
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.129057606
Short name T79
Test name
Test status
Simulation time 50503785267 ps
CPU time 13.82 seconds
Started Aug 16 05:03:48 PM PDT 24
Finished Aug 16 05:04:02 PM PDT 24
Peak memory 201008 kb
Host smart-c4c36afc-cd6b-4166-aaa4-ee3a998834a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129057606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.129057606
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1346579903
Short name T297
Test name
Test status
Simulation time 12588248427 ps
CPU time 149.06 seconds
Started Aug 16 05:03:45 PM PDT 24
Finished Aug 16 05:06:15 PM PDT 24
Peak memory 201024 kb
Host smart-20358fc5-560d-4020-ad5d-684075252c0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346579903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1346579903
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.211599850
Short name T385
Test name
Test status
Simulation time 3584593060 ps
CPU time 7.52 seconds
Started Aug 16 05:03:40 PM PDT 24
Finished Aug 16 05:03:48 PM PDT 24
Peak memory 199104 kb
Host smart-25de64b5-cf3f-4d74-a1af-7cd6c88942f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211599850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.211599850
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3872137354
Short name T429
Test name
Test status
Simulation time 6574992450 ps
CPU time 7.04 seconds
Started Aug 16 05:03:50 PM PDT 24
Finished Aug 16 05:03:57 PM PDT 24
Peak memory 200924 kb
Host smart-fceb15b8-a9de-494c-a724-d6ce9f2dc10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872137354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3872137354
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.655528736
Short name T428
Test name
Test status
Simulation time 43349524946 ps
CPU time 67.33 seconds
Started Aug 16 05:03:45 PM PDT 24
Finished Aug 16 05:04:53 PM PDT 24
Peak memory 197412 kb
Host smart-6b3e6218-63fd-46b1-bdb4-57fdbf480de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655528736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.655528736
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.4160274129
Short name T439
Test name
Test status
Simulation time 450701861 ps
CPU time 1.88 seconds
Started Aug 16 05:03:39 PM PDT 24
Finished Aug 16 05:03:41 PM PDT 24
Peak memory 200720 kb
Host smart-a3934806-9fa5-49fb-b205-e4281a845598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160274129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4160274129
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.585520809
Short name T47
Test name
Test status
Simulation time 205897592519 ps
CPU time 188.87 seconds
Started Aug 16 05:03:45 PM PDT 24
Finished Aug 16 05:06:54 PM PDT 24
Peak memory 200756 kb
Host smart-1fdb4e47-db70-4fe5-b0d6-8165c74bdbea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585520809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.585520809
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1963713503
Short name T18
Test name
Test status
Simulation time 1751485734 ps
CPU time 27.89 seconds
Started Aug 16 05:03:49 PM PDT 24
Finished Aug 16 05:04:17 PM PDT 24
Peak memory 216384 kb
Host smart-1f5a68d8-7e5e-4235-a173-8c0b3e8c9f98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963713503 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1963713503
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.4050723879
Short name T13
Test name
Test status
Simulation time 12264316537 ps
CPU time 33.19 seconds
Started Aug 16 05:03:50 PM PDT 24
Finished Aug 16 05:04:24 PM PDT 24
Peak memory 200924 kb
Host smart-2546bf1e-af3e-46e6-912e-33b1c915ba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050723879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.4050723879
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3930595447
Short name T285
Test name
Test status
Simulation time 52983306797 ps
CPU time 19.79 seconds
Started Aug 16 05:03:38 PM PDT 24
Finished Aug 16 05:03:58 PM PDT 24
Peak memory 200596 kb
Host smart-a608ba45-111d-4796-8413-9e46e5d27830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930595447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3930595447
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1846081556
Short name T365
Test name
Test status
Simulation time 77691941579 ps
CPU time 394.99 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:13:47 PM PDT 24
Peak memory 200860 kb
Host smart-fc39bdf5-da93-4086-9841-5add1b62b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846081556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1846081556
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2033523235
Short name T217
Test name
Test status
Simulation time 112496987731 ps
CPU time 21.5 seconds
Started Aug 16 05:07:12 PM PDT 24
Finished Aug 16 05:07:34 PM PDT 24
Peak memory 200876 kb
Host smart-5bc1022a-9597-4bb8-a616-39976b0e1cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033523235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2033523235
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3826029038
Short name T655
Test name
Test status
Simulation time 87326733748 ps
CPU time 124.74 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:09:16 PM PDT 24
Peak memory 200900 kb
Host smart-ae033da6-0c5b-4740-88d3-b86e32f5bd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826029038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3826029038
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.4213864242
Short name T744
Test name
Test status
Simulation time 13701258777 ps
CPU time 6.06 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:07:21 PM PDT 24
Peak memory 200912 kb
Host smart-7b52f54d-7a0f-4e73-989a-dcf3adc06138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213864242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.4213864242
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1594914714
Short name T940
Test name
Test status
Simulation time 13196509536 ps
CPU time 19.46 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:07:34 PM PDT 24
Peak memory 200740 kb
Host smart-d1acad3a-9444-4a59-a675-7ab49ee6ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594914714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1594914714
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3355314726
Short name T952
Test name
Test status
Simulation time 61376778333 ps
CPU time 57.79 seconds
Started Aug 16 05:07:12 PM PDT 24
Finished Aug 16 05:08:10 PM PDT 24
Peak memory 200736 kb
Host smart-e123d326-482b-41a3-9a08-0b832c54aa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355314726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3355314726
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2307193158
Short name T121
Test name
Test status
Simulation time 20176385154 ps
CPU time 10.85 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:07:25 PM PDT 24
Peak memory 200852 kb
Host smart-0a44223a-8ad3-4afb-a822-8ad8d7dfa676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307193158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2307193158
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1248178077
Short name T637
Test name
Test status
Simulation time 17289997872 ps
CPU time 33.86 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:07:45 PM PDT 24
Peak memory 200900 kb
Host smart-fbe8eeb7-efb3-486a-8f82-7b780d3af18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248178077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1248178077
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.563849031
Short name T395
Test name
Test status
Simulation time 11361074 ps
CPU time 0.58 seconds
Started Aug 16 05:03:56 PM PDT 24
Finished Aug 16 05:03:56 PM PDT 24
Peak memory 196496 kb
Host smart-ffc5093f-aa4c-4996-b6ec-0d0603ff67c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563849031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.563849031
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3750072856
Short name T602
Test name
Test status
Simulation time 145280538845 ps
CPU time 30.67 seconds
Started Aug 16 05:03:49 PM PDT 24
Finished Aug 16 05:04:19 PM PDT 24
Peak memory 200916 kb
Host smart-d48462b4-4b2c-47d2-b2ca-146cd57456f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750072856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3750072856
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3120837060
Short name T638
Test name
Test status
Simulation time 140743524658 ps
CPU time 56.02 seconds
Started Aug 16 05:03:49 PM PDT 24
Finished Aug 16 05:04:45 PM PDT 24
Peak memory 200872 kb
Host smart-e8578c45-af78-45f1-807c-ac9e58bc30fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120837060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3120837060
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4061542079
Short name T206
Test name
Test status
Simulation time 90757988849 ps
CPU time 74.37 seconds
Started Aug 16 05:03:46 PM PDT 24
Finished Aug 16 05:05:00 PM PDT 24
Peak memory 200860 kb
Host smart-92dc2a88-45a3-4caa-a46a-d9c436ddaf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061542079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4061542079
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3304666062
Short name T840
Test name
Test status
Simulation time 92309521346 ps
CPU time 55.61 seconds
Started Aug 16 05:03:45 PM PDT 24
Finished Aug 16 05:04:40 PM PDT 24
Peak memory 198752 kb
Host smart-0ec4197f-aae9-4ce4-9826-8f343350742d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304666062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3304666062
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2221862148
Short name T941
Test name
Test status
Simulation time 36265821050 ps
CPU time 92.32 seconds
Started Aug 16 05:03:47 PM PDT 24
Finished Aug 16 05:05:19 PM PDT 24
Peak memory 200844 kb
Host smart-9e902c34-b6f1-4cd6-84a8-e1a2e506ff4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221862148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2221862148
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1712577052
Short name T384
Test name
Test status
Simulation time 7924770340 ps
CPU time 14.78 seconds
Started Aug 16 05:03:49 PM PDT 24
Finished Aug 16 05:04:04 PM PDT 24
Peak memory 199624 kb
Host smart-76434a60-8702-47b8-83c1-5a23cc9294d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712577052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1712577052
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3507315026
Short name T1122
Test name
Test status
Simulation time 35290966450 ps
CPU time 59.01 seconds
Started Aug 16 05:03:46 PM PDT 24
Finished Aug 16 05:04:45 PM PDT 24
Peak memory 200968 kb
Host smart-ed4e0f26-992d-4e71-96aa-f9e64fda9eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507315026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3507315026
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.4221166250
Short name T330
Test name
Test status
Simulation time 9278758129 ps
CPU time 455.92 seconds
Started Aug 16 05:03:50 PM PDT 24
Finished Aug 16 05:11:26 PM PDT 24
Peak memory 200904 kb
Host smart-44ec169c-ba88-4772-ba2d-13b123c8032d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221166250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.4221166250
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3599755163
Short name T412
Test name
Test status
Simulation time 3704419063 ps
CPU time 25.26 seconds
Started Aug 16 05:03:45 PM PDT 24
Finished Aug 16 05:04:10 PM PDT 24
Peak memory 199336 kb
Host smart-5778da5b-23bf-4e26-8155-8478c410fa7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599755163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3599755163
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4223247060
Short name T1052
Test name
Test status
Simulation time 81556672262 ps
CPU time 66.54 seconds
Started Aug 16 05:03:48 PM PDT 24
Finished Aug 16 05:04:55 PM PDT 24
Peak memory 200760 kb
Host smart-db502f7d-b19f-40cc-a89d-a5337e80b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223247060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4223247060
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3244507941
Short name T912
Test name
Test status
Simulation time 6331434211 ps
CPU time 3.19 seconds
Started Aug 16 05:03:46 PM PDT 24
Finished Aug 16 05:03:49 PM PDT 24
Peak memory 197032 kb
Host smart-3ec6486d-bc93-4ea1-bbe0-63ed48efe4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244507941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3244507941
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.567513651
Short name T386
Test name
Test status
Simulation time 6197064483 ps
CPU time 10.73 seconds
Started Aug 16 05:03:48 PM PDT 24
Finished Aug 16 05:03:59 PM PDT 24
Peak memory 200664 kb
Host smart-e3aedbef-1b62-4d05-ab29-a6b25f597306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567513651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.567513651
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.822379783
Short name T23
Test name
Test status
Simulation time 3514186354 ps
CPU time 42.45 seconds
Started Aug 16 05:04:20 PM PDT 24
Finished Aug 16 05:05:03 PM PDT 24
Peak memory 216448 kb
Host smart-4774608c-3042-452d-a310-d241a5c5a871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822379783 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.822379783
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3602296071
Short name T962
Test name
Test status
Simulation time 7212650844 ps
CPU time 9.89 seconds
Started Aug 16 05:03:47 PM PDT 24
Finished Aug 16 05:03:57 PM PDT 24
Peak memory 200796 kb
Host smart-7e3dcbe9-0286-4ddc-9816-5b0ae3939ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602296071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3602296071
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3236706611
Short name T630
Test name
Test status
Simulation time 72590433460 ps
CPU time 29.24 seconds
Started Aug 16 05:03:45 PM PDT 24
Finished Aug 16 05:04:14 PM PDT 24
Peak memory 200840 kb
Host smart-20b01685-7ff0-4f80-a2af-f105d68511c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236706611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3236706611
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3931248049
Short name T625
Test name
Test status
Simulation time 138060231011 ps
CPU time 218.58 seconds
Started Aug 16 05:07:13 PM PDT 24
Finished Aug 16 05:10:51 PM PDT 24
Peak memory 200796 kb
Host smart-36f04667-fe3c-42f7-856f-a152aea77ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931248049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3931248049
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3337362419
Short name T215
Test name
Test status
Simulation time 382554429947 ps
CPU time 32.36 seconds
Started Aug 16 05:07:14 PM PDT 24
Finished Aug 16 05:07:47 PM PDT 24
Peak memory 200976 kb
Host smart-a1bde46c-1b72-400b-ac18-e874e829a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337362419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3337362419
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2581403270
Short name T176
Test name
Test status
Simulation time 164717497090 ps
CPU time 70.65 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:08:22 PM PDT 24
Peak memory 200848 kb
Host smart-41cd7676-6755-44c2-9a58-014ae27593c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581403270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2581403270
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.638271426
Short name T1017
Test name
Test status
Simulation time 14251169193 ps
CPU time 23.84 seconds
Started Aug 16 05:07:13 PM PDT 24
Finished Aug 16 05:07:37 PM PDT 24
Peak memory 200852 kb
Host smart-a9c0bfe7-d505-4e5b-a789-6832b0423102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638271426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.638271426
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3690421789
Short name T153
Test name
Test status
Simulation time 168959475388 ps
CPU time 270.73 seconds
Started Aug 16 05:07:11 PM PDT 24
Finished Aug 16 05:11:42 PM PDT 24
Peak memory 200632 kb
Host smart-7ac5acc1-4085-4e82-b0d0-35f4c190a503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690421789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3690421789
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3772092873
Short name T183
Test name
Test status
Simulation time 15082371630 ps
CPU time 14.97 seconds
Started Aug 16 05:07:10 PM PDT 24
Finished Aug 16 05:07:25 PM PDT 24
Peak memory 200824 kb
Host smart-6f38ea5b-4e04-4396-957f-cc35c99da4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772092873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3772092873
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1164356930
Short name T388
Test name
Test status
Simulation time 12970282 ps
CPU time 0.57 seconds
Started Aug 16 05:03:55 PM PDT 24
Finished Aug 16 05:03:56 PM PDT 24
Peak memory 195896 kb
Host smart-ea49de82-cd1d-443c-9741-6fa1c09fdef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164356930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1164356930
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3573239504
Short name T808
Test name
Test status
Simulation time 109479478948 ps
CPU time 164.38 seconds
Started Aug 16 05:03:56 PM PDT 24
Finished Aug 16 05:06:41 PM PDT 24
Peak memory 200904 kb
Host smart-0c038028-3fb0-4af3-9f2b-2bbe0f056a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573239504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3573239504
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2236474716
Short name T663
Test name
Test status
Simulation time 103194112693 ps
CPU time 20.97 seconds
Started Aug 16 05:03:53 PM PDT 24
Finished Aug 16 05:04:14 PM PDT 24
Peak memory 200940 kb
Host smart-46c1de7a-76b8-452f-8d09-3830c21bc402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236474716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2236474716
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.173577120
Short name T304
Test name
Test status
Simulation time 47712570160 ps
CPU time 41.67 seconds
Started Aug 16 05:03:55 PM PDT 24
Finished Aug 16 05:04:36 PM PDT 24
Peak memory 200900 kb
Host smart-503d440d-74f7-458b-bac5-a6f51bcf3ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173577120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.173577120
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2997155567
Short name T717
Test name
Test status
Simulation time 75561487548 ps
CPU time 32.34 seconds
Started Aug 16 05:03:53 PM PDT 24
Finished Aug 16 05:04:26 PM PDT 24
Peak memory 200736 kb
Host smart-4699b05d-93a1-43f5-ba18-6e2fd839534b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997155567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2997155567
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1522704347
Short name T432
Test name
Test status
Simulation time 45173818871 ps
CPU time 130.66 seconds
Started Aug 16 05:03:57 PM PDT 24
Finished Aug 16 05:06:08 PM PDT 24
Peak memory 200868 kb
Host smart-da7cfba0-cdfb-4e08-8a27-4d5cf02573d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522704347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1522704347
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4050264035
Short name T725
Test name
Test status
Simulation time 5761420539 ps
CPU time 5.34 seconds
Started Aug 16 05:03:56 PM PDT 24
Finished Aug 16 05:04:01 PM PDT 24
Peak memory 200604 kb
Host smart-c02bb733-3ed0-4abe-8feb-e1d91a3c7d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050264035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4050264035
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1052396997
Short name T1166
Test name
Test status
Simulation time 170603615997 ps
CPU time 70.63 seconds
Started Aug 16 05:04:14 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 200828 kb
Host smart-8e1027cd-b5ab-428d-94bf-b0ddbae5c35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052396997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1052396997
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.579749890
Short name T1070
Test name
Test status
Simulation time 3547590036 ps
CPU time 131.97 seconds
Started Aug 16 05:03:57 PM PDT 24
Finished Aug 16 05:06:09 PM PDT 24
Peak memory 200848 kb
Host smart-adcf204d-d58e-4d0d-9f1b-624dde9cc7eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579749890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.579749890
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2811371496
Short name T409
Test name
Test status
Simulation time 4644976419 ps
CPU time 9.79 seconds
Started Aug 16 05:03:52 PM PDT 24
Finished Aug 16 05:04:02 PM PDT 24
Peak memory 199636 kb
Host smart-6ce79dcc-9648-4e27-8a9f-020f8846b12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811371496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2811371496
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.217257692
Short name T1112
Test name
Test status
Simulation time 19535181367 ps
CPU time 10.98 seconds
Started Aug 16 05:03:56 PM PDT 24
Finished Aug 16 05:04:07 PM PDT 24
Peak memory 200592 kb
Host smart-eb9554b9-2ecd-45da-8b07-f26643f35317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217257692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.217257692
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2375212030
Short name T406
Test name
Test status
Simulation time 3154254428 ps
CPU time 2.86 seconds
Started Aug 16 05:03:53 PM PDT 24
Finished Aug 16 05:03:56 PM PDT 24
Peak memory 197420 kb
Host smart-62756a91-de9f-49cb-bf23-817535b8d8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375212030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2375212030
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.589952534
Short name T1015
Test name
Test status
Simulation time 105353057 ps
CPU time 0.89 seconds
Started Aug 16 05:03:54 PM PDT 24
Finished Aug 16 05:03:55 PM PDT 24
Peak memory 198560 kb
Host smart-c6df8fd7-17b9-409f-b4ca-83750f894e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589952534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.589952534
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2387620758
Short name T918
Test name
Test status
Simulation time 185779176033 ps
CPU time 1173.88 seconds
Started Aug 16 05:03:56 PM PDT 24
Finished Aug 16 05:23:30 PM PDT 24
Peak memory 200924 kb
Host smart-a87e4ac4-4240-49bf-90b2-c8f205278610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387620758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2387620758
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1434155440
Short name T302
Test name
Test status
Simulation time 16272662835 ps
CPU time 80.1 seconds
Started Aug 16 05:03:56 PM PDT 24
Finished Aug 16 05:05:16 PM PDT 24
Peak memory 217228 kb
Host smart-a9072b2b-16d9-4322-87f5-bf70da99b628
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434155440 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1434155440
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2781658668
Short name T274
Test name
Test status
Simulation time 932675047 ps
CPU time 3.05 seconds
Started Aug 16 05:03:54 PM PDT 24
Finished Aug 16 05:03:58 PM PDT 24
Peak memory 199780 kb
Host smart-c128b655-5a99-4452-805d-6f9498fe405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781658668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2781658668
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1394125292
Short name T1096
Test name
Test status
Simulation time 74326379289 ps
CPU time 16.48 seconds
Started Aug 16 05:03:53 PM PDT 24
Finished Aug 16 05:04:09 PM PDT 24
Peak memory 200976 kb
Host smart-6dcdd6f3-5201-47b8-8bc6-a32043326df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394125292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1394125292
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3075196422
Short name T219
Test name
Test status
Simulation time 41979085971 ps
CPU time 62.34 seconds
Started Aug 16 05:07:16 PM PDT 24
Finished Aug 16 05:08:18 PM PDT 24
Peak memory 200896 kb
Host smart-e4be70f1-5a25-4207-ad4a-3fe89cbcf479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075196422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3075196422
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2156443551
Short name T521
Test name
Test status
Simulation time 149987147731 ps
CPU time 297.28 seconds
Started Aug 16 05:07:20 PM PDT 24
Finished Aug 16 05:12:17 PM PDT 24
Peak memory 200872 kb
Host smart-90a68631-a86a-4f37-a1cf-21695052143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156443551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2156443551
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.53210511
Short name T197
Test name
Test status
Simulation time 103691298591 ps
CPU time 20.58 seconds
Started Aug 16 05:07:22 PM PDT 24
Finished Aug 16 05:07:42 PM PDT 24
Peak memory 200808 kb
Host smart-2856a1b1-4608-43ed-a677-08371fbf5ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53210511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.53210511
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1554420565
Short name T210
Test name
Test status
Simulation time 174454315555 ps
CPU time 290.05 seconds
Started Aug 16 05:07:17 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 200908 kb
Host smart-9a3d1e79-ecd3-444d-9b67-e5c64f20919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554420565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1554420565
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.234171717
Short name T561
Test name
Test status
Simulation time 47564840848 ps
CPU time 21.84 seconds
Started Aug 16 05:07:18 PM PDT 24
Finished Aug 16 05:07:40 PM PDT 24
Peak memory 200880 kb
Host smart-d0dda67d-aaf2-4db4-9eb2-8eea16d676f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234171717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.234171717
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2056668456
Short name T50
Test name
Test status
Simulation time 31943888614 ps
CPU time 23.29 seconds
Started Aug 16 05:07:20 PM PDT 24
Finished Aug 16 05:07:43 PM PDT 24
Peak memory 200776 kb
Host smart-cce0a256-7f89-493e-8eed-365ef1c35f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056668456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2056668456
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1603221695
Short name T148
Test name
Test status
Simulation time 33248046980 ps
CPU time 47.11 seconds
Started Aug 16 05:07:18 PM PDT 24
Finished Aug 16 05:08:05 PM PDT 24
Peak memory 200904 kb
Host smart-08226dd8-7033-4131-9eee-419e77cfea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603221695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1603221695
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2353437469
Short name T702
Test name
Test status
Simulation time 95109769059 ps
CPU time 30 seconds
Started Aug 16 05:07:20 PM PDT 24
Finished Aug 16 05:07:50 PM PDT 24
Peak memory 200824 kb
Host smart-049f425e-12cf-45e2-a944-e5fe87541750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353437469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2353437469
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1370513773
Short name T806
Test name
Test status
Simulation time 218495679678 ps
CPU time 45.56 seconds
Started Aug 16 05:07:18 PM PDT 24
Finished Aug 16 05:08:04 PM PDT 24
Peak memory 200904 kb
Host smart-cf8850a6-fcb3-4828-a91e-9300914e9da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370513773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1370513773
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.617911784
Short name T1149
Test name
Test status
Simulation time 13011346 ps
CPU time 0.58 seconds
Started Aug 16 05:02:01 PM PDT 24
Finished Aug 16 05:02:02 PM PDT 24
Peak memory 196212 kb
Host smart-8ad2143b-2df9-4917-bf4d-15b305696faa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617911784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.617911784
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1465835623
Short name T260
Test name
Test status
Simulation time 62824257061 ps
CPU time 25.89 seconds
Started Aug 16 05:02:01 PM PDT 24
Finished Aug 16 05:02:27 PM PDT 24
Peak memory 200916 kb
Host smart-56029c62-ec47-48d4-a247-647eb43ab530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465835623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1465835623
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2763470843
Short name T728
Test name
Test status
Simulation time 122642841398 ps
CPU time 45.71 seconds
Started Aug 16 05:02:00 PM PDT 24
Finished Aug 16 05:02:46 PM PDT 24
Peak memory 200844 kb
Host smart-cfee36fc-f1f3-4406-81c7-f7f74acb9688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763470843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2763470843
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1566292696
Short name T463
Test name
Test status
Simulation time 24237839384 ps
CPU time 11.83 seconds
Started Aug 16 05:02:08 PM PDT 24
Finished Aug 16 05:02:20 PM PDT 24
Peak memory 200932 kb
Host smart-52039bb6-4d7c-4137-8524-d05d5beccbf9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566292696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1566292696
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.131936938
Short name T866
Test name
Test status
Simulation time 58856199739 ps
CPU time 205.2 seconds
Started Aug 16 05:02:00 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 200896 kb
Host smart-63b771f4-bcbd-4ba0-b164-ae68ebbcfda8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131936938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.131936938
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2133648462
Short name T942
Test name
Test status
Simulation time 4641305161 ps
CPU time 5.95 seconds
Started Aug 16 05:01:59 PM PDT 24
Finished Aug 16 05:02:05 PM PDT 24
Peak memory 196712 kb
Host smart-37f83b4d-b4f6-49ee-a17d-84c5d63e5591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133648462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2133648462
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.367490015
Short name T1058
Test name
Test status
Simulation time 100378842185 ps
CPU time 87.12 seconds
Started Aug 16 05:01:59 PM PDT 24
Finished Aug 16 05:03:26 PM PDT 24
Peak memory 201104 kb
Host smart-028e178e-81f6-4c97-b45c-6fe0da171b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367490015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.367490015
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3549632388
Short name T1107
Test name
Test status
Simulation time 9316778136 ps
CPU time 416.56 seconds
Started Aug 16 05:01:58 PM PDT 24
Finished Aug 16 05:08:55 PM PDT 24
Peak memory 200888 kb
Host smart-9d9de46a-97e4-46a6-b489-fbc5b0edc3ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549632388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3549632388
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1549462098
Short name T378
Test name
Test status
Simulation time 6729060031 ps
CPU time 60.23 seconds
Started Aug 16 05:01:56 PM PDT 24
Finished Aug 16 05:02:56 PM PDT 24
Peak memory 199052 kb
Host smart-ecbaf00e-0f67-49d0-a87e-cbbcfcb91bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549462098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1549462098
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.851040809
Short name T843
Test name
Test status
Simulation time 18087818020 ps
CPU time 10.24 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:02:14 PM PDT 24
Peak memory 200860 kb
Host smart-b7e4e7a2-607c-4a78-8f65-61877ceb7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851040809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.851040809
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.979189387
Short name T1087
Test name
Test status
Simulation time 5956459738 ps
CPU time 3.19 seconds
Started Aug 16 05:01:59 PM PDT 24
Finished Aug 16 05:02:02 PM PDT 24
Peak memory 197396 kb
Host smart-ff5a72a3-81be-4d71-a9ed-61a1da1773f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979189387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.979189387
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.495818224
Short name T32
Test name
Test status
Simulation time 307735378 ps
CPU time 0.94 seconds
Started Aug 16 05:02:01 PM PDT 24
Finished Aug 16 05:02:02 PM PDT 24
Peak memory 220088 kb
Host smart-c6828757-e33e-4447-9a62-da703acca973
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495818224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.495818224
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2363168198
Short name T665
Test name
Test status
Simulation time 708976863 ps
CPU time 1.59 seconds
Started Aug 16 05:02:08 PM PDT 24
Finished Aug 16 05:02:10 PM PDT 24
Peak memory 199244 kb
Host smart-ad58fe46-0133-4f3d-89ff-24a55581cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363168198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2363168198
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1049792749
Short name T95
Test name
Test status
Simulation time 195121600612 ps
CPU time 84.94 seconds
Started Aug 16 05:02:02 PM PDT 24
Finished Aug 16 05:03:27 PM PDT 24
Peak memory 209272 kb
Host smart-afa33add-3620-4fac-825e-f97195a9b69b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049792749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1049792749
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1422946209
Short name T679
Test name
Test status
Simulation time 4574178257 ps
CPU time 25.04 seconds
Started Aug 16 05:02:03 PM PDT 24
Finished Aug 16 05:02:28 PM PDT 24
Peak memory 209376 kb
Host smart-3877ef2a-76d4-460d-8c1a-028cf01d5f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422946209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1422946209
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2733168746
Short name T265
Test name
Test status
Simulation time 422004218 ps
CPU time 1.81 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:02:06 PM PDT 24
Peak memory 199484 kb
Host smart-cf6e1efd-0ffb-45db-97a9-00599ff39d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733168746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2733168746
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3567386679
Short name T1028
Test name
Test status
Simulation time 13212987620 ps
CPU time 19.97 seconds
Started Aug 16 05:01:58 PM PDT 24
Finished Aug 16 05:02:18 PM PDT 24
Peak memory 200672 kb
Host smart-39a2ba12-3ff3-4dd1-abe4-51b9cc0ca8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567386679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3567386679
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3097720667
Short name T648
Test name
Test status
Simulation time 42311322 ps
CPU time 0.58 seconds
Started Aug 16 05:04:01 PM PDT 24
Finished Aug 16 05:04:02 PM PDT 24
Peak memory 195664 kb
Host smart-db07ad54-39de-40e6-86f5-42105d47517a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097720667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3097720667
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1716864584
Short name T576
Test name
Test status
Simulation time 104146504106 ps
CPU time 425.61 seconds
Started Aug 16 05:03:54 PM PDT 24
Finished Aug 16 05:10:59 PM PDT 24
Peak memory 200824 kb
Host smart-27e7e4ef-73b9-415e-9893-934d94aaf78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716864584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1716864584
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1989224051
Short name T128
Test name
Test status
Simulation time 70971077414 ps
CPU time 30.03 seconds
Started Aug 16 05:03:56 PM PDT 24
Finished Aug 16 05:04:26 PM PDT 24
Peak memory 200828 kb
Host smart-504fad49-9194-43cc-993f-5a427ef2ca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989224051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1989224051
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.1648884057
Short name T11
Test name
Test status
Simulation time 36655974203 ps
CPU time 29.16 seconds
Started Aug 16 05:04:01 PM PDT 24
Finished Aug 16 05:04:31 PM PDT 24
Peak memory 200888 kb
Host smart-5020c9bb-c027-4fd4-9c62-9d4cf2cf2d86
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648884057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1648884057
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_loopback.45845126
Short name T745
Test name
Test status
Simulation time 10594162486 ps
CPU time 6.08 seconds
Started Aug 16 05:04:02 PM PDT 24
Finished Aug 16 05:04:08 PM PDT 24
Peak memory 200536 kb
Host smart-2a1e1ec2-ad20-490e-890f-984aa0597fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45845126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.45845126
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3337595811
Short name T871
Test name
Test status
Simulation time 228386153095 ps
CPU time 98.72 seconds
Started Aug 16 05:04:02 PM PDT 24
Finished Aug 16 05:05:41 PM PDT 24
Peak memory 209080 kb
Host smart-b285349d-6c5f-4163-a5a2-2ba77ac93185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337595811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3337595811
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.734885888
Short name T1130
Test name
Test status
Simulation time 15208703762 ps
CPU time 98.73 seconds
Started Aug 16 05:04:02 PM PDT 24
Finished Aug 16 05:05:41 PM PDT 24
Peak memory 200852 kb
Host smart-2a8c51f0-a71b-4281-921b-16f9c24f7249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734885888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.734885888
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2348391727
Short name T82
Test name
Test status
Simulation time 2111433762 ps
CPU time 12.35 seconds
Started Aug 16 05:04:03 PM PDT 24
Finished Aug 16 05:04:15 PM PDT 24
Peak memory 198876 kb
Host smart-56a546cc-dd3b-4f23-8bf7-bfedaa219a30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348391727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2348391727
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1556124662
Short name T272
Test name
Test status
Simulation time 93279099716 ps
CPU time 135.64 seconds
Started Aug 16 05:04:03 PM PDT 24
Finished Aug 16 05:06:19 PM PDT 24
Peak memory 200728 kb
Host smart-2f2c7532-fd90-4396-9cf7-039ab4c0ce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556124662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1556124662
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3756876220
Short name T789
Test name
Test status
Simulation time 40553840461 ps
CPU time 13.85 seconds
Started Aug 16 05:04:03 PM PDT 24
Finished Aug 16 05:04:17 PM PDT 24
Peak memory 196848 kb
Host smart-b07a0945-acb7-4b65-aa93-03e833854fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756876220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3756876220
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.256501763
Short name T688
Test name
Test status
Simulation time 5827156859 ps
CPU time 21.6 seconds
Started Aug 16 05:03:56 PM PDT 24
Finished Aug 16 05:04:18 PM PDT 24
Peak memory 200628 kb
Host smart-b45b739b-f5a2-433c-a7bb-77147ab2660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256501763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.256501763
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.4077323296
Short name T860
Test name
Test status
Simulation time 4271689841 ps
CPU time 28.32 seconds
Started Aug 16 05:04:03 PM PDT 24
Finished Aug 16 05:04:31 PM PDT 24
Peak memory 217348 kb
Host smart-58122ef7-f15f-4dbe-b1ca-71b1d4536a49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077323296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.4077323296
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2264055510
Short name T555
Test name
Test status
Simulation time 6806115345 ps
CPU time 10.8 seconds
Started Aug 16 05:04:02 PM PDT 24
Finished Aug 16 05:04:13 PM PDT 24
Peak memory 200740 kb
Host smart-c5d591a9-c7e8-487e-9267-be0d6925a868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264055510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2264055510
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.170746941
Short name T656
Test name
Test status
Simulation time 2044002439 ps
CPU time 0.8 seconds
Started Aug 16 05:03:53 PM PDT 24
Finished Aug 16 05:03:54 PM PDT 24
Peak memory 197780 kb
Host smart-07b2fd4a-5a36-4de1-a376-e5edb1e191d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170746941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.170746941
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3056934235
Short name T664
Test name
Test status
Simulation time 30069078 ps
CPU time 0.57 seconds
Started Aug 16 05:04:13 PM PDT 24
Finished Aug 16 05:04:14 PM PDT 24
Peak memory 196012 kb
Host smart-33c5e0f2-ac0c-42cc-8613-bbc30641e24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056934235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3056934235
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3248967940
Short name T1088
Test name
Test status
Simulation time 281138849355 ps
CPU time 957.11 seconds
Started Aug 16 05:04:06 PM PDT 24
Finished Aug 16 05:20:03 PM PDT 24
Peak memory 200788 kb
Host smart-ad5a13f5-7fcf-48de-8c79-c30a627c30ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248967940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3248967940
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1032410675
Short name T506
Test name
Test status
Simulation time 39627554424 ps
CPU time 77.14 seconds
Started Aug 16 05:04:02 PM PDT 24
Finished Aug 16 05:05:19 PM PDT 24
Peak memory 200892 kb
Host smart-bd9ceb32-2c12-48ce-82dd-cca60a47f165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032410675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1032410675
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.555640653
Short name T1159
Test name
Test status
Simulation time 35673598753 ps
CPU time 45.35 seconds
Started Aug 16 05:04:03 PM PDT 24
Finished Aug 16 05:04:48 PM PDT 24
Peak memory 200392 kb
Host smart-f9a3264c-56e3-48b1-83ec-e1fabd5af37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555640653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.555640653
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3357550872
Short name T678
Test name
Test status
Simulation time 49805880635 ps
CPU time 44.21 seconds
Started Aug 16 05:04:08 PM PDT 24
Finished Aug 16 05:04:52 PM PDT 24
Peak memory 200836 kb
Host smart-20a3cb69-bd3b-428e-ada1-6b23cb9aa019
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357550872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3357550872
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2900592728
Short name T399
Test name
Test status
Simulation time 123625818287 ps
CPU time 441.7 seconds
Started Aug 16 05:04:09 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 200944 kb
Host smart-a05f18d1-2e1d-47a8-b635-8b490b272784
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900592728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2900592728
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2548482848
Short name T659
Test name
Test status
Simulation time 1976671178 ps
CPU time 1.57 seconds
Started Aug 16 05:04:04 PM PDT 24
Finished Aug 16 05:04:05 PM PDT 24
Peak memory 196896 kb
Host smart-57212639-7738-4317-8f64-ced0d0d58e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548482848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2548482848
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.664906927
Short name T768
Test name
Test status
Simulation time 36828663476 ps
CPU time 56.94 seconds
Started Aug 16 05:04:03 PM PDT 24
Finished Aug 16 05:05:00 PM PDT 24
Peak memory 201088 kb
Host smart-db84277d-b70f-41e0-b322-a220da657759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664906927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.664906927
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1231448604
Short name T791
Test name
Test status
Simulation time 22639180242 ps
CPU time 1398.14 seconds
Started Aug 16 05:04:07 PM PDT 24
Finished Aug 16 05:27:25 PM PDT 24
Peak memory 200820 kb
Host smart-33c87553-b858-4faa-a9cc-f43b2062d55a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231448604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1231448604
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1452998431
Short name T666
Test name
Test status
Simulation time 6985293744 ps
CPU time 14.1 seconds
Started Aug 16 05:04:02 PM PDT 24
Finished Aug 16 05:04:16 PM PDT 24
Peak memory 200716 kb
Host smart-64ab9e87-cf64-4e5b-8bcb-dad7f17768c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452998431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1452998431
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2484620600
Short name T1
Test name
Test status
Simulation time 36210834589 ps
CPU time 15.34 seconds
Started Aug 16 05:04:05 PM PDT 24
Finished Aug 16 05:04:20 PM PDT 24
Peak memory 200704 kb
Host smart-c54b1797-734b-4218-acfb-dcfc93f33477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484620600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2484620600
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3281991688
Short name T829
Test name
Test status
Simulation time 690191202 ps
CPU time 1.73 seconds
Started Aug 16 05:04:03 PM PDT 24
Finished Aug 16 05:04:05 PM PDT 24
Peak memory 196364 kb
Host smart-cf8f60a6-c7f2-4ba7-9e5c-0c6a456ad496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281991688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3281991688
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.4285250247
Short name T447
Test name
Test status
Simulation time 691485636 ps
CPU time 1.85 seconds
Started Aug 16 05:04:02 PM PDT 24
Finished Aug 16 05:04:04 PM PDT 24
Peak memory 199228 kb
Host smart-c06fca38-f203-4011-bba6-193768044aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285250247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4285250247
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1630756825
Short name T984
Test name
Test status
Simulation time 250760614789 ps
CPU time 110.2 seconds
Started Aug 16 05:04:09 PM PDT 24
Finished Aug 16 05:06:00 PM PDT 24
Peak memory 200904 kb
Host smart-17221941-8406-4dd1-aea4-e3d7e409f429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630756825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1630756825
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.723257164
Short name T8
Test name
Test status
Simulation time 2599314268 ps
CPU time 15.9 seconds
Started Aug 16 05:04:13 PM PDT 24
Finished Aug 16 05:04:29 PM PDT 24
Peak memory 216584 kb
Host smart-b6e49774-4891-4a4e-98ff-42ea503d7300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723257164 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.723257164
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3597689902
Short name T396
Test name
Test status
Simulation time 7279040841 ps
CPU time 13.16 seconds
Started Aug 16 05:04:03 PM PDT 24
Finished Aug 16 05:04:16 PM PDT 24
Peak memory 200872 kb
Host smart-c417080e-9e65-4967-9d71-f340204e5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597689902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3597689902
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.273803924
Short name T640
Test name
Test status
Simulation time 79570359469 ps
CPU time 15.74 seconds
Started Aug 16 05:04:06 PM PDT 24
Finished Aug 16 05:04:22 PM PDT 24
Peak memory 200888 kb
Host smart-53eb1251-6bad-4f4b-8f34-080c8da98485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273803924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.273803924
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1689828889
Short name T419
Test name
Test status
Simulation time 32958456 ps
CPU time 0.57 seconds
Started Aug 16 05:04:11 PM PDT 24
Finished Aug 16 05:04:12 PM PDT 24
Peak memory 196212 kb
Host smart-ea2f44c4-7f16-4f6d-b2af-29b42c493dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689828889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1689828889
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1719750645
Short name T834
Test name
Test status
Simulation time 26208137413 ps
CPU time 96.71 seconds
Started Aug 16 05:04:13 PM PDT 24
Finished Aug 16 05:05:50 PM PDT 24
Peak memory 200492 kb
Host smart-9bf40612-f208-4107-97a8-f93938be4c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719750645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1719750645
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2582293815
Short name T1042
Test name
Test status
Simulation time 77922058570 ps
CPU time 35.64 seconds
Started Aug 16 05:04:10 PM PDT 24
Finished Aug 16 05:04:46 PM PDT 24
Peak memory 199684 kb
Host smart-69f9813c-0551-4a50-a9dd-1dcd22f5faf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582293815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2582293815
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1020356757
Short name T817
Test name
Test status
Simulation time 125684733388 ps
CPU time 53.45 seconds
Started Aug 16 05:04:14 PM PDT 24
Finished Aug 16 05:05:07 PM PDT 24
Peak memory 200828 kb
Host smart-74912cb1-aa20-4f49-af75-1b8ab9538544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020356757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1020356757
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2252364488
Short name T680
Test name
Test status
Simulation time 33099487863 ps
CPU time 31.17 seconds
Started Aug 16 05:04:12 PM PDT 24
Finished Aug 16 05:04:43 PM PDT 24
Peak memory 200900 kb
Host smart-24eea784-3b27-4eca-928f-96513611c11b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252364488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2252364488
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.494856221
Short name T695
Test name
Test status
Simulation time 72726383169 ps
CPU time 157.66 seconds
Started Aug 16 05:04:10 PM PDT 24
Finished Aug 16 05:06:48 PM PDT 24
Peak memory 200904 kb
Host smart-3a51417c-85c0-424b-9210-cd931e8777ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494856221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.494856221
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2203084474
Short name T445
Test name
Test status
Simulation time 2302646987 ps
CPU time 5.49 seconds
Started Aug 16 05:04:10 PM PDT 24
Finished Aug 16 05:04:16 PM PDT 24
Peak memory 199108 kb
Host smart-0f89ef2c-aed9-4a52-9f62-b8c7724af2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203084474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2203084474
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.75904711
Short name T368
Test name
Test status
Simulation time 47972228946 ps
CPU time 71.68 seconds
Started Aug 16 05:04:13 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 200756 kb
Host smart-ed3598fa-8cc9-4ef8-8cc9-34e8d7d8635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75904711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.75904711
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.559481842
Short name T770
Test name
Test status
Simulation time 9268638383 ps
CPU time 49.67 seconds
Started Aug 16 05:04:09 PM PDT 24
Finished Aug 16 05:04:59 PM PDT 24
Peak memory 200888 kb
Host smart-f0b22f81-01c0-4c07-951a-aecfb5077582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559481842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.559481842
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1406432143
Short name T781
Test name
Test status
Simulation time 4391934030 ps
CPU time 8.91 seconds
Started Aug 16 05:04:10 PM PDT 24
Finished Aug 16 05:04:20 PM PDT 24
Peak memory 199332 kb
Host smart-c5e6a6f5-861c-44a8-a351-f9c71438098d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406432143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1406432143
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3124687388
Short name T1155
Test name
Test status
Simulation time 120278652059 ps
CPU time 119.4 seconds
Started Aug 16 05:04:09 PM PDT 24
Finished Aug 16 05:06:09 PM PDT 24
Peak memory 200936 kb
Host smart-a55b3eca-9017-4543-a79e-22d95e154e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124687388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3124687388
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.520861233
Short name T312
Test name
Test status
Simulation time 5705851843 ps
CPU time 2.78 seconds
Started Aug 16 05:04:11 PM PDT 24
Finished Aug 16 05:04:14 PM PDT 24
Peak memory 196988 kb
Host smart-4cb2cb20-cbd6-465f-b3f8-e0891ae7a2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520861233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.520861233
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1359401641
Short name T322
Test name
Test status
Simulation time 253154501 ps
CPU time 1.24 seconds
Started Aug 16 05:04:09 PM PDT 24
Finished Aug 16 05:04:11 PM PDT 24
Peak memory 199148 kb
Host smart-bb2028a7-3dad-4d38-8104-73b999eed516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359401641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1359401641
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.359044647
Short name T756
Test name
Test status
Simulation time 564397665886 ps
CPU time 133.24 seconds
Started Aug 16 05:04:09 PM PDT 24
Finished Aug 16 05:06:22 PM PDT 24
Peak memory 209300 kb
Host smart-5708f9f9-9a6c-4c68-88d1-baea3a658e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359044647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.359044647
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1690732538
Short name T930
Test name
Test status
Simulation time 15722714113 ps
CPU time 74.08 seconds
Started Aug 16 05:04:10 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 209200 kb
Host smart-34491d84-5879-4f8b-ae16-20a2ebeeb44d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690732538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1690732538
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.533411632
Short name T1090
Test name
Test status
Simulation time 8200643377 ps
CPU time 11.61 seconds
Started Aug 16 05:04:10 PM PDT 24
Finished Aug 16 05:04:22 PM PDT 24
Peak memory 200040 kb
Host smart-7a3a4c5e-0444-438f-9e2d-8b47cc74ccaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533411632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.533411632
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1449646787
Short name T1160
Test name
Test status
Simulation time 32814519594 ps
CPU time 90.49 seconds
Started Aug 16 05:04:10 PM PDT 24
Finished Aug 16 05:05:40 PM PDT 24
Peak memory 200768 kb
Host smart-2644adde-cc28-4f07-b6bf-ab2e6406d873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449646787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1449646787
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.4251183357
Short name T657
Test name
Test status
Simulation time 31179223 ps
CPU time 0.59 seconds
Started Aug 16 05:04:16 PM PDT 24
Finished Aug 16 05:04:17 PM PDT 24
Peak memory 196204 kb
Host smart-0a2194f7-28cb-464a-ada9-ee7bd3c0ade9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251183357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.4251183357
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3560101315
Short name T924
Test name
Test status
Simulation time 102307913921 ps
CPU time 145.06 seconds
Started Aug 16 05:04:11 PM PDT 24
Finished Aug 16 05:06:37 PM PDT 24
Peak memory 200796 kb
Host smart-61259ae0-e5e2-40a8-9ac5-610558286fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560101315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3560101315
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2625268774
Short name T937
Test name
Test status
Simulation time 181307754672 ps
CPU time 327.73 seconds
Started Aug 16 05:04:11 PM PDT 24
Finished Aug 16 05:09:39 PM PDT 24
Peak memory 200892 kb
Host smart-3075a541-c25b-4f86-be00-91eb83d50266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625268774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2625268774
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_intr.1433188120
Short name T994
Test name
Test status
Simulation time 11050314168 ps
CPU time 19.8 seconds
Started Aug 16 05:04:12 PM PDT 24
Finished Aug 16 05:04:32 PM PDT 24
Peak memory 200832 kb
Host smart-62053aad-d0fa-4479-aef0-6d47104b96c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433188120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1433188120
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.625109998
Short name T932
Test name
Test status
Simulation time 71116476278 ps
CPU time 88.82 seconds
Started Aug 16 05:04:20 PM PDT 24
Finished Aug 16 05:05:48 PM PDT 24
Peak memory 200848 kb
Host smart-2beda4b2-d6db-4e1b-8f84-27765f7aa6a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625109998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.625109998
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1389574195
Short name T1067
Test name
Test status
Simulation time 4270041685 ps
CPU time 11.03 seconds
Started Aug 16 05:04:17 PM PDT 24
Finished Aug 16 05:04:29 PM PDT 24
Peak memory 200836 kb
Host smart-600dc0de-06a1-494d-85f7-7c9114ef15e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389574195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1389574195
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3586345286
Short name T1023
Test name
Test status
Simulation time 54654798053 ps
CPU time 83.47 seconds
Started Aug 16 05:04:09 PM PDT 24
Finished Aug 16 05:05:33 PM PDT 24
Peak memory 199664 kb
Host smart-7e435270-85a4-4c89-98e2-d198f4efd65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586345286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3586345286
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.28669513
Short name T43
Test name
Test status
Simulation time 7776242639 ps
CPU time 110.08 seconds
Started Aug 16 05:04:18 PM PDT 24
Finished Aug 16 05:06:08 PM PDT 24
Peak memory 200828 kb
Host smart-311ca755-ae2b-4ce8-8689-ec055cd56e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28669513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.28669513
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1188530128
Short name T1019
Test name
Test status
Simulation time 4307479108 ps
CPU time 33.02 seconds
Started Aug 16 05:04:10 PM PDT 24
Finished Aug 16 05:04:43 PM PDT 24
Peak memory 199932 kb
Host smart-98e88b46-9467-437c-a5f7-b2cfe99d17df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188530128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1188530128
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.4170204197
Short name T570
Test name
Test status
Simulation time 109774674380 ps
CPU time 48.97 seconds
Started Aug 16 05:04:18 PM PDT 24
Finished Aug 16 05:05:08 PM PDT 24
Peak memory 199624 kb
Host smart-8633e6ef-5188-4b40-8222-c9da01d81e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170204197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4170204197
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.262013589
Short name T821
Test name
Test status
Simulation time 2774208462 ps
CPU time 2.82 seconds
Started Aug 16 05:04:12 PM PDT 24
Finished Aug 16 05:04:15 PM PDT 24
Peak memory 196708 kb
Host smart-ff5b8982-621d-4221-91d0-d1603826e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262013589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.262013589
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3180336535
Short name T724
Test name
Test status
Simulation time 5683133926 ps
CPU time 23.22 seconds
Started Aug 16 05:04:13 PM PDT 24
Finished Aug 16 05:04:36 PM PDT 24
Peak memory 200624 kb
Host smart-e376954d-fc61-458a-b3b5-4f1d2cdfa7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180336535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3180336535
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2917511732
Short name T495
Test name
Test status
Simulation time 257156033424 ps
CPU time 39.96 seconds
Started Aug 16 05:04:22 PM PDT 24
Finished Aug 16 05:05:03 PM PDT 24
Peak memory 200772 kb
Host smart-d1e9c0d6-1556-4472-a2ef-723001664dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917511732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2917511732
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2653034906
Short name T298
Test name
Test status
Simulation time 4155598736 ps
CPU time 48.24 seconds
Started Aug 16 05:04:22 PM PDT 24
Finished Aug 16 05:05:10 PM PDT 24
Peak memory 210092 kb
Host smart-156abbd3-ee0d-4c78-94d2-cb75761229dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653034906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2653034906
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3607955829
Short name T967
Test name
Test status
Simulation time 862114821 ps
CPU time 3.8 seconds
Started Aug 16 05:04:17 PM PDT 24
Finished Aug 16 05:04:21 PM PDT 24
Peak memory 199900 kb
Host smart-86810828-88c6-4dde-991f-bb274fbf9454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607955829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3607955829
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3910821214
Short name T338
Test name
Test status
Simulation time 46153023129 ps
CPU time 98.89 seconds
Started Aug 16 05:04:11 PM PDT 24
Finished Aug 16 05:05:50 PM PDT 24
Peak memory 200900 kb
Host smart-85ba776a-26c1-4ee3-b290-33d66f6e4fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910821214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3910821214
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.673005443
Short name T402
Test name
Test status
Simulation time 71805571 ps
CPU time 0.56 seconds
Started Aug 16 05:04:29 PM PDT 24
Finished Aug 16 05:04:30 PM PDT 24
Peak memory 196212 kb
Host smart-568ac798-d93e-408a-b64c-9256f302f2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673005443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.673005443
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2083955335
Short name T1032
Test name
Test status
Simulation time 60786303544 ps
CPU time 96.88 seconds
Started Aug 16 05:04:22 PM PDT 24
Finished Aug 16 05:05:59 PM PDT 24
Peak memory 200824 kb
Host smart-f452eeca-aa9f-4fb8-8613-548e1ca9ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083955335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2083955335
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1165798309
Short name T569
Test name
Test status
Simulation time 170573165594 ps
CPU time 242.96 seconds
Started Aug 16 05:04:19 PM PDT 24
Finished Aug 16 05:08:22 PM PDT 24
Peak memory 200908 kb
Host smart-92e1f0f8-36f6-4514-b5a9-552d50f57bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165798309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1165798309
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3072720260
Short name T218
Test name
Test status
Simulation time 22752140969 ps
CPU time 10.34 seconds
Started Aug 16 05:04:20 PM PDT 24
Finished Aug 16 05:04:30 PM PDT 24
Peak memory 200844 kb
Host smart-f24a4e60-5f53-4f14-a957-a6f3579cc178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072720260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3072720260
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1050731347
Short name T321
Test name
Test status
Simulation time 14236925747 ps
CPU time 8.27 seconds
Started Aug 16 05:04:16 PM PDT 24
Finished Aug 16 05:04:25 PM PDT 24
Peak memory 200832 kb
Host smart-5e4e8031-4552-4c37-a1d5-1ce552ce0344
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050731347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1050731347
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2281566043
Short name T758
Test name
Test status
Simulation time 39258106842 ps
CPU time 79.2 seconds
Started Aug 16 05:04:19 PM PDT 24
Finished Aug 16 05:05:39 PM PDT 24
Peak memory 200828 kb
Host smart-ecff7ccb-b1cc-4ee5-a416-11e8d2975e76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281566043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2281566043
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1002391032
Short name T1029
Test name
Test status
Simulation time 7748953447 ps
CPU time 9.37 seconds
Started Aug 16 05:04:17 PM PDT 24
Finished Aug 16 05:04:27 PM PDT 24
Peak memory 200828 kb
Host smart-4f0d2f17-e932-43c9-b69a-b2d17d714751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002391032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1002391032
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.394141329
Short name T1078
Test name
Test status
Simulation time 32110404442 ps
CPU time 57.7 seconds
Started Aug 16 05:04:17 PM PDT 24
Finished Aug 16 05:05:15 PM PDT 24
Peak memory 201036 kb
Host smart-38a47967-79ad-4197-b7e8-1f63c426a08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394141329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.394141329
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.4246079935
Short name T1054
Test name
Test status
Simulation time 14972104197 ps
CPU time 880.26 seconds
Started Aug 16 05:04:16 PM PDT 24
Finished Aug 16 05:18:57 PM PDT 24
Peak memory 200920 kb
Host smart-3064bcf3-6453-4214-a5f0-45a6d13ec557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246079935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4246079935
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1705858662
Short name T475
Test name
Test status
Simulation time 6967823258 ps
CPU time 14.09 seconds
Started Aug 16 05:04:19 PM PDT 24
Finished Aug 16 05:04:33 PM PDT 24
Peak memory 199700 kb
Host smart-a06d0850-3c7c-4d55-a730-40ce84650c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705858662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1705858662
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.850962213
Short name T892
Test name
Test status
Simulation time 61789314039 ps
CPU time 33.11 seconds
Started Aug 16 05:04:17 PM PDT 24
Finished Aug 16 05:04:50 PM PDT 24
Peak memory 200840 kb
Host smart-d051e06f-5ff1-435d-985b-1742fc241668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850962213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.850962213
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2335496238
Short name T628
Test name
Test status
Simulation time 29657116881 ps
CPU time 46.74 seconds
Started Aug 16 05:04:17 PM PDT 24
Finished Aug 16 05:05:04 PM PDT 24
Peak memory 196808 kb
Host smart-7ba84b0a-2884-4ea8-9356-0415bf85d254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335496238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2335496238
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2173763497
Short name T926
Test name
Test status
Simulation time 11056439143 ps
CPU time 14.97 seconds
Started Aug 16 05:04:16 PM PDT 24
Finished Aug 16 05:04:31 PM PDT 24
Peak memory 200776 kb
Host smart-d35e72d7-cb0f-44b6-866c-44ff21d1f0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173763497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2173763497
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3516648240
Short name T397
Test name
Test status
Simulation time 134670852928 ps
CPU time 2318.19 seconds
Started Aug 16 05:04:26 PM PDT 24
Finished Aug 16 05:43:04 PM PDT 24
Peak memory 200832 kb
Host smart-3d85e73c-657d-4905-b70b-1e0e03033218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516648240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3516648240
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1667243821
Short name T350
Test name
Test status
Simulation time 2383946247 ps
CPU time 32.26 seconds
Started Aug 16 05:04:17 PM PDT 24
Finished Aug 16 05:04:49 PM PDT 24
Peak memory 209404 kb
Host smart-a0e1114e-f0f5-4194-b9f8-1d3583f58756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667243821 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1667243821
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1522468807
Short name T645
Test name
Test status
Simulation time 1031487227 ps
CPU time 3.8 seconds
Started Aug 16 05:04:20 PM PDT 24
Finished Aug 16 05:04:24 PM PDT 24
Peak memory 199372 kb
Host smart-bdaba068-7637-4930-9a29-52b51336cbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522468807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1522468807
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3780401522
Short name T818
Test name
Test status
Simulation time 121220265485 ps
CPU time 29.27 seconds
Started Aug 16 05:04:18 PM PDT 24
Finished Aug 16 05:04:47 PM PDT 24
Peak memory 200856 kb
Host smart-eb5851c6-d037-433e-ad7a-b6761d30288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780401522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3780401522
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2638315547
Short name T466
Test name
Test status
Simulation time 16035257 ps
CPU time 0.6 seconds
Started Aug 16 05:04:28 PM PDT 24
Finished Aug 16 05:04:29 PM PDT 24
Peak memory 196212 kb
Host smart-42df56f5-a7c4-4389-b821-459c51dea39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638315547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2638315547
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3246439239
Short name T454
Test name
Test status
Simulation time 165449654375 ps
CPU time 535.87 seconds
Started Aug 16 05:04:27 PM PDT 24
Finished Aug 16 05:13:23 PM PDT 24
Peak memory 200916 kb
Host smart-ff6868a1-1f26-43e8-92bf-8896dc2177db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246439239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3246439239
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3131996970
Short name T77
Test name
Test status
Simulation time 225260508439 ps
CPU time 56.12 seconds
Started Aug 16 05:04:28 PM PDT 24
Finished Aug 16 05:05:24 PM PDT 24
Peak memory 200880 kb
Host smart-d8665c12-7047-4140-853c-6f39d90a9e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131996970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3131996970
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1628631937
Short name T1110
Test name
Test status
Simulation time 42305861936 ps
CPU time 34.53 seconds
Started Aug 16 05:04:28 PM PDT 24
Finished Aug 16 05:05:02 PM PDT 24
Peak memory 200924 kb
Host smart-1d0fc80f-0a25-4bf0-a49f-fa12cae00dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628631937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1628631937
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1536667743
Short name T798
Test name
Test status
Simulation time 9613403100 ps
CPU time 14.04 seconds
Started Aug 16 05:04:29 PM PDT 24
Finished Aug 16 05:04:43 PM PDT 24
Peak memory 198820 kb
Host smart-04b7a951-3148-4466-99df-8572692af1ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536667743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1536667743
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1266577028
Short name T294
Test name
Test status
Simulation time 105249700825 ps
CPU time 331.96 seconds
Started Aug 16 05:04:29 PM PDT 24
Finished Aug 16 05:10:02 PM PDT 24
Peak memory 200800 kb
Host smart-138c59fd-82d7-4b24-8835-bb701e569635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266577028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1266577028
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2188552537
Short name T1178
Test name
Test status
Simulation time 10906510873 ps
CPU time 9 seconds
Started Aug 16 05:04:27 PM PDT 24
Finished Aug 16 05:04:36 PM PDT 24
Peak memory 200748 kb
Host smart-64a28391-7bd8-4fba-8586-f573e16cb723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188552537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2188552537
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.742694261
Short name T696
Test name
Test status
Simulation time 90018952389 ps
CPU time 134.94 seconds
Started Aug 16 05:04:27 PM PDT 24
Finished Aug 16 05:06:42 PM PDT 24
Peak memory 200600 kb
Host smart-e09106fb-b91e-4cc8-8959-5f22e2f7687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742694261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.742694261
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3583172099
Short name T1134
Test name
Test status
Simulation time 24450418406 ps
CPU time 1276.39 seconds
Started Aug 16 05:04:30 PM PDT 24
Finished Aug 16 05:25:47 PM PDT 24
Peak memory 200864 kb
Host smart-5b3262f2-76f8-44e6-a255-59a9c6cc9a0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583172099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3583172099
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2853578464
Short name T954
Test name
Test status
Simulation time 5040913445 ps
CPU time 37.47 seconds
Started Aug 16 05:04:28 PM PDT 24
Finished Aug 16 05:05:05 PM PDT 24
Peak memory 200880 kb
Host smart-e7032add-53c7-4b42-a0b5-f25f93bf687b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853578464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2853578464
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1279525576
Short name T974
Test name
Test status
Simulation time 18747543810 ps
CPU time 52.02 seconds
Started Aug 16 05:04:27 PM PDT 24
Finished Aug 16 05:05:19 PM PDT 24
Peak memory 200856 kb
Host smart-69e68d07-7902-4016-8e4c-0b344e49875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279525576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1279525576
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.720326085
Short name T528
Test name
Test status
Simulation time 45448073455 ps
CPU time 19.26 seconds
Started Aug 16 05:04:28 PM PDT 24
Finished Aug 16 05:04:47 PM PDT 24
Peak memory 197060 kb
Host smart-71a83a3a-fed6-4888-980b-44013bd448b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720326085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.720326085
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.4148598440
Short name T487
Test name
Test status
Simulation time 723240855 ps
CPU time 2.26 seconds
Started Aug 16 05:04:29 PM PDT 24
Finished Aug 16 05:04:32 PM PDT 24
Peak memory 199492 kb
Host smart-ba2bd8f7-5666-4b5a-80d3-0d7e6cf20cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148598440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4148598440
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2383603683
Short name T311
Test name
Test status
Simulation time 107930279184 ps
CPU time 159.97 seconds
Started Aug 16 05:04:29 PM PDT 24
Finished Aug 16 05:07:10 PM PDT 24
Peak memory 200820 kb
Host smart-faafc7ed-caab-4627-ae8d-6cac3446b41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383603683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2383603683
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3713007939
Short name T880
Test name
Test status
Simulation time 4843074562 ps
CPU time 52.13 seconds
Started Aug 16 05:04:31 PM PDT 24
Finished Aug 16 05:05:23 PM PDT 24
Peak memory 216580 kb
Host smart-b4353500-c110-4607-8a38-310cfc79362a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713007939 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3713007939
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2792740157
Short name T797
Test name
Test status
Simulation time 8486006495 ps
CPU time 9.75 seconds
Started Aug 16 05:04:28 PM PDT 24
Finished Aug 16 05:04:38 PM PDT 24
Peak memory 200896 kb
Host smart-accffe60-5990-40f1-8678-f5c2e26f368e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792740157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2792740157
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1142506789
Short name T1158
Test name
Test status
Simulation time 115441350723 ps
CPU time 51.97 seconds
Started Aug 16 05:04:30 PM PDT 24
Finished Aug 16 05:05:22 PM PDT 24
Peak memory 200860 kb
Host smart-507b89f4-25fb-4282-b2bb-61fdb0978d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142506789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1142506789
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1109476128
Short name T31
Test name
Test status
Simulation time 62134236 ps
CPU time 0.57 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:04:37 PM PDT 24
Peak memory 196204 kb
Host smart-25c7a283-7ea4-4429-a9aa-68e5e4f9e4b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109476128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1109476128
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2111361546
Short name T303
Test name
Test status
Simulation time 244855431071 ps
CPU time 98.34 seconds
Started Aug 16 05:04:34 PM PDT 24
Finished Aug 16 05:06:12 PM PDT 24
Peak memory 200904 kb
Host smart-85b008bf-ee82-493d-844d-0be86809909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111361546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2111361546
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1867534605
Short name T1171
Test name
Test status
Simulation time 43994930807 ps
CPU time 25.53 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:05:02 PM PDT 24
Peak memory 200896 kb
Host smart-8b4679a5-fa36-4d44-9925-09f62f3cd0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867534605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1867534605
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3184350005
Short name T459
Test name
Test status
Simulation time 147955930880 ps
CPU time 63.44 seconds
Started Aug 16 05:04:34 PM PDT 24
Finished Aug 16 05:05:37 PM PDT 24
Peak memory 200904 kb
Host smart-5e2d3ad9-a1b5-4c54-a5cb-0cee342fbbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184350005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3184350005
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.56760037
Short name T985
Test name
Test status
Simulation time 33480284103 ps
CPU time 17.33 seconds
Started Aug 16 05:04:32 PM PDT 24
Finished Aug 16 05:04:50 PM PDT 24
Peak memory 200888 kb
Host smart-4a32723d-e101-46f6-9377-90b53f243b27
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56760037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.56760037
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.364419257
Short name T254
Test name
Test status
Simulation time 189948121841 ps
CPU time 989.44 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:21:03 PM PDT 24
Peak memory 200888 kb
Host smart-d6c6553d-f232-4450-a1a2-13c6e9c7d030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364419257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.364419257
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2053576020
Short name T383
Test name
Test status
Simulation time 1657620971 ps
CPU time 3.08 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:04:39 PM PDT 24
Peak memory 199284 kb
Host smart-9aa16586-edca-4bfa-962d-024017b2032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053576020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2053576020
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.325150630
Short name T1144
Test name
Test status
Simulation time 22212475551 ps
CPU time 20.03 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:04:53 PM PDT 24
Peak memory 200436 kb
Host smart-59710011-9814-4d81-be2b-09c25abf9839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325150630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.325150630
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1808840135
Short name T1120
Test name
Test status
Simulation time 12788071968 ps
CPU time 40.28 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:05:14 PM PDT 24
Peak memory 200912 kb
Host smart-03ea88e9-ad34-49ea-b334-03accaf0c7bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808840135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1808840135
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3158260965
Short name T486
Test name
Test status
Simulation time 4530326653 ps
CPU time 37.03 seconds
Started Aug 16 05:04:31 PM PDT 24
Finished Aug 16 05:05:08 PM PDT 24
Peak memory 200056 kb
Host smart-1153cf1c-28af-4b76-bfd6-d775c246d665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158260965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3158260965
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2255766309
Short name T269
Test name
Test status
Simulation time 76245244493 ps
CPU time 61.83 seconds
Started Aug 16 05:04:32 PM PDT 24
Finished Aug 16 05:05:35 PM PDT 24
Peak memory 200908 kb
Host smart-76f87234-1f71-49c3-b1f1-b590a96f64df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255766309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2255766309
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.905914214
Short name T340
Test name
Test status
Simulation time 3890064536 ps
CPU time 2.04 seconds
Started Aug 16 05:04:34 PM PDT 24
Finished Aug 16 05:04:36 PM PDT 24
Peak memory 197160 kb
Host smart-955c7e25-87ce-45db-95e4-165daf884a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905914214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.905914214
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3810919675
Short name T41
Test name
Test status
Simulation time 891214460 ps
CPU time 3.91 seconds
Started Aug 16 05:04:27 PM PDT 24
Finished Aug 16 05:04:31 PM PDT 24
Peak memory 200764 kb
Host smart-7576410b-6f94-415a-8bac-744ef9c3350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810919675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3810919675
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1741384492
Short name T88
Test name
Test status
Simulation time 2680111402 ps
CPU time 10.21 seconds
Started Aug 16 05:04:32 PM PDT 24
Finished Aug 16 05:04:42 PM PDT 24
Peak memory 209388 kb
Host smart-7758638a-d53b-496f-8c06-d119ba6ffccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741384492 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1741384492
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2098117088
Short name T7
Test name
Test status
Simulation time 1113604745 ps
CPU time 1.86 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:04:35 PM PDT 24
Peak memory 198856 kb
Host smart-653b765e-00f1-496c-bcb1-6a8cb8af91c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098117088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2098117088
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.81702354
Short name T868
Test name
Test status
Simulation time 17762698662 ps
CPU time 12.64 seconds
Started Aug 16 05:04:35 PM PDT 24
Finished Aug 16 05:04:48 PM PDT 24
Peak memory 198408 kb
Host smart-3ab8b560-be56-4bb9-b853-b074cec5045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81702354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.81702354
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1554573583
Short name T732
Test name
Test status
Simulation time 32443840 ps
CPU time 0.58 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:04:37 PM PDT 24
Peak memory 196212 kb
Host smart-d885e8f1-85d4-4e8d-9374-5308cbeeebcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554573583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1554573583
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1928259817
Short name T599
Test name
Test status
Simulation time 46591718064 ps
CPU time 29.97 seconds
Started Aug 16 05:04:35 PM PDT 24
Finished Aug 16 05:05:05 PM PDT 24
Peak memory 200888 kb
Host smart-e9f1f3b9-7417-4653-b5cf-af1b60c6fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928259817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1928259817
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3095380740
Short name T935
Test name
Test status
Simulation time 29422726423 ps
CPU time 48.38 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 200896 kb
Host smart-e62626c7-bfca-4bf8-a59e-d6db5e7e48e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095380740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3095380740
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4242239095
Short name T526
Test name
Test status
Simulation time 81854029036 ps
CPU time 70.35 seconds
Started Aug 16 05:04:34 PM PDT 24
Finished Aug 16 05:05:44 PM PDT 24
Peak memory 200880 kb
Host smart-3add7ff3-feac-4dbf-8f9d-a3218369e8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242239095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4242239095
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2141489133
Short name T76
Test name
Test status
Simulation time 26112026446 ps
CPU time 14.54 seconds
Started Aug 16 05:04:34 PM PDT 24
Finished Aug 16 05:04:49 PM PDT 24
Peak memory 200616 kb
Host smart-ab3cfebd-781e-4ba7-8191-e29ee02f0b92
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141489133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2141489133
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1740195032
Short name T660
Test name
Test status
Simulation time 79261453933 ps
CPU time 379.22 seconds
Started Aug 16 05:04:32 PM PDT 24
Finished Aug 16 05:10:52 PM PDT 24
Peak memory 200900 kb
Host smart-9a0e84a5-c070-4c77-8191-4c6fdca93cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740195032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1740195032
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2939928013
Short name T26
Test name
Test status
Simulation time 3863863536 ps
CPU time 2.03 seconds
Started Aug 16 05:04:32 PM PDT 24
Finished Aug 16 05:04:34 PM PDT 24
Peak memory 199088 kb
Host smart-caecbeb5-00f3-474a-9b50-bb504a085665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939928013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2939928013
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1491831701
Short name T920
Test name
Test status
Simulation time 23071705384 ps
CPU time 39.93 seconds
Started Aug 16 05:04:31 PM PDT 24
Finished Aug 16 05:05:11 PM PDT 24
Peak memory 199680 kb
Host smart-34914054-22d4-4da0-b43c-db44fa5d36cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491831701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1491831701
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4006128818
Short name T433
Test name
Test status
Simulation time 6166336744 ps
CPU time 26.35 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:05:00 PM PDT 24
Peak memory 200820 kb
Host smart-e6768bc7-f1b5-46bf-a7a8-61a78c369df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006128818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4006128818
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2525490544
Short name T828
Test name
Test status
Simulation time 3919290303 ps
CPU time 31.02 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:05:04 PM PDT 24
Peak memory 199004 kb
Host smart-634492bd-94f7-4492-ac62-1aeda04590b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525490544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2525490544
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.856058655
Short name T309
Test name
Test status
Simulation time 93984077364 ps
CPU time 152.72 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:07:09 PM PDT 24
Peak memory 200828 kb
Host smart-9b418d23-fbee-4c8b-8772-f7f99efe8e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856058655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.856058655
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1530869996
Short name T938
Test name
Test status
Simulation time 2735034150 ps
CPU time 1.78 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:04:35 PM PDT 24
Peak memory 197392 kb
Host smart-ee17018e-2cb7-43af-8296-47a0b3fc41ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530869996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1530869996
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2665104969
Short name T335
Test name
Test status
Simulation time 6212836867 ps
CPU time 13.75 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:04:50 PM PDT 24
Peak memory 200372 kb
Host smart-4b26a9d9-3625-4b35-9899-4cfe0b6fc852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665104969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2665104969
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3430787935
Short name T1030
Test name
Test status
Simulation time 243520171498 ps
CPU time 585.58 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:14:18 PM PDT 24
Peak memory 200876 kb
Host smart-b6f4974d-4ac9-4848-91d2-8bf972548204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430787935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3430787935
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.670315783
Short name T793
Test name
Test status
Simulation time 13749109313 ps
CPU time 37.88 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:05:14 PM PDT 24
Peak memory 216776 kb
Host smart-dd361822-2370-4617-951d-05261fc2a69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670315783 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.670315783
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.733318560
Short name T879
Test name
Test status
Simulation time 797253357 ps
CPU time 2.28 seconds
Started Aug 16 05:04:33 PM PDT 24
Finished Aug 16 05:04:36 PM PDT 24
Peak memory 199464 kb
Host smart-6ddf6640-8a65-418f-a69d-6392fcb03eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733318560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.733318560
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1010646984
Short name T366
Test name
Test status
Simulation time 44725849697 ps
CPU time 73.69 seconds
Started Aug 16 05:04:32 PM PDT 24
Finished Aug 16 05:05:46 PM PDT 24
Peak memory 200848 kb
Host smart-5feb90f7-5777-413a-bc7d-7e1bfda0dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010646984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1010646984
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3355537095
Short name T400
Test name
Test status
Simulation time 19005062 ps
CPU time 0.53 seconds
Started Aug 16 05:04:41 PM PDT 24
Finished Aug 16 05:04:41 PM PDT 24
Peak memory 195468 kb
Host smart-3300c3ec-7b93-41c9-8c61-831d2639af6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355537095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3355537095
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3026872088
Short name T84
Test name
Test status
Simulation time 38681595585 ps
CPU time 62.2 seconds
Started Aug 16 05:04:41 PM PDT 24
Finished Aug 16 05:05:43 PM PDT 24
Peak memory 200848 kb
Host smart-471ef684-1d6c-4b1c-a2ba-be96c900646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026872088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3026872088
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1312355888
Short name T267
Test name
Test status
Simulation time 93116474505 ps
CPU time 73.11 seconds
Started Aug 16 05:04:40 PM PDT 24
Finished Aug 16 05:05:53 PM PDT 24
Peak memory 200804 kb
Host smart-5f85c720-451b-486b-af5f-29dadc4d00e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312355888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1312355888
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2882574717
Short name T144
Test name
Test status
Simulation time 80801034012 ps
CPU time 26.06 seconds
Started Aug 16 05:04:44 PM PDT 24
Finished Aug 16 05:05:10 PM PDT 24
Peak memory 200804 kb
Host smart-5fc1f22d-a45b-4450-b64c-1b4365fa60f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882574717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2882574717
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.457775830
Short name T361
Test name
Test status
Simulation time 389016896939 ps
CPU time 287.46 seconds
Started Aug 16 05:04:40 PM PDT 24
Finished Aug 16 05:09:28 PM PDT 24
Peak memory 199480 kb
Host smart-64d2a8b8-cbb5-4a1b-9106-28f9645b41bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457775830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.457775830
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_loopback.3535000854
Short name T28
Test name
Test status
Simulation time 1736113628 ps
CPU time 3.95 seconds
Started Aug 16 05:04:43 PM PDT 24
Finished Aug 16 05:04:47 PM PDT 24
Peak memory 199460 kb
Host smart-3d558fd6-de37-45cc-8550-c97958cf59c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535000854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3535000854
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2802404635
Short name T865
Test name
Test status
Simulation time 13497353711 ps
CPU time 19.89 seconds
Started Aug 16 05:04:41 PM PDT 24
Finished Aug 16 05:05:01 PM PDT 24
Peak memory 201116 kb
Host smart-f3941dd0-0c36-4ba3-a502-a75d8d427881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802404635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2802404635
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2975103612
Short name T480
Test name
Test status
Simulation time 9104919682 ps
CPU time 125.69 seconds
Started Aug 16 05:04:43 PM PDT 24
Finished Aug 16 05:06:49 PM PDT 24
Peak memory 200896 kb
Host smart-5a080b17-8a66-4d22-a36d-5294a6c3df2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975103612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2975103612
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.725098728
Short name T604
Test name
Test status
Simulation time 2423498119 ps
CPU time 7.91 seconds
Started Aug 16 05:04:41 PM PDT 24
Finished Aug 16 05:04:49 PM PDT 24
Peak memory 199852 kb
Host smart-4ba8f50d-2c9a-4330-8634-700777305e56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725098728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.725098728
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.3738942361
Short name T112
Test name
Test status
Simulation time 32472172559 ps
CPU time 52.23 seconds
Started Aug 16 05:04:41 PM PDT 24
Finished Aug 16 05:05:34 PM PDT 24
Peak memory 200848 kb
Host smart-e03f06f3-855d-482b-a2a5-b4e257022fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738942361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3738942361
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3608108339
Short name T1156
Test name
Test status
Simulation time 84035396282 ps
CPU time 107.06 seconds
Started Aug 16 05:04:42 PM PDT 24
Finished Aug 16 05:06:29 PM PDT 24
Peak memory 196736 kb
Host smart-0c6542f7-cb11-4697-9eea-9c24614508c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608108339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3608108339
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1577331927
Short name T736
Test name
Test status
Simulation time 148594816 ps
CPU time 0.86 seconds
Started Aug 16 05:04:36 PM PDT 24
Finished Aug 16 05:04:37 PM PDT 24
Peak memory 198080 kb
Host smart-518c09fc-19f1-47ed-b6d4-2402a0a91b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577331927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1577331927
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2223611536
Short name T986
Test name
Test status
Simulation time 223119482759 ps
CPU time 116.32 seconds
Started Aug 16 05:04:40 PM PDT 24
Finished Aug 16 05:06:37 PM PDT 24
Peak memory 200884 kb
Host smart-7abbb7bf-0afe-46f7-b18a-8af77fe2ea79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223611536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2223611536
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3971079380
Short name T692
Test name
Test status
Simulation time 1341827873 ps
CPU time 28.43 seconds
Started Aug 16 05:04:43 PM PDT 24
Finished Aug 16 05:05:12 PM PDT 24
Peak memory 209264 kb
Host smart-8415a653-9615-4ca1-a25b-4b0299de738c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971079380 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3971079380
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.322856649
Short name T421
Test name
Test status
Simulation time 6295847893 ps
CPU time 21.69 seconds
Started Aug 16 05:04:42 PM PDT 24
Finished Aug 16 05:05:04 PM PDT 24
Peak memory 200224 kb
Host smart-3e863fc6-63dc-4024-97db-79d8ede8c09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322856649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.322856649
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2214067781
Short name T622
Test name
Test status
Simulation time 103907200232 ps
CPU time 23.7 seconds
Started Aug 16 05:04:42 PM PDT 24
Finished Aug 16 05:05:06 PM PDT 24
Peak memory 200904 kb
Host smart-1c8bccac-2e74-44ba-8d27-c10d244052ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214067781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2214067781
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.141440344
Short name T820
Test name
Test status
Simulation time 12235875 ps
CPU time 0.55 seconds
Started Aug 16 05:04:51 PM PDT 24
Finished Aug 16 05:04:52 PM PDT 24
Peak memory 196228 kb
Host smart-17e995a1-e19e-4526-ac10-fd089c2f09cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141440344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.141440344
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2662664729
Short name T552
Test name
Test status
Simulation time 10270216508 ps
CPU time 9.05 seconds
Started Aug 16 05:04:40 PM PDT 24
Finished Aug 16 05:04:49 PM PDT 24
Peak memory 200872 kb
Host smart-90fffda7-24a1-45cd-8077-1f5be83640cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662664729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2662664729
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1622100234
Short name T346
Test name
Test status
Simulation time 122161676942 ps
CPU time 176.07 seconds
Started Aug 16 05:04:40 PM PDT 24
Finished Aug 16 05:07:36 PM PDT 24
Peak memory 200892 kb
Host smart-e4d8ae26-3f26-4887-aa5a-e95ec331b8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622100234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1622100234
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.2699393689
Short name T948
Test name
Test status
Simulation time 24834958581 ps
CPU time 46.35 seconds
Started Aug 16 05:04:41 PM PDT 24
Finished Aug 16 05:05:28 PM PDT 24
Peak memory 200916 kb
Host smart-08ea2fb2-220b-4132-bf40-9a052bf3043f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699393689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2699393689
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1316585922
Short name T538
Test name
Test status
Simulation time 82405799493 ps
CPU time 402.24 seconds
Started Aug 16 05:04:53 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 200848 kb
Host smart-06415d53-bbcb-4eb1-9930-ff0211265c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1316585922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1316585922
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2929081444
Short name T504
Test name
Test status
Simulation time 3351082295 ps
CPU time 2.32 seconds
Started Aug 16 05:04:51 PM PDT 24
Finished Aug 16 05:04:53 PM PDT 24
Peak memory 197216 kb
Host smart-81b0a22d-b497-486c-b6da-0edb47c5d8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929081444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2929081444
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3149496661
Short name T310
Test name
Test status
Simulation time 35473764677 ps
CPU time 59.91 seconds
Started Aug 16 05:04:41 PM PDT 24
Finished Aug 16 05:05:41 PM PDT 24
Peak memory 201128 kb
Host smart-f6a07c75-6391-4a3c-bcc5-f06221711b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149496661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3149496661
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1203402136
Short name T923
Test name
Test status
Simulation time 9052859682 ps
CPU time 67.28 seconds
Started Aug 16 05:04:54 PM PDT 24
Finished Aug 16 05:06:01 PM PDT 24
Peak memory 200892 kb
Host smart-be96959a-b3d2-48b1-b33c-7a995129ee15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203402136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1203402136
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.218606592
Short name T392
Test name
Test status
Simulation time 2137156486 ps
CPU time 3.31 seconds
Started Aug 16 05:04:40 PM PDT 24
Finished Aug 16 05:04:43 PM PDT 24
Peak memory 199108 kb
Host smart-8d80722c-fdef-49ea-9ebd-30e36afc7dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218606592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.218606592
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1039448654
Short name T109
Test name
Test status
Simulation time 56166189478 ps
CPU time 86.44 seconds
Started Aug 16 05:04:52 PM PDT 24
Finished Aug 16 05:06:19 PM PDT 24
Peak memory 200760 kb
Host smart-0f86bc2a-0c1a-4ab0-85d0-c35199d7c1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039448654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1039448654
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3775596070
Short name T955
Test name
Test status
Simulation time 1833900275 ps
CPU time 2.98 seconds
Started Aug 16 05:04:42 PM PDT 24
Finished Aug 16 05:04:45 PM PDT 24
Peak memory 196572 kb
Host smart-1bdd5f77-6dd0-4d16-8c13-d4f0c287039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775596070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3775596070
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.728116373
Short name T387
Test name
Test status
Simulation time 526613854 ps
CPU time 1.57 seconds
Started Aug 16 05:04:42 PM PDT 24
Finished Aug 16 05:04:44 PM PDT 24
Peak memory 199236 kb
Host smart-5e84b85c-1f35-475b-b2ed-33e7edc627f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728116373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.728116373
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.651731902
Short name T359
Test name
Test status
Simulation time 1461660191 ps
CPU time 29.05 seconds
Started Aug 16 05:04:53 PM PDT 24
Finished Aug 16 05:05:22 PM PDT 24
Peak memory 209108 kb
Host smart-ef558a43-9ed3-4c78-b3c5-b967d29e73c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651731902 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.651731902
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1707069578
Short name T425
Test name
Test status
Simulation time 1911636668 ps
CPU time 1.98 seconds
Started Aug 16 05:04:54 PM PDT 24
Finished Aug 16 05:04:56 PM PDT 24
Peak memory 199412 kb
Host smart-985490d7-2c3d-4b6b-a1fb-a3ecf0aad34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707069578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1707069578
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1133157950
Short name T270
Test name
Test status
Simulation time 52391598789 ps
CPU time 21.44 seconds
Started Aug 16 05:04:43 PM PDT 24
Finished Aug 16 05:05:04 PM PDT 24
Peak memory 200840 kb
Host smart-9780af09-ffbb-4eb8-844d-67fb6b5f6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133157950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1133157950
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.96148238
Short name T977
Test name
Test status
Simulation time 33389871 ps
CPU time 0.55 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:02:05 PM PDT 24
Peak memory 195192 kb
Host smart-9b96a4db-c630-48a1-842a-01d4026fab3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96148238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.96148238
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3476660839
Short name T266
Test name
Test status
Simulation time 151662423167 ps
CPU time 65.76 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:03:10 PM PDT 24
Peak memory 200904 kb
Host smart-34c17c7a-8d01-412c-ac32-586780a86e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476660839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3476660839
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2220053105
Short name T449
Test name
Test status
Simulation time 179998837515 ps
CPU time 44.83 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:02:49 PM PDT 24
Peak memory 200828 kb
Host smart-576ad4a2-7d37-4355-90fb-69f2ab99ad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220053105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2220053105
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3793406544
Short name T970
Test name
Test status
Simulation time 24558972119 ps
CPU time 45.65 seconds
Started Aug 16 05:02:03 PM PDT 24
Finished Aug 16 05:02:49 PM PDT 24
Peak memory 200820 kb
Host smart-a97a9705-15e9-42e2-904e-4762e338fcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793406544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3793406544
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3116526536
Short name T102
Test name
Test status
Simulation time 307409372413 ps
CPU time 448.93 seconds
Started Aug 16 05:02:00 PM PDT 24
Finished Aug 16 05:09:29 PM PDT 24
Peak memory 199012 kb
Host smart-7bd4ffdf-30eb-4f9e-b5de-933d91f0f70a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116526536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3116526536
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3888399416
Short name T976
Test name
Test status
Simulation time 169942990081 ps
CPU time 1709.5 seconds
Started Aug 16 05:02:05 PM PDT 24
Finished Aug 16 05:30:35 PM PDT 24
Peak memory 200800 kb
Host smart-b565713b-9c3c-447d-9a91-648de764f358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888399416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3888399416
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.456068303
Short name T382
Test name
Test status
Simulation time 8773387587 ps
CPU time 5.63 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:02:10 PM PDT 24
Peak memory 200208 kb
Host smart-e94d12fb-4897-4486-8e0b-6b38b7cfe056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456068303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.456068303
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3621149336
Short name T299
Test name
Test status
Simulation time 156079328182 ps
CPU time 61.03 seconds
Started Aug 16 05:02:00 PM PDT 24
Finished Aug 16 05:03:01 PM PDT 24
Peak memory 200976 kb
Host smart-9897bf18-c134-4bbd-8b2b-8a0ea63b662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621149336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3621149336
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2065409405
Short name T778
Test name
Test status
Simulation time 23004658432 ps
CPU time 639.51 seconds
Started Aug 16 05:02:06 PM PDT 24
Finished Aug 16 05:12:46 PM PDT 24
Peak memory 200940 kb
Host smart-83e8d3a7-d416-4a6c-872b-48ed9f1b7edd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065409405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2065409405
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2023810314
Short name T1074
Test name
Test status
Simulation time 5708423088 ps
CPU time 27.57 seconds
Started Aug 16 05:02:00 PM PDT 24
Finished Aug 16 05:02:27 PM PDT 24
Peak memory 200320 kb
Host smart-fe9a5041-964f-4432-bf1d-48afb82e32c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023810314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2023810314
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3811316834
Short name T675
Test name
Test status
Simulation time 32455637981 ps
CPU time 16.45 seconds
Started Aug 16 05:02:08 PM PDT 24
Finished Aug 16 05:02:25 PM PDT 24
Peak memory 200816 kb
Host smart-15f0484f-d986-49ad-82fb-0c029ee58357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811316834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3811316834
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2838073806
Short name T740
Test name
Test status
Simulation time 50450584848 ps
CPU time 40.19 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:02:45 PM PDT 24
Peak memory 196796 kb
Host smart-112acf1f-e1fe-4852-afd5-f4887edbc421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838073806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2838073806
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1469928164
Short name T34
Test name
Test status
Simulation time 175149309 ps
CPU time 0.78 seconds
Started Aug 16 05:02:08 PM PDT 24
Finished Aug 16 05:02:09 PM PDT 24
Peak memory 219068 kb
Host smart-bdc84257-3f6a-4ec4-a527-5f97039c6e40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469928164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1469928164
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1695443933
Short name T1177
Test name
Test status
Simulation time 450290388 ps
CPU time 1.86 seconds
Started Aug 16 05:02:06 PM PDT 24
Finished Aug 16 05:02:08 PM PDT 24
Peak memory 200392 kb
Host smart-7b94f6a3-5770-45f3-b043-695d56bc7e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695443933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1695443933
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2552917732
Short name T1118
Test name
Test status
Simulation time 4343051510 ps
CPU time 18.57 seconds
Started Aug 16 05:02:07 PM PDT 24
Finished Aug 16 05:02:25 PM PDT 24
Peak memory 209436 kb
Host smart-2be19951-259a-481f-8990-9b6e6c0b87bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552917732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2552917732
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.652221630
Short name T308
Test name
Test status
Simulation time 2713268632 ps
CPU time 2.82 seconds
Started Aug 16 05:02:07 PM PDT 24
Finished Aug 16 05:02:10 PM PDT 24
Peak memory 200864 kb
Host smart-3a9e0d37-9a4c-4990-83ee-b9b2746e2334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652221630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.652221630
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3303031064
Short name T973
Test name
Test status
Simulation time 28858345303 ps
CPU time 24.66 seconds
Started Aug 16 05:02:06 PM PDT 24
Finished Aug 16 05:02:31 PM PDT 24
Peak memory 200352 kb
Host smart-71050bcb-60d1-4ad4-ad0b-70e1520243d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303031064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3303031064
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2845236349
Short name T875
Test name
Test status
Simulation time 19202533 ps
CPU time 0.57 seconds
Started Aug 16 05:05:02 PM PDT 24
Finished Aug 16 05:05:03 PM PDT 24
Peak memory 196224 kb
Host smart-69b54e42-f6ad-4832-b851-d14e8ea523e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845236349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2845236349
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3100384113
Short name T523
Test name
Test status
Simulation time 100333474157 ps
CPU time 136.83 seconds
Started Aug 16 05:04:54 PM PDT 24
Finished Aug 16 05:07:11 PM PDT 24
Peak memory 200904 kb
Host smart-8a35d972-de6f-4e0d-9cf7-13f02a492582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100384113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3100384113
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3444542665
Short name T125
Test name
Test status
Simulation time 21219820768 ps
CPU time 32.92 seconds
Started Aug 16 05:04:52 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 200968 kb
Host smart-12b5856c-eed3-48f0-94ce-147021b3adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444542665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3444542665
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2045975119
Short name T237
Test name
Test status
Simulation time 75147517916 ps
CPU time 38.62 seconds
Started Aug 16 05:04:51 PM PDT 24
Finished Aug 16 05:05:30 PM PDT 24
Peak memory 200852 kb
Host smart-53229351-f604-4b56-8859-2155ceb75cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045975119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2045975119
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1894041254
Short name T996
Test name
Test status
Simulation time 804270442245 ps
CPU time 1252.99 seconds
Started Aug 16 05:04:52 PM PDT 24
Finished Aug 16 05:25:45 PM PDT 24
Peak memory 200940 kb
Host smart-e3b7d772-8587-4f96-842d-f18138d82a5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894041254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1894041254
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.815669974
Short name T1009
Test name
Test status
Simulation time 67575652658 ps
CPU time 207.87 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:08:28 PM PDT 24
Peak memory 200864 kb
Host smart-a5ce2bee-b21f-4e67-b9a1-e48a14c084fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815669974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.815669974
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2606905718
Short name T579
Test name
Test status
Simulation time 1157252336 ps
CPU time 3.74 seconds
Started Aug 16 05:05:42 PM PDT 24
Finished Aug 16 05:05:45 PM PDT 24
Peak memory 199716 kb
Host smart-ba62018c-006b-43ef-b885-982f642ec23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606905718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2606905718
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.625079273
Short name T910
Test name
Test status
Simulation time 62274038839 ps
CPU time 24.53 seconds
Started Aug 16 05:04:52 PM PDT 24
Finished Aug 16 05:05:17 PM PDT 24
Peak memory 201012 kb
Host smart-e2f70afa-4f4a-4240-b9da-625247492b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625079273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.625079273
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2014446555
Short name T268
Test name
Test status
Simulation time 16569407434 ps
CPU time 421.08 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:12:02 PM PDT 24
Peak memory 200828 kb
Host smart-a1530862-a8d7-4656-bb2c-c9746e105e37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014446555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2014446555
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1087296315
Short name T1060
Test name
Test status
Simulation time 6851037711 ps
CPU time 7.44 seconds
Started Aug 16 05:04:53 PM PDT 24
Finished Aug 16 05:05:01 PM PDT 24
Peak memory 200124 kb
Host smart-62f9b303-5ed8-4795-a3be-6eb264a88e47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087296315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1087296315
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1972007976
Short name T895
Test name
Test status
Simulation time 144116976251 ps
CPU time 125.65 seconds
Started Aug 16 05:04:53 PM PDT 24
Finished Aug 16 05:06:59 PM PDT 24
Peak memory 200832 kb
Host smart-b85cb16f-6aa1-4da1-a615-f4cd02e3cb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972007976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1972007976
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1585433168
Short name T320
Test name
Test status
Simulation time 1335689613 ps
CPU time 1.59 seconds
Started Aug 16 05:04:51 PM PDT 24
Finished Aug 16 05:04:52 PM PDT 24
Peak memory 196368 kb
Host smart-7dfbc0d8-f124-4d4e-8c12-636d1e76512e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585433168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1585433168
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2448798903
Short name T810
Test name
Test status
Simulation time 109545327 ps
CPU time 0.87 seconds
Started Aug 16 05:04:51 PM PDT 24
Finished Aug 16 05:04:52 PM PDT 24
Peak memory 198060 kb
Host smart-dafb8f20-670c-4a2b-a55c-22abd56ea959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448798903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2448798903
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3318771860
Short name T36
Test name
Test status
Simulation time 3159376940 ps
CPU time 38.9 seconds
Started Aug 16 05:05:02 PM PDT 24
Finished Aug 16 05:05:41 PM PDT 24
Peak memory 216852 kb
Host smart-aae84dcc-78ca-4539-9d9f-4e36b06484eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318771860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3318771860
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3747733870
Short name T264
Test name
Test status
Simulation time 1512151915 ps
CPU time 1.88 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:05:02 PM PDT 24
Peak memory 200816 kb
Host smart-8de68391-0c16-4b75-abfe-11fcb8ca0a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747733870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3747733870
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2018996061
Short name T801
Test name
Test status
Simulation time 111478332070 ps
CPU time 312.94 seconds
Started Aug 16 05:04:51 PM PDT 24
Finished Aug 16 05:10:04 PM PDT 24
Peak memory 200904 kb
Host smart-5b3e8b30-1e5a-4584-bff2-5c027a4bc3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018996061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2018996061
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4205193341
Short name T641
Test name
Test status
Simulation time 34947367 ps
CPU time 0.59 seconds
Started Aug 16 05:05:03 PM PDT 24
Finished Aug 16 05:05:04 PM PDT 24
Peak memory 196212 kb
Host smart-55e7f487-e259-4bc5-af49-2eafd02c4b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205193341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4205193341
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1623901250
Short name T1077
Test name
Test status
Simulation time 48419384739 ps
CPU time 21.76 seconds
Started Aug 16 05:05:01 PM PDT 24
Finished Aug 16 05:05:23 PM PDT 24
Peak memory 200912 kb
Host smart-819d440c-e71b-4a82-b53f-4c094e6dd71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623901250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1623901250
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2295130430
Short name T140
Test name
Test status
Simulation time 235592690330 ps
CPU time 71.34 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:06:11 PM PDT 24
Peak memory 200780 kb
Host smart-d84b3ece-bb2e-4b0d-bf83-7f8c203470c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295130430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2295130430
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3233327334
Short name T944
Test name
Test status
Simulation time 213318015765 ps
CPU time 246.68 seconds
Started Aug 16 05:05:06 PM PDT 24
Finished Aug 16 05:09:13 PM PDT 24
Peak memory 200888 kb
Host smart-546a36c9-25a6-4758-a440-f7c8615fac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233327334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3233327334
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1942235615
Short name T353
Test name
Test status
Simulation time 5315983776 ps
CPU time 1.69 seconds
Started Aug 16 05:04:59 PM PDT 24
Finished Aug 16 05:05:01 PM PDT 24
Peak memory 197404 kb
Host smart-c958484d-5beb-484b-bf33-96aa3e7d5cdc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942235615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1942235615
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.994746114
Short name T554
Test name
Test status
Simulation time 123469857508 ps
CPU time 619.74 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:15:20 PM PDT 24
Peak memory 200852 kb
Host smart-e0b40407-7f41-4e02-878d-d7928a7170c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994746114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.994746114
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3611775983
Short name T380
Test name
Test status
Simulation time 3814139954 ps
CPU time 9.16 seconds
Started Aug 16 05:05:01 PM PDT 24
Finished Aug 16 05:05:10 PM PDT 24
Peak memory 199444 kb
Host smart-fcef40a1-a793-4cac-99f0-2dd84b45e171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611775983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3611775983
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2174127624
Short name T844
Test name
Test status
Simulation time 101742360623 ps
CPU time 130.82 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:07:11 PM PDT 24
Peak memory 200928 kb
Host smart-61ac03fe-1802-40e2-ac1d-71bfdf0780d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174127624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2174127624
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3758883516
Short name T1154
Test name
Test status
Simulation time 13297480577 ps
CPU time 607.72 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:15:08 PM PDT 24
Peak memory 200888 kb
Host smart-bfa393a9-548a-429a-b0c8-9ec6066a748e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758883516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3758883516
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3419199547
Short name T540
Test name
Test status
Simulation time 3789044534 ps
CPU time 21.11 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:05:21 PM PDT 24
Peak memory 198972 kb
Host smart-8a775954-921c-434a-b8ae-8a8930976246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419199547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3419199547
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2955692727
Short name T118
Test name
Test status
Simulation time 116828371490 ps
CPU time 29 seconds
Started Aug 16 05:05:03 PM PDT 24
Finished Aug 16 05:05:32 PM PDT 24
Peak memory 200536 kb
Host smart-2e346e79-a06e-4084-895d-7eb6fa1bb712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955692727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2955692727
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1674344040
Short name T1100
Test name
Test status
Simulation time 1947825737 ps
CPU time 3.49 seconds
Started Aug 16 05:04:59 PM PDT 24
Finished Aug 16 05:05:02 PM PDT 24
Peak memory 196560 kb
Host smart-405f0b4e-ea9e-4a76-a44d-488c3a918b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674344040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1674344040
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.533883965
Short name T939
Test name
Test status
Simulation time 267432383 ps
CPU time 1.64 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:05:02 PM PDT 24
Peak memory 199680 kb
Host smart-8f8ff44a-f2f9-4aa4-9715-d24a6caf021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533883965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.533883965
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1746419954
Short name T1151
Test name
Test status
Simulation time 77423765840 ps
CPU time 36.56 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:05:36 PM PDT 24
Peak memory 200876 kb
Host smart-471d195c-3966-457e-91d7-498cc9c39cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746419954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1746419954
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1193445131
Short name T726
Test name
Test status
Simulation time 781466227 ps
CPU time 1.72 seconds
Started Aug 16 05:05:01 PM PDT 24
Finished Aug 16 05:05:03 PM PDT 24
Peak memory 199176 kb
Host smart-ef8f9e51-eb03-4bea-ba70-30316ae3e799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193445131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1193445131
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.4187554057
Short name T716
Test name
Test status
Simulation time 55681762466 ps
CPU time 98 seconds
Started Aug 16 05:04:59 PM PDT 24
Finished Aug 16 05:06:37 PM PDT 24
Peak memory 200900 kb
Host smart-321ae170-c7bc-4d6e-a4f2-15d2c92be068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187554057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.4187554057
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2258092817
Short name T1128
Test name
Test status
Simulation time 62568726 ps
CPU time 0.56 seconds
Started Aug 16 05:05:09 PM PDT 24
Finished Aug 16 05:05:09 PM PDT 24
Peak memory 196212 kb
Host smart-98521a45-8b09-4a59-99ee-47370c702258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258092817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2258092817
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.308464322
Short name T1040
Test name
Test status
Simulation time 53948900833 ps
CPU time 11.24 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:05:12 PM PDT 24
Peak memory 200692 kb
Host smart-4cbf1724-e9d8-4f56-b317-57fe1a0a88bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308464322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.308464322
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1775897081
Short name T907
Test name
Test status
Simulation time 79211979209 ps
CPU time 64.8 seconds
Started Aug 16 05:04:59 PM PDT 24
Finished Aug 16 05:06:04 PM PDT 24
Peak memory 200864 kb
Host smart-7ed037cc-2015-4ecc-b744-0556cc1d5b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775897081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1775897081
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.92252525
Short name T1179
Test name
Test status
Simulation time 63346709229 ps
CPU time 150.63 seconds
Started Aug 16 05:05:01 PM PDT 24
Finished Aug 16 05:07:32 PM PDT 24
Peak memory 200916 kb
Host smart-699e1042-25d9-48e9-a7a2-cc07f8e3c14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92252525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.92252525
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3092157306
Short name T902
Test name
Test status
Simulation time 147514491949 ps
CPU time 206.49 seconds
Started Aug 16 05:04:59 PM PDT 24
Finished Aug 16 05:08:26 PM PDT 24
Peak memory 197600 kb
Host smart-db10acdb-db99-4ce8-a7b9-b80035b63c3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092157306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3092157306
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2002981716
Short name T946
Test name
Test status
Simulation time 49740766594 ps
CPU time 292.47 seconds
Started Aug 16 05:05:08 PM PDT 24
Finished Aug 16 05:10:01 PM PDT 24
Peak memory 200744 kb
Host smart-ffe9d975-8f21-4799-9120-0eaed40a7d17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002981716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2002981716
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2647356902
Short name T596
Test name
Test status
Simulation time 4318870142 ps
CPU time 5.7 seconds
Started Aug 16 05:05:09 PM PDT 24
Finished Aug 16 05:05:15 PM PDT 24
Peak memory 199620 kb
Host smart-e5970134-5064-450c-b0fd-eff03b0833de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647356902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2647356902
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3187068939
Short name T1059
Test name
Test status
Simulation time 89122633926 ps
CPU time 72.92 seconds
Started Aug 16 05:05:00 PM PDT 24
Finished Aug 16 05:06:13 PM PDT 24
Peak memory 201076 kb
Host smart-3f90b4c9-6b19-46bf-a3b1-d45c956a4a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187068939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3187068939
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2724129512
Short name T575
Test name
Test status
Simulation time 10075000880 ps
CPU time 112.55 seconds
Started Aug 16 05:05:06 PM PDT 24
Finished Aug 16 05:06:59 PM PDT 24
Peak memory 200920 kb
Host smart-18fb3534-addb-47ca-a5ca-14f0aeee14cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724129512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2724129512
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3589647444
Short name T714
Test name
Test status
Simulation time 5683670751 ps
CPU time 48.48 seconds
Started Aug 16 05:05:01 PM PDT 24
Finished Aug 16 05:05:49 PM PDT 24
Peak memory 199148 kb
Host smart-b30e8523-5e25-44e5-8ab2-aec88f38e1d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589647444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3589647444
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.4256469816
Short name T511
Test name
Test status
Simulation time 30365495595 ps
CPU time 17.7 seconds
Started Aug 16 05:05:01 PM PDT 24
Finished Aug 16 05:05:19 PM PDT 24
Peak memory 200892 kb
Host smart-211e72de-9fac-4f5f-b5ea-b6534521ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256469816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.4256469816
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3703659165
Short name T987
Test name
Test status
Simulation time 24627581198 ps
CPU time 17.86 seconds
Started Aug 16 05:05:02 PM PDT 24
Finished Aug 16 05:05:20 PM PDT 24
Peak memory 197372 kb
Host smart-ecf5c1c8-3fa5-4a8a-b048-313007f400d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703659165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3703659165
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3326132886
Short name T934
Test name
Test status
Simulation time 6156678568 ps
CPU time 7.96 seconds
Started Aug 16 05:05:02 PM PDT 24
Finished Aug 16 05:05:10 PM PDT 24
Peak memory 200876 kb
Host smart-69b706bb-0c10-4e9c-bcd4-7bd1d7a9b784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326132886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3326132886
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3973199226
Short name T611
Test name
Test status
Simulation time 33200798635 ps
CPU time 435.46 seconds
Started Aug 16 05:05:10 PM PDT 24
Finished Aug 16 05:12:25 PM PDT 24
Peak memory 200924 kb
Host smart-97b543b3-bc74-4b68-a50d-7773cdaf7b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973199226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3973199226
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1653961688
Short name T742
Test name
Test status
Simulation time 3147974241 ps
CPU time 43.31 seconds
Started Aug 16 05:05:07 PM PDT 24
Finished Aug 16 05:05:50 PM PDT 24
Peak memory 210392 kb
Host smart-18aea277-6f2a-474e-ae34-188d7c74cd2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653961688 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1653961688
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1760016893
Short name T296
Test name
Test status
Simulation time 1392221218 ps
CPU time 4.58 seconds
Started Aug 16 05:05:08 PM PDT 24
Finished Aug 16 05:05:13 PM PDT 24
Peak memory 200140 kb
Host smart-d2c3ba6b-5ca0-4bd6-a01e-d00048471299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760016893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1760016893
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.555296299
Short name T598
Test name
Test status
Simulation time 82009503227 ps
CPU time 65.54 seconds
Started Aug 16 05:04:58 PM PDT 24
Finished Aug 16 05:06:04 PM PDT 24
Peak memory 200916 kb
Host smart-f51d86a2-c33c-4eb4-8d5d-3d870366717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555296299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.555296299
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.438950252
Short name T481
Test name
Test status
Simulation time 12443432 ps
CPU time 0.56 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:05:18 PM PDT 24
Peak memory 196520 kb
Host smart-179c6d6b-8929-4b24-acf0-c25bb006d1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438950252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.438950252
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1714065107
Short name T1000
Test name
Test status
Simulation time 142441230922 ps
CPU time 57.62 seconds
Started Aug 16 05:05:09 PM PDT 24
Finished Aug 16 05:06:06 PM PDT 24
Peak memory 200852 kb
Host smart-bc2944c4-24db-410d-bf35-7eeca7f64449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714065107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1714065107
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1094732390
Short name T123
Test name
Test status
Simulation time 19702826813 ps
CPU time 92.75 seconds
Started Aug 16 05:05:06 PM PDT 24
Finished Aug 16 05:06:39 PM PDT 24
Peak memory 200900 kb
Host smart-f02890ba-fd57-4445-8cc2-a08dd6698fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094732390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1094732390
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2867059404
Short name T704
Test name
Test status
Simulation time 183123520917 ps
CPU time 396.42 seconds
Started Aug 16 05:05:08 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 200720 kb
Host smart-902349b7-1a39-4c30-a775-126b9d66b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867059404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2867059404
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4259306868
Short name T100
Test name
Test status
Simulation time 18059071762 ps
CPU time 33 seconds
Started Aug 16 05:05:08 PM PDT 24
Finished Aug 16 05:05:41 PM PDT 24
Peak memory 200836 kb
Host smart-43feee78-0e25-45c0-902c-b1e884a21102
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259306868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4259306868
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3310748467
Short name T505
Test name
Test status
Simulation time 148173332802 ps
CPU time 1399.98 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:28:38 PM PDT 24
Peak memory 200900 kb
Host smart-e8bc447b-e34e-47a4-90b6-80b430be349e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310748467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3310748467
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3831334479
Short name T1026
Test name
Test status
Simulation time 735212561 ps
CPU time 1.85 seconds
Started Aug 16 05:05:07 PM PDT 24
Finished Aug 16 05:05:08 PM PDT 24
Peak memory 198184 kb
Host smart-ce6adbb6-81fc-4e8f-87f8-34ddcdec1d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831334479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3831334479
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.106091666
Short name T470
Test name
Test status
Simulation time 140753873852 ps
CPU time 62.58 seconds
Started Aug 16 05:05:08 PM PDT 24
Finished Aug 16 05:06:11 PM PDT 24
Peak memory 200980 kb
Host smart-a9dbd107-554c-487d-b693-4e862c37dff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106091666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.106091666
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1625944215
Short name T795
Test name
Test status
Simulation time 10906748579 ps
CPU time 604.89 seconds
Started Aug 16 05:05:07 PM PDT 24
Finished Aug 16 05:15:12 PM PDT 24
Peak memory 200816 kb
Host smart-df3d130e-22eb-4423-8b08-b8c65a566cf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625944215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1625944215
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2856680262
Short name T482
Test name
Test status
Simulation time 2848952851 ps
CPU time 5.04 seconds
Started Aug 16 05:05:07 PM PDT 24
Finished Aug 16 05:05:12 PM PDT 24
Peak memory 198988 kb
Host smart-34e1fc01-d1c1-47ad-8bf8-02219f78a1de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856680262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2856680262
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2821440721
Short name T1099
Test name
Test status
Simulation time 15197130208 ps
CPU time 24.65 seconds
Started Aug 16 05:05:09 PM PDT 24
Finished Aug 16 05:05:34 PM PDT 24
Peak memory 200916 kb
Host smart-0540bcd6-6ee4-4a15-ad9d-1b52e5451409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821440721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2821440721
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.838031117
Short name T1095
Test name
Test status
Simulation time 28497487872 ps
CPU time 3.17 seconds
Started Aug 16 05:05:08 PM PDT 24
Finished Aug 16 05:05:12 PM PDT 24
Peak memory 197724 kb
Host smart-0ee26390-6cf8-4bc4-b994-4d28db9ad345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838031117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.838031117
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1961692062
Short name T909
Test name
Test status
Simulation time 6295735032 ps
CPU time 16.64 seconds
Started Aug 16 05:05:07 PM PDT 24
Finished Aug 16 05:05:23 PM PDT 24
Peak memory 200908 kb
Host smart-cd14ca54-06ad-4941-972d-3d6509005039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961692062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1961692062
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2746360095
Short name T87
Test name
Test status
Simulation time 19124090921 ps
CPU time 32.92 seconds
Started Aug 16 05:05:17 PM PDT 24
Finished Aug 16 05:05:50 PM PDT 24
Peak memory 209452 kb
Host smart-f69de496-b9cc-4b27-af9e-40984da634e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746360095 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2746360095
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.4274237346
Short name T404
Test name
Test status
Simulation time 6756829116 ps
CPU time 13.44 seconds
Started Aug 16 05:05:08 PM PDT 24
Finished Aug 16 05:05:21 PM PDT 24
Peak memory 200336 kb
Host smart-af845bbd-0ab2-4f77-a80e-16c485e6c3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274237346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.4274237346
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2416091961
Short name T499
Test name
Test status
Simulation time 143276221121 ps
CPU time 103.64 seconds
Started Aug 16 05:05:09 PM PDT 24
Finished Aug 16 05:06:53 PM PDT 24
Peak memory 200844 kb
Host smart-aee58d25-1bad-4b19-93c8-615d851081c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416091961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2416091961
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.511684861
Short name T852
Test name
Test status
Simulation time 13585475 ps
CPU time 0.55 seconds
Started Aug 16 05:05:17 PM PDT 24
Finished Aug 16 05:05:18 PM PDT 24
Peak memory 196228 kb
Host smart-2b5ca91f-9966-4b15-8fc8-cd9a9ec387d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511684861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.511684861
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4221950201
Short name T1007
Test name
Test status
Simulation time 47558388806 ps
CPU time 70.06 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:06:28 PM PDT 24
Peak memory 200760 kb
Host smart-d50c862d-a479-4277-a1eb-dbce60266d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221950201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4221950201
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1896518922
Short name T893
Test name
Test status
Simulation time 261123843497 ps
CPU time 166.95 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:08:03 PM PDT 24
Peak memory 200952 kb
Host smart-71f6dfb7-204e-41f3-858d-8694de1badce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896518922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1896518922
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.257971718
Short name T166
Test name
Test status
Simulation time 9766788487 ps
CPU time 14.23 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:05:32 PM PDT 24
Peak memory 200904 kb
Host smart-d33a43f1-e210-44e2-9342-a048a583253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257971718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.257971718
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.760556141
Short name T773
Test name
Test status
Simulation time 7906992921 ps
CPU time 6.27 seconds
Started Aug 16 05:05:14 PM PDT 24
Finished Aug 16 05:05:21 PM PDT 24
Peak memory 197608 kb
Host smart-7c9daeb4-00e6-43e2-80ba-b0c1f846714c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760556141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.760556141
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3161698735
Short name T351
Test name
Test status
Simulation time 103542612638 ps
CPU time 720.23 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:17:16 PM PDT 24
Peak memory 200892 kb
Host smart-e45f1699-6d9a-4259-b35b-5335c8e7adb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161698735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3161698735
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.272874638
Short name T980
Test name
Test status
Simulation time 371352110 ps
CPU time 1.33 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:05:19 PM PDT 24
Peak memory 199164 kb
Host smart-4eff765e-44ce-4dda-939a-da94ed2d15b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272874638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.272874638
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3059767361
Short name T884
Test name
Test status
Simulation time 64687631564 ps
CPU time 128.6 seconds
Started Aug 16 05:05:17 PM PDT 24
Finished Aug 16 05:07:26 PM PDT 24
Peak memory 209144 kb
Host smart-406894e9-9d76-42ef-9467-6f9b9bd97635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059767361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3059767361
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.369698275
Short name T258
Test name
Test status
Simulation time 26928585664 ps
CPU time 214.26 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:08:52 PM PDT 24
Peak memory 200868 kb
Host smart-45afd6b3-53b6-4ba2-9e4e-20bdb90fab87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369698275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.369698275
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3706800405
Short name T1080
Test name
Test status
Simulation time 5904951314 ps
CPU time 12.57 seconds
Started Aug 16 05:05:17 PM PDT 24
Finished Aug 16 05:05:30 PM PDT 24
Peak memory 200804 kb
Host smart-d730c75f-403b-4603-8cc1-312116caba9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706800405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3706800405
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3198340371
Short name T718
Test name
Test status
Simulation time 39852926849 ps
CPU time 118.82 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:07:15 PM PDT 24
Peak memory 200860 kb
Host smart-e0d2e2cc-0694-4b5a-94c7-544ed81ec509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198340371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3198340371
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3432799162
Short name T777
Test name
Test status
Simulation time 2998307289 ps
CPU time 1.25 seconds
Started Aug 16 05:05:17 PM PDT 24
Finished Aug 16 05:05:18 PM PDT 24
Peak memory 197516 kb
Host smart-76520f4c-5c71-4342-ab13-b68e33b5174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432799162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3432799162
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.4087232092
Short name T394
Test name
Test status
Simulation time 487786265 ps
CPU time 1.17 seconds
Started Aug 16 05:05:17 PM PDT 24
Finished Aug 16 05:05:18 PM PDT 24
Peak memory 199536 kb
Host smart-daa89920-cad1-4d66-ac68-93097284c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087232092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4087232092
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1340225992
Short name T1012
Test name
Test status
Simulation time 367445909443 ps
CPU time 586.15 seconds
Started Aug 16 05:05:15 PM PDT 24
Finished Aug 16 05:15:01 PM PDT 24
Peak memory 209288 kb
Host smart-d9afd0c3-76e2-4aee-bd02-95e3cfb9170c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340225992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1340225992
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3286861037
Short name T646
Test name
Test status
Simulation time 6835468612 ps
CPU time 23.68 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:05:42 PM PDT 24
Peak memory 217324 kb
Host smart-a1f881df-aa53-4260-8545-248ba89d7f25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286861037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3286861037
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.586962809
Short name T417
Test name
Test status
Simulation time 8143740246 ps
CPU time 10.33 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:05:26 PM PDT 24
Peak memory 200820 kb
Host smart-59a0dc1b-fb3a-422c-b59d-9f45b3b5ea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586962809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.586962809
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1430679290
Short name T1172
Test name
Test status
Simulation time 23598877476 ps
CPU time 17.64 seconds
Started Aug 16 05:05:17 PM PDT 24
Finished Aug 16 05:05:35 PM PDT 24
Peak memory 200836 kb
Host smart-c29b68c7-1e87-4f87-a381-c414d007d27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430679290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1430679290
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3682007603
Short name T1020
Test name
Test status
Simulation time 41377983 ps
CPU time 0.56 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:05:24 PM PDT 24
Peak memory 196228 kb
Host smart-dc40ec79-cdbf-468c-b19b-9efde67fed90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682007603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3682007603
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1193133303
Short name T446
Test name
Test status
Simulation time 117217147503 ps
CPU time 183.45 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:08:19 PM PDT 24
Peak memory 200932 kb
Host smart-bec58eeb-ebbb-4d7d-a9dd-f07bffbe2d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193133303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1193133303
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1706041391
Short name T639
Test name
Test status
Simulation time 69027214467 ps
CPU time 93.95 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:06:52 PM PDT 24
Peak memory 200848 kb
Host smart-051c7518-f73b-445e-8cc2-6b08d056c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706041391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1706041391
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4239246875
Short name T185
Test name
Test status
Simulation time 74745511624 ps
CPU time 31.69 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:05:48 PM PDT 24
Peak memory 200776 kb
Host smart-cd4c9dba-8c50-47fd-b6d5-6d83625c4555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239246875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4239246875
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3328027803
Short name T890
Test name
Test status
Simulation time 99095611926 ps
CPU time 131.44 seconds
Started Aug 16 05:05:17 PM PDT 24
Finished Aug 16 05:07:28 PM PDT 24
Peak memory 199164 kb
Host smart-dc014d8a-6409-498c-95a8-c66a5c55d9f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328027803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3328027803
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1935524051
Short name T591
Test name
Test status
Simulation time 73853599136 ps
CPU time 305.69 seconds
Started Aug 16 05:05:23 PM PDT 24
Finished Aug 16 05:10:29 PM PDT 24
Peak memory 200864 kb
Host smart-171d918a-0170-40f5-abac-5a70295ae591
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935524051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1935524051
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3239737233
Short name T667
Test name
Test status
Simulation time 2732308606 ps
CPU time 1.05 seconds
Started Aug 16 05:05:23 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 197180 kb
Host smart-02a5bf23-03f5-4876-b643-ef7dc730bf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239737233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3239737233
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.4132814255
Short name T489
Test name
Test status
Simulation time 100996561665 ps
CPU time 17.06 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:05:35 PM PDT 24
Peak memory 209064 kb
Host smart-4550cf9e-0827-4e93-b2ba-be3f6c53f7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132814255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4132814255
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.119234626
Short name T502
Test name
Test status
Simulation time 15260221521 ps
CPU time 435.35 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:12:40 PM PDT 24
Peak memory 200908 kb
Host smart-8ef98ac8-18fa-4d04-9775-42fd1cc9a317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119234626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.119234626
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3495912200
Short name T374
Test name
Test status
Simulation time 3153748899 ps
CPU time 17.65 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:05:34 PM PDT 24
Peak memory 198984 kb
Host smart-34239771-3e6d-4741-a8cc-e25860a683a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3495912200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3495912200
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2509669244
Short name T737
Test name
Test status
Simulation time 75494653056 ps
CPU time 20.58 seconds
Started Aug 16 05:05:23 PM PDT 24
Finished Aug 16 05:05:43 PM PDT 24
Peak memory 200908 kb
Host smart-6ab19b78-65c1-4f95-b39a-322c7d45d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509669244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2509669244
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2759259507
Short name T1125
Test name
Test status
Simulation time 1551441970 ps
CPU time 1.13 seconds
Started Aug 16 05:05:15 PM PDT 24
Finished Aug 16 05:05:16 PM PDT 24
Peak memory 196376 kb
Host smart-15465f42-bfb1-4952-8679-29167c9ea4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759259507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2759259507
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.151659833
Short name T306
Test name
Test status
Simulation time 637762868 ps
CPU time 1.88 seconds
Started Aug 16 05:05:18 PM PDT 24
Finished Aug 16 05:05:20 PM PDT 24
Peak memory 200260 kb
Host smart-26286340-6114-4937-b9c2-899890ef4f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151659833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.151659833
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3121405698
Short name T1046
Test name
Test status
Simulation time 170843189981 ps
CPU time 223.64 seconds
Started Aug 16 05:05:25 PM PDT 24
Finished Aug 16 05:09:09 PM PDT 24
Peak memory 216868 kb
Host smart-5835a075-1120-48bf-885a-aa63a1a3d74f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121405698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3121405698
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1195256438
Short name T85
Test name
Test status
Simulation time 2717772622 ps
CPU time 46.81 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:06:11 PM PDT 24
Peak memory 217276 kb
Host smart-b4a2f9ba-2957-497e-ae5e-7e097a80610f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195256438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1195256438
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3624865340
Short name T337
Test name
Test status
Simulation time 7383366210 ps
CPU time 13.57 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:05:37 PM PDT 24
Peak memory 200884 kb
Host smart-2c16c90a-0733-4130-9b4e-d7f58fb7108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624865340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3624865340
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.680075884
Short name T345
Test name
Test status
Simulation time 19668590445 ps
CPU time 28.07 seconds
Started Aug 16 05:05:16 PM PDT 24
Finished Aug 16 05:05:45 PM PDT 24
Peak memory 200876 kb
Host smart-d76cf904-31ce-443e-a0a4-ad3c56e9ae28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680075884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.680075884
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.186609488
Short name T517
Test name
Test status
Simulation time 13160994 ps
CPU time 0.58 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 196172 kb
Host smart-bed9aa72-367b-4819-b76f-b8e808034f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186609488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.186609488
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.603288641
Short name T700
Test name
Test status
Simulation time 160590069907 ps
CPU time 129.65 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:07:34 PM PDT 24
Peak memory 200836 kb
Host smart-8d1abd36-95fd-4db8-acfe-64d2af6d3b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603288641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.603288641
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3058410511
Short name T1141
Test name
Test status
Simulation time 29422063251 ps
CPU time 49.73 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:06:14 PM PDT 24
Peak memory 200844 kb
Host smart-c796a2f0-2f90-4b5e-8c40-53ae1faeec54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058410511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3058410511
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1922505054
Short name T235
Test name
Test status
Simulation time 86760092676 ps
CPU time 134.65 seconds
Started Aug 16 05:05:26 PM PDT 24
Finished Aug 16 05:07:41 PM PDT 24
Peak memory 200940 kb
Host smart-5c0c1c57-d860-40f3-b45d-c7cc438b10e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922505054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1922505054
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3962511988
Short name T22
Test name
Test status
Simulation time 31290664996 ps
CPU time 26.26 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:05:51 PM PDT 24
Peak memory 200696 kb
Host smart-4dd451c9-9789-4c3f-ae59-0b948e7a71ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962511988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3962511988
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2665675967
Short name T779
Test name
Test status
Simulation time 107180320776 ps
CPU time 460.89 seconds
Started Aug 16 05:05:25 PM PDT 24
Finished Aug 16 05:13:06 PM PDT 24
Peak memory 200788 kb
Host smart-29f04661-f4e8-45a1-8def-ea685133073b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665675967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2665675967
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2085178889
Short name T27
Test name
Test status
Simulation time 2730384125 ps
CPU time 1.28 seconds
Started Aug 16 05:05:25 PM PDT 24
Finished Aug 16 05:05:27 PM PDT 24
Peak memory 199276 kb
Host smart-abcc1704-70d6-4338-8e2d-75bfa27ab418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085178889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2085178889
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1281410292
Short name T261
Test name
Test status
Simulation time 157798619560 ps
CPU time 124.26 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:07:28 PM PDT 24
Peak memory 200472 kb
Host smart-d7f957c4-a4c6-4ae4-bee0-cb42d8978d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281410292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1281410292
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2649114177
Short name T1011
Test name
Test status
Simulation time 10588504954 ps
CPU time 619.75 seconds
Started Aug 16 05:05:26 PM PDT 24
Finished Aug 16 05:15:46 PM PDT 24
Peak memory 200984 kb
Host smart-9cd151b2-c693-4103-a584-00c1f956470b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649114177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2649114177
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1568024391
Short name T455
Test name
Test status
Simulation time 5668282989 ps
CPU time 11.7 seconds
Started Aug 16 05:05:20 PM PDT 24
Finished Aug 16 05:05:32 PM PDT 24
Peak memory 199060 kb
Host smart-02d82344-a6c8-4b41-9ffd-18f94b4ad54e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568024391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1568024391
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.768715909
Short name T316
Test name
Test status
Simulation time 108642484517 ps
CPU time 33.29 seconds
Started Aug 16 05:05:26 PM PDT 24
Finished Aug 16 05:06:00 PM PDT 24
Peak memory 200828 kb
Host smart-ddb1a5ef-e4a8-4bc1-b0b3-c9d39bf2b489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768715909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.768715909
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3169237942
Short name T327
Test name
Test status
Simulation time 1555627715 ps
CPU time 2.01 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:05:26 PM PDT 24
Peak memory 196416 kb
Host smart-4b2bd65e-cdf7-42fd-9914-ab9f70eff132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169237942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3169237942
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1152873900
Short name T981
Test name
Test status
Simulation time 127626217 ps
CPU time 0.92 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:05:25 PM PDT 24
Peak memory 199196 kb
Host smart-599ebe80-2c5e-430e-837c-241222688fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152873900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1152873900
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.903065602
Short name T568
Test name
Test status
Simulation time 248649150395 ps
CPU time 302.35 seconds
Started Aug 16 05:05:24 PM PDT 24
Finished Aug 16 05:10:26 PM PDT 24
Peak memory 200932 kb
Host smart-aa9dbb6c-93b5-4e01-b9b8-5045ee2c16eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903065602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.903065602
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2236563571
Short name T356
Test name
Test status
Simulation time 2157038457 ps
CPU time 40.04 seconds
Started Aug 16 05:05:23 PM PDT 24
Finished Aug 16 05:06:03 PM PDT 24
Peak memory 217584 kb
Host smart-1159b767-728c-40fc-86b4-a54d56290f56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236563571 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2236563571
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.876669516
Short name T845
Test name
Test status
Simulation time 649918152 ps
CPU time 1.9 seconds
Started Aug 16 05:05:26 PM PDT 24
Finished Aug 16 05:05:28 PM PDT 24
Peak memory 198880 kb
Host smart-22276166-cb09-499f-b39d-e6f77aa95c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876669516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.876669516
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2780817708
Short name T1027
Test name
Test status
Simulation time 48815169184 ps
CPU time 37.87 seconds
Started Aug 16 05:05:22 PM PDT 24
Finished Aug 16 05:06:00 PM PDT 24
Peak memory 200908 kb
Host smart-5a88f8d1-8656-497d-8fa4-0379beb71ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780817708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2780817708
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.354905944
Short name T536
Test name
Test status
Simulation time 11854945 ps
CPU time 0.53 seconds
Started Aug 16 05:05:30 PM PDT 24
Finished Aug 16 05:05:31 PM PDT 24
Peak memory 195200 kb
Host smart-ecadeeea-8098-4178-9142-34d30c99f0ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354905944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.354905944
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3482889516
Short name T339
Test name
Test status
Simulation time 61370743703 ps
CPU time 108.52 seconds
Started Aug 16 05:05:26 PM PDT 24
Finished Aug 16 05:07:14 PM PDT 24
Peak memory 200932 kb
Host smart-ac6e270b-e49b-4b5c-93b3-a080b4f204fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482889516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3482889516
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4096422897
Short name T643
Test name
Test status
Simulation time 34153886666 ps
CPU time 59.16 seconds
Started Aug 16 05:05:26 PM PDT 24
Finished Aug 16 05:06:26 PM PDT 24
Peak memory 200984 kb
Host smart-7df5fcec-bc86-4d70-b082-e654c5a6bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096422897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4096422897
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1228245015
Short name T961
Test name
Test status
Simulation time 9328304188 ps
CPU time 13.51 seconds
Started Aug 16 05:05:26 PM PDT 24
Finished Aug 16 05:05:40 PM PDT 24
Peak memory 200936 kb
Host smart-f0ef3153-4feb-41f4-8680-8162f184970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228245015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1228245015
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1969111500
Short name T451
Test name
Test status
Simulation time 21207095784 ps
CPU time 13.38 seconds
Started Aug 16 05:05:32 PM PDT 24
Finished Aug 16 05:05:46 PM PDT 24
Peak memory 200652 kb
Host smart-87c79e6d-393e-4d2b-ac0a-e59ed9837c44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969111500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1969111500
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.205605890
Short name T947
Test name
Test status
Simulation time 90377013344 ps
CPU time 907.1 seconds
Started Aug 16 05:05:33 PM PDT 24
Finished Aug 16 05:20:40 PM PDT 24
Peak memory 200900 kb
Host smart-eccd190b-c67d-4f39-9447-b8a45496f5db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205605890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.205605890
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3434975162
Short name T709
Test name
Test status
Simulation time 1427762828 ps
CPU time 2.96 seconds
Started Aug 16 05:05:30 PM PDT 24
Finished Aug 16 05:05:33 PM PDT 24
Peak memory 196508 kb
Host smart-b4c067bd-35b0-424f-9c9d-680c8d226f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434975162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3434975162
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2438395079
Short name T991
Test name
Test status
Simulation time 138705237580 ps
CPU time 56.54 seconds
Started Aug 16 05:05:30 PM PDT 24
Finished Aug 16 05:06:27 PM PDT 24
Peak memory 201120 kb
Host smart-bf20c642-2c68-4c6a-88cf-cae10ecc599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438395079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2438395079
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.701117656
Short name T389
Test name
Test status
Simulation time 8411456841 ps
CPU time 518.9 seconds
Started Aug 16 05:05:33 PM PDT 24
Finished Aug 16 05:14:13 PM PDT 24
Peak memory 200896 kb
Host smart-459f2e1a-5010-4b33-a49d-e9472d519d84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701117656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.701117656
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1969326441
Short name T787
Test name
Test status
Simulation time 2989460496 ps
CPU time 5.03 seconds
Started Aug 16 05:05:33 PM PDT 24
Finished Aug 16 05:05:38 PM PDT 24
Peak memory 199868 kb
Host smart-39d8d5f3-32a8-4879-8d51-b5ac7a4a9277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969326441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1969326441
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3312567033
Short name T565
Test name
Test status
Simulation time 28598319855 ps
CPU time 47.92 seconds
Started Aug 16 05:05:31 PM PDT 24
Finished Aug 16 05:06:19 PM PDT 24
Peak memory 200860 kb
Host smart-7dc4ba5b-3992-421a-b172-5748901882bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312567033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3312567033
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.410560891
Short name T501
Test name
Test status
Simulation time 36780857696 ps
CPU time 26.32 seconds
Started Aug 16 05:05:31 PM PDT 24
Finished Aug 16 05:05:57 PM PDT 24
Peak memory 197724 kb
Host smart-9be36bf0-1ca8-438c-b2c1-8c82587a10ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410560891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.410560891
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.563609933
Short name T650
Test name
Test status
Simulation time 494059657 ps
CPU time 1.26 seconds
Started Aug 16 05:05:26 PM PDT 24
Finished Aug 16 05:05:27 PM PDT 24
Peak memory 199208 kb
Host smart-06179b97-14b1-4f11-ba16-09eae69d277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563609933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.563609933
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3047080556
Short name T619
Test name
Test status
Simulation time 1499969538 ps
CPU time 15.86 seconds
Started Aug 16 05:05:31 PM PDT 24
Finished Aug 16 05:05:47 PM PDT 24
Peak memory 209020 kb
Host smart-005678e5-67de-4688-b004-00f97216248d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047080556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3047080556
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3855837677
Short name T424
Test name
Test status
Simulation time 2622242459 ps
CPU time 2.67 seconds
Started Aug 16 05:05:32 PM PDT 24
Finished Aug 16 05:05:35 PM PDT 24
Peak memory 199808 kb
Host smart-0b5c5bcb-aefe-4e24-b621-89e5966b6898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855837677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3855837677
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.454243975
Short name T558
Test name
Test status
Simulation time 149927323202 ps
CPU time 122.59 seconds
Started Aug 16 05:05:27 PM PDT 24
Finished Aug 16 05:07:30 PM PDT 24
Peak memory 200900 kb
Host smart-2f82c132-9c3e-43d4-bcf2-8834348e760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454243975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.454243975
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.704458081
Short name T1016
Test name
Test status
Simulation time 14723792 ps
CPU time 0.56 seconds
Started Aug 16 05:05:41 PM PDT 24
Finished Aug 16 05:05:41 PM PDT 24
Peak memory 196224 kb
Host smart-744e6481-6336-4bcd-bc28-7b47b1419bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704458081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.704458081
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2021457781
Short name T815
Test name
Test status
Simulation time 122582470974 ps
CPU time 116.98 seconds
Started Aug 16 05:05:30 PM PDT 24
Finished Aug 16 05:07:27 PM PDT 24
Peak memory 201020 kb
Host smart-eec5dc8a-df74-452f-81fd-3f784240cfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021457781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2021457781
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.4163096908
Short name T733
Test name
Test status
Simulation time 29118502364 ps
CPU time 51.17 seconds
Started Aug 16 05:06:07 PM PDT 24
Finished Aug 16 05:06:59 PM PDT 24
Peak memory 200848 kb
Host smart-856ad747-8e1c-48e8-9681-c7e59e7c5222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163096908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.4163096908
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3382803756
Short name T1169
Test name
Test status
Simulation time 201555177459 ps
CPU time 62.57 seconds
Started Aug 16 05:05:33 PM PDT 24
Finished Aug 16 05:06:35 PM PDT 24
Peak memory 200776 kb
Host smart-1f864173-b335-4b1c-bad4-173e09f7c605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382803756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3382803756
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.335223098
Short name T958
Test name
Test status
Simulation time 28807844237 ps
CPU time 12.05 seconds
Started Aug 16 05:05:32 PM PDT 24
Finished Aug 16 05:05:44 PM PDT 24
Peak memory 199868 kb
Host smart-16795ccc-a7c4-4009-9d81-63728498af13
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335223098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.335223098
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1584195749
Short name T863
Test name
Test status
Simulation time 124067870612 ps
CPU time 258.76 seconds
Started Aug 16 05:05:37 PM PDT 24
Finished Aug 16 05:09:56 PM PDT 24
Peak memory 200972 kb
Host smart-b54ef50d-e961-4c78-ad1d-0c21493d1565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1584195749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1584195749
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3173565052
Short name T1148
Test name
Test status
Simulation time 10106004365 ps
CPU time 21.26 seconds
Started Aug 16 05:05:38 PM PDT 24
Finished Aug 16 05:06:00 PM PDT 24
Peak memory 200872 kb
Host smart-da09c30e-f823-4584-9082-99075c5a9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173565052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3173565052
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1471852202
Short name T931
Test name
Test status
Simulation time 21983280819 ps
CPU time 9.5 seconds
Started Aug 16 05:05:30 PM PDT 24
Finished Aug 16 05:05:39 PM PDT 24
Peak memory 200996 kb
Host smart-e4e34441-f187-4a21-8c25-c44956448471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471852202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1471852202
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3011786109
Short name T1123
Test name
Test status
Simulation time 9717497606 ps
CPU time 522.98 seconds
Started Aug 16 05:05:41 PM PDT 24
Finished Aug 16 05:14:24 PM PDT 24
Peak memory 200920 kb
Host smart-f966265f-1488-4dfc-bcfb-6e7058a2464d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011786109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3011786109
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1673673848
Short name T698
Test name
Test status
Simulation time 4974613039 ps
CPU time 6.87 seconds
Started Aug 16 05:05:30 PM PDT 24
Finished Aug 16 05:05:37 PM PDT 24
Peak memory 198428 kb
Host smart-0ffd4adb-ce64-4c08-b105-2d4b0d067a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673673848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1673673848
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1873243434
Short name T515
Test name
Test status
Simulation time 18946238906 ps
CPU time 41.71 seconds
Started Aug 16 05:05:30 PM PDT 24
Finished Aug 16 05:06:12 PM PDT 24
Peak memory 200904 kb
Host smart-817eee01-e307-4ef4-be71-6c0aae5183b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873243434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1873243434
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3820177051
Short name T29
Test name
Test status
Simulation time 6451291615 ps
CPU time 10.91 seconds
Started Aug 16 05:05:32 PM PDT 24
Finished Aug 16 05:05:43 PM PDT 24
Peak memory 197052 kb
Host smart-8ef0a3ff-4809-4709-8d77-6fa1904ce88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820177051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3820177051
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2155773987
Short name T434
Test name
Test status
Simulation time 731021837 ps
CPU time 1.81 seconds
Started Aug 16 05:05:31 PM PDT 24
Finished Aug 16 05:05:33 PM PDT 24
Peak memory 200620 kb
Host smart-2211c8f3-982f-4df0-8c36-22a11c57f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155773987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2155773987
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.540730561
Short name T651
Test name
Test status
Simulation time 346876845525 ps
CPU time 903.62 seconds
Started Aug 16 05:05:40 PM PDT 24
Finished Aug 16 05:20:44 PM PDT 24
Peak memory 200908 kb
Host smart-21d67a3e-0043-4cbd-9df1-40716de24c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540730561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.540730561
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3655434647
Short name T685
Test name
Test status
Simulation time 9376341644 ps
CPU time 31.89 seconds
Started Aug 16 05:05:43 PM PDT 24
Finished Aug 16 05:06:15 PM PDT 24
Peak memory 210636 kb
Host smart-7141e853-48d1-4516-9ca5-c78d075a6215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655434647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3655434647
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3094152899
Short name T478
Test name
Test status
Simulation time 1252255098 ps
CPU time 1.38 seconds
Started Aug 16 05:05:31 PM PDT 24
Finished Aug 16 05:05:32 PM PDT 24
Peak memory 200016 kb
Host smart-ef4f8c7d-fec1-4090-bc9c-c4437fa11cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094152899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3094152899
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1155794739
Short name T539
Test name
Test status
Simulation time 93126118755 ps
CPU time 84.54 seconds
Started Aug 16 05:05:31 PM PDT 24
Finished Aug 16 05:06:55 PM PDT 24
Peak memory 200960 kb
Host smart-d4f9561d-ba76-4b5b-bb3a-5f93a36a859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155794739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1155794739
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.76336831
Short name T448
Test name
Test status
Simulation time 21071477 ps
CPU time 0.57 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:05:49 PM PDT 24
Peak memory 196212 kb
Host smart-921b3eed-7cc4-4c1b-9ac9-6fc7936bf297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76336831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.76336831
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3956550892
Short name T519
Test name
Test status
Simulation time 121201205619 ps
CPU time 275.45 seconds
Started Aug 16 05:05:38 PM PDT 24
Finished Aug 16 05:10:13 PM PDT 24
Peak memory 200860 kb
Host smart-9c25ef43-b3dc-491e-a50f-f3dc6c5f884c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956550892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3956550892
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3297812289
Short name T814
Test name
Test status
Simulation time 45142490258 ps
CPU time 36.9 seconds
Started Aug 16 05:05:39 PM PDT 24
Finished Aug 16 05:06:16 PM PDT 24
Peak memory 200812 kb
Host smart-18feb7a4-f3cc-4ad3-b324-1ea353e528e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297812289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3297812289
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.687708215
Short name T761
Test name
Test status
Simulation time 394264771435 ps
CPU time 618.48 seconds
Started Aug 16 05:05:40 PM PDT 24
Finished Aug 16 05:15:59 PM PDT 24
Peak memory 200860 kb
Host smart-3f80cc2c-1fbd-462e-993f-c721536a91cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687708215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.687708215
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.23145174
Short name T590
Test name
Test status
Simulation time 69450369937 ps
CPU time 318.34 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:11:07 PM PDT 24
Peak memory 200892 kb
Host smart-c5225706-06ba-4347-a179-cbcab30d7173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23145174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.23145174
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1192281466
Short name T416
Test name
Test status
Simulation time 5148507000 ps
CPU time 2.14 seconds
Started Aug 16 05:05:52 PM PDT 24
Finished Aug 16 05:05:54 PM PDT 24
Peak memory 198992 kb
Host smart-b372bf8b-7011-40e6-82ad-b81d0ff8a98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192281466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1192281466
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.799898567
Short name T881
Test name
Test status
Simulation time 202839664786 ps
CPU time 104.69 seconds
Started Aug 16 05:05:40 PM PDT 24
Finished Aug 16 05:07:25 PM PDT 24
Peak memory 209140 kb
Host smart-f5bfa841-3cf8-4ef8-b426-11a329eadc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799898567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.799898567
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2230251011
Short name T1119
Test name
Test status
Simulation time 24708071593 ps
CPU time 676.02 seconds
Started Aug 16 05:05:47 PM PDT 24
Finished Aug 16 05:17:03 PM PDT 24
Peak memory 200852 kb
Host smart-6c1eac90-abd7-4f15-a2c8-0707cfb8c0e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230251011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2230251011
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3098918266
Short name T748
Test name
Test status
Simulation time 6031201008 ps
CPU time 7.51 seconds
Started Aug 16 05:05:39 PM PDT 24
Finished Aug 16 05:05:47 PM PDT 24
Peak memory 200196 kb
Host smart-77b32e82-a352-408c-b61b-6f44debd1aa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098918266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3098918266
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3733154321
Short name T106
Test name
Test status
Simulation time 40952428868 ps
CPU time 32.07 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:20 PM PDT 24
Peak memory 200812 kb
Host smart-d3042802-2018-49c5-9b74-89add5575e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733154321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3733154321
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.835701344
Short name T612
Test name
Test status
Simulation time 1695505751 ps
CPU time 2.01 seconds
Started Aug 16 05:05:40 PM PDT 24
Finished Aug 16 05:05:43 PM PDT 24
Peak memory 196364 kb
Host smart-fefa2cd9-c542-4d94-96af-017e8fdfefb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835701344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.835701344
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2477420006
Short name T1033
Test name
Test status
Simulation time 6166598763 ps
CPU time 24.54 seconds
Started Aug 16 05:05:47 PM PDT 24
Finished Aug 16 05:06:12 PM PDT 24
Peak memory 200080 kb
Host smart-d50fcde4-fbb8-453b-824b-9b7a5c91b2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477420006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2477420006
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1565694185
Short name T747
Test name
Test status
Simulation time 101848551647 ps
CPU time 275.67 seconds
Started Aug 16 05:05:49 PM PDT 24
Finished Aug 16 05:10:25 PM PDT 24
Peak memory 200908 kb
Host smart-2b0207bb-b7f8-4b82-af13-4e97a3ccb3fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565694185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1565694185
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1322890485
Short name T883
Test name
Test status
Simulation time 5457800824 ps
CPU time 26.63 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:15 PM PDT 24
Peak memory 209124 kb
Host smart-a0934e96-841c-405b-8e08-940910fd03fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322890485 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1322890485
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3263770350
Short name T882
Test name
Test status
Simulation time 6624945244 ps
CPU time 19.35 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:07 PM PDT 24
Peak memory 200924 kb
Host smart-19f2fbc6-d53a-4930-8d19-4e0853cd4973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263770350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3263770350
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3053639619
Short name T859
Test name
Test status
Simulation time 99813254703 ps
CPU time 140.62 seconds
Started Aug 16 05:05:38 PM PDT 24
Finished Aug 16 05:07:59 PM PDT 24
Peak memory 200848 kb
Host smart-27631fa0-3565-456c-906c-6db1b0902b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053639619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3053639619
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.4040115014
Short name T30
Test name
Test status
Simulation time 75449918 ps
CPU time 0.56 seconds
Started Aug 16 05:02:09 PM PDT 24
Finished Aug 16 05:02:09 PM PDT 24
Peak memory 196376 kb
Host smart-ed1ab7a5-c301-419e-8907-b27c8e7d6792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040115014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.4040115014
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2770999939
Short name T705
Test name
Test status
Simulation time 31995173947 ps
CPU time 35.92 seconds
Started Aug 16 05:02:06 PM PDT 24
Finished Aug 16 05:02:43 PM PDT 24
Peak memory 200896 kb
Host smart-173a20a5-9a0d-4532-a260-b60f528ad211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770999939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2770999939
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2855823718
Short name T291
Test name
Test status
Simulation time 78181253875 ps
CPU time 82.57 seconds
Started Aug 16 05:02:08 PM PDT 24
Finished Aug 16 05:03:31 PM PDT 24
Peak memory 200852 kb
Host smart-77ea1d71-df28-42e5-a2c5-31a1bfcf0ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855823718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2855823718
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3443895564
Short name T804
Test name
Test status
Simulation time 62423235317 ps
CPU time 99.02 seconds
Started Aug 16 05:02:04 PM PDT 24
Finished Aug 16 05:03:44 PM PDT 24
Peak memory 200900 kb
Host smart-9377443f-8d00-4fe6-8e02-b8c9d2b984d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443895564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3443895564
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1713187467
Short name T498
Test name
Test status
Simulation time 44737996426 ps
CPU time 68.69 seconds
Started Aug 16 05:02:10 PM PDT 24
Finished Aug 16 05:03:19 PM PDT 24
Peak memory 199264 kb
Host smart-dad51744-87f7-4ce4-8696-f437f909ce29
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713187467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1713187467
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1492092792
Short name T975
Test name
Test status
Simulation time 70086522815 ps
CPU time 222.34 seconds
Started Aug 16 05:02:05 PM PDT 24
Finished Aug 16 05:05:48 PM PDT 24
Peak memory 200912 kb
Host smart-edf93832-dc60-403d-a106-a2a7c5432aa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492092792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1492092792
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.471811772
Short name T856
Test name
Test status
Simulation time 4827236396 ps
CPU time 9.03 seconds
Started Aug 16 05:02:06 PM PDT 24
Finished Aug 16 05:02:16 PM PDT 24
Peak memory 196836 kb
Host smart-45263dbc-da6b-4a7d-9492-03bf06632d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471811772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.471811772
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1946687041
Short name T760
Test name
Test status
Simulation time 25479437907 ps
CPU time 13.94 seconds
Started Aug 16 05:02:09 PM PDT 24
Finished Aug 16 05:02:23 PM PDT 24
Peak memory 200044 kb
Host smart-df822ebe-f762-40f1-8f39-424b70cfb147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946687041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1946687041
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2261765589
Short name T960
Test name
Test status
Simulation time 3396431153 ps
CPU time 100.92 seconds
Started Aug 16 05:02:10 PM PDT 24
Finished Aug 16 05:03:51 PM PDT 24
Peak memory 200908 kb
Host smart-beba3bc8-3f99-4bf8-9d00-130fd6bb33d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261765589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2261765589
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1640421827
Short name T16
Test name
Test status
Simulation time 6233470780 ps
CPU time 27.09 seconds
Started Aug 16 05:02:05 PM PDT 24
Finished Aug 16 05:02:32 PM PDT 24
Peak memory 199848 kb
Host smart-59729a94-1e95-4a38-913b-ddbf52e446b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640421827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1640421827
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1605060766
Short name T1116
Test name
Test status
Simulation time 267959695186 ps
CPU time 33.54 seconds
Started Aug 16 05:02:06 PM PDT 24
Finished Aug 16 05:02:40 PM PDT 24
Peak memory 200884 kb
Host smart-3035ffc7-fb5d-4d6b-b7b9-48e4e65164f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605060766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1605060766
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3425044053
Short name T743
Test name
Test status
Simulation time 32281359862 ps
CPU time 9.44 seconds
Started Aug 16 05:02:07 PM PDT 24
Finished Aug 16 05:02:17 PM PDT 24
Peak memory 196912 kb
Host smart-9def785a-a1e2-4338-be81-252b0c77bc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425044053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3425044053
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1571448463
Short name T414
Test name
Test status
Simulation time 264446192 ps
CPU time 1.26 seconds
Started Aug 16 05:02:09 PM PDT 24
Finished Aug 16 05:02:11 PM PDT 24
Peak memory 199268 kb
Host smart-ef9fd9fb-bd40-4654-8f99-328216a4add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571448463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1571448463
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2110612748
Short name T661
Test name
Test status
Simulation time 58204553524 ps
CPU time 1599.28 seconds
Started Aug 16 05:02:09 PM PDT 24
Finished Aug 16 05:28:49 PM PDT 24
Peak memory 200916 kb
Host smart-79232e4f-a629-4ab6-bceb-6b2d329b95b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110612748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2110612748
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2994278413
Short name T1082
Test name
Test status
Simulation time 6435226571 ps
CPU time 55.61 seconds
Started Aug 16 05:02:09 PM PDT 24
Finished Aug 16 05:03:05 PM PDT 24
Peak memory 217564 kb
Host smart-06385a2b-ce82-462b-a362-c6fa4893f350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994278413 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2994278413
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1945801794
Short name T708
Test name
Test status
Simulation time 1367879424 ps
CPU time 4.76 seconds
Started Aug 16 05:02:06 PM PDT 24
Finished Aug 16 05:02:11 PM PDT 24
Peak memory 200516 kb
Host smart-d3376ca7-f04a-4cf5-9d21-4e44ec0aa6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945801794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1945801794
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.888013350
Short name T252
Test name
Test status
Simulation time 69000784615 ps
CPU time 25.84 seconds
Started Aug 16 05:02:07 PM PDT 24
Finished Aug 16 05:02:33 PM PDT 24
Peak memory 200832 kb
Host smart-32780319-4501-4329-8d0d-1f6de7a7a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888013350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.888013350
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2237796977
Short name T467
Test name
Test status
Simulation time 7947867158 ps
CPU time 37.88 seconds
Started Aug 16 05:05:51 PM PDT 24
Finished Aug 16 05:06:30 PM PDT 24
Peak memory 209392 kb
Host smart-a33e9a5e-2fef-46cb-9369-407ad9f29bbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237796977 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2237796977
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3962493756
Short name T670
Test name
Test status
Simulation time 163635576854 ps
CPU time 237.5 seconds
Started Aug 16 05:05:46 PM PDT 24
Finished Aug 16 05:09:43 PM PDT 24
Peak memory 200868 kb
Host smart-8beb6f44-c2f0-478b-ab67-a07898ee9363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962493756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3962493756
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1748753855
Short name T548
Test name
Test status
Simulation time 22054991493 ps
CPU time 58.81 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:47 PM PDT 24
Peak memory 200844 kb
Host smart-c48b9a2d-f6a8-4052-855c-51be824f4773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748753855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1748753855
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2486754206
Short name T35
Test name
Test status
Simulation time 1108541134 ps
CPU time 26.36 seconds
Started Aug 16 05:05:46 PM PDT 24
Finished Aug 16 05:06:13 PM PDT 24
Peak memory 200888 kb
Host smart-c3f6fb29-6983-4edb-9980-b28a9a294d0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486754206 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2486754206
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1990811220
Short name T537
Test name
Test status
Simulation time 6794655328 ps
CPU time 15.87 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:04 PM PDT 24
Peak memory 200840 kb
Host smart-b4cdaf12-ee0d-412e-b885-6615c79e1739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990811220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1990811220
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.4183773558
Short name T209
Test name
Test status
Simulation time 10402455511 ps
CPU time 28.03 seconds
Started Aug 16 05:05:47 PM PDT 24
Finished Aug 16 05:06:16 PM PDT 24
Peak memory 217024 kb
Host smart-95106a77-8b99-4b5d-b9a1-b0dc29a3226f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183773558 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.4183773558
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.429275107
Short name T1073
Test name
Test status
Simulation time 208936415421 ps
CPU time 301.65 seconds
Started Aug 16 05:05:47 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 200864 kb
Host smart-1a7032d9-6640-4c06-98eb-a514c668fad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429275107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.429275107
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.466348293
Short name T1173
Test name
Test status
Simulation time 5655712229 ps
CPU time 108.79 seconds
Started Aug 16 05:05:49 PM PDT 24
Finished Aug 16 05:07:38 PM PDT 24
Peak memory 209000 kb
Host smart-832e10dd-921b-4803-b871-ee10c174dc6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466348293 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.466348293
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3740298039
Short name T1049
Test name
Test status
Simulation time 114216122238 ps
CPU time 81.83 seconds
Started Aug 16 05:05:46 PM PDT 24
Finished Aug 16 05:07:08 PM PDT 24
Peak memory 200920 kb
Host smart-d2e6cf54-ba8d-402b-8f06-19ad8c1817dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740298039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3740298039
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3414071940
Short name T472
Test name
Test status
Simulation time 2014258669 ps
CPU time 35.85 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:24 PM PDT 24
Peak memory 209068 kb
Host smart-cc575ad5-df8c-4a9f-a24e-fbb4a0a14327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414071940 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3414071940
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3307902064
Short name T485
Test name
Test status
Simulation time 84039169536 ps
CPU time 58.37 seconds
Started Aug 16 05:05:47 PM PDT 24
Finished Aug 16 05:06:45 PM PDT 24
Peak memory 200860 kb
Host smart-de9ffa0a-9a83-4a5e-8301-a9a96dd9e4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307902064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3307902064
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3792193292
Short name T514
Test name
Test status
Simulation time 8838057814 ps
CPU time 50.69 seconds
Started Aug 16 05:05:49 PM PDT 24
Finished Aug 16 05:06:39 PM PDT 24
Peak memory 217512 kb
Host smart-e89a56d2-3de7-4d41-b7cd-7cb399521c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792193292 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3792193292
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2652808212
Short name T171
Test name
Test status
Simulation time 32433424372 ps
CPU time 26.4 seconds
Started Aug 16 05:05:49 PM PDT 24
Finished Aug 16 05:06:15 PM PDT 24
Peak memory 200156 kb
Host smart-1fba3c87-be14-4540-83e8-d10473fc0434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652808212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2652808212
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2789687635
Short name T90
Test name
Test status
Simulation time 5658956755 ps
CPU time 26.81 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:15 PM PDT 24
Peak memory 209540 kb
Host smart-13b120c2-460f-4f96-a93e-a3429841fb31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789687635 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2789687635
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2160001163
Short name T367
Test name
Test status
Simulation time 19372834321 ps
CPU time 17.38 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:05 PM PDT 24
Peak memory 200752 kb
Host smart-19f72468-c7da-412e-8355-1120f5dd52a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160001163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2160001163
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.4260563654
Short name T730
Test name
Test status
Simulation time 3731140448 ps
CPU time 17.37 seconds
Started Aug 16 05:05:47 PM PDT 24
Finished Aug 16 05:06:04 PM PDT 24
Peak memory 217352 kb
Host smart-96b980ce-8809-488f-8048-854471739f80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260563654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.4260563654
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3883473718
Short name T1175
Test name
Test status
Simulation time 35550125306 ps
CPU time 54.59 seconds
Started Aug 16 05:05:46 PM PDT 24
Finished Aug 16 05:06:41 PM PDT 24
Peak memory 200908 kb
Host smart-8db51688-dc7c-4b29-b5b5-78d6b76a2618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883473718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3883473718
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2116293572
Short name T904
Test name
Test status
Simulation time 5003106380 ps
CPU time 11.21 seconds
Started Aug 16 05:05:51 PM PDT 24
Finished Aug 16 05:06:02 PM PDT 24
Peak memory 217000 kb
Host smart-48754dee-c4bc-4f59-a3e1-061011e9d594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116293572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2116293572
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2508077199
Short name T921
Test name
Test status
Simulation time 13326879 ps
CPU time 0.58 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:02:20 PM PDT 24
Peak memory 196208 kb
Host smart-237e12a3-5d60-4399-b6b7-9062ba470494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508077199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2508077199
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1989103183
Short name T497
Test name
Test status
Simulation time 181804411749 ps
CPU time 47.98 seconds
Started Aug 16 05:02:07 PM PDT 24
Finished Aug 16 05:02:55 PM PDT 24
Peak memory 200568 kb
Host smart-5482beb9-8936-4f3f-aee5-58f9d5aeb395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989103183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1989103183
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3014643097
Short name T167
Test name
Test status
Simulation time 118118730487 ps
CPU time 69.4 seconds
Started Aug 16 05:02:05 PM PDT 24
Finished Aug 16 05:03:15 PM PDT 24
Peak memory 200896 kb
Host smart-0293a27d-1452-4112-a1b6-ef260444f2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014643097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3014643097
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1379494203
Short name T557
Test name
Test status
Simulation time 20385669262 ps
CPU time 9.63 seconds
Started Aug 16 05:02:12 PM PDT 24
Finished Aug 16 05:02:22 PM PDT 24
Peak memory 200920 kb
Host smart-b8e560a9-d8fd-452c-9d1b-0beb436504c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379494203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1379494203
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.333026807
Short name T1091
Test name
Test status
Simulation time 63470201079 ps
CPU time 681.08 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:13:35 PM PDT 24
Peak memory 200848 kb
Host smart-ca34e994-427f-4687-85b0-c24717b91ab1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333026807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.333026807
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.985938236
Short name T503
Test name
Test status
Simulation time 3830314174 ps
CPU time 1.35 seconds
Started Aug 16 05:02:13 PM PDT 24
Finished Aug 16 05:02:15 PM PDT 24
Peak memory 198524 kb
Host smart-5bce908e-3189-40b3-befb-ca57e7e08c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985938236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.985938236
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3264775853
Short name T1008
Test name
Test status
Simulation time 220096387389 ps
CPU time 198.53 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:05:33 PM PDT 24
Peak memory 209276 kb
Host smart-8246de5d-64ec-40e3-ae53-294b2479729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264775853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3264775853
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3201941282
Short name T897
Test name
Test status
Simulation time 7361910710 ps
CPU time 158.75 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:04:53 PM PDT 24
Peak memory 200868 kb
Host smart-9bb7d764-8441-42f4-a9ed-eed7d9cca732
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201941282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3201941282
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.284141688
Short name T25
Test name
Test status
Simulation time 2329686935 ps
CPU time 15.02 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:02:33 PM PDT 24
Peak memory 198736 kb
Host smart-bf6b451f-58b3-4dfa-842a-859ad4150167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284141688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.284141688
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2103583506
Short name T1075
Test name
Test status
Simulation time 145542177517 ps
CPU time 45.57 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:03:00 PM PDT 24
Peak memory 200892 kb
Host smart-6f0b0de4-2cd5-4afe-ab5f-5bb187bdd4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103583506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2103583506
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3438692472
Short name T442
Test name
Test status
Simulation time 509479514 ps
CPU time 1.47 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:02:19 PM PDT 24
Peak memory 196368 kb
Host smart-d3d436fa-187b-4625-9273-0ecd6674e564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438692472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3438692472
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2697042977
Short name T393
Test name
Test status
Simulation time 526681644 ps
CPU time 1.41 seconds
Started Aug 16 05:02:07 PM PDT 24
Finished Aug 16 05:02:08 PM PDT 24
Peak memory 199328 kb
Host smart-6fe7aa29-836e-4894-a0e8-07b431b2015e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697042977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2697042977
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2556542606
Short name T257
Test name
Test status
Simulation time 153994621704 ps
CPU time 206.32 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:05:40 PM PDT 24
Peak memory 200912 kb
Host smart-1ba0f47e-79a9-4d7f-9d83-18564317806a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556542606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2556542606
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.357849973
Short name T956
Test name
Test status
Simulation time 3770189103 ps
CPU time 22.6 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:02:40 PM PDT 24
Peak memory 209332 kb
Host smart-2275359c-47af-4171-808f-fdc1797f948c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357849973 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.357849973
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2742904227
Short name T784
Test name
Test status
Simulation time 989401804 ps
CPU time 3.74 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:02:19 PM PDT 24
Peak memory 199368 kb
Host smart-f1a7cea8-73df-4e67-bd0c-8d619060c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742904227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2742904227
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2422475238
Short name T1036
Test name
Test status
Simulation time 9905834233 ps
CPU time 15.06 seconds
Started Aug 16 05:02:10 PM PDT 24
Finished Aug 16 05:02:26 PM PDT 24
Peak memory 199944 kb
Host smart-c6025122-06f2-4a01-918e-d6db90aaa048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422475238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2422475238
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3874410771
Short name T370
Test name
Test status
Simulation time 63756447622 ps
CPU time 97.19 seconds
Started Aug 16 05:05:47 PM PDT 24
Finished Aug 16 05:07:24 PM PDT 24
Peak memory 200924 kb
Host smart-7cad0c17-2c71-4634-89de-0d4abb6807cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874410771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3874410771
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.340313693
Short name T836
Test name
Test status
Simulation time 4263930844 ps
CPU time 53.92 seconds
Started Aug 16 05:05:48 PM PDT 24
Finished Aug 16 05:06:42 PM PDT 24
Peak memory 217524 kb
Host smart-1e32cfec-52bd-4da7-a151-219b17cafbfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340313693 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.340313693
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2620425605
Short name T689
Test name
Test status
Simulation time 105589211039 ps
CPU time 19.67 seconds
Started Aug 16 05:05:49 PM PDT 24
Finished Aug 16 05:06:09 PM PDT 24
Peak memory 200844 kb
Host smart-8d92dd03-8f8c-4c51-a4c9-8a0c94060633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620425605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2620425605
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3401360991
Short name T20
Test name
Test status
Simulation time 8175298005 ps
CPU time 38.36 seconds
Started Aug 16 05:05:56 PM PDT 24
Finished Aug 16 05:06:35 PM PDT 24
Peak memory 217124 kb
Host smart-5c292c9d-cf41-40d0-b3c5-9177db83ce25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401360991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3401360991
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3872899886
Short name T1056
Test name
Test status
Simulation time 21287934799 ps
CPU time 43.82 seconds
Started Aug 16 05:05:53 PM PDT 24
Finished Aug 16 05:06:37 PM PDT 24
Peak memory 200844 kb
Host smart-96454217-9cae-4ee2-b037-6525e74b9b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872899886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3872899886
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3909527882
Short name T453
Test name
Test status
Simulation time 10706230763 ps
CPU time 33.88 seconds
Started Aug 16 05:05:53 PM PDT 24
Finished Aug 16 05:06:27 PM PDT 24
Peak memory 217284 kb
Host smart-4ed40085-0ec0-4931-8b1f-264d7c6e8ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909527882 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3909527882
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3705749992
Short name T674
Test name
Test status
Simulation time 7112814193 ps
CPU time 12.06 seconds
Started Aug 16 05:05:53 PM PDT 24
Finished Aug 16 05:06:06 PM PDT 24
Peak memory 200928 kb
Host smart-1f24bbc8-665e-4470-b912-eeb0e143420e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705749992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3705749992
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3520912391
Short name T809
Test name
Test status
Simulation time 10829396817 ps
CPU time 31.17 seconds
Started Aug 16 05:05:53 PM PDT 24
Finished Aug 16 05:06:24 PM PDT 24
Peak memory 201160 kb
Host smart-84c2e7d2-6b8b-4c6b-98ec-37807ee43a74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520912391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3520912391
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1771810650
Short name T790
Test name
Test status
Simulation time 47969240739 ps
CPU time 24.33 seconds
Started Aug 16 05:05:53 PM PDT 24
Finished Aug 16 05:06:18 PM PDT 24
Peak memory 200908 kb
Host smart-c41b2e54-f34b-4069-b9b8-3ee691df2006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771810650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1771810650
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.953611759
Short name T566
Test name
Test status
Simulation time 20035154105 ps
CPU time 65.37 seconds
Started Aug 16 05:05:54 PM PDT 24
Finished Aug 16 05:07:00 PM PDT 24
Peak memory 213484 kb
Host smart-461471fc-256a-4444-a4f5-da3ad6dc17a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953611759 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.953611759
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2261894159
Short name T933
Test name
Test status
Simulation time 191506456232 ps
CPU time 185.64 seconds
Started Aug 16 05:05:56 PM PDT 24
Finished Aug 16 05:09:02 PM PDT 24
Peak memory 200880 kb
Host smart-c5c68c77-92cf-487b-8aa2-fd2c22a2537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261894159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2261894159
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.4091818606
Short name T957
Test name
Test status
Simulation time 2231779449 ps
CPU time 73.02 seconds
Started Aug 16 05:05:54 PM PDT 24
Finished Aug 16 05:07:08 PM PDT 24
Peak memory 216172 kb
Host smart-e811b421-fe4d-47a3-9608-5738b85970e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091818606 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.4091818606
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2123774597
Short name T658
Test name
Test status
Simulation time 23856299389 ps
CPU time 11.8 seconds
Started Aug 16 05:05:53 PM PDT 24
Finished Aug 16 05:06:05 PM PDT 24
Peak memory 200908 kb
Host smart-35d4a971-bee1-4961-96a2-f7a2f0e56a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123774597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2123774597
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1494379623
Short name T963
Test name
Test status
Simulation time 3886594203 ps
CPU time 51.82 seconds
Started Aug 16 05:05:57 PM PDT 24
Finished Aug 16 05:06:49 PM PDT 24
Peak memory 217580 kb
Host smart-7cbec41e-84db-4db9-9011-4776d70a4642
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494379623 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1494379623
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2225747297
Short name T669
Test name
Test status
Simulation time 60109408140 ps
CPU time 45.08 seconds
Started Aug 16 05:05:54 PM PDT 24
Finished Aug 16 05:06:39 PM PDT 24
Peak memory 200856 kb
Host smart-2c0c960e-015b-4eb9-97fd-89c9efadab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225747297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2225747297
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2715584932
Short name T634
Test name
Test status
Simulation time 1627565764 ps
CPU time 7.26 seconds
Started Aug 16 05:05:53 PM PDT 24
Finished Aug 16 05:06:00 PM PDT 24
Peak memory 217252 kb
Host smart-769ab57a-738f-4672-b89c-9a3bbe560e76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715584932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2715584932
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.56473452
Short name T1124
Test name
Test status
Simulation time 260536090208 ps
CPU time 114.9 seconds
Started Aug 16 05:06:03 PM PDT 24
Finished Aug 16 05:07:58 PM PDT 24
Peak memory 200912 kb
Host smart-76143741-fe5f-49f7-bb72-8c0a416c8542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56473452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.56473452
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3451526879
Short name T80
Test name
Test status
Simulation time 3946817875 ps
CPU time 50.34 seconds
Started Aug 16 05:05:55 PM PDT 24
Finished Aug 16 05:06:45 PM PDT 24
Peak memory 209636 kb
Host smart-6487e7d7-d455-482d-a7c6-de3f41e11882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451526879 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3451526879
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.717128128
Short name T174
Test name
Test status
Simulation time 25987952334 ps
CPU time 47.11 seconds
Started Aug 16 05:06:04 PM PDT 24
Finished Aug 16 05:06:51 PM PDT 24
Peak memory 200908 kb
Host smart-67615d2d-e6ef-4110-85dd-c1d61f7dbd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717128128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.717128128
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.944929723
Short name T1140
Test name
Test status
Simulation time 3825152185 ps
CPU time 47.72 seconds
Started Aug 16 05:05:54 PM PDT 24
Finished Aug 16 05:06:42 PM PDT 24
Peak memory 210344 kb
Host smart-4197fbb5-517b-45eb-8459-b6015bd61169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944929723 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.944929723
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.286793077
Short name T376
Test name
Test status
Simulation time 16460216 ps
CPU time 0.54 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:02:16 PM PDT 24
Peak memory 196476 kb
Host smart-f80de5bb-f26d-489d-a5be-f1007ae8ec2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286793077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.286793077
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.789899895
Short name T440
Test name
Test status
Simulation time 46349114902 ps
CPU time 67.25 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:03:23 PM PDT 24
Peak memory 200912 kb
Host smart-611d885b-fde6-4695-965c-6e184e222882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789899895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.789899895
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3322705334
Short name T124
Test name
Test status
Simulation time 14011063672 ps
CPU time 23.02 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:02:38 PM PDT 24
Peak memory 199968 kb
Host smart-8cd1c4f3-872e-48ee-8827-8fd416d14f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322705334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3322705334
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1258195980
Short name T507
Test name
Test status
Simulation time 179713093631 ps
CPU time 284.51 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:07:02 PM PDT 24
Peak memory 200920 kb
Host smart-89528645-5e61-468c-9976-e373f3e4e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258195980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1258195980
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2564296303
Short name T355
Test name
Test status
Simulation time 8636310913 ps
CPU time 7.97 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:02:22 PM PDT 24
Peak memory 199328 kb
Host smart-0786979e-1ac9-425d-81db-d4f866c2bda7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564296303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2564296303
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2257816514
Short name T1004
Test name
Test status
Simulation time 52837386256 ps
CPU time 101.14 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:03:58 PM PDT 24
Peak memory 200892 kb
Host smart-affdd0c0-47cf-4e9c-8398-65f12eeb322b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257816514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2257816514
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3907126780
Short name T652
Test name
Test status
Simulation time 8193319965 ps
CPU time 7.22 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:02:24 PM PDT 24
Peak memory 200760 kb
Host smart-433d6ce6-d124-404a-8108-461287afbe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907126780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3907126780
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1082358637
Short name T636
Test name
Test status
Simulation time 31828993507 ps
CPU time 25.11 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:02:44 PM PDT 24
Peak memory 201060 kb
Host smart-4e798ed5-35e7-4537-8dc4-35c528082a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082358637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1082358637
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.4058025830
Short name T256
Test name
Test status
Simulation time 14303309395 ps
CPU time 189.11 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:05:26 PM PDT 24
Peak memory 200904 kb
Host smart-c3bb11fd-928f-4050-b62d-88e4cf6706fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058025830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.4058025830
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1543552587
Short name T39
Test name
Test status
Simulation time 5830785336 ps
CPU time 10.63 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:02:29 PM PDT 24
Peak memory 199200 kb
Host smart-19350fbb-d3c9-41fd-8999-0f11ee53f619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543552587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1543552587
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2417003508
Short name T925
Test name
Test status
Simulation time 73104365573 ps
CPU time 304.81 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:07:24 PM PDT 24
Peak memory 200896 kb
Host smart-3e07e556-46a4-4914-87be-971acee54f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417003508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2417003508
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3597941037
Short name T460
Test name
Test status
Simulation time 5090762302 ps
CPU time 2.61 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:02:16 PM PDT 24
Peak memory 197724 kb
Host smart-ccdc1a1d-23d6-4730-9f5d-1bdff40cbe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597941037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3597941037
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2350439429
Short name T929
Test name
Test status
Simulation time 977995279 ps
CPU time 5.25 seconds
Started Aug 16 05:02:16 PM PDT 24
Finished Aug 16 05:02:21 PM PDT 24
Peak memory 199560 kb
Host smart-2bcb231a-f111-43f0-baa3-9e0cdc3ae17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350439429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2350439429
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1983418701
Short name T1170
Test name
Test status
Simulation time 80627397098 ps
CPU time 1016.98 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:19:14 PM PDT 24
Peak memory 209312 kb
Host smart-31639d4e-074b-411c-8afb-676b64aba85b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983418701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1983418701
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2298449067
Short name T1168
Test name
Test status
Simulation time 4475746225 ps
CPU time 51.18 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:03:06 PM PDT 24
Peak memory 209152 kb
Host smart-be5662a7-1b32-4650-9ad5-a63ec64c0bc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298449067 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2298449067
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2501702037
Short name T391
Test name
Test status
Simulation time 866102112 ps
CPU time 1.31 seconds
Started Aug 16 05:02:16 PM PDT 24
Finished Aug 16 05:02:18 PM PDT 24
Peak memory 199616 kb
Host smart-7edb28e3-68a5-48d4-9d13-8a365dd4558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501702037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2501702037
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2283182022
Short name T715
Test name
Test status
Simulation time 70847224011 ps
CPU time 32.36 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:02:47 PM PDT 24
Peak memory 200856 kb
Host smart-fec6bc30-7055-4544-ab91-b16365611d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283182022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2283182022
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1132625504
Short name T444
Test name
Test status
Simulation time 40878915974 ps
CPU time 17.65 seconds
Started Aug 16 05:05:55 PM PDT 24
Finished Aug 16 05:06:13 PM PDT 24
Peak memory 201020 kb
Host smart-a1dcb390-e33e-4e23-b92d-14c3be6dbf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132625504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1132625504
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1936599453
Short name T484
Test name
Test status
Simulation time 1768346056 ps
CPU time 16.82 seconds
Started Aug 16 05:06:04 PM PDT 24
Finished Aug 16 05:06:21 PM PDT 24
Peak memory 217240 kb
Host smart-f54d7915-a3e2-4afb-a0d8-a04a6c562955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936599453 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1936599453
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1003738802
Short name T205
Test name
Test status
Simulation time 26961311732 ps
CPU time 16.17 seconds
Started Aug 16 05:05:58 PM PDT 24
Finished Aug 16 05:06:14 PM PDT 24
Peak memory 200772 kb
Host smart-08aa15f2-bf49-4235-9159-2d5b990c557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003738802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1003738802
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1459050583
Short name T1145
Test name
Test status
Simulation time 1447786758 ps
CPU time 17.21 seconds
Started Aug 16 05:06:04 PM PDT 24
Finished Aug 16 05:06:21 PM PDT 24
Peak memory 209284 kb
Host smart-ca9cf811-5ee6-449b-a582-adac5bd35bde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459050583 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1459050583
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1319270101
Short name T1137
Test name
Test status
Simulation time 23073774105 ps
CPU time 44.34 seconds
Started Aug 16 05:05:54 PM PDT 24
Finished Aug 16 05:06:38 PM PDT 24
Peak memory 200920 kb
Host smart-f63c48e6-b12c-469d-98cc-3b1cc8b1f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319270101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1319270101
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2550039040
Short name T225
Test name
Test status
Simulation time 17251896564 ps
CPU time 29.37 seconds
Started Aug 16 05:05:53 PM PDT 24
Finished Aug 16 05:06:22 PM PDT 24
Peak memory 200908 kb
Host smart-b725d059-200b-4d06-898f-9556c0f2a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550039040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2550039040
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1821775240
Short name T878
Test name
Test status
Simulation time 19317287491 ps
CPU time 81.84 seconds
Started Aug 16 05:06:03 PM PDT 24
Finished Aug 16 05:07:25 PM PDT 24
Peak memory 216368 kb
Host smart-0179003b-76c2-4d13-8ad8-62dbc797617f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821775240 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1821775240
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.484598801
Short name T1061
Test name
Test status
Simulation time 3141244745 ps
CPU time 27.95 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:30 PM PDT 24
Peak memory 209356 kb
Host smart-44455944-6f3d-4eaa-b531-d7937e496305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484598801 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.484598801
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.43837346
Short name T122
Test name
Test status
Simulation time 51409357294 ps
CPU time 68.87 seconds
Started Aug 16 05:06:05 PM PDT 24
Finished Aug 16 05:07:14 PM PDT 24
Peak memory 200896 kb
Host smart-85f2466b-5196-4946-950e-7453543dcf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43837346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.43837346
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1861351526
Short name T38
Test name
Test status
Simulation time 5842832664 ps
CPU time 27.54 seconds
Started Aug 16 05:06:03 PM PDT 24
Finished Aug 16 05:06:31 PM PDT 24
Peak memory 209160 kb
Host smart-1b99a369-e1e5-446e-a1c5-1ddf5a4bc1d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861351526 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1861351526
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.235269881
Short name T633
Test name
Test status
Simulation time 30567626490 ps
CPU time 32.62 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:35 PM PDT 24
Peak memory 200820 kb
Host smart-4ca67329-8e11-48da-89c7-b65fd327d25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235269881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.235269881
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3916995269
Short name T786
Test name
Test status
Simulation time 1106094019 ps
CPU time 10.22 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:12 PM PDT 24
Peak memory 209152 kb
Host smart-a537fb93-142f-4da6-bad7-00251ffcd43e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916995269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3916995269
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4102615507
Short name T887
Test name
Test status
Simulation time 31889450464 ps
CPU time 23.24 seconds
Started Aug 16 05:06:05 PM PDT 24
Finished Aug 16 05:06:29 PM PDT 24
Peak memory 200908 kb
Host smart-9cce7f5c-685e-4190-b771-2b2782386dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102615507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4102615507
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1235254643
Short name T1044
Test name
Test status
Simulation time 1498628493 ps
CPU time 4.76 seconds
Started Aug 16 05:06:05 PM PDT 24
Finished Aug 16 05:06:10 PM PDT 24
Peak memory 200896 kb
Host smart-6efa1707-2095-4ddc-9482-108e7d00465c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235254643 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1235254643
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.640769245
Short name T839
Test name
Test status
Simulation time 40312486792 ps
CPU time 12.03 seconds
Started Aug 16 05:06:06 PM PDT 24
Finished Aug 16 05:06:18 PM PDT 24
Peak memory 200860 kb
Host smart-172fd8b9-11d4-4679-a059-79cb8da88cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640769245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.640769245
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1763248489
Short name T870
Test name
Test status
Simulation time 22037516098 ps
CPU time 29.54 seconds
Started Aug 16 05:06:03 PM PDT 24
Finished Aug 16 05:06:33 PM PDT 24
Peak memory 210332 kb
Host smart-8b0cb0e4-ef3e-4ef8-b08b-e2394a657697
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763248489 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1763248489
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.906829519
Short name T401
Test name
Test status
Simulation time 47232309 ps
CPU time 0.55 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:02:15 PM PDT 24
Peak memory 195112 kb
Host smart-454fdee2-00c4-4d1e-a123-35f71e093cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906829519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.906829519
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.961657821
Short name T149
Test name
Test status
Simulation time 133040033491 ps
CPU time 66.68 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:03:24 PM PDT 24
Peak memory 200840 kb
Host smart-785c30a6-13b4-48e7-b7a4-99f72c7c4f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961657821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.961657821
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3533426723
Short name T275
Test name
Test status
Simulation time 216348932628 ps
CPU time 447.21 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:09:47 PM PDT 24
Peak memory 200900 kb
Host smart-2883b97f-0613-4212-b361-218511d3eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533426723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3533426723
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1326005358
Short name T207
Test name
Test status
Simulation time 207487031736 ps
CPU time 86.36 seconds
Started Aug 16 05:02:16 PM PDT 24
Finished Aug 16 05:03:42 PM PDT 24
Peak memory 200876 kb
Host smart-1cfdf3bc-9cd8-40ab-ac0a-7e843ce3acd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326005358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1326005358
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2839125888
Short name T101
Test name
Test status
Simulation time 747013001496 ps
CPU time 335.05 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:07:49 PM PDT 24
Peak memory 200864 kb
Host smart-df69e479-b9eb-4757-b405-60d6d5a9dc63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839125888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2839125888
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1335057401
Short name T49
Test name
Test status
Simulation time 124300742120 ps
CPU time 81.47 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:03:39 PM PDT 24
Peak memory 200920 kb
Host smart-3b3d286b-275a-4ee5-9e16-adae2a5b2390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335057401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1335057401
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1430126836
Short name T490
Test name
Test status
Simulation time 11169726424 ps
CPU time 25.31 seconds
Started Aug 16 05:02:20 PM PDT 24
Finished Aug 16 05:02:46 PM PDT 24
Peak memory 200792 kb
Host smart-3b2c0f21-820b-4daf-b317-314928a0fb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430126836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1430126836
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1859933451
Short name T751
Test name
Test status
Simulation time 113921136789 ps
CPU time 191.19 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:05:30 PM PDT 24
Peak memory 200164 kb
Host smart-83a300d8-651e-4c58-9dec-96d63e770917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859933451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1859933451
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3262756170
Short name T284
Test name
Test status
Simulation time 7474586853 ps
CPU time 389.1 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:08:43 PM PDT 24
Peak memory 200912 kb
Host smart-563d68ea-012f-4584-9879-79c8dc9f1318
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3262756170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3262756170
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2713401552
Short name T438
Test name
Test status
Simulation time 2501480350 ps
CPU time 12.38 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:02:30 PM PDT 24
Peak memory 199948 kb
Host smart-b362095d-8f8f-407a-9cbb-92d7757d6abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713401552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2713401552
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2298124375
Short name T672
Test name
Test status
Simulation time 30404043149 ps
CPU time 57.72 seconds
Started Aug 16 05:02:16 PM PDT 24
Finished Aug 16 05:03:14 PM PDT 24
Peak memory 200928 kb
Host smart-c4c18698-4953-4750-ba79-c09696311f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298124375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2298124375
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1160738289
Short name T983
Test name
Test status
Simulation time 30778354007 ps
CPU time 30.39 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:02:45 PM PDT 24
Peak memory 196700 kb
Host smart-45de271c-2540-47ee-93d7-20faf5bd9830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160738289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1160738289
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.386780151
Short name T488
Test name
Test status
Simulation time 5758036120 ps
CPU time 21.85 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:02:40 PM PDT 24
Peak memory 200688 kb
Host smart-2dca1534-6cec-4708-b8d4-7179ab28ad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386780151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.386780151
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.4159041086
Short name T1105
Test name
Test status
Simulation time 121522842391 ps
CPU time 172.72 seconds
Started Aug 16 05:02:14 PM PDT 24
Finished Aug 16 05:05:07 PM PDT 24
Peak memory 216932 kb
Host smart-adf46882-c1de-4da3-a131-bb20be93d6d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159041086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4159041086
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3172804721
Short name T1024
Test name
Test status
Simulation time 4753313236 ps
CPU time 56.8 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:03:14 PM PDT 24
Peak memory 217348 kb
Host smart-8cc2e49a-fad0-402e-9b33-d92bf11c055d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172804721 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3172804721
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3120249702
Short name T841
Test name
Test status
Simulation time 385338993 ps
CPU time 1.4 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:02:19 PM PDT 24
Peak memory 200012 kb
Host smart-731ea170-d27d-4fb1-82da-afacb3d8b2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120249702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3120249702
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.422567410
Short name T635
Test name
Test status
Simulation time 108855698822 ps
CPU time 55.19 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:03:14 PM PDT 24
Peak memory 200872 kb
Host smart-51296f50-0d38-42d1-86cf-60e9aa624fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422567410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.422567410
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2464115077
Short name T607
Test name
Test status
Simulation time 18988812057 ps
CPU time 8.05 seconds
Started Aug 16 05:06:03 PM PDT 24
Finished Aug 16 05:06:11 PM PDT 24
Peak memory 200852 kb
Host smart-e5db9c22-588b-4d7c-a84a-3ef038f35248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464115077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2464115077
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1316598022
Short name T618
Test name
Test status
Simulation time 3143489183 ps
CPU time 9.55 seconds
Started Aug 16 05:06:04 PM PDT 24
Finished Aug 16 05:06:13 PM PDT 24
Peak memory 209276 kb
Host smart-e8839bc7-b485-4442-8ef0-e1b670d194aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316598022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1316598022
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.4134869795
Short name T534
Test name
Test status
Simulation time 158916065202 ps
CPU time 107.16 seconds
Started Aug 16 05:06:03 PM PDT 24
Finished Aug 16 05:07:50 PM PDT 24
Peak memory 200848 kb
Host smart-0a795f78-680d-47dd-a2c3-0ffd87a72775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134869795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4134869795
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2877903788
Short name T358
Test name
Test status
Simulation time 4889725316 ps
CPU time 62.67 seconds
Started Aug 16 05:06:05 PM PDT 24
Finished Aug 16 05:07:08 PM PDT 24
Peak memory 217292 kb
Host smart-60ae4f47-f53b-43ec-8b4a-9c8bfd74eccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877903788 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2877903788
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2670351660
Short name T533
Test name
Test status
Simulation time 92936240247 ps
CPU time 42.26 seconds
Started Aug 16 05:06:04 PM PDT 24
Finished Aug 16 05:06:46 PM PDT 24
Peak memory 200892 kb
Host smart-be0e59d9-0c24-4bd0-83ba-3d693a0abcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670351660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2670351660
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.394061160
Short name T794
Test name
Test status
Simulation time 59950975073 ps
CPU time 80.77 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:07:23 PM PDT 24
Peak memory 216720 kb
Host smart-edbf456d-c044-4721-b8b1-0fc94dee6890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394061160 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.394061160
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.445673990
Short name T271
Test name
Test status
Simulation time 92564091829 ps
CPU time 135.01 seconds
Started Aug 16 05:06:04 PM PDT 24
Finished Aug 16 05:08:19 PM PDT 24
Peak memory 200904 kb
Host smart-5eb65b9d-a850-4297-9df7-4fc9b89a4a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445673990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.445673990
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2552160617
Short name T19
Test name
Test status
Simulation time 5072750701 ps
CPU time 51.66 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:54 PM PDT 24
Peak memory 217288 kb
Host smart-d491e78f-8cb7-4d35-bf00-4ae421ef80aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552160617 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2552160617
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2063234623
Short name T509
Test name
Test status
Simulation time 132904799419 ps
CPU time 53.79 seconds
Started Aug 16 05:06:01 PM PDT 24
Finished Aug 16 05:06:55 PM PDT 24
Peak memory 200908 kb
Host smart-36bb56db-1285-4abe-b689-68590031daa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063234623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2063234623
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.4139670345
Short name T605
Test name
Test status
Simulation time 5530492805 ps
CPU time 9.55 seconds
Started Aug 16 05:06:04 PM PDT 24
Finished Aug 16 05:06:14 PM PDT 24
Peak memory 209436 kb
Host smart-e647efa6-d4b2-4698-b6e2-14e76e294f3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139670345 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.4139670345
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2505221187
Short name T627
Test name
Test status
Simulation time 123374693185 ps
CPU time 52 seconds
Started Aug 16 05:06:06 PM PDT 24
Finished Aug 16 05:06:58 PM PDT 24
Peak memory 200796 kb
Host smart-94e9ebdb-1946-4f6e-9214-ab672b652bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505221187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2505221187
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3113765150
Short name T759
Test name
Test status
Simulation time 2686619283 ps
CPU time 27.56 seconds
Started Aug 16 05:06:05 PM PDT 24
Finished Aug 16 05:06:32 PM PDT 24
Peak memory 216636 kb
Host smart-649d7720-a1dd-4400-be2b-27ec4ee5fbc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113765150 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3113765150
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2562929237
Short name T816
Test name
Test status
Simulation time 12004500776 ps
CPU time 21.46 seconds
Started Aug 16 05:06:05 PM PDT 24
Finished Aug 16 05:06:26 PM PDT 24
Peak memory 200824 kb
Host smart-3505c30a-7987-4ca7-89c5-8bb502541e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562929237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2562929237
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2597820306
Short name T621
Test name
Test status
Simulation time 2699637092 ps
CPU time 30.98 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:33 PM PDT 24
Peak memory 209324 kb
Host smart-385cb502-9ce3-4dbe-ac2c-5962d81f66bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597820306 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2597820306
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2451272320
Short name T593
Test name
Test status
Simulation time 197933563988 ps
CPU time 118.08 seconds
Started Aug 16 05:06:06 PM PDT 24
Finished Aug 16 05:08:04 PM PDT 24
Peak memory 200908 kb
Host smart-d4095971-f2e4-4d29-9afb-cf851e0f2ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451272320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2451272320
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2341626016
Short name T802
Test name
Test status
Simulation time 852973012 ps
CPU time 9.6 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:12 PM PDT 24
Peak memory 201040 kb
Host smart-07fa56fe-d73f-4ccb-bbcc-15c86f39c0fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341626016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2341626016
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3696619018
Short name T824
Test name
Test status
Simulation time 104652985323 ps
CPU time 173.14 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:08:56 PM PDT 24
Peak memory 200924 kb
Host smart-146bf135-e276-4386-a730-a658c41d31a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696619018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3696619018
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1442322668
Short name T37
Test name
Test status
Simulation time 9716258226 ps
CPU time 47.99 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:50 PM PDT 24
Peak memory 217552 kb
Host smart-e2d6dbb6-0413-4b2a-ab00-f9e2e1d8e920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442322668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1442322668
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2879272049
Short name T632
Test name
Test status
Simulation time 56355193645 ps
CPU time 17.63 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:20 PM PDT 24
Peak memory 200868 kb
Host smart-78f3088e-67ac-40c0-bfe9-26c3604e7508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879272049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2879272049
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2145849890
Short name T357
Test name
Test status
Simulation time 2546580264 ps
CPU time 28.61 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:31 PM PDT 24
Peak memory 209348 kb
Host smart-cc56295c-4219-4185-acbe-0ef5e7bef3f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145849890 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2145849890
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2061485196
Short name T889
Test name
Test status
Simulation time 15078654 ps
CPU time 0.6 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:02:19 PM PDT 24
Peak memory 196220 kb
Host smart-496c4515-833c-47d9-ba7d-3a1dfad8180f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061485196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2061485196
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1958588377
Short name T147
Test name
Test status
Simulation time 57771023951 ps
CPU time 101.16 seconds
Started Aug 16 05:02:13 PM PDT 24
Finished Aug 16 05:03:55 PM PDT 24
Peak memory 200884 kb
Host smart-9cebbd75-f886-4900-8d73-8bec73a78f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958588377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1958588377
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1270625272
Short name T277
Test name
Test status
Simulation time 119728382443 ps
CPU time 40.61 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:02:59 PM PDT 24
Peak memory 200824 kb
Host smart-9c4478a7-67b0-4291-878e-50743dd2df0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270625272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1270625272
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.454886017
Short name T208
Test name
Test status
Simulation time 131976320438 ps
CPU time 32.94 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:02:48 PM PDT 24
Peak memory 200832 kb
Host smart-80be018b-d647-43a2-a2ba-14a25ec1d504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454886017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.454886017
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3386595900
Short name T754
Test name
Test status
Simulation time 12432016786 ps
CPU time 9.58 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:02:24 PM PDT 24
Peak memory 198732 kb
Host smart-4b0be203-b423-48a6-bb04-053110c64abe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386595900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3386595900
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1338006835
Short name T706
Test name
Test status
Simulation time 67443034430 ps
CPU time 682.58 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:13:41 PM PDT 24
Peak memory 200912 kb
Host smart-c15d905a-2fcc-409f-be0c-15610752f254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338006835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1338006835
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4030986856
Short name T423
Test name
Test status
Simulation time 8700859250 ps
CPU time 12.64 seconds
Started Aug 16 05:02:20 PM PDT 24
Finished Aug 16 05:02:32 PM PDT 24
Peak memory 200732 kb
Host smart-f5d94273-1e6a-42ca-8179-b214b4d38b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030986856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4030986856
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2841698367
Short name T796
Test name
Test status
Simulation time 25772906158 ps
CPU time 22.22 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:02:42 PM PDT 24
Peak memory 199168 kb
Host smart-875fb966-02b4-4625-a20a-b758e06eb957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841698367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2841698367
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.697378154
Short name T850
Test name
Test status
Simulation time 20822647102 ps
CPU time 1152.15 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:21:31 PM PDT 24
Peak memory 200896 kb
Host smart-22c85d5f-1a0c-45d1-b2dd-dd70a86d6d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697378154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.697378154
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1112924328
Short name T654
Test name
Test status
Simulation time 5994422662 ps
CPU time 54.35 seconds
Started Aug 16 05:02:17 PM PDT 24
Finished Aug 16 05:03:11 PM PDT 24
Peak memory 200240 kb
Host smart-c9340867-13c8-4c3d-9898-5a0de222dd72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112924328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1112924328
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.592612777
Short name T1108
Test name
Test status
Simulation time 22639674042 ps
CPU time 38 seconds
Started Aug 16 05:02:16 PM PDT 24
Finished Aug 16 05:02:55 PM PDT 24
Peak memory 200860 kb
Host smart-c6691764-6345-4d28-8ccd-7d51509afa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592612777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.592612777
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2537257886
Short name T474
Test name
Test status
Simulation time 468042491 ps
CPU time 1.4 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:02:20 PM PDT 24
Peak memory 196600 kb
Host smart-f155f6cb-9776-4a05-86f4-268d527d97c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537257886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2537257886
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1649931434
Short name T1031
Test name
Test status
Simulation time 449861739 ps
CPU time 2.28 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:02:22 PM PDT 24
Peak memory 200480 kb
Host smart-3f9fb7bb-b20d-4c0c-8d94-24a77aa247d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649931434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1649931434
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3958339791
Short name T516
Test name
Test status
Simulation time 189553634364 ps
CPU time 928.87 seconds
Started Aug 16 05:02:18 PM PDT 24
Finished Aug 16 05:17:47 PM PDT 24
Peak memory 200916 kb
Host smart-b2871bdc-e048-4cbd-847f-c213cfbbf038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958339791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3958339791
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.698918501
Short name T1069
Test name
Test status
Simulation time 14819473308 ps
CPU time 68.8 seconds
Started Aug 16 05:02:19 PM PDT 24
Finished Aug 16 05:03:28 PM PDT 24
Peak memory 217524 kb
Host smart-eedc7a31-9ed5-4dd6-94f0-cbd9108d8aff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698918501 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.698918501
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.620968384
Short name T662
Test name
Test status
Simulation time 6024905132 ps
CPU time 28.53 seconds
Started Aug 16 05:02:15 PM PDT 24
Finished Aug 16 05:02:43 PM PDT 24
Peak memory 200856 kb
Host smart-698f74a5-34fd-4468-a9ca-9dcc30942dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620968384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.620968384
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.4236261157
Short name T491
Test name
Test status
Simulation time 145572470143 ps
CPU time 233.25 seconds
Started Aug 16 05:02:16 PM PDT 24
Finished Aug 16 05:06:09 PM PDT 24
Peak memory 200836 kb
Host smart-c985fbff-8580-40a7-a238-ae50cdcb35d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236261157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.4236261157
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1944751994
Short name T1101
Test name
Test status
Simulation time 119701981029 ps
CPU time 49.96 seconds
Started Aug 16 05:06:05 PM PDT 24
Finished Aug 16 05:06:55 PM PDT 24
Peak memory 200628 kb
Host smart-3c5371c4-01cb-479e-bc47-e596909b85d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944751994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1944751994
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1118634348
Short name T281
Test name
Test status
Simulation time 6457710801 ps
CPU time 42.47 seconds
Started Aug 16 05:06:02 PM PDT 24
Finished Aug 16 05:06:44 PM PDT 24
Peak memory 217516 kb
Host smart-a3d1ea9a-3601-4cf9-b17b-d81feb8f3d77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118634348 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1118634348
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3089855483
Short name T582
Test name
Test status
Simulation time 138944839166 ps
CPU time 213.11 seconds
Started Aug 16 05:06:05 PM PDT 24
Finished Aug 16 05:09:39 PM PDT 24
Peak memory 200940 kb
Host smart-33f9e75c-36fd-479b-8c5a-42afaba715e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089855483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3089855483
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3657711686
Short name T597
Test name
Test status
Simulation time 25466546442 ps
CPU time 25.11 seconds
Started Aug 16 05:06:13 PM PDT 24
Finished Aug 16 05:06:38 PM PDT 24
Peak memory 217352 kb
Host smart-2689d20d-e818-403c-969f-4852c3a3d365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657711686 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3657711686
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.18769692
Short name T313
Test name
Test status
Simulation time 97176398511 ps
CPU time 95.44 seconds
Started Aug 16 05:06:13 PM PDT 24
Finished Aug 16 05:07:48 PM PDT 24
Peak memory 200832 kb
Host smart-4cd9f0b2-73f8-42d4-8eab-7bf6644f3eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18769692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.18769692
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3977696235
Short name T668
Test name
Test status
Simulation time 3925747789 ps
CPU time 41.21 seconds
Started Aug 16 05:06:12 PM PDT 24
Finished Aug 16 05:06:53 PM PDT 24
Peak memory 217344 kb
Host smart-2ae4ddd0-da7e-4793-9ba6-7158142ec9c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977696235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3977696235
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.197048436
Short name T369
Test name
Test status
Simulation time 79135972027 ps
CPU time 59.28 seconds
Started Aug 16 05:06:10 PM PDT 24
Finished Aug 16 05:07:10 PM PDT 24
Peak memory 200844 kb
Host smart-0c2d0749-dad9-435f-ae15-7a648b515eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197048436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.197048436
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3832552613
Short name T979
Test name
Test status
Simulation time 10612737425 ps
CPU time 38.18 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:06:49 PM PDT 24
Peak memory 217236 kb
Host smart-fd9c0050-13df-4d99-8601-811edf04df95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832552613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3832552613
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.167974903
Short name T671
Test name
Test status
Simulation time 83022655543 ps
CPU time 215.53 seconds
Started Aug 16 05:06:10 PM PDT 24
Finished Aug 16 05:09:46 PM PDT 24
Peak memory 200836 kb
Host smart-0eb61c91-db26-4e3b-a326-1d3573997cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167974903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.167974903
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2030473449
Short name T468
Test name
Test status
Simulation time 10951461165 ps
CPU time 47.51 seconds
Started Aug 16 05:06:10 PM PDT 24
Finished Aug 16 05:06:57 PM PDT 24
Peak memory 216944 kb
Host smart-a8b820c8-bf51-466c-81f8-6c78cd6d6907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030473449 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2030473449
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1076488203
Short name T846
Test name
Test status
Simulation time 64688646633 ps
CPU time 58.5 seconds
Started Aug 16 05:06:09 PM PDT 24
Finished Aug 16 05:07:08 PM PDT 24
Peak memory 200924 kb
Host smart-62c5c976-2a3d-43a3-b231-0842af569fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076488203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1076488203
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2292677026
Short name T945
Test name
Test status
Simulation time 6165219650 ps
CPU time 17.12 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:06:28 PM PDT 24
Peak memory 217044 kb
Host smart-a719d168-b3e0-414d-aa68-9e79b601e1bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292677026 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2292677026
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2590302476
Short name T616
Test name
Test status
Simulation time 110125702464 ps
CPU time 153.59 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:08:44 PM PDT 24
Peak memory 200908 kb
Host smart-6bfdab87-4ce4-4e47-87b3-bbc8398c06e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590302476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2590302476
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2923943684
Short name T805
Test name
Test status
Simulation time 61936186914 ps
CPU time 118.35 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:08:10 PM PDT 24
Peak memory 217496 kb
Host smart-215c827c-b242-46f4-afba-101533287778
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923943684 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2923943684
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.507674769
Short name T988
Test name
Test status
Simulation time 13483027870 ps
CPU time 13.7 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:06:25 PM PDT 24
Peak memory 200840 kb
Host smart-303d7627-afed-49cb-93b7-a4e2644bd93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507674769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.507674769
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3093430858
Short name T89
Test name
Test status
Simulation time 7608498681 ps
CPU time 39.53 seconds
Started Aug 16 05:06:10 PM PDT 24
Finished Aug 16 05:06:50 PM PDT 24
Peak memory 209964 kb
Host smart-6adc5a7c-ac36-44b9-987a-222801adb83a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093430858 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3093430858
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1233386979
Short name T851
Test name
Test status
Simulation time 107259321547 ps
CPU time 31.19 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:06:42 PM PDT 24
Peak memory 200868 kb
Host smart-8c9fd3f4-f36f-4f84-9116-441e9cb157f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233386979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1233386979
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2126294265
Short name T707
Test name
Test status
Simulation time 2999380492 ps
CPU time 16.44 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:06:27 PM PDT 24
Peak memory 200672 kb
Host smart-fd2e866c-1b01-461c-b89e-04b63eabb3d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126294265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2126294265
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1302228231
Short name T224
Test name
Test status
Simulation time 31261864284 ps
CPU time 25.74 seconds
Started Aug 16 05:06:13 PM PDT 24
Finished Aug 16 05:06:39 PM PDT 24
Peak memory 200856 kb
Host smart-74b01157-21d7-46ff-a280-7ad224b806d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302228231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1302228231
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.491529829
Short name T908
Test name
Test status
Simulation time 6814146714 ps
CPU time 19.75 seconds
Started Aug 16 05:06:11 PM PDT 24
Finished Aug 16 05:06:31 PM PDT 24
Peak memory 200932 kb
Host smart-49e26019-5c0d-41f6-92c0-ff488f434eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491529829 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.491529829
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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