Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	77345	1			T1	1		T2	1		T3	18
all_values[1]	77345	1			T1	1		T2	1		T3	18
all_values[2]	77345	1			T1	1		T2	1		T3	18
all_values[3]	77345	1			T1	1		T2	1		T3	18
all_values[4]	77345	1			T1	1		T2	1		T3	18
all_values[5]	77345	1			T1	1		T2	1		T3	18
all_values[6]	77345	1			T1	1		T2	1		T3	18
all_values[7]	77345	1			T1	1		T2	1		T3	18
all_values[8]	77345	1			T1	1		T2	1		T3	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

360683

1

T1

7

T2

5

T3

100

auto[1]

335422

1

T1

2

T2

4

T3

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630806

1

T1

7

T2

7

T3

128

auto[1]

65299

1

T1

2

T2

2

T3

34

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	23637	1			T3	1		T4	7		T13	376
all_values[0]	auto[0]	auto[1]	16094	1			T1	1		T3	15		T4	11
all_values[0]	auto[1]	auto[0]	21743	1			T9	15		T13	10		T36	7
all_values[0]	auto[1]	auto[1]	15871	1			T2	1		T3	2		T4	2
all_values[1]	auto[0]	auto[0]	36489	1			T1	1		T3	4		T4	7
all_values[1]	auto[0]	auto[1]	1140	1			T11	16		T14	4		T77	1
all_values[1]	auto[1]	auto[0]	38227	1			T2	1		T3	11		T4	13
all_values[1]	auto[1]	auto[1]	1489	1			T3	3		T10	6		T14	25
all_values[2]	auto[0]	auto[0]	39571	1			T1	1		T3	7		T4	16
all_values[2]	auto[0]	auto[1]	2175	1			T4	1		T5	1		T8	1
all_values[2]	auto[1]	auto[0]	33581	1			T2	1		T3	11		T4	3
all_values[2]	auto[1]	auto[1]	2018	1			T9	1		T10	1		T13	1
all_values[3]	auto[0]	auto[0]	39400	1			T2	1		T3	16		T4	3
all_values[3]	auto[0]	auto[1]	258	1			T11	1		T14	1		T30	1
all_values[3]	auto[1]	auto[0]	37418	1			T1	1		T3	2		T4	17
all_values[3]	auto[1]	auto[1]	269	1			T14	2		T15	1		T16	3
all_values[4]	auto[0]	auto[0]	40480	1			T1	1		T2	1		T3	14
all_values[4]	auto[0]	auto[1]	318	1			T3	1		T7	2		T11	9
all_values[4]	auto[1]	auto[0]	36145	1			T3	3		T4	1		T9	10
all_values[4]	auto[1]	auto[1]	402	1			T14	5		T16	4		T22	3
all_values[5]	auto[0]	auto[0]	40975	1			T1	1		T2	1		T3	17
all_values[5]	auto[0]	auto[1]	179	1			T30	2		T16	2		T43	6
all_values[5]	auto[1]	auto[0]	36075	1			T3	1		T4	13		T6	1
all_values[5]	auto[1]	auto[1]	116	1			T16	5		T43	2		T123	1
all_values[6]	auto[0]	auto[0]	41166	1			T1	1		T2	1		T3	8
all_values[6]	auto[0]	auto[1]	157	1			T30	1		T16	2		T43	4
all_values[6]	auto[1]	auto[0]	35859	1			T3	10		T4	15		T6	1
all_values[6]	auto[1]	auto[1]	163	1			T30	1		T16	4		T43	3
all_values[7]	auto[0]	auto[0]	39218	1			T3	2		T4	11		T5	2
all_values[7]	auto[0]	auto[1]	332	1			T14	8		T77	3		T16	2
all_values[7]	auto[1]	auto[0]	37497	1			T1	1		T2	1		T3	16
all_values[7]	auto[1]	auto[1]	298	1			T9	3		T11	9		T14	5
all_values[8]	auto[0]	auto[0]	26125	1			T3	3		T4	6		T7	9
all_values[8]	auto[0]	auto[1]	12969	1			T1	1		T2	1		T3	12
all_values[8]	auto[1]	auto[0]	27200	1			T3	2		T4	1		T7	3
all_values[8]	auto[1]	auto[1]	11051	1			T3	1		T4	9		T6	1