Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2525

1

T1

1

T2

1

T3

6

auto[UartRx]

2525

1

T1

1

T2

1

T3

6

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4444	1			T1	2		T2	2		T3	9
values[1]	38	1			T7	1		T30	1		T124	1
values[2]	50	1			T7	1		T30	1		T32	3
values[3]	48	1			T31	1		T32	1		T34	1
values[4]	55	1			T21	1		T16	1		T31	1
values[5]	45	1			T21	1		T30	1		T34	1
values[6]	62	1			T31	1		T33	1		T361	1
values[7]	56	1			T30	1		T32	1		T35	2
values[8]	54	1			T31	1		T33	1		T361	2
values[9]	69	1			T3	1		T21	1		T31	2
values[10]	89	1			T3	2		T7	1		T16	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2314	1			T1	1		T2	1		T3	6
auto[UartTx]	values[1]	5	1			T366	1		T367	1		T368	1
auto[UartTx]	values[2]	22	1			T30	1		T369	1		T370	1
auto[UartTx]	values[3]	15	1			T31	1		T123	1		T102	1
auto[UartTx]	values[4]	16	1			T34	1		T101	1		T369	2
auto[UartTx]	values[5]	15	1			T21	1		T361	1		T126	1
auto[UartTx]	values[6]	21	1			T31	1		T100	1		T123	1
auto[UartTx]	values[7]	24	1			T32	1		T371	1		T349	1
auto[UartTx]	values[8]	19	1			T361	1		T372	2		T349	1
auto[UartTx]	values[9]	27	1			T31	1		T33	1		T372	1
auto[UartTx]	values[10]	35	1			T16	1		T32	1		T100	1
auto[UartRx]	values[0]	2130	1			T1	1		T2	1		T3	3
auto[UartRx]	values[1]	33	1			T7	1		T30	1		T124	1
auto[UartRx]	values[2]	28	1			T7	1		T32	3		T103	1
auto[UartRx]	values[3]	33	1			T32	1		T34	1		T101	1
auto[UartRx]	values[4]	39	1			T21	1		T16	1		T31	1
auto[UartRx]	values[5]	30	1			T30	1		T34	1		T35	1
auto[UartRx]	values[6]	41	1			T33	1		T361	1		T124	1
auto[UartRx]	values[7]	32	1			T30	1		T35	2		T372	1
auto[UartRx]	values[8]	35	1			T31	1		T33	1		T361	1
auto[UartRx]	values[9]	42	1			T3	1		T21	1		T31	1
auto[UartRx]	values[10]	54	1			T3	2		T7	1		T33	1