Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1953	1			T1	19		T2	3		T4	1
auto[BaudRate115200]	1612	1			T2	3		T7	3		T8	1
auto[BaudRate230400]	1524	1			T2	6		T3	2		T4	2
auto[BaudRate128Kbps]	1522	1			T9	3		T10	1		T12	1
auto[BaudRate256Kbps]	1613	1			T3	3		T4	1		T5	1
auto[BaudRate1Mbps]	1445	1			T2	6		T4	1		T9	1
auto[BaudRate1p5Mbps]	1077	1			T3	2		T5	1		T23	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1005	1			T4	5		T8	2		T332	7
freqs[25]	1060	1			T9	7		T77	9		T40	18
freqs[48]	403	1			T2	18		T191	8		T44	8
freqs[50]	479	1			T36	4		T21	11		T15	8
freqs[100]	1074	1			T19	17		T212	6		T130	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	158	1			T4	1		T18	1		T39	4
auto[BaudRate9600]	freqs[25]	205	1			T9	1		T77	1		T40	18
auto[BaudRate9600]	freqs[48]	65	1			T2	3		T108	1		T223	1
auto[BaudRate9600]	freqs[50]	77	1			T21	1		T114	6		T295	1
auto[BaudRate9600]	freqs[100]	165	1			T19	17		T130	1		T20	3
auto[BaudRate115200]	freqs[24]	160	1			T8	1		T332	1		T39	3
auto[BaudRate115200]	freqs[25]	136	1			T9	1		T41	2		T43	5
auto[BaudRate115200]	freqs[48]	46	1			T2	3		T191	2		T318	1
auto[BaudRate115200]	freqs[50]	82	1			T36	1		T21	2		T15	3
auto[BaudRate115200]	freqs[100]	159	1			T212	3		T135	1		T33	2
auto[BaudRate230400]	freqs[24]	133	1			T4	2		T332	2		T18	1
auto[BaudRate230400]	freqs[25]	147	1			T9	1		T77	1		T41	1
auto[BaudRate230400]	freqs[48]	68	1			T2	6		T191	2		T108	4
auto[BaudRate230400]	freqs[50]	55	1			T36	2		T21	3		T114	3
auto[BaudRate230400]	freqs[100]	153	1			T212	1		T130	5		T20	3
auto[BaudRate128Kbps]	freqs[24]	162	1			T332	1		T39	3		T297	1
auto[BaudRate128Kbps]	freqs[25]	183	1			T9	3		T77	3		T41	1
auto[BaudRate128Kbps]	freqs[48]	43	1			T191	2		T108	2		T318	3
auto[BaudRate128Kbps]	freqs[50]	51	1			T36	1		T15	1		T37	1
auto[BaudRate128Kbps]	freqs[100]	161	1			T212	2		T130	1		T20	9
auto[BaudRate256Kbps]	freqs[24]	163	1			T4	1		T8	1		T332	2
auto[BaudRate256Kbps]	freqs[25]	162	1			T41	1		T43	6		T373	6
auto[BaudRate256Kbps]	freqs[48]	56	1			T44	1		T223	1		T300	3
auto[BaudRate256Kbps]	freqs[50]	70	1			T21	3		T15	1		T114	17
auto[BaudRate256Kbps]	freqs[100]	153	1			T130	2		T20	3		T135	1
auto[BaudRate1Mbps]	freqs[24]	148	1			T4	1		T39	3		T297	1
auto[BaudRate1Mbps]	freqs[25]	149	1			T9	1		T77	4		T41	3
auto[BaudRate1Mbps]	freqs[48]	63	1			T2	6		T44	1		T108	2
auto[BaudRate1Mbps]	freqs[50]	74	1			T21	1		T15	2		T37	2
auto[BaudRate1Mbps]	freqs[100]	127	1			T130	1		T20	3		T111	3
auto[BaudRate1p5Mbps]	freqs[25]	78	1			T43	2		T373	6		T301	2
auto[BaudRate1p5Mbps]	freqs[48]	62	1			T191	2		T44	6		T108	1
auto[BaudRate1p5Mbps]	freqs[50]	70	1			T21	1		T15	1		T114	8
auto[BaudRate1p5Mbps]	freqs[100]	156	1			T135	3		T110	2		T111	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded