Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	22861256	1			T1	1		T2	5		T3	1271
all_levels[1]	162208	1			T7	3		T9	1		T13	149
all_levels[2]	1882	1			T7	1		T23	12		T21	1
all_levels[3]	791	1			T9	2		T23	8		T21	3
all_levels[4]	495	1			T3	1		T23	3		T15	1
all_levels[5]	392	1			T9	1		T15	3		T129	3
all_levels[6]	308	1			T77	1		T15	2		T130	1
all_levels[7]	263	1			T77	1		T129	2		T130	2
all_levels[8]	248	1			T21	1		T15	3		T130	1
all_levels[9]	199	1			T129	4		T130	2		T31	1
all_levels[10]	164	1			T10	3		T129	1		T130	1
all_levels[11]	151	1			T15	1		T130	3		T38	1
all_levels[12]	127	1			T15	1		T130	2		T38	1
all_levels[13]	112	1			T130	1		T131	1		T132	1
all_levels[14]	113	1			T9	1		T129	1		T39	2
all_levels[15]	113	1			T10	3		T43	1		T133	1
all_levels[16]	85	1			T15	1		T133	1		T108	2
all_levels[17]	96	1			T9	1		T134	1		T43	1
all_levels[18]	66	1			T9	1		T135	1		T136	1
all_levels[19]	84	1			T9	1		T38	2		T43	1
all_levels[20]	66	1			T9	3		T15	2		T43	1
all_levels[21]	68	1			T15	3		T137	4		T138	1
all_levels[22]	48	1			T139	1		T138	2		T140	1
all_levels[23]	57	1			T141	1		T138	3		T142	2
all_levels[24]	49	1			T43	1		T143	1		T144	2
all_levels[25]	50	1			T134	2		T43	1		T135	1
all_levels[26]	33	1			T145	1		T96	1		T146	1
all_levels[27]	40	1			T10	1		T146	1		T147	1
all_levels[28]	32	1			T148	1		T149	1		T150	1
all_levels[29]	13	1			T151	1		T149	1		T152	1
all_levels[30]	30	1			T153	1		T154	1		T155	1
all_levels[31]	37	1			T156	1		T146	2		T157	2
all_levels[32]	21	1			T142	1		T140	1		T158	1
all_levels[33]	23	1			T140	1		T159	1		T160	1
all_levels[34]	27	1			T136	1		T96	1		T161	1
all_levels[35]	20	1			T134	2		T139	1		T108	3
all_levels[36]	30	1			T43	1		T136	1		T140	2
all_levels[37]	25	1			T130	2		T139	1		T162	1
all_levels[38]	26	1			T161	1		T163	4		T164	1
all_levels[39]	19	1			T165	1		T166	1		T167	1
all_levels[40]	21	1			T168	2		T164	1		T122	1
all_levels[41]	19	1			T130	1		T148	1		T169	1
all_levels[42]	14	1			T170	1		T155	1		T171	1
all_levels[43]	15	1			T172	1		T132	1		T173	2
all_levels[44]	12	1			T174	1		T175	1		T176	1
all_levels[45]	12	1			T145	2		T118	1		T177	1
all_levels[46]	11	1			T139	1		T178	1		T179	1
all_levels[47]	12	1			T180	1		T122	1		T181	4
all_levels[48]	9	1			T182	1		T183	1		T184	2
all_levels[49]	8	1			T140	1		T147	1		T185	1
all_levels[50]	13	1			T9	2		T110	4		T186	1
all_levels[51]	7	1			T187	1		T188	1		T189	1
all_levels[52]	3	1			T154	1		T190	1		T122	1
all_levels[53]	12	1			T191	5		T161	1		T192	1
all_levels[54]	14	1			T193	1		T170	3		T194	1
all_levels[55]	5	1			T195	2		T176	1		T196	1
all_levels[56]	7	1			T122	1		T197	1		T198	1
all_levels[57]	9	1			T169	2		T147	1		T199	2
all_levels[58]	5	1			T200	2		T201	1		T187	1
all_levels[59]	7	1			T134	2		T202	1		T203	1
all_levels[60]	8	1			T140	1		T204	1		T205	3
all_levels[61]	6	1			T182	1		T201	1		T187	1
all_levels[62]	6	1			T206	2		T207	3		T208	1
all_levels[63]	5	1			T144	1		T209	2		T210	1
all_levels[64]	96	1			T30	1		T120	3		T195	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23026087

1

T3

1270

T4

22

T7

4114

auto[1]

4116

1

T1

1

T2

5

T3

2

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[44] , all_levels[45]]	[auto[1]]	--	--	2
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	22857567	1			T3	1269		T4	22		T7	4110
all_levels[0]	auto[1]	3689	1			T1	1		T2	5		T3	2
all_levels[1]	auto[0]	162142	1			T7	3		T9	1		T13	149
all_levels[1]	auto[1]	66	1			T38	1		T211	1		T120	1
all_levels[2]	auto[0]	1848	1			T7	1		T23	12		T21	1
all_levels[2]	auto[1]	34	1			T212	3		T213	2		T195	2
all_levels[3]	auto[0]	776	1			T9	2		T23	8		T21	3
all_levels[3]	auto[1]	15	1			T214	1		T215	2		T216	4
all_levels[4]	auto[0]	487	1			T3	1		T23	3		T15	1
all_levels[4]	auto[1]	8	1			T217	1		T218	1		T219	1
all_levels[5]	auto[0]	374	1			T9	1		T15	3		T129	3
all_levels[5]	auto[1]	18	1			T131	1		T220	1		T200	2
all_levels[6]	auto[0]	303	1			T77	1		T15	2		T130	1
all_levels[6]	auto[1]	5	1			T220	1		T221	1		T222	1
all_levels[7]	auto[0]	252	1			T77	1		T129	2		T130	2
all_levels[7]	auto[1]	11	1			T108	1		T223	1		T169	2
all_levels[8]	auto[0]	237	1			T21	1		T15	3		T130	1
all_levels[8]	auto[1]	11	1			T138	1		T170	1		T224	1
all_levels[9]	auto[0]	183	1			T129	4		T130	2		T31	1
all_levels[9]	auto[1]	16	1			T225	1		T226	3		T227	1
all_levels[10]	auto[0]	152	1			T10	2		T129	1		T130	1
all_levels[10]	auto[1]	12	1			T10	1		T131	1		T228	1
all_levels[11]	auto[0]	135	1			T15	1		T130	3		T38	1
all_levels[11]	auto[1]	16	1			T111	1		T229	1		T230	1
all_levels[12]	auto[0]	115	1			T15	1		T130	2		T38	1
all_levels[12]	auto[1]	12	1			T146	2		T231	2		T174	2
all_levels[13]	auto[0]	102	1			T130	1		T131	1		T132	1
all_levels[13]	auto[1]	10	1			T232	2		T233	1		T152	4
all_levels[14]	auto[0]	95	1			T9	1		T129	1		T39	2
all_levels[14]	auto[1]	18	1			T132	2		T145	2		T234	1
all_levels[15]	auto[0]	102	1			T10	1		T43	1		T133	1
all_levels[15]	auto[1]	11	1			T10	2		T235	1		T180	1
all_levels[16]	auto[0]	77	1			T15	1		T133	1		T108	2
all_levels[16]	auto[1]	8	1			T236	2		T237	2		T238	1
all_levels[17]	auto[0]	86	1			T9	1		T134	1		T43	1
all_levels[17]	auto[1]	10	1			T117	1		T177	1		T239	1
all_levels[18]	auto[0]	60	1			T9	1		T135	1		T136	1
all_levels[18]	auto[1]	6	1			T198	1		T240	5		-	-
all_levels[19]	auto[0]	75	1			T9	1		T38	2		T43	1
all_levels[19]	auto[1]	9	1			T111	2		T241	1		T242	2
all_levels[20]	auto[0]	61	1			T9	3		T15	1		T43	1
all_levels[20]	auto[1]	5	1			T15	1		T146	3		T243	1
all_levels[21]	auto[0]	53	1			T15	1		T137	1		T138	1
all_levels[21]	auto[1]	15	1			T15	2		T137	3		T244	1
all_levels[22]	auto[0]	47	1			T139	1		T138	2		T140	1
all_levels[22]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[23]	auto[0]	51	1			T141	1		T138	3		T142	2
all_levels[23]	auto[1]	6	1			T246	1		T247	1		T248	1
all_levels[24]	auto[0]	48	1			T43	1		T143	1		T144	2
all_levels[24]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[25]	auto[0]	44	1			T134	1		T43	1		T135	1
all_levels[25]	auto[1]	6	1			T134	1		T177	1		T250	1
all_levels[26]	auto[0]	31	1			T145	1		T96	1		T146	1
all_levels[26]	auto[1]	2	1			T251	2		-	-		-	-
all_levels[27]	auto[0]	35	1			T10	1		T146	1		T147	1
all_levels[27]	auto[1]	5	1			T252	2		T253	1		T254	1
all_levels[28]	auto[0]	27	1			T148	1		T149	1		T150	1
all_levels[28]	auto[1]	5	1			T255	2		T256	3		-	-
all_levels[29]	auto[0]	12	1			T151	1		T149	1		T152	1
all_levels[29]	auto[1]	1	1			T257	1		-	-		-	-
all_levels[30]	auto[0]	29	1			T153	1		T154	1		T155	1
all_levels[30]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[31]	auto[0]	34	1			T156	1		T146	2		T157	1
all_levels[31]	auto[1]	3	1			T157	1		T259	1		T260	1
all_levels[32]	auto[0]	18	1			T142	1		T140	1		T158	1
all_levels[32]	auto[1]	3	1			T261	1		T262	1		T263	1
all_levels[33]	auto[0]	21	1			T140	1		T159	1		T160	1
all_levels[33]	auto[1]	2	1			T215	1		T256	1		-	-
all_levels[34]	auto[0]	25	1			T136	1		T96	1		T161	1
all_levels[34]	auto[1]	2	1			T157	1		T264	1		-	-
all_levels[35]	auto[0]	17	1			T134	1		T139	1		T108	2
all_levels[35]	auto[1]	3	1			T134	1		T108	1		T265	1
all_levels[36]	auto[0]	24	1			T43	1		T136	1		T140	2
all_levels[36]	auto[1]	6	1			T171	3		T266	3		-	-
all_levels[37]	auto[0]	24	1			T130	1		T139	1		T162	1
all_levels[37]	auto[1]	1	1			T130	1		-	-		-	-
all_levels[38]	auto[0]	20	1			T161	1		T163	1		T164	1
all_levels[38]	auto[1]	6	1			T163	3		T267	3		-	-
all_levels[39]	auto[0]	17	1			T165	1		T166	1		T167	1
all_levels[39]	auto[1]	2	1			T268	2		-	-		-	-
all_levels[40]	auto[0]	18	1			T168	1		T164	1		T122	1
all_levels[40]	auto[1]	3	1			T168	1		T269	2		-	-
all_levels[41]	auto[0]	17	1			T130	1		T148	1		T169	1
all_levels[41]	auto[1]	2	1			T265	1		T270	1		-	-
all_levels[42]	auto[0]	13	1			T170	1		T155	1		T171	1
all_levels[42]	auto[1]	1	1			T268	1		-	-		-	-
all_levels[43]	auto[0]	14	1			T172	1		T132	1		T173	1
all_levels[43]	auto[1]	1	1			T173	1		-	-		-	-
all_levels[44]	auto[0]	12	1			T174	1		T175	1		T176	1
all_levels[45]	auto[0]	12	1			T145	2		T118	1		T177	1
all_levels[46]	auto[0]	10	1			T139	1		T178	1		T179	1
all_levels[46]	auto[1]	1	1			T219	1		-	-		-	-
all_levels[47]	auto[0]	9	1			T180	1		T122	1		T181	1
all_levels[47]	auto[1]	3	1			T181	3		-	-		-	-
all_levels[48]	auto[0]	8	1			T182	1		T183	1		T184	2
all_levels[48]	auto[1]	1	1			T271	1		-	-		-	-
all_levels[49]	auto[0]	8	1			T140	1		T147	1		T185	1
all_levels[50]	auto[0]	11	1			T9	2		T110	3		T186	1
all_levels[50]	auto[1]	2	1			T110	1		T272	1		-	-
all_levels[51]	auto[0]	7	1			T187	1		T188	1		T189	1
all_levels[52]	auto[0]	3	1			T154	1		T190	1		T122	1
all_levels[53]	auto[0]	7	1			T191	1		T161	1		T192	1
all_levels[53]	auto[1]	5	1			T191	4		T273	1		-	-
all_levels[54]	auto[0]	10	1			T193	1		T170	1		T194	1
all_levels[54]	auto[1]	4	1			T170	2		T246	1		T274	1
all_levels[55]	auto[0]	4	1			T195	1		T176	1		T196	1
all_levels[55]	auto[1]	1	1			T195	1		-	-		-	-
all_levels[56]	auto[0]	7	1			T122	1		T197	1		T198	1
all_levels[57]	auto[0]	7	1			T169	1		T147	1		T199	2
all_levels[57]	auto[1]	2	1			T169	1		T275	1		-	-
all_levels[58]	auto[0]	4	1			T200	1		T201	1		T187	1
all_levels[58]	auto[1]	1	1			T200	1		-	-		-	-
all_levels[59]	auto[0]	5	1			T134	1		T202	1		T203	1
all_levels[59]	auto[1]	2	1			T134	1		T276	1		-	-
all_levels[60]	auto[0]	6	1			T140	1		T204	1		T205	1
all_levels[60]	auto[1]	2	1			T205	2		-	-		-	-
all_levels[61]	auto[0]	6	1			T182	1		T201	1		T187	1
all_levels[62]	auto[0]	4	1			T206	2		T207	1		T208	1
all_levels[62]	auto[1]	2	1			T207	2		-	-		-	-
all_levels[63]	auto[0]	5	1			T144	1		T209	2		T210	1
all_levels[64]	auto[0]	74	1			T30	1		T120	1		T195	1
all_levels[64]	auto[1]	22	1			T120	2		T111	1		T277	2