Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	77345	1			T1	1		T2	1		T3	18
all_pins[1]	77345	1			T1	1		T2	1		T3	18
all_pins[2]	77345	1			T1	1		T2	1		T3	18
all_pins[3]	77345	1			T1	1		T2	1		T3	18
all_pins[4]	77345	1			T1	1		T2	1		T3	18
all_pins[5]	77345	1			T1	1		T2	1		T3	18
all_pins[6]	77345	1			T1	1		T2	1		T3	18
all_pins[7]	77345	1			T1	1		T2	1		T3	18
all_pins[8]	77345	1			T1	1		T2	1		T3	18

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	663640	1			T1	9		T2	8		T3	156
values[0x1]	32465	1			T2	1		T3	6		T4	12
transitions[0x0=>0x1]	25444	1			T2	1		T3	5		T4	11
transitions[0x1=>0x0]	25230	1			T3	5		T4	10		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61392	1			T1	1		T3	16		T4	18
all_pins[0]	values[0x1]	15953	1			T2	1		T3	2		T4	2
all_pins[0]	transitions[0x0=>0x1]	15418	1			T2	1		T3	2		T4	2
all_pins[0]	transitions[0x1=>0x0]	949	1			T3	3		T10	6		T14	4
all_pins[1]	values[0x0]	75861	1			T1	1		T2	1		T3	15
all_pins[1]	values[0x1]	1484	1			T3	3		T10	6		T14	25
all_pins[1]	transitions[0x0=>0x1]	1382	1			T3	3		T10	5		T14	25
all_pins[1]	transitions[0x1=>0x0]	1973	1			T9	1		T13	1		T36	3
all_pins[2]	values[0x0]	75270	1			T1	1		T2	1		T3	18
all_pins[2]	values[0x1]	2075	1			T9	1		T10	1		T13	1
all_pins[2]	transitions[0x0=>0x1]	2003	1			T9	1		T10	1		T13	1
all_pins[2]	transitions[0x1=>0x0]	197	1			T14	2		T15	1		T16	3
all_pins[3]	values[0x0]	77076	1			T1	1		T2	1		T3	18
all_pins[3]	values[0x1]	269	1			T14	2		T15	1		T16	3
all_pins[3]	transitions[0x0=>0x1]	231	1			T14	2		T15	1		T16	2
all_pins[3]	transitions[0x1=>0x0]	364	1			T14	5		T16	3		T22	3
all_pins[4]	values[0x0]	76943	1			T1	1		T2	1		T3	18
all_pins[4]	values[0x1]	402	1			T14	5		T16	4		T22	3
all_pins[4]	transitions[0x0=>0x1]	349	1			T14	4		T16	2		T22	3
all_pins[4]	transitions[0x1=>0x0]	108	1			T7	1		T11	3		T14	1
all_pins[5]	values[0x0]	77184	1			T1	1		T2	1		T3	18
all_pins[5]	values[0x1]	161	1			T7	1		T11	3		T14	2
all_pins[5]	transitions[0x0=>0x1]	123	1			T7	1		T11	3		T14	2
all_pins[5]	transitions[0x1=>0x0]	665	1			T4	1		T10	1		T11	2
all_pins[6]	values[0x0]	76642	1			T1	1		T2	1		T3	18
all_pins[6]	values[0x1]	703	1			T4	1		T10	1		T11	2
all_pins[6]	transitions[0x0=>0x1]	655	1			T4	1		T10	1		T11	2
all_pins[6]	transitions[0x1=>0x0]	250	1			T9	3		T11	9		T14	5
all_pins[7]	values[0x0]	77047	1			T1	1		T2	1		T3	18
all_pins[7]	values[0x1]	298	1			T9	3		T11	9		T14	5
all_pins[7]	transitions[0x0=>0x1]	182	1			T9	3		T11	9		T14	5
all_pins[7]	transitions[0x1=>0x0]	11004	1			T3	1		T4	9		T6	1
all_pins[8]	values[0x0]	66225	1			T1	1		T2	1		T3	17
all_pins[8]	values[0x1]	11120	1			T3	1		T4	9		T6	1
all_pins[8]	transitions[0x0=>0x1]	5101	1			T4	8		T7	1		T13	51
all_pins[8]	transitions[0x1=>0x0]	9720	1			T3	1		T7	11		T10	1