Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	4432268	1			T1	1		T3	10		T4	5
all_levels[1]	1361660	1			T3	1259		T7	4104		T9	2
all_levels[2]	396528	1			T3	2		T13	1271		T36	2287
all_levels[3]	274378	1			T9	1		T13	1283		T23	3
all_levels[4]	226404	1			T4	20		T9	1		T13	1280
all_levels[5]	161952	1			T13	1284		T21	2		T129	9
all_levels[6]	134530	1			T13	1252		T21	2		T15	2
all_levels[7]	452663	1			T9	1		T13	1281		T21	2
all_levels[8]	189977	1			T13	1282		T21	719		T129	2
all_levels[9]	135946	1			T9	1		T13	1270		T23	2
all_levels[10]	143094	1			T13	1249		T21	1077		T77	2
all_levels[11]	291973	1			T13	1281		T23	7		T21	910
all_levels[12]	150949	1			T9	1		T13	1286		T23	2
all_levels[13]	132006	1			T13	1281		T23	1		T21	1063
all_levels[14]	148599	1			T13	1289		T23	3		T21	1077
all_levels[15]	134348	1			T9	1		T13	1273		T21	1076
all_levels[16]	183319	1			T13	1281		T23	4		T21	885
all_levels[17]	263223	1			T9	4		T13	1278		T23	24
all_levels[18]	139203	1			T9	3		T13	9439		T23	1
all_levels[19]	200116	1			T13	1277		T21	1075		T15	1
all_levels[20]	311858	1			T13	1279		T21	1069		T15	1
all_levels[21]	246242	1			T13	1280		T21	1077		T129	2
all_levels[22]	129255	1			T13	1284		T21	778		T129	5
all_levels[23]	121303	1			T9	1		T13	1285		T23	5
all_levels[24]	163594	1			T13	1276		T23	1		T21	1077
all_levels[25]	124471	1			T9	1		T13	1278		T21	1076
all_levels[26]	193403	1			T9	1		T13	1256		T21	956
all_levels[27]	138143	1			T13	1280		T15	1		T37	266
all_levels[28]	129961	1			T9	2		T13	1286		T23	41
all_levels[29]	142041	1			T9	8		T13	1671		T129	3
all_levels[30]	163958	1			T9	3		T13	15987		T129	4
all_levels[31]	398946	1			T9	6		T13	7621		T23	69
all_levels[32]	11213677	1			T9	3		T13	40739		T23	139

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23026087

1

T3

1270

T4

22

T7

4114

auto[1]

3901

1

T1

1

T3

1

T4

3

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	4430052	1			T3	9		T4	4		T7	10
all_levels[0]	auto[1]	2216	1			T1	1		T3	1		T4	1
all_levels[1]	auto[0]	1361361	1			T3	1259		T7	4104		T9	2
all_levels[1]	auto[1]	299	1			T10	1		T36	8		T38	2
all_levels[2]	auto[0]	396490	1			T3	2		T13	1271		T36	2287
all_levels[2]	auto[1]	38	1			T130	1		T131	1		T225	1
all_levels[3]	auto[0]	274320	1			T9	1		T13	1283		T23	3
all_levels[3]	auto[1]	58	1			T76	1		T292	1		T341	5
all_levels[4]	auto[0]	226376	1			T4	18		T9	1		T13	1280
all_levels[4]	auto[1]	28	1			T4	2		T138	1		T177	1
all_levels[5]	auto[0]	161928	1			T13	1284		T21	2		T129	9
all_levels[5]	auto[1]	24	1			T212	1		T302	1		T239	1
all_levels[6]	auto[0]	134507	1			T13	1252		T21	2		T15	2
all_levels[6]	auto[1]	23	1			T120	1		T312	1		T145	1
all_levels[7]	auto[0]	452501	1			T9	1		T13	1281		T21	2
all_levels[7]	auto[1]	162	1			T281	13		T290	1		T110	1
all_levels[8]	auto[0]	189966	1			T13	1282		T21	719		T129	2
all_levels[8]	auto[1]	11	1			T132	2		T225	2		T280	1
all_levels[9]	auto[0]	135920	1			T9	1		T13	1270		T23	2
all_levels[9]	auto[1]	26	1			T139	1		T108	2		T171	3
all_levels[10]	auto[0]	143066	1			T13	1249		T21	1077		T77	2
all_levels[10]	auto[1]	28	1			T287	2		T132	1		T108	1
all_levels[11]	auto[0]	291950	1			T13	1281		T23	7		T21	910
all_levels[11]	auto[1]	23	1			T120	2		T376	1		T321	1
all_levels[12]	auto[0]	150925	1			T9	1		T13	1286		T23	2
all_levels[12]	auto[1]	24	1			T292	1		T110	1		T337	2
all_levels[13]	auto[0]	131989	1			T13	1281		T23	1		T21	1063
all_levels[13]	auto[1]	17	1			T133	1		T139	2		T111	1
all_levels[14]	auto[0]	148564	1			T13	1289		T23	3		T21	1077
all_levels[14]	auto[1]	35	1			T17	1		T131	1		T213	1
all_levels[15]	auto[0]	134223	1			T9	1		T13	1273		T21	1076
all_levels[15]	auto[1]	125	1			T286	1		T133	1		T113	5
all_levels[16]	auto[0]	183299	1			T13	1281		T23	4		T21	885
all_levels[16]	auto[1]	20	1			T292	2		T173	1		T177	2
all_levels[17]	auto[0]	263208	1			T9	4		T13	1278		T23	24
all_levels[17]	auto[1]	15	1			T76	2		T162	1		T232	1
all_levels[18]	auto[0]	139186	1			T9	3		T13	9439		T23	1
all_levels[18]	auto[1]	17	1			T212	2		T363	1		T377	1
all_levels[19]	auto[0]	200098	1			T13	1277		T21	1075		T15	1
all_levels[19]	auto[1]	18	1			T137	1		T288	1		T231	3
all_levels[20]	auto[0]	311830	1			T13	1279		T21	1069		T15	1
all_levels[20]	auto[1]	28	1			T111	2		T114	1		T378	1
all_levels[21]	auto[0]	246233	1			T13	1280		T21	1077		T129	2
all_levels[21]	auto[1]	9	1			T234	1		T220	1		T163	1
all_levels[22]	auto[0]	129238	1			T13	1284		T21	778		T129	5
all_levels[22]	auto[1]	17	1			T134	2		T303	1		T379	3
all_levels[23]	auto[0]	121294	1			T9	1		T13	1285		T23	5
all_levels[23]	auto[1]	9	1			T167	1		T380	1		T381	1
all_levels[24]	auto[0]	163583	1			T13	1276		T23	1		T21	1077
all_levels[24]	auto[1]	11	1			T306	1		T153	1		T231	1
all_levels[25]	auto[0]	124455	1			T9	1		T13	1278		T21	1076
all_levels[25]	auto[1]	16	1			T362	1		T163	1		T246	1
all_levels[26]	auto[0]	193393	1			T9	1		T13	1256		T21	956
all_levels[26]	auto[1]	10	1			T225	1		T111	1		T217	1
all_levels[27]	auto[0]	138127	1			T13	1280		T15	1		T37	266
all_levels[27]	auto[1]	16	1			T145	2		T356	1		T198	2
all_levels[28]	auto[0]	129946	1			T9	2		T13	1286		T23	41
all_levels[28]	auto[1]	15	1			T213	2		T356	1		T382	1
all_levels[29]	auto[0]	142020	1			T9	8		T13	1671		T129	3
all_levels[29]	auto[1]	21	1			T287	1		T211	1		T131	1
all_levels[30]	auto[0]	163945	1			T9	3		T13	15987		T129	4
all_levels[30]	auto[1]	13	1			T234	2		T182	2		T383	1
all_levels[31]	auto[0]	398925	1			T9	6		T13	7621		T23	69
all_levels[31]	auto[1]	21	1			T38	1		T287	1		T145	3
all_levels[32]	auto[0]	11213169	1			T9	3		T13	40738		T23	138
all_levels[32]	auto[1]	508	1			T13	1		T23	1		T15	2