Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	636	1			T30	11		T16	11		T43	11
all_values[1]	636	1			T30	11		T16	11		T43	11
all_values[2]	636	1			T30	11		T16	11		T43	11
all_values[3]	636	1			T30	11		T16	11		T43	11
all_values[4]	636	1			T30	11		T16	11		T43	11
all_values[5]	636	1			T30	11		T16	11		T43	11
all_values[6]	636	1			T30	11		T16	11		T43	11
all_values[7]	636	1			T30	11		T16	11		T43	11
all_values[8]	636	1			T30	11		T16	11		T43	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3181

1

T30

54

T16

60

T43

62

auto[1]

2543

1

T30

45

T16

39

T43

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1886

1

T30

50

T16

25

T43

30

auto[1]

3838

1

T30

49

T16

74

T43

69

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3402

1

T30

70

T16

56

T43

56

auto[1]

2322

1

T30

29

T16

43

T43

43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	232	1			T30	7		T16	3		T43	6
all_values[0]	auto[0]	auto[1]	auto[1]	157	1			T16	5		T123	2		T102	1
all_values[0]	auto[1]	auto[0]	auto[1]	129	1			T30	1		T16	3		T43	4
all_values[0]	auto[1]	auto[1]	auto[1]	118	1			T30	3		T43	1		T32	1
all_values[1]	auto[0]	auto[0]	auto[0]	228	1			T30	4		T16	5		T43	2
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T30	3		T16	1		T43	1
all_values[1]	auto[1]	auto[0]	auto[1]	151	1			T30	4		T16	4		T43	4
all_values[1]	auto[1]	auto[1]	auto[1]	101	1			T16	1		T43	4		T102	3
all_values[2]	auto[0]	auto[0]	auto[0]	138	1			T16	3		T43	4		T124	1
all_values[2]	auto[0]	auto[0]	auto[1]	58	1			T30	1		T16	2		T125	1
all_values[2]	auto[0]	auto[1]	auto[0]	115	1			T30	8		T43	2		T32	1
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T43	1		T32	2		T124	1
all_values[2]	auto[1]	auto[0]	auto[1]	130	1			T30	1		T16	6		T43	2
all_values[2]	auto[1]	auto[1]	auto[1]	127	1			T30	1		T43	2		T124	2
all_values[3]	auto[0]	auto[0]	auto[0]	139	1			T30	1		T16	2		T43	2
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T30	1		T16	2		T43	5
all_values[3]	auto[0]	auto[1]	auto[0]	116	1			T30	6		T16	2		T43	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T16	1		T124	1		T126	3
all_values[3]	auto[1]	auto[0]	auto[1]	153	1			T30	2		T16	2		T43	1
all_values[3]	auto[1]	auto[1]	auto[1]	99	1			T30	1		T16	2		T43	2
all_values[4]	auto[0]	auto[0]	auto[0]	151	1			T30	4		T16	1		T43	3
all_values[4]	auto[0]	auto[0]	auto[1]	56	1			T16	1		T43	1		T124	1
all_values[4]	auto[0]	auto[1]	auto[0]	116	1			T30	6		T16	1		T43	3
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T16	4		T43	1		T124	1
all_values[4]	auto[1]	auto[0]	auto[1]	130	1			T16	2		T43	1		T124	2
all_values[4]	auto[1]	auto[1]	auto[1]	122	1			T30	1		T16	2		T43	2
all_values[5]	auto[0]	auto[0]	auto[0]	160	1			T30	5		T16	1		T43	2
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T43	2		T123	1		T102	2
all_values[5]	auto[0]	auto[1]	auto[0]	95	1			T30	1		T43	1		T32	2
all_values[5]	auto[0]	auto[1]	auto[1]	50	1			T30	1		T16	3		T126	1
all_values[5]	auto[1]	auto[0]	auto[1]	164	1			T30	3		T16	5		T43	3
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T30	1		T16	2		T43	3
all_values[6]	auto[0]	auto[0]	auto[0]	114	1			T30	5		T16	1		T32	3
all_values[6]	auto[0]	auto[0]	auto[1]	66	1			T30	2		T16	1		T43	2
all_values[6]	auto[0]	auto[1]	auto[0]	102	1			T30	1		T16	2		T43	3
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T16	3		T43	1		T124	1
all_values[6]	auto[1]	auto[0]	auto[1]	152	1			T30	2		T16	2		T43	3
all_values[6]	auto[1]	auto[1]	auto[1]	128	1			T30	1		T16	2		T43	2
all_values[7]	auto[0]	auto[0]	auto[0]	135	1			T30	3		T16	2		T43	4
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T43	1		T124	1		T123	2
all_values[7]	auto[0]	auto[1]	auto[0]	121	1			T30	3		T16	4		T43	2
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T30	1		T43	1		T123	1
all_values[7]	auto[1]	auto[0]	auto[1]	153	1			T30	1		T16	4		T43	3
all_values[7]	auto[1]	auto[1]	auto[1]	99	1			T30	3		T16	1		T123	1
all_values[8]	auto[0]	auto[0]	auto[1]	197	1			T30	4		T16	4		T43	2
all_values[8]	auto[0]	auto[1]	auto[1]	173	1			T30	3		T16	2		T43	3
all_values[8]	auto[1]	auto[0]	auto[1]	147	1			T30	3		T16	4		T43	5
all_values[8]	auto[1]	auto[1]	auto[1]	119	1			T30	1		T16	1		T43	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal