Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.59


Total test records in report: 1315
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T1257 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1307064566 Aug 17 04:56:50 PM PDT 24 Aug 17 04:56:51 PM PDT 24 29723211 ps
T1258 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3494985029 Aug 17 04:56:23 PM PDT 24 Aug 17 04:56:26 PM PDT 24 737694756 ps
T1259 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3331401905 Aug 17 04:56:23 PM PDT 24 Aug 17 04:56:23 PM PDT 24 20176570 ps
T1260 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1547390711 Aug 17 04:56:33 PM PDT 24 Aug 17 04:56:34 PM PDT 24 21097035 ps
T1261 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.685548643 Aug 17 04:56:22 PM PDT 24 Aug 17 04:56:25 PM PDT 24 693286814 ps
T1262 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1591756058 Aug 17 04:56:23 PM PDT 24 Aug 17 04:56:24 PM PDT 24 48519845 ps
T85 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3956534350 Aug 17 04:56:32 PM PDT 24 Aug 17 04:56:34 PM PDT 24 247384785 ps
T1263 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1073927552 Aug 17 04:56:38 PM PDT 24 Aug 17 04:56:39 PM PDT 24 25632253 ps
T1264 /workspace/coverage/cover_reg_top/12.uart_tl_errors.4041915717 Aug 17 04:56:40 PM PDT 24 Aug 17 04:56:41 PM PDT 24 61911040 ps
T1265 /workspace/coverage/cover_reg_top/11.uart_tl_errors.555670831 Aug 17 04:56:51 PM PDT 24 Aug 17 04:56:53 PM PDT 24 408902782 ps
T1266 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.891164625 Aug 17 04:56:49 PM PDT 24 Aug 17 04:56:50 PM PDT 24 122114259 ps
T1267 /workspace/coverage/cover_reg_top/2.uart_intr_test.648197959 Aug 17 04:56:26 PM PDT 24 Aug 17 04:56:27 PM PDT 24 49045532 ps
T61 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1390697965 Aug 17 04:56:40 PM PDT 24 Aug 17 04:56:40 PM PDT 24 28831305 ps
T1268 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3280377106 Aug 17 04:56:51 PM PDT 24 Aug 17 04:56:52 PM PDT 24 23839813 ps
T1269 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.464819209 Aug 17 04:56:51 PM PDT 24 Aug 17 04:56:53 PM PDT 24 415348378 ps
T1270 /workspace/coverage/cover_reg_top/21.uart_intr_test.2487553596 Aug 17 04:56:58 PM PDT 24 Aug 17 04:56:59 PM PDT 24 39268819 ps
T1271 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3828625048 Aug 17 04:56:12 PM PDT 24 Aug 17 04:56:13 PM PDT 24 28728357 ps
T1272 /workspace/coverage/cover_reg_top/19.uart_intr_test.1037785436 Aug 17 04:56:47 PM PDT 24 Aug 17 04:56:48 PM PDT 24 52680957 ps
T1273 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2591315248 Aug 17 04:56:49 PM PDT 24 Aug 17 04:56:50 PM PDT 24 72996246 ps
T1274 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3918283786 Aug 17 04:56:42 PM PDT 24 Aug 17 04:56:44 PM PDT 24 407065597 ps
T1275 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.891971605 Aug 17 04:56:24 PM PDT 24 Aug 17 04:56:24 PM PDT 24 64732064 ps
T1276 /workspace/coverage/cover_reg_top/5.uart_intr_test.582491446 Aug 17 04:56:32 PM PDT 24 Aug 17 04:56:33 PM PDT 24 17222619 ps
T62 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3700151003 Aug 17 04:56:49 PM PDT 24 Aug 17 04:56:50 PM PDT 24 14666810 ps
T1277 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1913767955 Aug 17 04:56:27 PM PDT 24 Aug 17 04:56:29 PM PDT 24 56266589 ps
T1278 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.557600384 Aug 17 04:56:51 PM PDT 24 Aug 17 04:56:52 PM PDT 24 73751072 ps
T1279 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1474616055 Aug 17 04:56:46 PM PDT 24 Aug 17 04:56:47 PM PDT 24 43902950 ps
T1280 /workspace/coverage/cover_reg_top/38.uart_intr_test.703649890 Aug 17 04:57:00 PM PDT 24 Aug 17 04:57:00 PM PDT 24 11460910 ps
T1281 /workspace/coverage/cover_reg_top/39.uart_intr_test.1279654910 Aug 17 04:56:58 PM PDT 24 Aug 17 04:56:58 PM PDT 24 26254742 ps
T1282 /workspace/coverage/cover_reg_top/14.uart_intr_test.1329538593 Aug 17 04:56:38 PM PDT 24 Aug 17 04:56:38 PM PDT 24 43279379 ps
T1283 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2012501392 Aug 17 04:56:33 PM PDT 24 Aug 17 04:56:35 PM PDT 24 489239889 ps
T1284 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1015285486 Aug 17 04:56:49 PM PDT 24 Aug 17 04:56:50 PM PDT 24 50184412 ps
T1285 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2811273787 Aug 17 04:56:24 PM PDT 24 Aug 17 04:56:25 PM PDT 24 156223292 ps
T1286 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3636945830 Aug 17 04:56:29 PM PDT 24 Aug 17 04:56:30 PM PDT 24 44506367 ps
T1287 /workspace/coverage/cover_reg_top/26.uart_intr_test.1823158122 Aug 17 04:57:00 PM PDT 24 Aug 17 04:57:01 PM PDT 24 20282167 ps
T1288 /workspace/coverage/cover_reg_top/15.uart_intr_test.777130582 Aug 17 04:56:48 PM PDT 24 Aug 17 04:56:48 PM PDT 24 14590875 ps
T1289 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.857369780 Aug 17 04:56:48 PM PDT 24 Aug 17 04:56:48 PM PDT 24 25695209 ps
T1290 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1038272886 Aug 17 04:56:34 PM PDT 24 Aug 17 04:56:34 PM PDT 24 24483413 ps
T63 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3870196188 Aug 17 04:56:49 PM PDT 24 Aug 17 04:56:49 PM PDT 24 31681777 ps
T1291 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3841986559 Aug 17 04:56:42 PM PDT 24 Aug 17 04:56:43 PM PDT 24 50070425 ps
T1292 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2186565257 Aug 17 04:56:22 PM PDT 24 Aug 17 04:56:23 PM PDT 24 16036718 ps
T1293 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3946339747 Aug 17 04:56:21 PM PDT 24 Aug 17 04:56:22 PM PDT 24 15765701 ps
T1294 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3397292910 Aug 17 04:56:25 PM PDT 24 Aug 17 04:56:25 PM PDT 24 133464495 ps
T1295 /workspace/coverage/cover_reg_top/47.uart_intr_test.1317739026 Aug 17 04:56:59 PM PDT 24 Aug 17 04:57:00 PM PDT 24 26023594 ps
T1296 /workspace/coverage/cover_reg_top/13.uart_intr_test.3894108172 Aug 17 04:56:38 PM PDT 24 Aug 17 04:56:39 PM PDT 24 99979047 ps
T1297 /workspace/coverage/cover_reg_top/1.uart_intr_test.1671615831 Aug 17 04:56:21 PM PDT 24 Aug 17 04:56:21 PM PDT 24 42707334 ps
T1298 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.209854430 Aug 17 04:56:25 PM PDT 24 Aug 17 04:56:27 PM PDT 24 137925770 ps
T1299 /workspace/coverage/cover_reg_top/41.uart_intr_test.3880867407 Aug 17 04:56:59 PM PDT 24 Aug 17 04:57:00 PM PDT 24 86393309 ps
T1300 /workspace/coverage/cover_reg_top/46.uart_intr_test.2680935848 Aug 17 04:56:59 PM PDT 24 Aug 17 04:57:00 PM PDT 24 50923252 ps
T1301 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1240053994 Aug 17 04:56:50 PM PDT 24 Aug 17 04:56:51 PM PDT 24 16305008 ps
T65 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3788584174 Aug 17 04:56:30 PM PDT 24 Aug 17 04:56:31 PM PDT 24 102622871 ps
T1302 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3234810473 Aug 17 04:56:49 PM PDT 24 Aug 17 04:56:50 PM PDT 24 38495501 ps
T1303 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1200942646 Aug 17 04:56:36 PM PDT 24 Aug 17 04:56:37 PM PDT 24 44006159 ps
T1304 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3236406631 Aug 17 04:56:31 PM PDT 24 Aug 17 04:56:32 PM PDT 24 74979066 ps
T1305 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3125005736 Aug 17 04:56:38 PM PDT 24 Aug 17 04:56:40 PM PDT 24 325217704 ps
T1306 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1240803669 Aug 17 04:56:30 PM PDT 24 Aug 17 04:56:31 PM PDT 24 196215856 ps
T1307 /workspace/coverage/cover_reg_top/25.uart_intr_test.3405497203 Aug 17 04:57:05 PM PDT 24 Aug 17 04:57:06 PM PDT 24 35874977 ps
T1308 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3341118192 Aug 17 04:56:43 PM PDT 24 Aug 17 04:56:44 PM PDT 24 32109248 ps
T1309 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3031248892 Aug 17 04:56:30 PM PDT 24 Aug 17 04:56:31 PM PDT 24 59416384 ps
T1310 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1005148739 Aug 17 04:56:40 PM PDT 24 Aug 17 04:56:41 PM PDT 24 115409072 ps
T1311 /workspace/coverage/cover_reg_top/1.uart_tl_errors.750801785 Aug 17 04:56:20 PM PDT 24 Aug 17 04:56:21 PM PDT 24 207222420 ps
T66 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2785084427 Aug 17 04:56:17 PM PDT 24 Aug 17 04:56:17 PM PDT 24 15330872 ps
T1312 /workspace/coverage/cover_reg_top/44.uart_intr_test.2689401749 Aug 17 04:56:58 PM PDT 24 Aug 17 04:56:59 PM PDT 24 13854800 ps
T1313 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3417787377 Aug 17 04:56:50 PM PDT 24 Aug 17 04:56:51 PM PDT 24 21172428 ps
T1314 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.320641853 Aug 17 04:56:22 PM PDT 24 Aug 17 04:56:23 PM PDT 24 16197779 ps
T1315 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3564045707 Aug 17 04:56:32 PM PDT 24 Aug 17 04:56:33 PM PDT 24 13917820 ps

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1638284211
Short name T3
Test name
Test status
Simulation time 2001878758 ps
CPU time 26.76 seconds
Started Aug 17 05:22:18 PM PDT 24
Finished Aug 17 05:22:45 PM PDT 24
Peak memory 216812 kb
Host smart-cedcec8c-4ae6-4118-9688-490501dd2981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638284211 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1638284211
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.3621525415
Short name T43
Test name
Test status
Simulation time 492474560701 ps
CPU time 224.02 seconds
Started Aug 17 05:14:39 PM PDT 24
Finished Aug 17 05:18:23 PM PDT 24
Peak memory 200972 kb
Host smart-fc39d097-466d-4d12-8c06-91d021c51434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621525415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3621525415
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all.1489571788
Short name T38
Test name
Test status
Simulation time 448210629189 ps
CPU time 375.24 seconds
Started Aug 17 05:16:28 PM PDT 24
Finished Aug 17 05:22:43 PM PDT 24
Peak memory 200900 kb
Host smart-c9491d58-75e5-45b5-843d-12f89980dd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489571788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1489571788
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all.3539617194
Short name T143
Test name
Test status
Simulation time 231185597478 ps
CPU time 773.65 seconds
Started Aug 17 05:09:46 PM PDT 24
Finished Aug 17 05:22:40 PM PDT 24
Peak memory 200896 kb
Host smart-95374501-d297-4f0e-8476-02a585addb3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539617194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3539617194
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.812322925
Short name T9
Test name
Test status
Simulation time 63300027733 ps
CPU time 24.2 seconds
Started Aug 17 05:14:02 PM PDT 24
Finished Aug 17 05:14:27 PM PDT 24
Peak memory 200740 kb
Host smart-f2bcb33a-e39e-4b46-afec-c7f7c8a02cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812322925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.812322925
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4278708034
Short name T129
Test name
Test status
Simulation time 178128613091 ps
CPU time 43.46 seconds
Started Aug 17 05:10:01 PM PDT 24
Finished Aug 17 05:10:44 PM PDT 24
Peak memory 200848 kb
Host smart-039be093-66cc-448c-bb55-533d932b9830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278708034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4278708034
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/22.uart_stress_all.173467085
Short name T17
Test name
Test status
Simulation time 342377983673 ps
CPU time 136.98 seconds
Started Aug 17 05:14:24 PM PDT 24
Finished Aug 17 05:16:42 PM PDT 24
Peak memory 201204 kb
Host smart-23038bc5-f92c-4da7-9274-2eaf549c98cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173467085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.173467085
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.4285705925
Short name T132
Test name
Test status
Simulation time 105905309426 ps
CPU time 39.15 seconds
Started Aug 17 05:19:33 PM PDT 24
Finished Aug 17 05:20:12 PM PDT 24
Peak memory 200956 kb
Host smart-35b2efa2-08b1-4a2f-937f-72468679daae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285705925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.4285705925
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3629373116
Short name T27
Test name
Test status
Simulation time 63826137 ps
CPU time 0.86 seconds
Started Aug 17 05:09:41 PM PDT 24
Finished Aug 17 05:09:42 PM PDT 24
Peak memory 218900 kb
Host smart-a0fe47ad-2209-4109-b3c1-ef98fac86a22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629373116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3629373116
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3064212002
Short name T140
Test name
Test status
Simulation time 92915969545 ps
CPU time 42.67 seconds
Started Aug 17 05:19:42 PM PDT 24
Finished Aug 17 05:20:25 PM PDT 24
Peak memory 200884 kb
Host smart-59a14d3b-527d-420c-83d2-1fbdd0a66e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064212002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3064212002
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_intr.3214931196
Short name T36
Test name
Test status
Simulation time 52486193197 ps
CPU time 54.57 seconds
Started Aug 17 05:09:44 PM PDT 24
Finished Aug 17 05:10:39 PM PDT 24
Peak memory 200948 kb
Host smart-c0b78d8a-eaf4-438a-b10b-b4fab23d300b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214931196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3214931196
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2313139356
Short name T111
Test name
Test status
Simulation time 83825416233 ps
CPU time 299.5 seconds
Started Aug 17 05:22:44 PM PDT 24
Finished Aug 17 05:27:44 PM PDT 24
Peak memory 200936 kb
Host smart-60825cc9-db92-4b98-9dc8-161489813fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313139356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2313139356
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.3281655986
Short name T201
Test name
Test status
Simulation time 475202670367 ps
CPU time 206.3 seconds
Started Aug 17 05:13:54 PM PDT 24
Finished Aug 17 05:17:21 PM PDT 24
Peak memory 209348 kb
Host smart-4e39e764-3eca-47aa-a0d3-5ec89f0ad4b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281655986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3281655986
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.592293515
Short name T59
Test name
Test status
Simulation time 28380786 ps
CPU time 0.62 seconds
Started Aug 17 04:56:23 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 195516 kb
Host smart-80953e4a-4d7f-4a37-90c4-6a419ee307f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592293515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.592293515
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2176751159
Short name T102
Test name
Test status
Simulation time 62018764926 ps
CPU time 39.33 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:22:58 PM PDT 24
Peak memory 217488 kb
Host smart-fd86f884-4112-4e65-bd0f-e40ce7e1a24f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176751159 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2176751159
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_rx.758080187
Short name T39
Test name
Test status
Simulation time 89082716361 ps
CPU time 36.96 seconds
Started Aug 17 05:15:41 PM PDT 24
Finished Aug 17 05:16:18 PM PDT 24
Peak memory 200948 kb
Host smart-5a3abbee-a729-49cd-a6f1-2628c5d3fbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758080187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.758080187
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_stress_all.2554212232
Short name T118
Test name
Test status
Simulation time 246868961742 ps
CPU time 201.7 seconds
Started Aug 17 05:19:58 PM PDT 24
Finished Aug 17 05:23:20 PM PDT 24
Peak memory 200940 kb
Host smart-9b4754d2-c8c4-46e0-ad46-f75ae42ce63f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554212232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2554212232
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all.2978225039
Short name T114
Test name
Test status
Simulation time 290602283844 ps
CPU time 291.79 seconds
Started Aug 17 05:19:00 PM PDT 24
Finished Aug 17 05:23:52 PM PDT 24
Peak memory 217544 kb
Host smart-e3ff7518-0375-4052-8975-84c610d604b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978225039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2978225039
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_perf.1180115876
Short name T13
Test name
Test status
Simulation time 24019751435 ps
CPU time 285.04 seconds
Started Aug 17 05:12:48 PM PDT 24
Finished Aug 17 05:17:33 PM PDT 24
Peak memory 200956 kb
Host smart-1cc51a4e-4d1a-4156-bfb4-829f1b96d1b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180115876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1180115876
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/13.uart_stress_all.2848234580
Short name T115
Test name
Test status
Simulation time 117749381104 ps
CPU time 50.88 seconds
Started Aug 17 05:11:41 PM PDT 24
Finished Aug 17 05:12:32 PM PDT 24
Peak memory 200928 kb
Host smart-0b6c5eeb-fe25-42a6-b78d-b5fa024a12b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848234580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2848234580
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1141545307
Short name T83
Test name
Test status
Simulation time 535172499 ps
CPU time 1.32 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 199464 kb
Host smart-c8cc3814-011f-4cb4-ba5f-0a25e52c65ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141545307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1141545307
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.824914151
Short name T284
Test name
Test status
Simulation time 105805505551 ps
CPU time 974.56 seconds
Started Aug 17 05:14:40 PM PDT 24
Finished Aug 17 05:30:55 PM PDT 24
Peak memory 201120 kb
Host smart-963a659a-b980-4664-8e76-d984a21b46db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824914151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.824914151
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_stress_all.3853834347
Short name T206
Test name
Test status
Simulation time 205122667933 ps
CPU time 514.28 seconds
Started Aug 17 05:09:31 PM PDT 24
Finished Aug 17 05:18:05 PM PDT 24
Peak memory 216768 kb
Host smart-3264559a-37ee-4dea-a2a8-f23ea306288b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853834347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3853834347
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1852698990
Short name T154
Test name
Test status
Simulation time 135291215891 ps
CPU time 665.13 seconds
Started Aug 17 05:23:18 PM PDT 24
Finished Aug 17 05:34:23 PM PDT 24
Peak memory 200892 kb
Host smart-ab4084ac-87e9-44b7-bd42-11c1c1398d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852698990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1852698990
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3027414408
Short name T191
Test name
Test status
Simulation time 21121284523 ps
CPU time 19.98 seconds
Started Aug 17 05:21:05 PM PDT 24
Finished Aug 17 05:21:25 PM PDT 24
Peak memory 200944 kb
Host smart-12c0dcbf-0eb8-4cf6-ad9b-0ad7ec68f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027414408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3027414408
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_alert_test.2693647832
Short name T26
Test name
Test status
Simulation time 40896954 ps
CPU time 0.57 seconds
Started Aug 17 05:11:02 PM PDT 24
Finished Aug 17 05:11:02 PM PDT 24
Peak memory 196256 kb
Host smart-0e47f7d8-d459-42d3-9d21-95276613f82f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693647832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2693647832
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3503188856
Short name T156
Test name
Test status
Simulation time 103896738100 ps
CPU time 49.9 seconds
Started Aug 17 05:14:41 PM PDT 24
Finished Aug 17 05:15:31 PM PDT 24
Peak memory 200692 kb
Host smart-ed593c67-5224-4e5f-87bc-b588ae3e0b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503188856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3503188856
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.852137566
Short name T365
Test name
Test status
Simulation time 104950262721 ps
CPU time 139.57 seconds
Started Aug 17 05:23:16 PM PDT 24
Finished Aug 17 05:25:36 PM PDT 24
Peak memory 200872 kb
Host smart-49cae265-aea9-42d2-b2ad-3942da1e9442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852137566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.852137566
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.3063071961
Short name T261
Test name
Test status
Simulation time 378461717617 ps
CPU time 259.91 seconds
Started Aug 17 05:17:23 PM PDT 24
Finished Aug 17 05:21:43 PM PDT 24
Peak memory 200908 kb
Host smart-675c7135-5c40-4c54-ba60-ea3b59f351ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063071961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3063071961
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2903234839
Short name T138
Test name
Test status
Simulation time 123136745204 ps
CPU time 204.83 seconds
Started Aug 17 05:22:18 PM PDT 24
Finished Aug 17 05:25:43 PM PDT 24
Peak memory 200840 kb
Host smart-678f9d1b-bf42-43b5-9ebd-347ddff57c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903234839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2903234839
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3314072482
Short name T75
Test name
Test status
Simulation time 20192907 ps
CPU time 0.65 seconds
Started Aug 17 04:56:20 PM PDT 24
Finished Aug 17 04:56:20 PM PDT 24
Peak memory 195832 kb
Host smart-a4d0eac4-ab1c-45eb-bb84-7b4a3d3f28c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314072482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3314072482
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/9.uart_stress_all.346545103
Short name T122
Test name
Test status
Simulation time 287541432875 ps
CPU time 474.93 seconds
Started Aug 17 05:10:43 PM PDT 24
Finished Aug 17 05:18:38 PM PDT 24
Peak memory 200920 kb
Host smart-b527fa14-96b0-418d-b6c1-d3175a5bd01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346545103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.346545103
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all.386523864
Short name T116
Test name
Test status
Simulation time 173945895861 ps
CPU time 266.64 seconds
Started Aug 17 05:14:57 PM PDT 24
Finished Aug 17 05:19:24 PM PDT 24
Peak memory 200960 kb
Host smart-23edadf2-f1c5-4128-84fe-ec4a0b751da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386523864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.386523864
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.941446549
Short name T108
Test name
Test status
Simulation time 48975376282 ps
CPU time 46.24 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:23:13 PM PDT 24
Peak memory 200932 kb
Host smart-12c067d0-e18b-40f3-a624-96033d66ea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941446549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.941446549
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2258086264
Short name T80
Test name
Test status
Simulation time 82996266 ps
CPU time 1.3 seconds
Started Aug 17 04:56:33 PM PDT 24
Finished Aug 17 04:56:35 PM PDT 24
Peak memory 199444 kb
Host smart-7debfc4c-433f-446f-80dd-9da8e36f1b08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258086264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2258086264
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/37.uart_stress_all.3030931841
Short name T235
Test name
Test status
Simulation time 387756498375 ps
CPU time 75.72 seconds
Started Aug 17 05:18:54 PM PDT 24
Finished Aug 17 05:20:10 PM PDT 24
Peak memory 217348 kb
Host smart-592fc63a-1611-4cf8-8a5b-d3ffb6029b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030931841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3030931841
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.760151848
Short name T219
Test name
Test status
Simulation time 51371399209 ps
CPU time 135.55 seconds
Started Aug 17 05:22:52 PM PDT 24
Finished Aug 17 05:25:07 PM PDT 24
Peak memory 200956 kb
Host smart-d1013f5f-5526-4d63-a3a2-214b57929f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760151848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.760151848
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1687213271
Short name T573
Test name
Test status
Simulation time 269191374232 ps
CPU time 306.59 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:28:14 PM PDT 24
Peak memory 200840 kb
Host smart-b224e406-3e2a-4862-843f-08dcc43e3ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687213271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1687213271
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2987910187
Short name T103
Test name
Test status
Simulation time 10756379204 ps
CPU time 55.72 seconds
Started Aug 17 05:17:42 PM PDT 24
Finished Aug 17 05:18:38 PM PDT 24
Peak memory 209820 kb
Host smart-8cfc15f7-8bbb-43ea-add8-6548ee771c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987910187 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2987910187
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1641911813
Short name T252
Test name
Test status
Simulation time 122137490193 ps
CPU time 46.88 seconds
Started Aug 17 05:23:24 PM PDT 24
Finished Aug 17 05:24:11 PM PDT 24
Peak memory 200808 kb
Host smart-917343be-9396-4f50-ae15-be11d7b46203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641911813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1641911813
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.4153221226
Short name T110
Test name
Test status
Simulation time 114455215539 ps
CPU time 245.54 seconds
Started Aug 17 05:23:32 PM PDT 24
Finished Aug 17 05:27:38 PM PDT 24
Peak memory 200884 kb
Host smart-d47f588c-f3ea-461e-b8e1-40b79f9d0d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153221226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.4153221226
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2730102765
Short name T215
Test name
Test status
Simulation time 40684873695 ps
CPU time 32.25 seconds
Started Aug 17 05:23:33 PM PDT 24
Finished Aug 17 05:24:05 PM PDT 24
Peak memory 200840 kb
Host smart-19e8f3af-370a-46cc-8a88-a28cde0f2f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730102765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2730102765
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.773084188
Short name T275
Test name
Test status
Simulation time 48418121490 ps
CPU time 132.65 seconds
Started Aug 17 05:23:51 PM PDT 24
Finished Aug 17 05:26:04 PM PDT 24
Peak memory 200940 kb
Host smart-9e68e27e-c7f8-45e6-8690-6366adadb870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773084188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.773084188
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1963605233
Short name T361
Test name
Test status
Simulation time 2561004183 ps
CPU time 76.04 seconds
Started Aug 17 05:22:06 PM PDT 24
Finished Aug 17 05:23:23 PM PDT 24
Peak memory 200976 kb
Host smart-f71fcc6c-607f-4a38-b968-0f78c5cf10bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963605233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1963605233
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2096165935
Short name T188
Test name
Test status
Simulation time 39860101403 ps
CPU time 56.23 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:24:28 PM PDT 24
Peak memory 200952 kb
Host smart-acb2ee88-cb92-420e-a4a0-27a61ef8f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096165935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2096165935
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3543197676
Short name T514
Test name
Test status
Simulation time 80198799417 ps
CPU time 67.79 seconds
Started Aug 17 05:23:41 PM PDT 24
Finished Aug 17 05:24:49 PM PDT 24
Peak memory 200880 kb
Host smart-98ca00b8-6b48-43f2-9588-5980797d7b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543197676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3543197676
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3398771220
Short name T134
Test name
Test status
Simulation time 41334326789 ps
CPU time 17.35 seconds
Started Aug 17 05:20:29 PM PDT 24
Finished Aug 17 05:20:47 PM PDT 24
Peak memory 200920 kb
Host smart-d8dbf783-8f05-4cb5-9f0b-be3ad5ce9fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398771220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3398771220
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.1761589477
Short name T197
Test name
Test status
Simulation time 372267216162 ps
CPU time 67.09 seconds
Started Aug 17 05:12:55 PM PDT 24
Finished Aug 17 05:14:02 PM PDT 24
Peak memory 200892 kb
Host smart-b3a00d1e-f374-4e22-902f-fc20f67d7b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761589477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1761589477
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3550234958
Short name T271
Test name
Test status
Simulation time 55754487988 ps
CPU time 59.79 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:23:27 PM PDT 24
Peak memory 200896 kb
Host smart-3e2f885a-ed5d-4308-bc87-13d0874f7d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550234958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3550234958
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_full.4244987545
Short name T336
Test name
Test status
Simulation time 39708694161 ps
CPU time 16.4 seconds
Started Aug 17 05:10:19 PM PDT 24
Finished Aug 17 05:10:35 PM PDT 24
Peak memory 200812 kb
Host smart-b1bfb0d6-7b8f-406e-ba42-d5b7a7a55f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244987545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.4244987545
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2855929823
Short name T222
Test name
Test status
Simulation time 15746588990 ps
CPU time 23.24 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:23:30 PM PDT 24
Peak memory 200916 kb
Host smart-fb338143-20af-4d42-a973-84f2a0e83614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855929823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2855929823
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.878068969
Short name T195
Test name
Test status
Simulation time 52323917761 ps
CPU time 44.44 seconds
Started Aug 17 05:23:17 PM PDT 24
Finished Aug 17 05:24:02 PM PDT 24
Peak memory 200620 kb
Host smart-2a272bc7-f9be-405f-b124-927bf8fd8b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878068969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.878068969
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2579181048
Short name T173
Test name
Test status
Simulation time 25970170381 ps
CPU time 26.61 seconds
Started Aug 17 05:12:38 PM PDT 24
Finished Aug 17 05:13:05 PM PDT 24
Peak memory 200876 kb
Host smart-1cb2ca91-7a3f-45b4-bf95-ed85368a901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579181048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2579181048
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1848351583
Short name T303
Test name
Test status
Simulation time 335821594703 ps
CPU time 48.07 seconds
Started Aug 17 05:13:36 PM PDT 24
Finished Aug 17 05:14:24 PM PDT 24
Peak memory 200832 kb
Host smart-a7c314e8-68e7-468b-9a9d-f807a5f06c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848351583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1848351583
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.4243735918
Short name T246
Test name
Test status
Simulation time 36437466573 ps
CPU time 74.99 seconds
Started Aug 17 05:23:56 PM PDT 24
Finished Aug 17 05:25:11 PM PDT 24
Peak memory 200880 kb
Host smart-ac084607-d5be-4de8-a711-d2cbfb23e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243735918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4243735918
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3908718698
Short name T451
Test name
Test status
Simulation time 219383225747 ps
CPU time 481.93 seconds
Started Aug 17 05:15:22 PM PDT 24
Finished Aug 17 05:23:24 PM PDT 24
Peak memory 200920 kb
Host smart-23b33c6b-b9f6-417d-addd-918865bac770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908718698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3908718698
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.626795647
Short name T661
Test name
Test status
Simulation time 2857507635 ps
CPU time 40.41 seconds
Started Aug 17 05:16:11 PM PDT 24
Finished Aug 17 05:16:52 PM PDT 24
Peak memory 217368 kb
Host smart-b1d3b03f-4ea8-49e6-bf40-5bcce093f905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626795647 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.626795647
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.446408428
Short name T232
Test name
Test status
Simulation time 103360165336 ps
CPU time 125.81 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:26:14 PM PDT 24
Peak memory 200956 kb
Host smart-602c979f-c787-4c12-9e99-2a65f4544b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446408428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.446408428
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2886053740
Short name T144
Test name
Test status
Simulation time 31142960687 ps
CPU time 27.52 seconds
Started Aug 17 05:10:42 PM PDT 24
Finished Aug 17 05:11:10 PM PDT 24
Peak memory 200900 kb
Host smart-f5e445b9-27db-4deb-802c-0f76861964a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886053740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2886053740
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1532914940
Short name T130
Test name
Test status
Simulation time 61027013580 ps
CPU time 98.27 seconds
Started Aug 17 05:22:52 PM PDT 24
Finished Aug 17 05:24:30 PM PDT 24
Peak memory 200952 kb
Host smart-574355f4-5c92-4d3a-995e-a13eb0ad1e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532914940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1532914940
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1010810822
Short name T266
Test name
Test status
Simulation time 25346316740 ps
CPU time 10.06 seconds
Started Aug 17 05:22:52 PM PDT 24
Finished Aug 17 05:23:02 PM PDT 24
Peak memory 200916 kb
Host smart-2e0466ba-34c3-422f-b14d-08a0328335f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010810822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1010810822
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2511271347
Short name T15
Test name
Test status
Simulation time 41067939079 ps
CPU time 38.19 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:23:45 PM PDT 24
Peak memory 200940 kb
Host smart-e4a7dec9-32f0-4059-98a4-1c22f66fc251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511271347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2511271347
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1385239762
Short name T245
Test name
Test status
Simulation time 43717369965 ps
CPU time 20.15 seconds
Started Aug 17 05:23:15 PM PDT 24
Finished Aug 17 05:23:35 PM PDT 24
Peak memory 200972 kb
Host smart-6e681282-8708-4e07-a898-a30455d6b3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385239762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1385239762
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.4088403982
Short name T268
Test name
Test status
Simulation time 126478894885 ps
CPU time 52.33 seconds
Started Aug 17 05:23:43 PM PDT 24
Finished Aug 17 05:24:35 PM PDT 24
Peak memory 200916 kb
Host smart-d49496bc-1fa3-4ede-9c17-db80aeec4b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088403982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4088403982
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4052546365
Short name T157
Test name
Test status
Simulation time 98654665256 ps
CPU time 29.63 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:24:10 PM PDT 24
Peak memory 200880 kb
Host smart-961c5018-13fe-426e-9027-8c720a245a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052546365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4052546365
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.776050874
Short name T257
Test name
Test status
Simulation time 54744923813 ps
CPU time 41.24 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:24:50 PM PDT 24
Peak memory 200840 kb
Host smart-eb574004-5737-4a97-bed3-ddb4f5cde1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776050874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.776050874
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2586863696
Short name T237
Test name
Test status
Simulation time 189422524153 ps
CPU time 268.76 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:28:37 PM PDT 24
Peak memory 200748 kb
Host smart-05c47a59-88ce-4efc-abcc-f27fc1e245b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586863696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2586863696
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2444989257
Short name T589
Test name
Test status
Simulation time 4633252754 ps
CPU time 66.1 seconds
Started Aug 17 05:09:56 PM PDT 24
Finished Aug 17 05:11:02 PM PDT 24
Peak memory 217060 kb
Host smart-e63125d1-bf9c-451b-b1e8-e2da46445c74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444989257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2444989257
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2782334102
Short name T127
Test name
Test status
Simulation time 76618247 ps
CPU time 0.92 seconds
Started Aug 17 04:56:46 PM PDT 24
Finished Aug 17 04:56:47 PM PDT 24
Peak memory 198992 kb
Host smart-462b6bfa-08ea-4d74-b002-14c48db4b038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782334102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2782334102
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2441022163
Short name T279
Test name
Test status
Simulation time 203448178843 ps
CPU time 71.88 seconds
Started Aug 17 05:09:31 PM PDT 24
Finished Aug 17 05:10:43 PM PDT 24
Peak memory 200948 kb
Host smart-8883ccce-40d7-4f09-873c-65ba49839f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441022163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2441022163
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_intr.1353790362
Short name T375
Test name
Test status
Simulation time 40019409957 ps
CPU time 26.19 seconds
Started Aug 17 05:10:44 PM PDT 24
Finished Aug 17 05:11:11 PM PDT 24
Peak memory 200956 kb
Host smart-a1155dea-c9ba-45e1-9dbc-07bd5ba8a462
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353790362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1353790362
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.130960413
Short name T765
Test name
Test status
Simulation time 9202346701 ps
CPU time 15.93 seconds
Started Aug 17 05:11:02 PM PDT 24
Finished Aug 17 05:11:18 PM PDT 24
Peak memory 200956 kb
Host smart-f20a2d0c-8b07-45c0-ba93-c94fa768cbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130960413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.130960413
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1488378442
Short name T181
Test name
Test status
Simulation time 57556932188 ps
CPU time 17.47 seconds
Started Aug 17 05:23:06 PM PDT 24
Finished Aug 17 05:23:23 PM PDT 24
Peak memory 200844 kb
Host smart-24b0aed3-3188-4ff7-8a1c-0fb31e25b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488378442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1488378442
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1272369638
Short name T355
Test name
Test status
Simulation time 176074612937 ps
CPU time 59.4 seconds
Started Aug 17 05:23:08 PM PDT 24
Finished Aug 17 05:24:07 PM PDT 24
Peak memory 200940 kb
Host smart-e1f65439-e5f6-4680-a3b3-0169902fdd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272369638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1272369638
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3192513821
Short name T168
Test name
Test status
Simulation time 225007147623 ps
CPU time 25.77 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:23:33 PM PDT 24
Peak memory 200872 kb
Host smart-0fc679db-3f8a-42b6-83a1-4e1a4aa0710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192513821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3192513821
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2983774778
Short name T92
Test name
Test status
Simulation time 171968280510 ps
CPU time 477.82 seconds
Started Aug 17 05:11:42 PM PDT 24
Finished Aug 17 05:19:40 PM PDT 24
Peak memory 200872 kb
Host smart-29f79608-63fb-49f6-82e8-2b3d1c4094a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983774778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2983774778
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.545976913
Short name T198
Test name
Test status
Simulation time 221533041252 ps
CPU time 308.25 seconds
Started Aug 17 05:12:05 PM PDT 24
Finished Aug 17 05:17:14 PM PDT 24
Peak memory 200956 kb
Host smart-7f954c00-7ef9-40aa-877b-1408669e5fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545976913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.545976913
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3394067796
Short name T163
Test name
Test status
Simulation time 39432544983 ps
CPU time 31.63 seconds
Started Aug 17 05:23:18 PM PDT 24
Finished Aug 17 05:23:50 PM PDT 24
Peak memory 200868 kb
Host smart-be9c9e32-7a73-48be-8f60-568ea06e9df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394067796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3394067796
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.402127633
Short name T200
Test name
Test status
Simulation time 139196136798 ps
CPU time 37.02 seconds
Started Aug 17 05:23:28 PM PDT 24
Finished Aug 17 05:24:05 PM PDT 24
Peak memory 200840 kb
Host smart-b2936589-8520-4313-bb86-2e1a610fb06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402127633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.402127633
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.578472351
Short name T249
Test name
Test status
Simulation time 32416265082 ps
CPU time 82.01 seconds
Started Aug 17 05:23:28 PM PDT 24
Finished Aug 17 05:24:50 PM PDT 24
Peak memory 200780 kb
Host smart-c637d6ed-aa3d-4b26-ad00-ca37cc65caca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578472351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.578472351
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.769736286
Short name T916
Test name
Test status
Simulation time 10626274079 ps
CPU time 32.71 seconds
Started Aug 17 05:13:12 PM PDT 24
Finished Aug 17 05:13:44 PM PDT 24
Peak memory 209380 kb
Host smart-2213770f-0413-4b96-a857-6a42ab28456e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769736286 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.769736286
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1545544399
Short name T265
Test name
Test status
Simulation time 119608504080 ps
CPU time 242.52 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:27:33 PM PDT 24
Peak memory 200884 kb
Host smart-07da5d34-8b55-414e-b7b9-31c8c7df8bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545544399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1545544399
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4080154676
Short name T255
Test name
Test status
Simulation time 57561408597 ps
CPU time 22.44 seconds
Started Aug 17 05:23:32 PM PDT 24
Finished Aug 17 05:23:55 PM PDT 24
Peak memory 200960 kb
Host smart-001bb6b5-62e0-41c8-8378-4c2efb4b44d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080154676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4080154676
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3284481570
Short name T251
Test name
Test status
Simulation time 80179277212 ps
CPU time 31.74 seconds
Started Aug 17 05:14:48 PM PDT 24
Finished Aug 17 05:15:20 PM PDT 24
Peak memory 200552 kb
Host smart-6d87b589-8574-44f7-8071-b1b61482fead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284481570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3284481570
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.97059701
Short name T207
Test name
Test status
Simulation time 58905074866 ps
CPU time 40.63 seconds
Started Aug 17 05:24:00 PM PDT 24
Finished Aug 17 05:24:41 PM PDT 24
Peak memory 200940 kb
Host smart-893a4549-f9b6-4962-b538-47441bc0bc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97059701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.97059701
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3232873166
Short name T205
Test name
Test status
Simulation time 175698775142 ps
CPU time 66.9 seconds
Started Aug 17 05:24:12 PM PDT 24
Finished Aug 17 05:25:18 PM PDT 24
Peak memory 200952 kb
Host smart-35faff62-6018-44f1-815c-343cf348d6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232873166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3232873166
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.667544942
Short name T258
Test name
Test status
Simulation time 69646477155 ps
CPU time 124.96 seconds
Started Aug 17 05:21:55 PM PDT 24
Finished Aug 17 05:24:00 PM PDT 24
Peak memory 200944 kb
Host smart-6f54cf46-5475-4db8-bda9-d5794713f254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667544942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.667544942
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3946339747
Short name T1293
Test name
Test status
Simulation time 15765701 ps
CPU time 0.65 seconds
Started Aug 17 04:56:21 PM PDT 24
Finished Aug 17 04:56:22 PM PDT 24
Peak memory 195572 kb
Host smart-e56034ba-1a17-4f79-b6b4-ce2aa1ad054e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946339747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3946339747
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.209854430
Short name T1298
Test name
Test status
Simulation time 137925770 ps
CPU time 1.56 seconds
Started Aug 17 04:56:25 PM PDT 24
Finished Aug 17 04:56:27 PM PDT 24
Peak memory 197940 kb
Host smart-3ffe2fc4-e476-4840-8118-4786c025d1cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209854430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.209854430
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3828625048
Short name T1271
Test name
Test status
Simulation time 28728357 ps
CPU time 0.67 seconds
Started Aug 17 04:56:12 PM PDT 24
Finished Aug 17 04:56:13 PM PDT 24
Peak memory 198252 kb
Host smart-e98bf3f1-f6db-4ee4-8c4a-098803f2a014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828625048 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3828625048
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2785084427
Short name T66
Test name
Test status
Simulation time 15330872 ps
CPU time 0.59 seconds
Started Aug 17 04:56:17 PM PDT 24
Finished Aug 17 04:56:17 PM PDT 24
Peak memory 195464 kb
Host smart-73bb184a-604a-4ad2-a0f9-dea0c6b168ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785084427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2785084427
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.991222158
Short name T1254
Test name
Test status
Simulation time 14588895 ps
CPU time 0.56 seconds
Started Aug 17 04:56:25 PM PDT 24
Finished Aug 17 04:56:25 PM PDT 24
Peak memory 194536 kb
Host smart-eb81285d-5089-487b-8496-d9795969d626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991222158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.991222158
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.4108261561
Short name T1216
Test name
Test status
Simulation time 238558266 ps
CPU time 1.31 seconds
Started Aug 17 04:56:16 PM PDT 24
Finished Aug 17 04:56:17 PM PDT 24
Peak memory 200256 kb
Host smart-e6ebae97-cddc-4742-a505-04f3545a7a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108261561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4108261561
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3372102304
Short name T89
Test name
Test status
Simulation time 133920015 ps
CPU time 0.95 seconds
Started Aug 17 04:56:19 PM PDT 24
Finished Aug 17 04:56:20 PM PDT 24
Peak memory 199424 kb
Host smart-e21f8d3b-d2c0-4a62-9b87-c3cd54b835f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372102304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3372102304
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.320641853
Short name T1314
Test name
Test status
Simulation time 16197779 ps
CPU time 0.65 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 195056 kb
Host smart-715d0c35-067e-438b-93e2-2bb5f0c05bf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320641853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.320641853
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2419018213
Short name T1199
Test name
Test status
Simulation time 101228037 ps
CPU time 1.44 seconds
Started Aug 17 04:56:21 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 198248 kb
Host smart-45e00b4e-35ed-47a5-96ff-8859a7797f57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419018213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2419018213
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1774010579
Short name T1255
Test name
Test status
Simulation time 16470966 ps
CPU time 0.6 seconds
Started Aug 17 04:56:17 PM PDT 24
Finished Aug 17 04:56:18 PM PDT 24
Peak memory 195544 kb
Host smart-4fbaca56-4a3c-4581-8e26-f630303474a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774010579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1774010579
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2514655872
Short name T1211
Test name
Test status
Simulation time 24938677 ps
CPU time 0.77 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 199520 kb
Host smart-9beb1787-0b91-4163-b2b7-e85f086e4ec6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514655872 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2514655872
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.99187224
Short name T60
Test name
Test status
Simulation time 32682334 ps
CPU time 0.62 seconds
Started Aug 17 04:56:19 PM PDT 24
Finished Aug 17 04:56:20 PM PDT 24
Peak memory 195728 kb
Host smart-7dface08-b69e-49f5-b7ab-39677e08d59c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99187224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.99187224
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1671615831
Short name T1297
Test name
Test status
Simulation time 42707334 ps
CPU time 0.57 seconds
Started Aug 17 04:56:21 PM PDT 24
Finished Aug 17 04:56:21 PM PDT 24
Peak memory 194532 kb
Host smart-db910d4c-1589-473f-9344-61ea9eca0e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671615831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1671615831
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3636945830
Short name T1286
Test name
Test status
Simulation time 44506367 ps
CPU time 0.61 seconds
Started Aug 17 04:56:29 PM PDT 24
Finished Aug 17 04:56:30 PM PDT 24
Peak memory 196084 kb
Host smart-1dd30915-9f18-4bd1-a67a-54f024cf7e65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636945830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3636945830
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.750801785
Short name T1311
Test name
Test status
Simulation time 207222420 ps
CPU time 1.74 seconds
Started Aug 17 04:56:20 PM PDT 24
Finished Aug 17 04:56:21 PM PDT 24
Peak memory 200224 kb
Host smart-98616d61-dc1c-401c-b442-4158b771781f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750801785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.750801785
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3955437931
Short name T86
Test name
Test status
Simulation time 99068795 ps
CPU time 0.95 seconds
Started Aug 17 04:56:16 PM PDT 24
Finished Aug 17 04:56:17 PM PDT 24
Peak memory 199272 kb
Host smart-2f9928ec-d238-42cf-b5ac-17657fc6a56d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955437931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3955437931
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3841986559
Short name T1291
Test name
Test status
Simulation time 50070425 ps
CPU time 0.64 seconds
Started Aug 17 04:56:42 PM PDT 24
Finished Aug 17 04:56:43 PM PDT 24
Peak memory 197848 kb
Host smart-e1d34210-ed15-488b-a635-fa4ed3348d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841986559 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3841986559
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2441743137
Short name T72
Test name
Test status
Simulation time 23211230 ps
CPU time 0.57 seconds
Started Aug 17 04:56:39 PM PDT 24
Finished Aug 17 04:56:39 PM PDT 24
Peak memory 195576 kb
Host smart-08c15f59-ad1c-4a35-b346-87b53e5edafa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441743137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2441743137
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2385287945
Short name T1192
Test name
Test status
Simulation time 17528033 ps
CPU time 0.55 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:41 PM PDT 24
Peak memory 194592 kb
Host smart-cb7478ce-2182-4f75-a3e6-cbba80d38aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385287945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2385287945
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.887887144
Short name T1217
Test name
Test status
Simulation time 14016528 ps
CPU time 0.64 seconds
Started Aug 17 04:56:51 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 195756 kb
Host smart-0654f98b-a1b0-4e7d-ade7-6c4a4a31f45f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887887144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.887887144
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1975464029
Short name T1207
Test name
Test status
Simulation time 131862735 ps
CPU time 2.54 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:53 PM PDT 24
Peak memory 200224 kb
Host smart-e09c859b-83f5-42a8-a167-21c74b5eba06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975464029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1975464029
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1005148739
Short name T1310
Test name
Test status
Simulation time 115409072 ps
CPU time 0.91 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:41 PM PDT 24
Peak memory 198884 kb
Host smart-a41e2475-5650-46cd-ad33-6bf574fcd648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005148739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1005148739
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1877809563
Short name T1219
Test name
Test status
Simulation time 23988486 ps
CPU time 0.83 seconds
Started Aug 17 04:56:45 PM PDT 24
Finished Aug 17 04:56:46 PM PDT 24
Peak memory 198504 kb
Host smart-14cf6a06-0869-4538-b0d6-9cee024c676e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877809563 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1877809563
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1742367206
Short name T70
Test name
Test status
Simulation time 56737144 ps
CPU time 0.64 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:41 PM PDT 24
Peak memory 195724 kb
Host smart-008a0979-2edb-41d8-9ef8-e75929a2edcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742367206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1742367206
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.797191084
Short name T1196
Test name
Test status
Simulation time 12194479 ps
CPU time 0.59 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:41 PM PDT 24
Peak memory 194632 kb
Host smart-794e9d24-d66b-47a8-978f-95b2061ac0bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797191084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.797191084
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3341118192
Short name T1308
Test name
Test status
Simulation time 32109248 ps
CPU time 0.68 seconds
Started Aug 17 04:56:43 PM PDT 24
Finished Aug 17 04:56:44 PM PDT 24
Peak memory 195048 kb
Host smart-4ca70f47-051f-4b4b-bc1c-7e82c328214d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341118192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3341118192
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.555670831
Short name T1265
Test name
Test status
Simulation time 408902782 ps
CPU time 1.79 seconds
Started Aug 17 04:56:51 PM PDT 24
Finished Aug 17 04:56:53 PM PDT 24
Peak memory 200192 kb
Host smart-2329e722-7737-430b-aa55-a7c402d78dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555670831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.555670831
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3125005736
Short name T1305
Test name
Test status
Simulation time 325217704 ps
CPU time 1.35 seconds
Started Aug 17 04:56:38 PM PDT 24
Finished Aug 17 04:56:40 PM PDT 24
Peak memory 199524 kb
Host smart-74e5d2a7-4b74-4dc7-b136-502a4f324f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125005736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3125005736
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1344337517
Short name T1230
Test name
Test status
Simulation time 59417725 ps
CPU time 0.88 seconds
Started Aug 17 04:56:39 PM PDT 24
Finished Aug 17 04:56:40 PM PDT 24
Peak memory 200064 kb
Host smart-3e91f406-e49c-4277-8d73-baae7a812ae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344337517 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1344337517
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1390697965
Short name T61
Test name
Test status
Simulation time 28831305 ps
CPU time 0.61 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:40 PM PDT 24
Peak memory 195524 kb
Host smart-ec4a1fd8-6553-4e18-b638-d2e81c53738f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390697965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1390697965
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2342604437
Short name T1218
Test name
Test status
Simulation time 71151718 ps
CPU time 0.57 seconds
Started Aug 17 04:56:39 PM PDT 24
Finished Aug 17 04:56:40 PM PDT 24
Peak memory 194604 kb
Host smart-e5355966-3d10-4896-b958-7b84b0ed739f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342604437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2342604437
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1073927552
Short name T1263
Test name
Test status
Simulation time 25632253 ps
CPU time 0.71 seconds
Started Aug 17 04:56:38 PM PDT 24
Finished Aug 17 04:56:39 PM PDT 24
Peak memory 197188 kb
Host smart-5c31f89f-a71e-499d-bf28-21750d693df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073927552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1073927552
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.4041915717
Short name T1264
Test name
Test status
Simulation time 61911040 ps
CPU time 1.33 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:41 PM PDT 24
Peak memory 200280 kb
Host smart-31c411ad-09a7-4c24-9301-75c5fa44d86c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041915717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4041915717
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.799594832
Short name T1210
Test name
Test status
Simulation time 1113268555 ps
CPU time 1.35 seconds
Started Aug 17 04:56:43 PM PDT 24
Finished Aug 17 04:56:45 PM PDT 24
Peak memory 199576 kb
Host smart-98e3f029-7002-4d4c-b387-b1734cb55c30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799594832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.799594832
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1474616055
Short name T1279
Test name
Test status
Simulation time 43902950 ps
CPU time 0.78 seconds
Started Aug 17 04:56:46 PM PDT 24
Finished Aug 17 04:56:47 PM PDT 24
Peak memory 200024 kb
Host smart-c1b48be9-7b3e-4994-b31f-56f91287c481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474616055 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1474616055
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.613425842
Short name T69
Test name
Test status
Simulation time 15143021 ps
CPU time 0.59 seconds
Started Aug 17 04:56:41 PM PDT 24
Finished Aug 17 04:56:42 PM PDT 24
Peak memory 195548 kb
Host smart-3252765a-5c1c-4b6d-9f37-c70310c8569f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613425842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.613425842
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3894108172
Short name T1296
Test name
Test status
Simulation time 99979047 ps
CPU time 0.58 seconds
Started Aug 17 04:56:38 PM PDT 24
Finished Aug 17 04:56:39 PM PDT 24
Peak memory 194600 kb
Host smart-394b56cc-4280-4636-af40-ba99266f6aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894108172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3894108172
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1395471309
Short name T71
Test name
Test status
Simulation time 19882345 ps
CPU time 0.77 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:40 PM PDT 24
Peak memory 197876 kb
Host smart-744f9d3b-2e1f-47b0-b345-51fc9c7eea58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395471309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1395471309
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.8081570
Short name T1202
Test name
Test status
Simulation time 116435682 ps
CPU time 1.77 seconds
Started Aug 17 04:56:47 PM PDT 24
Finished Aug 17 04:56:49 PM PDT 24
Peak memory 200248 kb
Host smart-402e5e9f-442a-4629-8932-13e3eb862082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8081570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.8081570
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.557600384
Short name T1278
Test name
Test status
Simulation time 73751072 ps
CPU time 0.94 seconds
Started Aug 17 04:56:51 PM PDT 24
Finished Aug 17 04:56:52 PM PDT 24
Peak memory 199080 kb
Host smart-2b678c5e-aebe-4051-bca0-2ae0bc94447f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557600384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.557600384
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.857369780
Short name T1289
Test name
Test status
Simulation time 25695209 ps
CPU time 0.81 seconds
Started Aug 17 04:56:48 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 199108 kb
Host smart-c900161d-d98f-4368-81fe-92744d9333ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857369780 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.857369780
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1519781491
Short name T1251
Test name
Test status
Simulation time 86219030 ps
CPU time 0.57 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:41 PM PDT 24
Peak memory 195508 kb
Host smart-b9682c82-7b0f-4db9-957b-b9bfb5b54bec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519781491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1519781491
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1329538593
Short name T1282
Test name
Test status
Simulation time 43279379 ps
CPU time 0.55 seconds
Started Aug 17 04:56:38 PM PDT 24
Finished Aug 17 04:56:38 PM PDT 24
Peak memory 194528 kb
Host smart-78257b9d-9270-425a-bb46-006cad2c7fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329538593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1329538593
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1163054194
Short name T74
Test name
Test status
Simulation time 59154856 ps
CPU time 0.79 seconds
Started Aug 17 04:56:47 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 197196 kb
Host smart-206abf3c-d081-4fdc-84ac-a9a10cef9945
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163054194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1163054194
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1394505101
Short name T1225
Test name
Test status
Simulation time 59253093 ps
CPU time 1.38 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:42 PM PDT 24
Peak memory 200192 kb
Host smart-e21a4d8f-c629-44a4-96fa-250039704118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394505101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1394505101
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3622785110
Short name T1239
Test name
Test status
Simulation time 55007067 ps
CPU time 0.86 seconds
Started Aug 17 04:56:47 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 199820 kb
Host smart-b59c0204-c8df-4cee-b7b5-a243a0f66c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622785110 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3622785110
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3700151003
Short name T62
Test name
Test status
Simulation time 14666810 ps
CPU time 0.62 seconds
Started Aug 17 04:56:49 PM PDT 24
Finished Aug 17 04:56:50 PM PDT 24
Peak memory 195500 kb
Host smart-90d86289-5a81-4a7a-8d9c-d2f210ea02e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700151003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3700151003
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.777130582
Short name T1288
Test name
Test status
Simulation time 14590875 ps
CPU time 0.58 seconds
Started Aug 17 04:56:48 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 194608 kb
Host smart-9e91549d-83b8-4f10-9741-390dc99a2c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777130582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.777130582
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2827513768
Short name T1248
Test name
Test status
Simulation time 105969643 ps
CPU time 0.73 seconds
Started Aug 17 04:56:48 PM PDT 24
Finished Aug 17 04:56:49 PM PDT 24
Peak memory 196048 kb
Host smart-9fdbbc96-7924-4b4b-a9bd-276261a5db4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827513768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2827513768
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3918283786
Short name T1274
Test name
Test status
Simulation time 407065597 ps
CPU time 1.33 seconds
Started Aug 17 04:56:42 PM PDT 24
Finished Aug 17 04:56:44 PM PDT 24
Peak memory 200300 kb
Host smart-62d6058a-ca36-46f1-b5d7-f7eb6fb2620e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918283786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3918283786
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2909327749
Short name T1235
Test name
Test status
Simulation time 70454504 ps
CPU time 0.91 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 198828 kb
Host smart-f782d408-b0fd-4c39-b37b-b24f58b54dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909327749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2909327749
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2591315248
Short name T1273
Test name
Test status
Simulation time 72996246 ps
CPU time 0.86 seconds
Started Aug 17 04:56:49 PM PDT 24
Finished Aug 17 04:56:50 PM PDT 24
Peak memory 199976 kb
Host smart-6132ca32-bf11-4847-aed9-fc4e91ef1be9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591315248 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2591315248
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3870196188
Short name T63
Test name
Test status
Simulation time 31681777 ps
CPU time 0.63 seconds
Started Aug 17 04:56:49 PM PDT 24
Finished Aug 17 04:56:49 PM PDT 24
Peak memory 195908 kb
Host smart-b4f99e23-23ff-4df7-bdec-87ff836896a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870196188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3870196188
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.712391457
Short name T1212
Test name
Test status
Simulation time 12483894 ps
CPU time 0.55 seconds
Started Aug 17 04:56:54 PM PDT 24
Finished Aug 17 04:56:55 PM PDT 24
Peak memory 194604 kb
Host smart-c9d2a437-6cad-4ff5-930d-f0f8e92951a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712391457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.712391457
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3280377106
Short name T1268
Test name
Test status
Simulation time 23839813 ps
CPU time 0.66 seconds
Started Aug 17 04:56:51 PM PDT 24
Finished Aug 17 04:56:52 PM PDT 24
Peak memory 195712 kb
Host smart-4618a7cd-1d0c-4c55-8db4-8a636f0f66a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280377106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3280377106
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1015285486
Short name T1284
Test name
Test status
Simulation time 50184412 ps
CPU time 1.43 seconds
Started Aug 17 04:56:49 PM PDT 24
Finished Aug 17 04:56:50 PM PDT 24
Peak memory 200220 kb
Host smart-e4bba84e-4633-4168-a223-0bd399700430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015285486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1015285486
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2641781805
Short name T1243
Test name
Test status
Simulation time 174789617 ps
CPU time 1.01 seconds
Started Aug 17 04:56:49 PM PDT 24
Finished Aug 17 04:56:50 PM PDT 24
Peak memory 199448 kb
Host smart-97e6cce9-2439-4535-997f-edd691802b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641781805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2641781805
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.891164625
Short name T1266
Test name
Test status
Simulation time 122114259 ps
CPU time 0.96 seconds
Started Aug 17 04:56:49 PM PDT 24
Finished Aug 17 04:56:50 PM PDT 24
Peak memory 200036 kb
Host smart-ab8a7c93-9bca-4922-83da-b7a4038bd2d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891164625 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.891164625
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.4021767183
Short name T67
Test name
Test status
Simulation time 50210609 ps
CPU time 0.58 seconds
Started Aug 17 04:56:48 PM PDT 24
Finished Aug 17 04:56:49 PM PDT 24
Peak memory 195628 kb
Host smart-fa1d0136-a2a1-4b04-b3d2-9d98af35d13f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021767183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.4021767183
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.431494322
Short name T1198
Test name
Test status
Simulation time 43251471 ps
CPU time 0.57 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 194456 kb
Host smart-301ac735-84db-41bb-9a43-d6b4ccb0df5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431494322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.431494322
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3307299951
Short name T1236
Test name
Test status
Simulation time 37535497 ps
CPU time 0.69 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 196980 kb
Host smart-031648d9-2844-40c7-9e6b-92c7d37d777a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307299951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3307299951
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.482116228
Short name T1215
Test name
Test status
Simulation time 140147610 ps
CPU time 1.36 seconds
Started Aug 17 04:56:49 PM PDT 24
Finished Aug 17 04:56:50 PM PDT 24
Peak memory 200208 kb
Host smart-0e8d0c44-0137-4757-a8c1-bc63abbdd914
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482116228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.482116228
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.753498458
Short name T81
Test name
Test status
Simulation time 162909582 ps
CPU time 0.98 seconds
Started Aug 17 04:56:48 PM PDT 24
Finished Aug 17 04:56:49 PM PDT 24
Peak memory 199192 kb
Host smart-8e351700-4efc-41e7-bde9-0db86a2587b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753498458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.753498458
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3417787377
Short name T1313
Test name
Test status
Simulation time 21172428 ps
CPU time 0.69 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 198892 kb
Host smart-65641718-338d-45cf-9346-de44cb8babf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417787377 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3417787377
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.729392699
Short name T1228
Test name
Test status
Simulation time 13707009 ps
CPU time 0.6 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 195576 kb
Host smart-3756d895-4faa-48d4-b4ca-16cded764663
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729392699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.729392699
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1393411944
Short name T1249
Test name
Test status
Simulation time 11181794 ps
CPU time 0.58 seconds
Started Aug 17 04:56:51 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 194540 kb
Host smart-e1b48ad6-e34e-46bd-92c1-5ed17a91ebb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393411944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1393411944
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1307064566
Short name T1257
Test name
Test status
Simulation time 29723211 ps
CPU time 0.79 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 197040 kb
Host smart-04d3e3cc-8b7c-4411-82da-d112d4f77ce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307064566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1307064566
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3234810473
Short name T1302
Test name
Test status
Simulation time 38495501 ps
CPU time 1.46 seconds
Started Aug 17 04:56:49 PM PDT 24
Finished Aug 17 04:56:50 PM PDT 24
Peak memory 200216 kb
Host smart-af334f83-dea3-4f63-92ec-584a89a6a1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234810473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3234810473
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.464819209
Short name T1269
Test name
Test status
Simulation time 415348378 ps
CPU time 1.42 seconds
Started Aug 17 04:56:51 PM PDT 24
Finished Aug 17 04:56:53 PM PDT 24
Peak memory 199592 kb
Host smart-ccbae184-07cf-4fbc-8118-5badab98fa6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464819209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.464819209
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1590965526
Short name T1253
Test name
Test status
Simulation time 18588863 ps
CPU time 0.91 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 200004 kb
Host smart-a4980f8e-c2b7-4d0e-b65d-9e07bf9b04e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590965526 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1590965526
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1240053994
Short name T1301
Test name
Test status
Simulation time 16305008 ps
CPU time 0.61 seconds
Started Aug 17 04:56:50 PM PDT 24
Finished Aug 17 04:56:51 PM PDT 24
Peak memory 195612 kb
Host smart-834e429b-49ab-49a9-9b2e-cbca84cbd121
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240053994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1240053994
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1037785436
Short name T1272
Test name
Test status
Simulation time 52680957 ps
CPU time 0.58 seconds
Started Aug 17 04:56:47 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 194528 kb
Host smart-be8290ef-369b-4c4f-99ee-714e7bf71b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037785436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1037785436
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2880278224
Short name T1241
Test name
Test status
Simulation time 181933040 ps
CPU time 0.65 seconds
Started Aug 17 04:56:48 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 195724 kb
Host smart-7badce68-350e-4625-b54c-692f1ef117b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880278224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2880278224
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2314929975
Short name T1200
Test name
Test status
Simulation time 124591117 ps
CPU time 1.74 seconds
Started Aug 17 04:56:53 PM PDT 24
Finished Aug 17 04:56:55 PM PDT 24
Peak memory 200324 kb
Host smart-669410e7-b8d0-444b-89c4-807dccc75bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314929975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2314929975
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3277599567
Short name T128
Test name
Test status
Simulation time 134336727 ps
CPU time 1.29 seconds
Started Aug 17 04:56:46 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 199632 kb
Host smart-1d573c66-ab0b-4fd9-a613-2651bc86e239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277599567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3277599567
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.751774164
Short name T56
Test name
Test status
Simulation time 75645759 ps
CPU time 0.66 seconds
Started Aug 17 04:56:24 PM PDT 24
Finished Aug 17 04:56:25 PM PDT 24
Peak memory 195492 kb
Host smart-ed9b9f7a-ba68-4329-b14d-1be243ac127e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751774164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.751774164
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3494985029
Short name T1258
Test name
Test status
Simulation time 737694756 ps
CPU time 2.38 seconds
Started Aug 17 04:56:23 PM PDT 24
Finished Aug 17 04:56:26 PM PDT 24
Peak memory 197864 kb
Host smart-c06a96ac-9cba-46d0-b650-d9590b412e35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494985029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3494985029
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2811273787
Short name T1285
Test name
Test status
Simulation time 156223292 ps
CPU time 0.64 seconds
Started Aug 17 04:56:24 PM PDT 24
Finished Aug 17 04:56:25 PM PDT 24
Peak memory 195772 kb
Host smart-0cdc7fbe-a3bb-4257-ac97-2a964028e503
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811273787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2811273787
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1913767955
Short name T1277
Test name
Test status
Simulation time 56266589 ps
CPU time 1.29 seconds
Started Aug 17 04:56:27 PM PDT 24
Finished Aug 17 04:56:29 PM PDT 24
Peak memory 200228 kb
Host smart-ef374e4e-9142-481b-a5f8-a0f6c5b9ac71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913767955 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1913767955
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3412857229
Short name T57
Test name
Test status
Simulation time 18389914 ps
CPU time 0.67 seconds
Started Aug 17 04:56:23 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 195596 kb
Host smart-008c11d9-6d16-44f0-aaa4-8c45ca5ce177
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412857229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3412857229
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.648197959
Short name T1267
Test name
Test status
Simulation time 49045532 ps
CPU time 0.56 seconds
Started Aug 17 04:56:26 PM PDT 24
Finished Aug 17 04:56:27 PM PDT 24
Peak memory 194612 kb
Host smart-4c417ad0-fab9-477b-bb14-66ce8cc038fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648197959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.648197959
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2056797595
Short name T1222
Test name
Test status
Simulation time 51974041 ps
CPU time 0.64 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 195772 kb
Host smart-34ee5b00-457c-4bbd-b660-32a3779978f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056797595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2056797595
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2851722728
Short name T1185
Test name
Test status
Simulation time 78818693 ps
CPU time 1.5 seconds
Started Aug 17 04:56:25 PM PDT 24
Finished Aug 17 04:56:26 PM PDT 24
Peak memory 200180 kb
Host smart-9a4d93fc-f551-48f6-a8ec-2c43cc2e0f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851722728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2851722728
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.182300131
Short name T87
Test name
Test status
Simulation time 37451263 ps
CPU time 0.92 seconds
Started Aug 17 04:56:21 PM PDT 24
Finished Aug 17 04:56:22 PM PDT 24
Peak memory 199180 kb
Host smart-6c3f23bd-2370-41a7-a30d-80c60879b9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182300131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.182300131
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3229221805
Short name T1213
Test name
Test status
Simulation time 15080607 ps
CPU time 0.58 seconds
Started Aug 17 04:56:59 PM PDT 24
Finished Aug 17 04:57:00 PM PDT 24
Peak memory 194476 kb
Host smart-96d7da82-198d-4755-a0c6-73f932a2003f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229221805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3229221805
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2487553596
Short name T1270
Test name
Test status
Simulation time 39268819 ps
CPU time 0.59 seconds
Started Aug 17 04:56:58 PM PDT 24
Finished Aug 17 04:56:59 PM PDT 24
Peak memory 194624 kb
Host smart-efa0aa9f-5ea7-4744-b458-1f2b79b032ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487553596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2487553596
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.206761044
Short name T1208
Test name
Test status
Simulation time 43204893 ps
CPU time 0.59 seconds
Started Aug 17 04:57:05 PM PDT 24
Finished Aug 17 04:57:06 PM PDT 24
Peak memory 194504 kb
Host smart-0d119e98-02d6-44fc-97b8-2dfa152c3752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206761044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.206761044
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.576304576
Short name T1229
Test name
Test status
Simulation time 14830929 ps
CPU time 0.56 seconds
Started Aug 17 04:56:59 PM PDT 24
Finished Aug 17 04:56:59 PM PDT 24
Peak memory 194608 kb
Host smart-f6accf0c-2d1c-4fa9-82d8-0fbae883d516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576304576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.576304576
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1825836185
Short name T1204
Test name
Test status
Simulation time 12161176 ps
CPU time 0.63 seconds
Started Aug 17 04:57:01 PM PDT 24
Finished Aug 17 04:57:02 PM PDT 24
Peak memory 194560 kb
Host smart-952b41a9-9836-46b7-9aaa-65e0f0c07610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825836185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1825836185
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3405497203
Short name T1307
Test name
Test status
Simulation time 35874977 ps
CPU time 0.57 seconds
Started Aug 17 04:57:05 PM PDT 24
Finished Aug 17 04:57:06 PM PDT 24
Peak memory 194532 kb
Host smart-225d92d3-0bff-4842-a24c-78d2c4d9c9b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405497203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3405497203
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1823158122
Short name T1287
Test name
Test status
Simulation time 20282167 ps
CPU time 0.56 seconds
Started Aug 17 04:57:00 PM PDT 24
Finished Aug 17 04:57:01 PM PDT 24
Peak memory 194540 kb
Host smart-4e0f9431-c7a1-4b2c-a0b2-f87e4231ad6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823158122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1823158122
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2219763065
Short name T1209
Test name
Test status
Simulation time 15053047 ps
CPU time 0.63 seconds
Started Aug 17 04:57:01 PM PDT 24
Finished Aug 17 04:57:02 PM PDT 24
Peak memory 194392 kb
Host smart-a82444de-9fcb-4ff7-b827-d311ff5add8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219763065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2219763065
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.163146347
Short name T1227
Test name
Test status
Simulation time 26361265 ps
CPU time 0.57 seconds
Started Aug 17 04:57:00 PM PDT 24
Finished Aug 17 04:57:00 PM PDT 24
Peak memory 194632 kb
Host smart-5bf84311-86fe-407c-bac2-823b7dde3706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163146347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.163146347
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.992738762
Short name T1189
Test name
Test status
Simulation time 42478815 ps
CPU time 0.62 seconds
Started Aug 17 04:56:59 PM PDT 24
Finished Aug 17 04:57:00 PM PDT 24
Peak memory 194512 kb
Host smart-d782e1dc-3e09-4c03-bcd5-424a560a751f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992738762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.992738762
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.683817743
Short name T1244
Test name
Test status
Simulation time 128234479 ps
CPU time 0.77 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 196460 kb
Host smart-d9f88392-bf21-4ba6-a0dd-1ed90a1772b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683817743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.683817743
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.538451540
Short name T64
Test name
Test status
Simulation time 1380573069 ps
CPU time 2.48 seconds
Started Aug 17 04:56:25 PM PDT 24
Finished Aug 17 04:56:27 PM PDT 24
Peak memory 197856 kb
Host smart-e94b181c-43cb-4f26-b929-fcf49ea06444
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538451540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.538451540
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3331401905
Short name T1259
Test name
Test status
Simulation time 20176570 ps
CPU time 0.59 seconds
Started Aug 17 04:56:23 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 195524 kb
Host smart-af6ed3dc-e51d-444e-882a-0aa445278188
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331401905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3331401905
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.891971605
Short name T1275
Test name
Test status
Simulation time 64732064 ps
CPU time 0.67 seconds
Started Aug 17 04:56:24 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 198032 kb
Host smart-1bb8c678-a6f8-46a7-ac63-65702112922c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891971605 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.891971605
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2186565257
Short name T1292
Test name
Test status
Simulation time 16036718 ps
CPU time 0.57 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 195484 kb
Host smart-f138ae58-ce74-4419-9eef-6e5c73e1377b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186565257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2186565257
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1489314058
Short name T1197
Test name
Test status
Simulation time 44008289 ps
CPU time 0.56 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 194580 kb
Host smart-377e4aed-7ec5-4ce9-ad2e-0a2eb859f565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489314058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1489314058
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3397292910
Short name T1294
Test name
Test status
Simulation time 133464495 ps
CPU time 0.73 seconds
Started Aug 17 04:56:25 PM PDT 24
Finished Aug 17 04:56:25 PM PDT 24
Peak memory 197068 kb
Host smart-9e62e8a1-72a6-444f-93f1-c7ccc171a3e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397292910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3397292910
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2778972763
Short name T1220
Test name
Test status
Simulation time 202619745 ps
CPU time 1.28 seconds
Started Aug 17 04:56:23 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 200132 kb
Host smart-11e0c594-17a7-409e-8efa-39de9fea6771
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778972763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2778972763
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3018391136
Short name T84
Test name
Test status
Simulation time 82490957 ps
CPU time 1.22 seconds
Started Aug 17 04:56:24 PM PDT 24
Finished Aug 17 04:56:26 PM PDT 24
Peak memory 199492 kb
Host smart-d3de3d54-a423-454d-888e-555a119e6388
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018391136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3018391136
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3282139393
Short name T1201
Test name
Test status
Simulation time 11276532 ps
CPU time 0.55 seconds
Started Aug 17 04:56:58 PM PDT 24
Finished Aug 17 04:56:59 PM PDT 24
Peak memory 194616 kb
Host smart-bda05b40-0ae2-45ce-a3fa-1feaa9b0c7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282139393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3282139393
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.4102621694
Short name T1191
Test name
Test status
Simulation time 88967882 ps
CPU time 0.55 seconds
Started Aug 17 04:56:59 PM PDT 24
Finished Aug 17 04:56:59 PM PDT 24
Peak memory 194628 kb
Host smart-1e5d4c09-38e4-454f-8633-53e0f59c5730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102621694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4102621694
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2356362777
Short name T1187
Test name
Test status
Simulation time 22642144 ps
CPU time 0.65 seconds
Started Aug 17 04:57:00 PM PDT 24
Finished Aug 17 04:57:01 PM PDT 24
Peak memory 194628 kb
Host smart-1fb8654a-9b1b-4430-a1de-7f8a9e9ab560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356362777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2356362777
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2159109035
Short name T1252
Test name
Test status
Simulation time 36995633 ps
CPU time 0.58 seconds
Started Aug 17 04:56:57 PM PDT 24
Finished Aug 17 04:56:58 PM PDT 24
Peak memory 194572 kb
Host smart-ce992e91-d3ed-4192-afad-ccaa6a6e9c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159109035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2159109035
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.94150795
Short name T1256
Test name
Test status
Simulation time 17844465 ps
CPU time 0.56 seconds
Started Aug 17 04:56:56 PM PDT 24
Finished Aug 17 04:56:57 PM PDT 24
Peak memory 194552 kb
Host smart-8d78fb09-7588-456e-892b-6e1dab8cdd68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94150795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.94150795
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1903012863
Short name T1240
Test name
Test status
Simulation time 16581864 ps
CPU time 0.58 seconds
Started Aug 17 04:56:57 PM PDT 24
Finished Aug 17 04:56:58 PM PDT 24
Peak memory 194536 kb
Host smart-5b4edb73-4a8e-4f68-ad9b-75451fab591a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903012863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1903012863
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.867137200
Short name T1221
Test name
Test status
Simulation time 14049304 ps
CPU time 0.65 seconds
Started Aug 17 04:57:01 PM PDT 24
Finished Aug 17 04:57:01 PM PDT 24
Peak memory 194600 kb
Host smart-17886487-946b-49ed-9476-c3fc40685be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867137200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.867137200
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2918119409
Short name T1184
Test name
Test status
Simulation time 20592200 ps
CPU time 0.61 seconds
Started Aug 17 04:56:57 PM PDT 24
Finished Aug 17 04:56:58 PM PDT 24
Peak memory 194536 kb
Host smart-b681aedd-1545-4e14-ac24-856f17c5a58c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918119409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2918119409
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.703649890
Short name T1280
Test name
Test status
Simulation time 11460910 ps
CPU time 0.6 seconds
Started Aug 17 04:57:00 PM PDT 24
Finished Aug 17 04:57:00 PM PDT 24
Peak memory 194624 kb
Host smart-0c959ce3-0769-4b79-b6b3-7e978d650196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703649890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.703649890
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1279654910
Short name T1281
Test name
Test status
Simulation time 26254742 ps
CPU time 0.58 seconds
Started Aug 17 04:56:58 PM PDT 24
Finished Aug 17 04:56:58 PM PDT 24
Peak memory 194508 kb
Host smart-bb48c92f-9e43-464b-a236-46673195c886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279654910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1279654910
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.846830213
Short name T58
Test name
Test status
Simulation time 29169448 ps
CPU time 0.77 seconds
Started Aug 17 04:56:23 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 196312 kb
Host smart-b54c71d0-1cec-4573-8b96-5a1cc7ea90a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846830213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.846830213
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.685548643
Short name T1261
Test name
Test status
Simulation time 693286814 ps
CPU time 2.36 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:25 PM PDT 24
Peak memory 197856 kb
Host smart-246f85f6-8a70-4cb5-adf4-a7da7ca29dfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685548643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.685548643
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1591756058
Short name T1262
Test name
Test status
Simulation time 48519845 ps
CPU time 0.58 seconds
Started Aug 17 04:56:23 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 195576 kb
Host smart-0a29eccc-26b3-4495-9b56-b524a1217dd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591756058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1591756058
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.161489387
Short name T1188
Test name
Test status
Simulation time 21777345 ps
CPU time 1.05 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 199984 kb
Host smart-f2d44fc0-0f9f-4ab8-890e-bdfe12be3f54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161489387 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.161489387
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2710580707
Short name T1205
Test name
Test status
Simulation time 16008250 ps
CPU time 0.56 seconds
Started Aug 17 04:56:24 PM PDT 24
Finished Aug 17 04:56:24 PM PDT 24
Peak memory 195544 kb
Host smart-ed7babb1-c96a-4f5f-ba68-c11783ca3ed8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710580707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2710580707
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.586510537
Short name T1231
Test name
Test status
Simulation time 113189200 ps
CPU time 0.55 seconds
Started Aug 17 04:56:27 PM PDT 24
Finished Aug 17 04:56:27 PM PDT 24
Peak memory 194604 kb
Host smart-e2637d42-dbae-407a-bca3-ec59f17517da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586510537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.586510537
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3587139002
Short name T1247
Test name
Test status
Simulation time 27833795 ps
CPU time 0.78 seconds
Started Aug 17 04:56:22 PM PDT 24
Finished Aug 17 04:56:23 PM PDT 24
Peak memory 197200 kb
Host smart-061c6c52-8b63-4c1e-a90e-7a56c6a74236
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587139002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3587139002
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3379343407
Short name T1224
Test name
Test status
Simulation time 63309987 ps
CPU time 1.24 seconds
Started Aug 17 04:56:21 PM PDT 24
Finished Aug 17 04:56:22 PM PDT 24
Peak memory 200128 kb
Host smart-392a2187-f031-4df5-acb3-af75576db437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379343407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3379343407
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2252250300
Short name T79
Test name
Test status
Simulation time 55241088 ps
CPU time 0.9 seconds
Started Aug 17 04:56:26 PM PDT 24
Finished Aug 17 04:56:27 PM PDT 24
Peak memory 199108 kb
Host smart-85539a41-7bce-46bb-95e9-164924ffc8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252250300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2252250300
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1220976878
Short name T1186
Test name
Test status
Simulation time 119233379 ps
CPU time 0.53 seconds
Started Aug 17 04:56:58 PM PDT 24
Finished Aug 17 04:56:59 PM PDT 24
Peak memory 194656 kb
Host smart-5dcd5620-cc62-4e28-8f31-a0ea11b61557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220976878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1220976878
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3880867407
Short name T1299
Test name
Test status
Simulation time 86393309 ps
CPU time 0.6 seconds
Started Aug 17 04:56:59 PM PDT 24
Finished Aug 17 04:57:00 PM PDT 24
Peak memory 194612 kb
Host smart-181630af-dfad-4348-b05f-a7a32e80c0c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880867407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3880867407
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2156501979
Short name T1238
Test name
Test status
Simulation time 12091721 ps
CPU time 0.57 seconds
Started Aug 17 04:57:01 PM PDT 24
Finished Aug 17 04:57:01 PM PDT 24
Peak memory 194552 kb
Host smart-a413e3a5-d657-4c67-b057-c964ad9bcd82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156501979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2156501979
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3687681255
Short name T1233
Test name
Test status
Simulation time 21380333 ps
CPU time 0.56 seconds
Started Aug 17 04:56:57 PM PDT 24
Finished Aug 17 04:56:57 PM PDT 24
Peak memory 194552 kb
Host smart-ea250d07-6c3d-4629-b157-4736a7b024b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687681255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3687681255
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2689401749
Short name T1312
Test name
Test status
Simulation time 13854800 ps
CPU time 0.56 seconds
Started Aug 17 04:56:58 PM PDT 24
Finished Aug 17 04:56:59 PM PDT 24
Peak memory 194624 kb
Host smart-1c42f681-6a9a-45c0-8496-9d8d15ac816f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689401749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2689401749
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3116551106
Short name T1214
Test name
Test status
Simulation time 30499919 ps
CPU time 0.55 seconds
Started Aug 17 04:57:05 PM PDT 24
Finished Aug 17 04:57:06 PM PDT 24
Peak memory 194504 kb
Host smart-f29978d7-9058-40e5-9bb0-c210070d555a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116551106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3116551106
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2680935848
Short name T1300
Test name
Test status
Simulation time 50923252 ps
CPU time 0.58 seconds
Started Aug 17 04:56:59 PM PDT 24
Finished Aug 17 04:57:00 PM PDT 24
Peak memory 194600 kb
Host smart-bc28e999-bbdb-4b7b-bbfa-56e73bb55105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680935848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2680935848
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1317739026
Short name T1295
Test name
Test status
Simulation time 26023594 ps
CPU time 0.63 seconds
Started Aug 17 04:56:59 PM PDT 24
Finished Aug 17 04:57:00 PM PDT 24
Peak memory 194624 kb
Host smart-224bd0a4-f947-4549-b6db-3ecba253c8db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317739026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1317739026
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.665410612
Short name T1246
Test name
Test status
Simulation time 53105622 ps
CPU time 0.59 seconds
Started Aug 17 04:57:00 PM PDT 24
Finished Aug 17 04:57:00 PM PDT 24
Peak memory 194628 kb
Host smart-b53e6425-c47f-4f53-8d69-993a982ef2bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665410612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.665410612
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3915086105
Short name T1234
Test name
Test status
Simulation time 174567288 ps
CPU time 0.6 seconds
Started Aug 17 04:56:58 PM PDT 24
Finished Aug 17 04:56:59 PM PDT 24
Peak memory 194604 kb
Host smart-95ac52c6-eef1-49e3-9757-8e599017a628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915086105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3915086105
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1547390711
Short name T1260
Test name
Test status
Simulation time 21097035 ps
CPU time 1.01 seconds
Started Aug 17 04:56:33 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 200028 kb
Host smart-ac4c03c1-c0e5-43b4-8975-2a9b5fc913da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547390711 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1547390711
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3564045707
Short name T1315
Test name
Test status
Simulation time 13917820 ps
CPU time 0.63 seconds
Started Aug 17 04:56:32 PM PDT 24
Finished Aug 17 04:56:33 PM PDT 24
Peak memory 195540 kb
Host smart-4e07981b-c853-4124-8fa2-18aaf94f26e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564045707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3564045707
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.582491446
Short name T1276
Test name
Test status
Simulation time 17222619 ps
CPU time 0.62 seconds
Started Aug 17 04:56:32 PM PDT 24
Finished Aug 17 04:56:33 PM PDT 24
Peak memory 194604 kb
Host smart-47d05005-897c-4830-b700-c2440020084e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582491446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.582491446
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.283089301
Short name T68
Test name
Test status
Simulation time 18620569 ps
CPU time 0.71 seconds
Started Aug 17 04:56:35 PM PDT 24
Finished Aug 17 04:56:36 PM PDT 24
Peak memory 197020 kb
Host smart-5c702759-b8bc-4d7e-8146-f3d1b0e3ad3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283089301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.283089301
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1812593147
Short name T1226
Test name
Test status
Simulation time 35344608 ps
CPU time 1.5 seconds
Started Aug 17 04:56:24 PM PDT 24
Finished Aug 17 04:56:26 PM PDT 24
Peak memory 200240 kb
Host smart-1499df99-6f7c-473c-8799-63af8ef41f03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812593147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1812593147
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3281281644
Short name T1206
Test name
Test status
Simulation time 20472832 ps
CPU time 0.9 seconds
Started Aug 17 04:56:35 PM PDT 24
Finished Aug 17 04:56:35 PM PDT 24
Peak memory 200068 kb
Host smart-03f74734-6a4c-4a48-8e9f-f71def219abd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281281644 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3281281644
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1334691087
Short name T73
Test name
Test status
Simulation time 25282620 ps
CPU time 0.6 seconds
Started Aug 17 04:56:30 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 195480 kb
Host smart-5e7a702a-edc6-4605-9700-63f02e02a8ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334691087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1334691087
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.14519578
Short name T1193
Test name
Test status
Simulation time 17559770 ps
CPU time 0.6 seconds
Started Aug 17 04:56:33 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 194616 kb
Host smart-3a39ee6f-875b-47c2-a2b3-ae70cb318759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14519578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.14519578
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1038272886
Short name T1290
Test name
Test status
Simulation time 24483413 ps
CPU time 0.66 seconds
Started Aug 17 04:56:34 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 196164 kb
Host smart-042b7b58-7e8a-4bce-90d7-a617f690c6cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038272886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1038272886
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.671066848
Short name T1194
Test name
Test status
Simulation time 134312787 ps
CPU time 2.17 seconds
Started Aug 17 04:56:32 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 200284 kb
Host smart-64795cc5-374d-4605-b0ea-9f73e6ecb13b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671066848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.671066848
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1240803669
Short name T1306
Test name
Test status
Simulation time 196215856 ps
CPU time 0.97 seconds
Started Aug 17 04:56:30 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 199512 kb
Host smart-2c0384cb-b725-4512-b24a-289451210347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240803669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1240803669
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2001421444
Short name T1237
Test name
Test status
Simulation time 21663914 ps
CPU time 0.78 seconds
Started Aug 17 04:56:34 PM PDT 24
Finished Aug 17 04:56:35 PM PDT 24
Peak memory 198556 kb
Host smart-92c19847-d9e3-4213-91b8-623bd4db4c66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001421444 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2001421444
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1766584698
Short name T55
Test name
Test status
Simulation time 15115586 ps
CPU time 0.63 seconds
Started Aug 17 04:56:33 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 195700 kb
Host smart-b2ed44b0-1def-42d6-bb94-f9c229137be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766584698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1766584698
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1529029428
Short name T1242
Test name
Test status
Simulation time 11321298 ps
CPU time 0.56 seconds
Started Aug 17 04:56:33 PM PDT 24
Finished Aug 17 04:56:33 PM PDT 24
Peak memory 194556 kb
Host smart-162ace8b-1a14-4189-8ad5-edf7344e17f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529029428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1529029428
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1200942646
Short name T1303
Test name
Test status
Simulation time 44006159 ps
CPU time 0.66 seconds
Started Aug 17 04:56:36 PM PDT 24
Finished Aug 17 04:56:37 PM PDT 24
Peak memory 195836 kb
Host smart-ec451340-30f1-4139-ac7a-404e37ae60d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200942646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1200942646
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2012501392
Short name T1283
Test name
Test status
Simulation time 489239889 ps
CPU time 1.94 seconds
Started Aug 17 04:56:33 PM PDT 24
Finished Aug 17 04:56:35 PM PDT 24
Peak memory 200156 kb
Host smart-7627b406-d6b0-4ce1-8ddd-895b37764219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012501392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2012501392
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3956534350
Short name T85
Test name
Test status
Simulation time 247384785 ps
CPU time 1.23 seconds
Started Aug 17 04:56:32 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 199364 kb
Host smart-45ebe117-bc94-479c-bea6-059e8e63d178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956534350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3956534350
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1438787895
Short name T1250
Test name
Test status
Simulation time 35045710 ps
CPU time 0.67 seconds
Started Aug 17 04:56:32 PM PDT 24
Finished Aug 17 04:56:33 PM PDT 24
Peak memory 197860 kb
Host smart-c872db0a-8c26-4583-8093-58a5d061bb72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438787895 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1438787895
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3788584174
Short name T65
Test name
Test status
Simulation time 102622871 ps
CPU time 0.58 seconds
Started Aug 17 04:56:30 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 195944 kb
Host smart-f5d512f6-fe07-48f7-bb68-c8250188a31b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788584174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3788584174
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2871589689
Short name T1232
Test name
Test status
Simulation time 96627357 ps
CPU time 0.6 seconds
Started Aug 17 04:56:34 PM PDT 24
Finished Aug 17 04:56:34 PM PDT 24
Peak memory 194640 kb
Host smart-e647cbee-c50b-4420-b83b-553641b4f8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871589689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2871589689
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3031248892
Short name T1309
Test name
Test status
Simulation time 59416384 ps
CPU time 0.63 seconds
Started Aug 17 04:56:30 PM PDT 24
Finished Aug 17 04:56:31 PM PDT 24
Peak memory 195860 kb
Host smart-09654eea-58d2-40ad-8dc3-1501df7158d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031248892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3031248892
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3236406631
Short name T1304
Test name
Test status
Simulation time 74979066 ps
CPU time 1.08 seconds
Started Aug 17 04:56:31 PM PDT 24
Finished Aug 17 04:56:32 PM PDT 24
Peak memory 199992 kb
Host smart-834f4885-2dad-446d-8f62-b98545409e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236406631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3236406631
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2357883967
Short name T1195
Test name
Test status
Simulation time 58661405 ps
CPU time 0.96 seconds
Started Aug 17 04:56:40 PM PDT 24
Finished Aug 17 04:56:41 PM PDT 24
Peak memory 199936 kb
Host smart-7bfced1a-db0b-451b-9401-098195d7f477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357883967 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2357883967
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3769915699
Short name T1190
Test name
Test status
Simulation time 67019692 ps
CPU time 0.59 seconds
Started Aug 17 04:56:47 PM PDT 24
Finished Aug 17 04:56:48 PM PDT 24
Peak memory 195640 kb
Host smart-bb0cbba2-4abe-4b63-a284-eb8347b0d0f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769915699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3769915699
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.4272626802
Short name T1245
Test name
Test status
Simulation time 16589157 ps
CPU time 0.58 seconds
Started Aug 17 04:56:34 PM PDT 24
Finished Aug 17 04:56:35 PM PDT 24
Peak memory 194528 kb
Host smart-085af9e6-2c3d-4c77-9916-ef4c8e551f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272626802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.4272626802
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1185845709
Short name T1223
Test name
Test status
Simulation time 22676962 ps
CPU time 0.7 seconds
Started Aug 17 04:56:37 PM PDT 24
Finished Aug 17 04:56:38 PM PDT 24
Peak memory 195636 kb
Host smart-ac2c9c7f-8f74-4a36-8981-d203d15da3b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185845709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1185845709
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3785676400
Short name T1203
Test name
Test status
Simulation time 92377666 ps
CPU time 1.88 seconds
Started Aug 17 04:56:30 PM PDT 24
Finished Aug 17 04:56:32 PM PDT 24
Peak memory 200192 kb
Host smart-deaa5f08-ef2c-4ad2-98d3-0c3bc359f229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785676400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3785676400
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3210492542
Short name T88
Test name
Test status
Simulation time 401760681 ps
CPU time 1.4 seconds
Started Aug 17 04:56:31 PM PDT 24
Finished Aug 17 04:56:33 PM PDT 24
Peak memory 199600 kb
Host smart-19c34538-61dc-4cd6-84c7-0dc939ea9551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210492542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3210492542
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3634424522
Short name T774
Test name
Test status
Simulation time 15986028 ps
CPU time 0.57 seconds
Started Aug 17 05:09:35 PM PDT 24
Finished Aug 17 05:09:35 PM PDT 24
Peak memory 196460 kb
Host smart-c89d9886-db33-4834-b4c0-497d554103ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634424522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3634424522
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.819999469
Short name T166
Test name
Test status
Simulation time 23639055868 ps
CPU time 9.54 seconds
Started Aug 17 05:09:24 PM PDT 24
Finished Aug 17 05:09:33 PM PDT 24
Peak memory 200880 kb
Host smart-e7dc53fe-bb42-4ca4-844e-922fb9ce1f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819999469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.819999469
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2191842542
Short name T285
Test name
Test status
Simulation time 68637354707 ps
CPU time 106.85 seconds
Started Aug 17 05:09:24 PM PDT 24
Finished Aug 17 05:11:11 PM PDT 24
Peak memory 200920 kb
Host smart-034ff766-2a5e-4067-9b24-f19167b80ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191842542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2191842542
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.554964664
Short name T383
Test name
Test status
Simulation time 14938197173 ps
CPU time 22.56 seconds
Started Aug 17 05:09:23 PM PDT 24
Finished Aug 17 05:09:46 PM PDT 24
Peak memory 200920 kb
Host smart-7c1cecb1-92d7-4f75-ae97-a60faf37618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554964664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.554964664
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3280898756
Short name T777
Test name
Test status
Simulation time 41248249449 ps
CPU time 68.41 seconds
Started Aug 17 05:09:25 PM PDT 24
Finished Aug 17 05:10:33 PM PDT 24
Peak memory 200880 kb
Host smart-5be0fc34-17e4-46b9-a4de-5ea438f46510
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280898756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3280898756
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.262521057
Short name T1084
Test name
Test status
Simulation time 161807587098 ps
CPU time 260.04 seconds
Started Aug 17 05:09:36 PM PDT 24
Finished Aug 17 05:13:57 PM PDT 24
Peak memory 200948 kb
Host smart-61a1c3b1-835a-4da1-bb6b-11bcf0406c1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262521057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.262521057
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.359399135
Short name T728
Test name
Test status
Simulation time 10803916253 ps
CPU time 9.38 seconds
Started Aug 17 05:09:32 PM PDT 24
Finished Aug 17 05:09:41 PM PDT 24
Peak memory 200228 kb
Host smart-126db810-f4a6-4145-ab04-549fbd483546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359399135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.359399135
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.31179154
Short name T50
Test name
Test status
Simulation time 33777888314 ps
CPU time 25.15 seconds
Started Aug 17 05:09:24 PM PDT 24
Finished Aug 17 05:09:50 PM PDT 24
Peak memory 200656 kb
Host smart-dc398563-6702-4b56-b430-76f6f9cf4235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31179154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.31179154
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.4176480340
Short name T571
Test name
Test status
Simulation time 5888661771 ps
CPU time 58.19 seconds
Started Aug 17 05:09:33 PM PDT 24
Finished Aug 17 05:10:32 PM PDT 24
Peak memory 200816 kb
Host smart-3a246a15-a612-4131-ab80-3f966e405727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176480340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4176480340
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.222230950
Short name T755
Test name
Test status
Simulation time 6241303141 ps
CPU time 27 seconds
Started Aug 17 05:09:24 PM PDT 24
Finished Aug 17 05:09:51 PM PDT 24
Peak memory 199784 kb
Host smart-abbf1c1e-7fe0-4c7f-a829-fef3c044e006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222230950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.222230950
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2001997962
Short name T975
Test name
Test status
Simulation time 91968843435 ps
CPU time 127.33 seconds
Started Aug 17 05:09:35 PM PDT 24
Finished Aug 17 05:11:43 PM PDT 24
Peak memory 200924 kb
Host smart-ba8075b5-18f3-40c2-9fdb-e496cea07ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001997962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2001997962
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4269178014
Short name T473
Test name
Test status
Simulation time 3741474371 ps
CPU time 1.45 seconds
Started Aug 17 05:09:32 PM PDT 24
Finished Aug 17 05:09:34 PM PDT 24
Peak memory 197124 kb
Host smart-a6d4ce35-f7e5-46a5-8198-631b5c86a56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269178014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4269178014
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3930652319
Short name T28
Test name
Test status
Simulation time 183954487 ps
CPU time 0.86 seconds
Started Aug 17 05:09:32 PM PDT 24
Finished Aug 17 05:09:33 PM PDT 24
Peak memory 219140 kb
Host smart-b12ac241-5595-4056-a0d0-ce026fccf771
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930652319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3930652319
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1238563393
Short name T802
Test name
Test status
Simulation time 6067432498 ps
CPU time 10.03 seconds
Started Aug 17 05:09:27 PM PDT 24
Finished Aug 17 05:09:37 PM PDT 24
Peak memory 200696 kb
Host smart-53bb711f-a15c-4419-8ec1-010decbbef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238563393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1238563393
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.4079542833
Short name T805
Test name
Test status
Simulation time 64741862252 ps
CPU time 109.99 seconds
Started Aug 17 05:09:35 PM PDT 24
Finished Aug 17 05:11:25 PM PDT 24
Peak memory 200880 kb
Host smart-302280e2-0650-4e58-aa51-824f8cb505df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079542833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.4079542833
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1839713442
Short name T845
Test name
Test status
Simulation time 160375167 ps
CPU time 3.51 seconds
Started Aug 17 05:09:34 PM PDT 24
Finished Aug 17 05:09:38 PM PDT 24
Peak memory 200912 kb
Host smart-6ee9e8b5-13a6-407e-a1d8-8b2e6a7e2743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839713442 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1839713442
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2697774002
Short name T752
Test name
Test status
Simulation time 6183428906 ps
CPU time 13.95 seconds
Started Aug 17 05:09:32 PM PDT 24
Finished Aug 17 05:09:46 PM PDT 24
Peak memory 200856 kb
Host smart-4b096b90-c541-4504-8baf-a9d342b45603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697774002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2697774002
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1100274444
Short name T703
Test name
Test status
Simulation time 15120899774 ps
CPU time 7.26 seconds
Started Aug 17 05:09:25 PM PDT 24
Finished Aug 17 05:09:32 PM PDT 24
Peak memory 199104 kb
Host smart-dd735118-78c7-4a6e-90f4-21eb0cfdf7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100274444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1100274444
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1901509344
Short name T874
Test name
Test status
Simulation time 22618843 ps
CPU time 0.57 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:09:40 PM PDT 24
Peak memory 195500 kb
Host smart-8f9a7f00-8e6d-4063-b3f6-de7b761ca71e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901509344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1901509344
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2425450790
Short name T515
Test name
Test status
Simulation time 147258062329 ps
CPU time 70.1 seconds
Started Aug 17 05:09:35 PM PDT 24
Finished Aug 17 05:10:45 PM PDT 24
Peak memory 200876 kb
Host smart-8987285f-817e-444d-b404-3da1d740d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425450790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2425450790
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1469629701
Short name T899
Test name
Test status
Simulation time 111275181996 ps
CPU time 132.7 seconds
Started Aug 17 05:09:32 PM PDT 24
Finished Aug 17 05:11:44 PM PDT 24
Peak memory 200852 kb
Host smart-ed3d8953-1165-4c58-b08b-e932adb69835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469629701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1469629701
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.30481306
Short name T878
Test name
Test status
Simulation time 28589455966 ps
CPU time 53.22 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:10:32 PM PDT 24
Peak memory 200808 kb
Host smart-f5d8e596-72fd-473f-8f98-b7fd3836755a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30481306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.30481306
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2023252743
Short name T439
Test name
Test status
Simulation time 70075464547 ps
CPU time 536.53 seconds
Started Aug 17 05:09:35 PM PDT 24
Finished Aug 17 05:18:32 PM PDT 24
Peak memory 200864 kb
Host smart-1aa32bf3-0e48-4da1-b384-bb9656144632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023252743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2023252743
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3990316695
Short name T456
Test name
Test status
Simulation time 2504214516 ps
CPU time 6.79 seconds
Started Aug 17 05:09:32 PM PDT 24
Finished Aug 17 05:09:39 PM PDT 24
Peak memory 200840 kb
Host smart-a3c05e6b-6c90-4f59-8f38-28a7ed257ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990316695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3990316695
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2924717774
Short name T965
Test name
Test status
Simulation time 112357294393 ps
CPU time 50.88 seconds
Started Aug 17 05:09:31 PM PDT 24
Finished Aug 17 05:10:22 PM PDT 24
Peak memory 200628 kb
Host smart-3d96f194-c64c-490d-aed4-baeb40b8b5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924717774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2924717774
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.66007088
Short name T41
Test name
Test status
Simulation time 16195933101 ps
CPU time 183.53 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:12:42 PM PDT 24
Peak memory 200852 kb
Host smart-63f71e95-edda-4e9c-a5cc-8fa8a2698f51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66007088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.66007088
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3573044206
Short name T1108
Test name
Test status
Simulation time 3399060730 ps
CPU time 14.85 seconds
Started Aug 17 05:09:35 PM PDT 24
Finished Aug 17 05:09:50 PM PDT 24
Peak memory 199080 kb
Host smart-346923e1-19a9-4628-a9fe-0e278aaa8267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573044206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3573044206
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.588154195
Short name T1035
Test name
Test status
Simulation time 171245013557 ps
CPU time 135.88 seconds
Started Aug 17 05:09:33 PM PDT 24
Finished Aug 17 05:11:49 PM PDT 24
Peak memory 200872 kb
Host smart-2b8b675b-b892-40f7-9e9d-6b4d63473083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588154195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.588154195
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2187938623
Short name T909
Test name
Test status
Simulation time 43496553481 ps
CPU time 4.11 seconds
Started Aug 17 05:09:30 PM PDT 24
Finished Aug 17 05:09:34 PM PDT 24
Peak memory 197260 kb
Host smart-220bbaa6-8fa2-47b1-b575-b2e9682e8086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187938623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2187938623
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.630447531
Short name T29
Test name
Test status
Simulation time 92698774 ps
CPU time 0.79 seconds
Started Aug 17 05:09:33 PM PDT 24
Finished Aug 17 05:09:33 PM PDT 24
Peak memory 219144 kb
Host smart-a177b10c-4330-4ad9-929c-9b97c63cf180
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630447531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.630447531
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.674625228
Short name T8
Test name
Test status
Simulation time 672650587 ps
CPU time 1.46 seconds
Started Aug 17 05:09:37 PM PDT 24
Finished Aug 17 05:09:38 PM PDT 24
Peak memory 199636 kb
Host smart-22d4f6bf-13ac-4104-b987-12b295533eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674625228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.674625228
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2730295542
Short name T543
Test name
Test status
Simulation time 1259582002 ps
CPU time 8.97 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:09:48 PM PDT 24
Peak memory 200864 kb
Host smart-8f3ea316-6f3f-48be-b11f-707c479a5ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730295542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2730295542
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3581577444
Short name T635
Test name
Test status
Simulation time 1897409998 ps
CPU time 2.48 seconds
Started Aug 17 05:09:34 PM PDT 24
Finished Aug 17 05:09:37 PM PDT 24
Peak memory 199952 kb
Host smart-5a6e6ff4-c4fc-4c6f-96c5-c7ed751281f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581577444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3581577444
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.413517763
Short name T971
Test name
Test status
Simulation time 40857252812 ps
CPU time 32.67 seconds
Started Aug 17 05:09:32 PM PDT 24
Finished Aug 17 05:10:05 PM PDT 24
Peak memory 200948 kb
Host smart-1531c31d-fd2f-49bc-a81b-fa5ca3d07656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413517763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.413517763
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1214267575
Short name T347
Test name
Test status
Simulation time 125439387840 ps
CPU time 93.64 seconds
Started Aug 17 05:10:43 PM PDT 24
Finished Aug 17 05:12:17 PM PDT 24
Peak memory 200904 kb
Host smart-3691745e-e913-42eb-9a20-fcfe3f5cb9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214267575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1214267575
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3160209814
Short name T211
Test name
Test status
Simulation time 61672480233 ps
CPU time 93.5 seconds
Started Aug 17 05:10:45 PM PDT 24
Finished Aug 17 05:12:18 PM PDT 24
Peak memory 200904 kb
Host smart-45ca4189-a5e0-4668-a892-f02698af5129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160209814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3160209814
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2057943690
Short name T625
Test name
Test status
Simulation time 139244940928 ps
CPU time 181.55 seconds
Started Aug 17 05:10:52 PM PDT 24
Finished Aug 17 05:13:54 PM PDT 24
Peak memory 200864 kb
Host smart-cc3b25fc-fa09-439e-bcab-b7fef9c8561e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057943690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2057943690
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.4247195878
Short name T1079
Test name
Test status
Simulation time 9941118249 ps
CPU time 8.19 seconds
Started Aug 17 05:10:52 PM PDT 24
Finished Aug 17 05:11:00 PM PDT 24
Peak memory 200648 kb
Host smart-97478bbd-b754-4c32-856c-5f5b2a0011f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247195878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4247195878
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3284769822
Short name T305
Test name
Test status
Simulation time 22385241575 ps
CPU time 9.12 seconds
Started Aug 17 05:10:52 PM PDT 24
Finished Aug 17 05:11:01 PM PDT 24
Peak memory 195564 kb
Host smart-7840bdef-cfd1-406b-a41a-d1213f42e62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284769822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3284769822
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.616175143
Short name T380
Test name
Test status
Simulation time 11108823879 ps
CPU time 414.16 seconds
Started Aug 17 05:10:52 PM PDT 24
Finished Aug 17 05:17:46 PM PDT 24
Peak memory 200940 kb
Host smart-257ff67d-e40f-422c-b91a-00d4e3abea30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616175143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.616175143
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.623273748
Short name T985
Test name
Test status
Simulation time 4017175557 ps
CPU time 29.93 seconds
Started Aug 17 05:10:45 PM PDT 24
Finished Aug 17 05:11:15 PM PDT 24
Peak memory 198884 kb
Host smart-1ddc7270-b790-4bdf-98e6-9715e3171b4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623273748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.623273748
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1901370167
Short name T1087
Test name
Test status
Simulation time 44149951197 ps
CPU time 42.27 seconds
Started Aug 17 05:10:51 PM PDT 24
Finished Aug 17 05:11:33 PM PDT 24
Peak memory 200672 kb
Host smart-7be4af72-13a9-4151-bb60-8db73d933471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901370167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1901370167
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2863415740
Short name T390
Test name
Test status
Simulation time 481159409 ps
CPU time 1.06 seconds
Started Aug 17 05:10:51 PM PDT 24
Finished Aug 17 05:10:52 PM PDT 24
Peak memory 196472 kb
Host smart-3bdb2824-81ee-423d-9d5a-6b6b660605ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863415740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2863415740
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1556589093
Short name T394
Test name
Test status
Simulation time 645608015 ps
CPU time 3.67 seconds
Started Aug 17 05:10:45 PM PDT 24
Finished Aug 17 05:10:49 PM PDT 24
Peak memory 199116 kb
Host smart-ad8a3cec-dd49-4dd1-8c75-d5b93057bd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556589093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1556589093
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2446665546
Short name T891
Test name
Test status
Simulation time 56039718721 ps
CPU time 41.6 seconds
Started Aug 17 05:11:00 PM PDT 24
Finished Aug 17 05:11:42 PM PDT 24
Peak memory 200944 kb
Host smart-b2b65b28-90f7-4d5f-8132-4aa2f80051c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446665546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2446665546
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2873735332
Short name T124
Test name
Test status
Simulation time 1841860590 ps
CPU time 58.28 seconds
Started Aug 17 05:10:59 PM PDT 24
Finished Aug 17 05:11:57 PM PDT 24
Peak memory 201152 kb
Host smart-478dd2b7-7a4c-4374-9a8b-8c9a9ad48a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873735332 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2873735332
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.192291368
Short name T546
Test name
Test status
Simulation time 13791724628 ps
CPU time 5.3 seconds
Started Aug 17 05:10:51 PM PDT 24
Finished Aug 17 05:10:57 PM PDT 24
Peak memory 200908 kb
Host smart-a5a68047-c4a0-4267-a2d2-11055a0317b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192291368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.192291368
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.534514388
Short name T330
Test name
Test status
Simulation time 19690215175 ps
CPU time 37.46 seconds
Started Aug 17 05:10:46 PM PDT 24
Finished Aug 17 05:11:24 PM PDT 24
Peak memory 200972 kb
Host smart-d4f0d5bd-2532-4242-87c3-19bb0245fed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534514388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.534514388
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.783935601
Short name T787
Test name
Test status
Simulation time 267090031643 ps
CPU time 210.38 seconds
Started Aug 17 05:22:51 PM PDT 24
Finished Aug 17 05:26:21 PM PDT 24
Peak memory 200892 kb
Host smart-fc7485d6-47ce-4a4c-a1ea-78cf3d9c2e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783935601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.783935601
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3865473520
Short name T322
Test name
Test status
Simulation time 289692983017 ps
CPU time 110.34 seconds
Started Aug 17 05:22:51 PM PDT 24
Finished Aug 17 05:24:41 PM PDT 24
Peak memory 200924 kb
Host smart-acbaa12e-6777-4a9a-a7a2-ada6748565cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865473520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3865473520
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3029225817
Short name T1181
Test name
Test status
Simulation time 19201063786 ps
CPU time 33.24 seconds
Started Aug 17 05:22:53 PM PDT 24
Finished Aug 17 05:23:26 PM PDT 24
Peak memory 200880 kb
Host smart-68a865cf-5888-44da-b6a2-6bedbd0c965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029225817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3029225817
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2862858617
Short name T692
Test name
Test status
Simulation time 21248226121 ps
CPU time 50.36 seconds
Started Aug 17 05:22:52 PM PDT 24
Finished Aug 17 05:23:43 PM PDT 24
Peak memory 200920 kb
Host smart-568da895-d336-4898-aefa-903136f5adfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862858617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2862858617
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3815519175
Short name T1075
Test name
Test status
Simulation time 19688479471 ps
CPU time 35.11 seconds
Started Aug 17 05:22:52 PM PDT 24
Finished Aug 17 05:23:27 PM PDT 24
Peak memory 200940 kb
Host smart-3b7adf07-f9ac-4974-9f56-8a47f5f024ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815519175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3815519175
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.941480169
Short name T958
Test name
Test status
Simulation time 28003193591 ps
CPU time 45.96 seconds
Started Aug 17 05:22:51 PM PDT 24
Finished Aug 17 05:23:37 PM PDT 24
Peak memory 200956 kb
Host smart-b6a17133-8bbf-4e55-9817-3c3ebc455fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941480169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.941480169
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.614250147
Short name T762
Test name
Test status
Simulation time 98414108017 ps
CPU time 53.86 seconds
Started Aug 17 05:22:53 PM PDT 24
Finished Aug 17 05:23:47 PM PDT 24
Peak memory 200956 kb
Host smart-45ac7368-3e47-4796-a2d5-27d08e8b9ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614250147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.614250147
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3262554765
Short name T554
Test name
Test status
Simulation time 19816310 ps
CPU time 0.58 seconds
Started Aug 17 05:11:08 PM PDT 24
Finished Aug 17 05:11:09 PM PDT 24
Peak memory 196232 kb
Host smart-58b3a300-8bc3-4a03-b86c-26cbe8abe64b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262554765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3262554765
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.748574948
Short name T496
Test name
Test status
Simulation time 85356721818 ps
CPU time 46.14 seconds
Started Aug 17 05:11:00 PM PDT 24
Finished Aug 17 05:11:47 PM PDT 24
Peak memory 200884 kb
Host smart-c6e8919c-b4a5-466b-8621-177ae1076fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748574948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.748574948
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.34984812
Short name T141
Test name
Test status
Simulation time 5978394329 ps
CPU time 9.15 seconds
Started Aug 17 05:11:02 PM PDT 24
Finished Aug 17 05:11:11 PM PDT 24
Peak memory 198816 kb
Host smart-9ec5cb44-2124-4bde-be85-c29ec7a0ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34984812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.34984812
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.2588360990
Short name T1008
Test name
Test status
Simulation time 27574370124 ps
CPU time 45.09 seconds
Started Aug 17 05:11:02 PM PDT 24
Finished Aug 17 05:11:47 PM PDT 24
Peak memory 200896 kb
Host smart-01225865-e27c-42d0-8682-427200164c5d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588360990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2588360990
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4262656879
Short name T1095
Test name
Test status
Simulation time 86283486620 ps
CPU time 187.98 seconds
Started Aug 17 05:11:07 PM PDT 24
Finished Aug 17 05:14:15 PM PDT 24
Peak memory 200788 kb
Host smart-88751272-5622-4e1b-82e8-8166db70553d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262656879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4262656879
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2289242358
Short name T812
Test name
Test status
Simulation time 2448905058 ps
CPU time 1.8 seconds
Started Aug 17 05:11:08 PM PDT 24
Finished Aug 17 05:11:10 PM PDT 24
Peak memory 198168 kb
Host smart-3e374674-8620-4e06-854b-c33c662e0252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289242358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2289242358
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.786482954
Short name T351
Test name
Test status
Simulation time 7885471076 ps
CPU time 11.82 seconds
Started Aug 17 05:10:58 PM PDT 24
Finished Aug 17 05:11:10 PM PDT 24
Peak memory 197580 kb
Host smart-930affd7-1754-4f4a-80c0-4b917912078e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786482954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.786482954
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1762438717
Short name T547
Test name
Test status
Simulation time 14747835516 ps
CPU time 852.23 seconds
Started Aug 17 05:11:08 PM PDT 24
Finished Aug 17 05:25:21 PM PDT 24
Peak memory 200956 kb
Host smart-a3152d39-1c04-48d2-857b-5f94a6786bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762438717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1762438717
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2826146452
Short name T478
Test name
Test status
Simulation time 3773834215 ps
CPU time 7.91 seconds
Started Aug 17 05:10:59 PM PDT 24
Finished Aug 17 05:11:07 PM PDT 24
Peak memory 199412 kb
Host smart-d442f2d5-3ac2-41a4-9c48-835de1f728a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826146452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2826146452
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1246921237
Short name T853
Test name
Test status
Simulation time 168807932536 ps
CPU time 140.47 seconds
Started Aug 17 05:11:01 PM PDT 24
Finished Aug 17 05:13:22 PM PDT 24
Peak memory 200980 kb
Host smart-f2fe1342-dc95-4c2b-bf23-3f275331ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246921237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1246921237
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2365663907
Short name T541
Test name
Test status
Simulation time 4682119294 ps
CPU time 2.23 seconds
Started Aug 17 05:10:57 PM PDT 24
Finished Aug 17 05:11:00 PM PDT 24
Peak memory 197052 kb
Host smart-691084c1-c312-4b6c-b6b5-cbdd880b3c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365663907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2365663907
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3878698317
Short name T784
Test name
Test status
Simulation time 712092127 ps
CPU time 2.67 seconds
Started Aug 17 05:10:57 PM PDT 24
Finished Aug 17 05:11:00 PM PDT 24
Peak memory 199544 kb
Host smart-782b6bbb-bd9b-436d-82d4-a92c756042b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878698317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3878698317
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.640945094
Short name T939
Test name
Test status
Simulation time 172432833349 ps
CPU time 709.67 seconds
Started Aug 17 05:11:08 PM PDT 24
Finished Aug 17 05:22:57 PM PDT 24
Peak memory 209304 kb
Host smart-01fc38bb-6b67-4f73-ba21-1a68c4556596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640945094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.640945094
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3779938418
Short name T576
Test name
Test status
Simulation time 5236357730 ps
CPU time 84.08 seconds
Started Aug 17 05:11:08 PM PDT 24
Finished Aug 17 05:12:32 PM PDT 24
Peak memory 217392 kb
Host smart-122a46df-bb83-4a60-aa8e-761da9ffc674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779938418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3779938418
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1601226883
Short name T503
Test name
Test status
Simulation time 7145533779 ps
CPU time 14.27 seconds
Started Aug 17 05:11:08 PM PDT 24
Finished Aug 17 05:11:22 PM PDT 24
Peak memory 200916 kb
Host smart-cf9d4137-6624-44a6-8a58-dcda42f9e749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601226883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1601226883
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3475291150
Short name T1151
Test name
Test status
Simulation time 28531998046 ps
CPU time 23.51 seconds
Started Aug 17 05:11:00 PM PDT 24
Finished Aug 17 05:11:24 PM PDT 24
Peak memory 200880 kb
Host smart-424e2721-1a16-448f-9721-4394a8897dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475291150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3475291150
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.658899963
Short name T601
Test name
Test status
Simulation time 64727248113 ps
CPU time 109.51 seconds
Started Aug 17 05:22:51 PM PDT 24
Finished Aug 17 05:24:40 PM PDT 24
Peak memory 200936 kb
Host smart-0f76f28d-af39-4a7a-9818-c63dd4cd6ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658899963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.658899963
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3038837814
Short name T824
Test name
Test status
Simulation time 10397970201 ps
CPU time 16.86 seconds
Started Aug 17 05:23:08 PM PDT 24
Finished Aug 17 05:23:25 PM PDT 24
Peak memory 200732 kb
Host smart-7cab6f96-38ca-4529-849d-289d17881511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038837814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3038837814
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4142573763
Short name T517
Test name
Test status
Simulation time 58246493372 ps
CPU time 48.62 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:23:56 PM PDT 24
Peak memory 200820 kb
Host smart-91530280-1c33-48e6-b3de-d8af78a18cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142573763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4142573763
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.377835660
Short name T153
Test name
Test status
Simulation time 15011185722 ps
CPU time 30.54 seconds
Started Aug 17 05:23:09 PM PDT 24
Finished Aug 17 05:23:40 PM PDT 24
Peak memory 200920 kb
Host smart-86340c4b-5863-4867-920d-e707473c909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377835660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.377835660
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3892491690
Short name T672
Test name
Test status
Simulation time 20993244257 ps
CPU time 16.7 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:23:24 PM PDT 24
Peak memory 200696 kb
Host smart-96e32506-2189-4e44-8e48-038cf7c70bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892491690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3892491690
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2709861902
Short name T887
Test name
Test status
Simulation time 219335402580 ps
CPU time 165.94 seconds
Started Aug 17 05:23:08 PM PDT 24
Finished Aug 17 05:25:54 PM PDT 24
Peak memory 200940 kb
Host smart-a4b0c350-998b-49fd-a067-9c287f7f87f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709861902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2709861902
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1839805239
Short name T214
Test name
Test status
Simulation time 64993453061 ps
CPU time 35.64 seconds
Started Aug 17 05:23:06 PM PDT 24
Finished Aug 17 05:23:42 PM PDT 24
Peak memory 200936 kb
Host smart-b1d13a4b-4a4f-49c3-9f5e-ff64e4ee1801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839805239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1839805239
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1537411912
Short name T539
Test name
Test status
Simulation time 97151578160 ps
CPU time 26.94 seconds
Started Aug 17 05:23:06 PM PDT 24
Finished Aug 17 05:23:33 PM PDT 24
Peak memory 200932 kb
Host smart-c7f8b279-56fb-4ccf-ab29-40028ae837ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537411912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1537411912
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2203526366
Short name T1004
Test name
Test status
Simulation time 20160124 ps
CPU time 0.55 seconds
Started Aug 17 05:11:33 PM PDT 24
Finished Aug 17 05:11:34 PM PDT 24
Peak memory 196256 kb
Host smart-4d11ebc1-5467-431b-bd51-7b9138825c40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203526366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2203526366
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3438057136
Short name T516
Test name
Test status
Simulation time 16628612707 ps
CPU time 21.31 seconds
Started Aug 17 05:11:19 PM PDT 24
Finished Aug 17 05:11:40 PM PDT 24
Peak memory 200960 kb
Host smart-014c150c-a3e6-4744-b814-4c8c5122b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438057136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3438057136
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2850071732
Short name T792
Test name
Test status
Simulation time 52423750274 ps
CPU time 20.47 seconds
Started Aug 17 05:11:21 PM PDT 24
Finished Aug 17 05:11:41 PM PDT 24
Peak memory 200856 kb
Host smart-2c4263c3-a523-4ce3-8b76-fb331e0cfea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850071732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2850071732
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1149080237
Short name T263
Test name
Test status
Simulation time 144458590437 ps
CPU time 17.58 seconds
Started Aug 17 05:11:18 PM PDT 24
Finished Aug 17 05:11:36 PM PDT 24
Peak memory 200876 kb
Host smart-dc10a047-536f-4993-bec9-8d50240dcd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149080237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1149080237
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2488342459
Short name T1060
Test name
Test status
Simulation time 29469237804 ps
CPU time 15.67 seconds
Started Aug 17 05:11:18 PM PDT 24
Finished Aug 17 05:11:34 PM PDT 24
Peak memory 200880 kb
Host smart-0595d53c-05c5-403b-8226-3a2fc33e369f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488342459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2488342459
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2091711041
Short name T476
Test name
Test status
Simulation time 54915236939 ps
CPU time 102.59 seconds
Started Aug 17 05:11:28 PM PDT 24
Finished Aug 17 05:13:11 PM PDT 24
Peak memory 200948 kb
Host smart-aaf84491-69a8-494b-8da7-e443f6677a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091711041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2091711041
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.829957132
Short name T889
Test name
Test status
Simulation time 6853676681 ps
CPU time 4.41 seconds
Started Aug 17 05:11:19 PM PDT 24
Finished Aug 17 05:11:23 PM PDT 24
Peak memory 199724 kb
Host smart-b3f6cb9c-d034-478a-b8a3-e0712b7acc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829957132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.829957132
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2564648072
Short name T970
Test name
Test status
Simulation time 21136060609 ps
CPU time 19.34 seconds
Started Aug 17 05:11:18 PM PDT 24
Finished Aug 17 05:11:37 PM PDT 24
Peak memory 199980 kb
Host smart-36a7c568-3298-42b3-807f-9a0592deb0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564648072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2564648072
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.948438935
Short name T407
Test name
Test status
Simulation time 14185272344 ps
CPU time 831.59 seconds
Started Aug 17 05:11:22 PM PDT 24
Finished Aug 17 05:25:13 PM PDT 24
Peak memory 200844 kb
Host smart-0e619852-7a5d-488d-9e86-03189017d478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948438935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.948438935
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1956774847
Short name T1044
Test name
Test status
Simulation time 3391368629 ps
CPU time 26.64 seconds
Started Aug 17 05:11:19 PM PDT 24
Finished Aug 17 05:11:45 PM PDT 24
Peak memory 199852 kb
Host smart-7a8ac8c7-d7e4-4b75-bec4-c75767623eef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956774847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1956774847
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.643306575
Short name T686
Test name
Test status
Simulation time 173904105953 ps
CPU time 120.88 seconds
Started Aug 17 05:11:18 PM PDT 24
Finished Aug 17 05:13:19 PM PDT 24
Peak memory 200860 kb
Host smart-6694fb74-b954-4e92-b7bd-113fcbc4959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643306575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.643306575
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.300416431
Short name T427
Test name
Test status
Simulation time 34663671801 ps
CPU time 52.09 seconds
Started Aug 17 05:11:17 PM PDT 24
Finished Aug 17 05:12:09 PM PDT 24
Peak memory 196728 kb
Host smart-af86d877-5f6b-4e05-b9ea-b7dec7014937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300416431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.300416431
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1033019494
Short name T447
Test name
Test status
Simulation time 689775049 ps
CPU time 3.64 seconds
Started Aug 17 05:11:08 PM PDT 24
Finished Aug 17 05:11:11 PM PDT 24
Peak memory 200548 kb
Host smart-453574b0-88fc-4542-8086-fd0ae126df8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033019494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1033019494
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3200576423
Short name T715
Test name
Test status
Simulation time 163362688856 ps
CPU time 804.25 seconds
Started Aug 17 05:11:28 PM PDT 24
Finished Aug 17 05:24:52 PM PDT 24
Peak memory 200944 kb
Host smart-fdbf6e68-b68b-4d9d-910b-55b15a70be39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200576423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3200576423
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1309642799
Short name T823
Test name
Test status
Simulation time 12460429066 ps
CPU time 100.23 seconds
Started Aug 17 05:11:27 PM PDT 24
Finished Aug 17 05:13:08 PM PDT 24
Peak memory 216920 kb
Host smart-be6ef146-ae3c-4e3f-ba24-83b4baeff4d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309642799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1309642799
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2721757892
Short name T733
Test name
Test status
Simulation time 1580718172 ps
CPU time 1.71 seconds
Started Aug 17 05:11:21 PM PDT 24
Finished Aug 17 05:11:23 PM PDT 24
Peak memory 200540 kb
Host smart-3d4a08d1-8ca9-45b6-bcad-2f5a8131ca18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721757892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2721757892
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4211143945
Short name T616
Test name
Test status
Simulation time 80001402033 ps
CPU time 127.54 seconds
Started Aug 17 05:11:18 PM PDT 24
Finished Aug 17 05:13:26 PM PDT 24
Peak memory 200908 kb
Host smart-3b528f7a-07c9-4386-872c-6b518d4bd144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211143945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4211143945
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4224352493
Short name T948
Test name
Test status
Simulation time 11282926531 ps
CPU time 16.77 seconds
Started Aug 17 05:23:08 PM PDT 24
Finished Aug 17 05:23:25 PM PDT 24
Peak memory 200896 kb
Host smart-ffd6f43b-7111-4036-90ec-f796922c9985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224352493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4224352493
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1555181836
Short name T735
Test name
Test status
Simulation time 129200030002 ps
CPU time 128.92 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:25:16 PM PDT 24
Peak memory 200920 kb
Host smart-f7c63c45-f308-4d18-960a-0932aa7ffe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555181836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1555181836
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.4011423741
Short name T253
Test name
Test status
Simulation time 106363202388 ps
CPU time 157.32 seconds
Started Aug 17 05:23:08 PM PDT 24
Finished Aug 17 05:25:46 PM PDT 24
Peak memory 200876 kb
Host smart-b0032f78-855e-47d9-95b7-8e740b3d6971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011423741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.4011423741
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3088891100
Short name T580
Test name
Test status
Simulation time 14700993356 ps
CPU time 24.05 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:23:31 PM PDT 24
Peak memory 200956 kb
Host smart-d06cd76e-b147-4c99-a230-ef7a2eaef47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088891100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3088891100
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1019706430
Short name T236
Test name
Test status
Simulation time 32202196615 ps
CPU time 10.41 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:23:18 PM PDT 24
Peak memory 199904 kb
Host smart-6b1093eb-3b7b-4026-8319-06715ae99627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019706430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1019706430
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.927319773
Short name T946
Test name
Test status
Simulation time 79246607659 ps
CPU time 40.31 seconds
Started Aug 17 05:23:08 PM PDT 24
Finished Aug 17 05:23:48 PM PDT 24
Peak memory 200892 kb
Host smart-56d61523-41d0-46f0-8295-b58922fa2bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927319773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.927319773
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1242253971
Short name T418
Test name
Test status
Simulation time 33203418618 ps
CPU time 14.46 seconds
Started Aug 17 05:23:10 PM PDT 24
Finished Aug 17 05:23:25 PM PDT 24
Peak memory 200816 kb
Host smart-b8a3b308-2bfb-4e56-92ea-37ef65b32eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242253971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1242253971
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.131389420
Short name T223
Test name
Test status
Simulation time 129933398615 ps
CPU time 87.92 seconds
Started Aug 17 05:23:09 PM PDT 24
Finished Aug 17 05:24:37 PM PDT 24
Peak memory 200928 kb
Host smart-54180b56-2a59-4a90-9208-1ce5e84a23df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131389420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.131389420
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3068541332
Short name T697
Test name
Test status
Simulation time 14621336 ps
CPU time 0.59 seconds
Started Aug 17 05:11:42 PM PDT 24
Finished Aug 17 05:11:43 PM PDT 24
Peak memory 196516 kb
Host smart-4c440e95-8556-4f00-bf8b-2ff6489e0f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068541332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3068541332
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.805747219
Short name T142
Test name
Test status
Simulation time 31996904277 ps
CPU time 8.92 seconds
Started Aug 17 05:11:26 PM PDT 24
Finished Aug 17 05:11:35 PM PDT 24
Peak memory 201108 kb
Host smart-558c0a46-d2bb-4a42-98ea-3fb5accf351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805747219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.805747219
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1659694491
Short name T495
Test name
Test status
Simulation time 217211644310 ps
CPU time 78.05 seconds
Started Aug 17 05:11:27 PM PDT 24
Finished Aug 17 05:12:45 PM PDT 24
Peak memory 200880 kb
Host smart-7de21808-6586-44ef-9d74-01f9345fb7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659694491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1659694491
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3435899587
Short name T47
Test name
Test status
Simulation time 75721359356 ps
CPU time 110.38 seconds
Started Aug 17 05:11:26 PM PDT 24
Finished Aug 17 05:13:17 PM PDT 24
Peak memory 200956 kb
Host smart-81233eab-3c22-4896-82c5-aca41885dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435899587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3435899587
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3131513159
Short name T119
Test name
Test status
Simulation time 44333352491 ps
CPU time 76.6 seconds
Started Aug 17 05:11:35 PM PDT 24
Finished Aug 17 05:12:52 PM PDT 24
Peak memory 200904 kb
Host smart-8414685a-f8c6-408c-a518-96b0b4985cc2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131513159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3131513159
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1586291989
Short name T657
Test name
Test status
Simulation time 148748573375 ps
CPU time 797.31 seconds
Started Aug 17 05:11:33 PM PDT 24
Finished Aug 17 05:24:51 PM PDT 24
Peak memory 200936 kb
Host smart-afd25b53-e986-48f7-999a-de3ac6191a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586291989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1586291989
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3270926153
Short name T626
Test name
Test status
Simulation time 8417862266 ps
CPU time 6.1 seconds
Started Aug 17 05:11:40 PM PDT 24
Finished Aug 17 05:11:46 PM PDT 24
Peak memory 200720 kb
Host smart-3e18374a-6210-4ab5-9040-ae6357a183f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270926153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3270926153
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1911992121
Short name T280
Test name
Test status
Simulation time 95783427452 ps
CPU time 398.02 seconds
Started Aug 17 05:11:37 PM PDT 24
Finished Aug 17 05:18:15 PM PDT 24
Peak memory 200928 kb
Host smart-307f01ca-a4eb-4c5e-b647-38a2b97a4a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911992121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1911992121
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2357636222
Short name T776
Test name
Test status
Simulation time 8776802173 ps
CPU time 394.58 seconds
Started Aug 17 05:11:41 PM PDT 24
Finished Aug 17 05:18:16 PM PDT 24
Peak memory 200948 kb
Host smart-9668f6e9-ab6d-4876-97b1-f16e1bf51895
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357636222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2357636222
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3095270011
Short name T997
Test name
Test status
Simulation time 6965285860 ps
CPU time 3.79 seconds
Started Aug 17 05:11:29 PM PDT 24
Finished Aug 17 05:11:32 PM PDT 24
Peak memory 200352 kb
Host smart-dbb77e7b-1085-4f2a-8369-a8de7f4f5097
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095270011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3095270011
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3182603444
Short name T151
Test name
Test status
Simulation time 115547053466 ps
CPU time 293.52 seconds
Started Aug 17 05:11:41 PM PDT 24
Finished Aug 17 05:16:35 PM PDT 24
Peak memory 200952 kb
Host smart-cef80870-7b64-498a-a01b-406b93e7e0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182603444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3182603444
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3188578327
Short name T667
Test name
Test status
Simulation time 3213281100 ps
CPU time 3.1 seconds
Started Aug 17 05:11:36 PM PDT 24
Finished Aug 17 05:11:40 PM PDT 24
Peak memory 196980 kb
Host smart-ef602822-c0aa-4b60-b33a-2ace1dbd2f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188578327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3188578327
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1874995288
Short name T754
Test name
Test status
Simulation time 487829740 ps
CPU time 2.75 seconds
Started Aug 17 05:11:27 PM PDT 24
Finished Aug 17 05:11:29 PM PDT 24
Peak memory 200556 kb
Host smart-fd856073-52b4-4104-bd02-6e3a2a1011ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874995288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1874995288
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2845931140
Short name T750
Test name
Test status
Simulation time 19559200369 ps
CPU time 59.67 seconds
Started Aug 17 05:11:35 PM PDT 24
Finished Aug 17 05:12:34 PM PDT 24
Peak memory 212604 kb
Host smart-6d3430b0-e378-4349-86e8-99f3bacc3819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845931140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2845931140
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3600220309
Short name T930
Test name
Test status
Simulation time 1469173977 ps
CPU time 3.95 seconds
Started Aug 17 05:11:34 PM PDT 24
Finished Aug 17 05:11:38 PM PDT 24
Peak memory 200520 kb
Host smart-a8d0e2a7-a290-42a4-b72d-8e5ae0e83503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600220309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3600220309
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2830697697
Short name T399
Test name
Test status
Simulation time 28204550379 ps
CPU time 21.59 seconds
Started Aug 17 05:11:28 PM PDT 24
Finished Aug 17 05:11:50 PM PDT 24
Peak memory 200936 kb
Host smart-04cd490c-3402-4fc6-9df3-bd989116deac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830697697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2830697697
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.347290256
Short name T234
Test name
Test status
Simulation time 182050603757 ps
CPU time 64.86 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:24:12 PM PDT 24
Peak memory 200952 kb
Host smart-ae14d79f-1536-4499-8bb0-486f1646bcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347290256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.347290256
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2045715740
Short name T976
Test name
Test status
Simulation time 39143000456 ps
CPU time 17.19 seconds
Started Aug 17 05:23:08 PM PDT 24
Finished Aug 17 05:23:26 PM PDT 24
Peak memory 200852 kb
Host smart-6c81d6da-88db-44dd-b01e-e2f9e5e7498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045715740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2045715740
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2403981686
Short name T621
Test name
Test status
Simulation time 50433518269 ps
CPU time 20 seconds
Started Aug 17 05:23:10 PM PDT 24
Finished Aug 17 05:23:31 PM PDT 24
Peak memory 200772 kb
Host smart-8c7501bb-979c-4ee3-a993-a8fa8af69a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403981686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2403981686
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3398728475
Short name T131
Test name
Test status
Simulation time 56364636356 ps
CPU time 92.87 seconds
Started Aug 17 05:23:08 PM PDT 24
Finished Aug 17 05:24:41 PM PDT 24
Peak memory 200956 kb
Host smart-d2373308-0cbf-432f-a902-268d3ee32f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398728475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3398728475
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2893317807
Short name T210
Test name
Test status
Simulation time 32722356428 ps
CPU time 53.98 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:24:01 PM PDT 24
Peak memory 200968 kb
Host smart-2350484c-0edd-4b4f-aac5-6761ba494eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893317807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2893317807
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3699148244
Short name T778
Test name
Test status
Simulation time 71372449053 ps
CPU time 59.8 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:24:07 PM PDT 24
Peak memory 200920 kb
Host smart-5278d3f3-d6ca-445a-a2f8-43d11da5850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699148244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3699148244
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.400681378
Short name T512
Test name
Test status
Simulation time 67293219759 ps
CPU time 84.91 seconds
Started Aug 17 05:23:07 PM PDT 24
Finished Aug 17 05:24:32 PM PDT 24
Peak memory 200916 kb
Host smart-2c7ce273-6657-40fa-8f64-1ed3df66705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400681378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.400681378
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3327327120
Short name T599
Test name
Test status
Simulation time 4599832844 ps
CPU time 8.17 seconds
Started Aug 17 05:23:18 PM PDT 24
Finished Aug 17 05:23:26 PM PDT 24
Peak memory 200728 kb
Host smart-2604804b-2aa9-4631-8539-35ace767a940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327327120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3327327120
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1240620045
Short name T753
Test name
Test status
Simulation time 13487804 ps
CPU time 0.56 seconds
Started Aug 17 05:12:06 PM PDT 24
Finished Aug 17 05:12:07 PM PDT 24
Peak memory 195512 kb
Host smart-75df3713-36af-46da-940d-0fb8c17a2a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240620045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1240620045
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1819757071
Short name T164
Test name
Test status
Simulation time 50812520407 ps
CPU time 18.25 seconds
Started Aug 17 05:11:44 PM PDT 24
Finished Aug 17 05:12:02 PM PDT 24
Peak memory 200848 kb
Host smart-d48b5c3e-090a-4e70-a41e-c0979cb2a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819757071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1819757071
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1671958683
Short name T242
Test name
Test status
Simulation time 39410178699 ps
CPU time 9.27 seconds
Started Aug 17 05:11:56 PM PDT 24
Finished Aug 17 05:12:05 PM PDT 24
Peak memory 200908 kb
Host smart-f95d0848-00eb-434f-8805-3dee62e422f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671958683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1671958683
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2286890361
Short name T867
Test name
Test status
Simulation time 387682146082 ps
CPU time 274.38 seconds
Started Aug 17 05:11:57 PM PDT 24
Finished Aug 17 05:16:32 PM PDT 24
Peak memory 200316 kb
Host smart-744a1c3b-1791-43f5-ab59-7570d239a2d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286890361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2286890361
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3700574772
Short name T1173
Test name
Test status
Simulation time 130176385355 ps
CPU time 611.3 seconds
Started Aug 17 05:11:50 PM PDT 24
Finished Aug 17 05:22:02 PM PDT 24
Peak memory 200936 kb
Host smart-8cc2f348-c5fa-4e9e-ae9b-d3ef6e4b5d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3700574772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3700574772
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3201752539
Short name T627
Test name
Test status
Simulation time 2681233816 ps
CPU time 2.36 seconds
Started Aug 17 05:11:50 PM PDT 24
Finished Aug 17 05:11:52 PM PDT 24
Peak memory 199364 kb
Host smart-2bbab525-72fd-4a8a-8ff1-ccac795c281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201752539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3201752539
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3077233383
Short name T386
Test name
Test status
Simulation time 33623065055 ps
CPU time 28.64 seconds
Started Aug 17 05:11:49 PM PDT 24
Finished Aug 17 05:12:18 PM PDT 24
Peak memory 200064 kb
Host smart-47117321-f359-47e5-a373-ff1d8692d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077233383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3077233383
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3942913404
Short name T1112
Test name
Test status
Simulation time 26137905495 ps
CPU time 90.91 seconds
Started Aug 17 05:11:54 PM PDT 24
Finished Aug 17 05:13:24 PM PDT 24
Peak memory 200880 kb
Host smart-992db383-8f62-4d7d-9c36-e878d6c4960c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942913404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3942913404
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3001171148
Short name T839
Test name
Test status
Simulation time 3518842496 ps
CPU time 8.59 seconds
Started Aug 17 05:11:50 PM PDT 24
Finished Aug 17 05:11:58 PM PDT 24
Peak memory 200020 kb
Host smart-09b99373-6253-45ea-8f51-d8e65590651d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001171148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3001171148
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1846565586
Short name T847
Test name
Test status
Simulation time 72807547051 ps
CPU time 66.16 seconds
Started Aug 17 05:11:50 PM PDT 24
Finished Aug 17 05:12:57 PM PDT 24
Peak memory 200764 kb
Host smart-dac96bea-f209-4c5a-bda6-80f13a654834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846565586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1846565586
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1157033769
Short name T1137
Test name
Test status
Simulation time 4525990166 ps
CPU time 2.43 seconds
Started Aug 17 05:11:51 PM PDT 24
Finished Aug 17 05:11:53 PM PDT 24
Peak memory 197488 kb
Host smart-49d7d56a-fdf8-41f2-b85e-b4a2e8203174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157033769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1157033769
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.509087205
Short name T357
Test name
Test status
Simulation time 657864254 ps
CPU time 1.42 seconds
Started Aug 17 05:11:42 PM PDT 24
Finished Aug 17 05:11:43 PM PDT 24
Peak memory 199892 kb
Host smart-0e54cb48-7b68-41e2-acf9-a235f9080b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509087205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.509087205
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2620545664
Short name T1047
Test name
Test status
Simulation time 90345419798 ps
CPU time 1353.5 seconds
Started Aug 17 05:12:07 PM PDT 24
Finished Aug 17 05:34:41 PM PDT 24
Peak memory 200900 kb
Host smart-92d26dda-b994-4b46-8c61-6a973e31920e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620545664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2620545664
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1988960263
Short name T1147
Test name
Test status
Simulation time 3195482760 ps
CPU time 49.05 seconds
Started Aug 17 05:11:50 PM PDT 24
Finished Aug 17 05:12:39 PM PDT 24
Peak memory 210336 kb
Host smart-f0872793-6798-4ac0-a26f-cff868a1f409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988960263 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1988960263
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3407045794
Short name T417
Test name
Test status
Simulation time 2845929666 ps
CPU time 2 seconds
Started Aug 17 05:11:57 PM PDT 24
Finished Aug 17 05:11:59 PM PDT 24
Peak memory 199852 kb
Host smart-3e2a9abd-4043-4572-8ed8-47aba3a86d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407045794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3407045794
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3612585407
Short name T828
Test name
Test status
Simulation time 71165039453 ps
CPU time 24.16 seconds
Started Aug 17 05:11:57 PM PDT 24
Finished Aug 17 05:12:21 PM PDT 24
Peak memory 200932 kb
Host smart-7c7c5dbc-bb87-42f9-ba6f-2ee8615497fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612585407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3612585407
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3762701886
Short name T273
Test name
Test status
Simulation time 54251299247 ps
CPU time 76.45 seconds
Started Aug 17 05:23:16 PM PDT 24
Finished Aug 17 05:24:32 PM PDT 24
Peak memory 200896 kb
Host smart-c365d6e5-4236-418b-9ba8-f3eef132fe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762701886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3762701886
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3274755178
Short name T76
Test name
Test status
Simulation time 36691831576 ps
CPU time 14.99 seconds
Started Aug 17 05:23:17 PM PDT 24
Finished Aug 17 05:23:32 PM PDT 24
Peak memory 200892 kb
Host smart-1710cfc8-e8ac-4ec5-890e-02216581ac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274755178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3274755178
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.143733974
Short name T923
Test name
Test status
Simulation time 151399165953 ps
CPU time 15.36 seconds
Started Aug 17 05:23:17 PM PDT 24
Finished Aug 17 05:23:33 PM PDT 24
Peak memory 200868 kb
Host smart-0a0f9ea5-ee23-423e-a1a5-c9e9e2801fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143733974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.143733974
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.4002541724
Short name T804
Test name
Test status
Simulation time 83751533130 ps
CPU time 8.54 seconds
Started Aug 17 05:23:16 PM PDT 24
Finished Aug 17 05:23:25 PM PDT 24
Peak memory 200576 kb
Host smart-27661964-4553-426b-afc7-47adfa912798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002541724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4002541724
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3475927410
Short name T962
Test name
Test status
Simulation time 40491691833 ps
CPU time 77.9 seconds
Started Aug 17 05:23:23 PM PDT 24
Finished Aug 17 05:24:41 PM PDT 24
Peak memory 200936 kb
Host smart-7030069b-4585-4c76-8455-15dc1f32c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475927410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3475927410
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3056131750
Short name T272
Test name
Test status
Simulation time 59767563879 ps
CPU time 65.18 seconds
Started Aug 17 05:23:18 PM PDT 24
Finished Aug 17 05:24:23 PM PDT 24
Peak memory 200908 kb
Host smart-e40a6723-bd45-4c0b-8a59-75e4bfdd1401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056131750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3056131750
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.779711731
Short name T558
Test name
Test status
Simulation time 112004693357 ps
CPU time 169.95 seconds
Started Aug 17 05:23:16 PM PDT 24
Finished Aug 17 05:26:06 PM PDT 24
Peak memory 199328 kb
Host smart-eb844a3c-e1c1-491f-9493-1d0005f817d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779711731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.779711731
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1636929568
Short name T146
Test name
Test status
Simulation time 120620832653 ps
CPU time 15.32 seconds
Started Aug 17 05:23:17 PM PDT 24
Finished Aug 17 05:23:33 PM PDT 24
Peak memory 200592 kb
Host smart-354ed22e-f972-4677-9af2-c4fa87dbfd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636929568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1636929568
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.993212663
Short name T1099
Test name
Test status
Simulation time 12809716 ps
CPU time 0.57 seconds
Started Aug 17 05:12:16 PM PDT 24
Finished Aug 17 05:12:16 PM PDT 24
Peak memory 196524 kb
Host smart-9eb9ba28-63e9-405a-babd-8039cd201ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993212663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.993212663
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1369028100
Short name T908
Test name
Test status
Simulation time 99064197756 ps
CPU time 62.63 seconds
Started Aug 17 05:12:04 PM PDT 24
Finished Aug 17 05:13:07 PM PDT 24
Peak memory 200820 kb
Host smart-e7bb9925-30c3-4bfb-9f78-3b50e9218d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369028100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1369028100
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2858889545
Short name T291
Test name
Test status
Simulation time 56795773662 ps
CPU time 84.38 seconds
Started Aug 17 05:12:05 PM PDT 24
Finished Aug 17 05:13:29 PM PDT 24
Peak memory 200256 kb
Host smart-e330fa85-ce37-465b-ba7c-25b68940cedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858889545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2858889545
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.2516305182
Short name T281
Test name
Test status
Simulation time 50017555406 ps
CPU time 69.76 seconds
Started Aug 17 05:12:08 PM PDT 24
Finished Aug 17 05:13:18 PM PDT 24
Peak memory 200960 kb
Host smart-095a1065-bb43-4cf4-9614-4eae39af1fd8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516305182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2516305182
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2771397696
Short name T542
Test name
Test status
Simulation time 85003834244 ps
CPU time 299.8 seconds
Started Aug 17 05:12:15 PM PDT 24
Finished Aug 17 05:17:15 PM PDT 24
Peak memory 200912 kb
Host smart-7305c046-e29a-49cc-bda4-495ed302fbf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771397696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2771397696
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1736376275
Short name T410
Test name
Test status
Simulation time 1074591900 ps
CPU time 1.07 seconds
Started Aug 17 05:12:14 PM PDT 24
Finished Aug 17 05:12:15 PM PDT 24
Peak memory 196468 kb
Host smart-a8ea2af3-4c59-4ad1-a17f-bacd1415ae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736376275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1736376275
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3323559903
Short name T1143
Test name
Test status
Simulation time 32454613269 ps
CPU time 48.8 seconds
Started Aug 17 05:12:07 PM PDT 24
Finished Aug 17 05:12:56 PM PDT 24
Peak memory 201160 kb
Host smart-578d286f-6305-4e2f-93df-861184c6e9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323559903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3323559903
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.4125725345
Short name T1120
Test name
Test status
Simulation time 11296679176 ps
CPU time 627.43 seconds
Started Aug 17 05:12:14 PM PDT 24
Finished Aug 17 05:22:42 PM PDT 24
Peak memory 201068 kb
Host smart-c55e0dce-4e35-492a-be58-f90d266b7f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125725345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4125725345
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.199152578
Short name T452
Test name
Test status
Simulation time 4572520684 ps
CPU time 8.29 seconds
Started Aug 17 05:12:09 PM PDT 24
Finished Aug 17 05:12:18 PM PDT 24
Peak memory 199064 kb
Host smart-0b55f176-8f66-4000-8d0f-f9e3c2b97922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199152578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.199152578
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1693024006
Short name T1041
Test name
Test status
Simulation time 74638598688 ps
CPU time 62.5 seconds
Started Aug 17 05:12:08 PM PDT 24
Finished Aug 17 05:13:11 PM PDT 24
Peak memory 200808 kb
Host smart-1bc32979-6467-4896-baeb-d3217a24ea24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693024006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1693024006
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3006226668
Short name T396
Test name
Test status
Simulation time 4376422233 ps
CPU time 6.92 seconds
Started Aug 17 05:12:08 PM PDT 24
Finished Aug 17 05:12:15 PM PDT 24
Peak memory 197276 kb
Host smart-97e309f4-9388-4bf4-8543-6f17c21778a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006226668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3006226668
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.261104600
Short name T391
Test name
Test status
Simulation time 507982781 ps
CPU time 1.14 seconds
Started Aug 17 05:12:06 PM PDT 24
Finished Aug 17 05:12:07 PM PDT 24
Peak memory 200272 kb
Host smart-d91f2c8f-d5ae-4c95-b216-5e58a928f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261104600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.261104600
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2164753860
Short name T155
Test name
Test status
Simulation time 41473560162 ps
CPU time 69.39 seconds
Started Aug 17 05:12:15 PM PDT 24
Finished Aug 17 05:13:25 PM PDT 24
Peak memory 201252 kb
Host smart-cd678a53-5d38-4b77-9f4f-660f62fb7ed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164753860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2164753860
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2059191976
Short name T500
Test name
Test status
Simulation time 4404844375 ps
CPU time 21.46 seconds
Started Aug 17 05:12:17 PM PDT 24
Finished Aug 17 05:12:38 PM PDT 24
Peak memory 201000 kb
Host smart-74891d0a-45d4-4b50-83e1-627029923c6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059191976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2059191976
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.259798085
Short name T797
Test name
Test status
Simulation time 449373165 ps
CPU time 1.87 seconds
Started Aug 17 05:12:08 PM PDT 24
Finished Aug 17 05:12:10 PM PDT 24
Peak memory 200488 kb
Host smart-b8ae4752-a42e-41a1-a23e-3d956ccf0b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259798085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.259798085
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3467833501
Short name T1098
Test name
Test status
Simulation time 179011143175 ps
CPU time 164.95 seconds
Started Aug 17 05:12:06 PM PDT 24
Finished Aug 17 05:14:51 PM PDT 24
Peak memory 200880 kb
Host smart-3a52f56a-5a93-4302-9f86-1a2bfcfac4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467833501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3467833501
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2466743173
Short name T1167
Test name
Test status
Simulation time 26454158461 ps
CPU time 44.64 seconds
Started Aug 17 05:23:18 PM PDT 24
Finished Aug 17 05:24:02 PM PDT 24
Peak memory 200880 kb
Host smart-2330f213-10e1-4024-ba30-d97087ff4f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466743173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2466743173
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1687662398
Short name T565
Test name
Test status
Simulation time 33995527386 ps
CPU time 13.65 seconds
Started Aug 17 05:23:18 PM PDT 24
Finished Aug 17 05:23:32 PM PDT 24
Peak memory 200952 kb
Host smart-649fcdc7-9fda-4010-88d5-74392e1d3a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687662398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1687662398
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.521573904
Short name T1175
Test name
Test status
Simulation time 9036672378 ps
CPU time 14.01 seconds
Started Aug 17 05:23:23 PM PDT 24
Finished Aug 17 05:23:37 PM PDT 24
Peak memory 200740 kb
Host smart-6634cd9f-6530-4f29-898d-1c32041f5f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521573904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.521573904
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1098662856
Short name T254
Test name
Test status
Simulation time 131992796249 ps
CPU time 49.78 seconds
Started Aug 17 05:23:22 PM PDT 24
Finished Aug 17 05:24:12 PM PDT 24
Peak memory 200872 kb
Host smart-1a2d7d9e-69cd-457c-a641-a5157c63507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098662856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1098662856
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3694014778
Short name T544
Test name
Test status
Simulation time 20792379715 ps
CPU time 16.29 seconds
Started Aug 17 05:23:15 PM PDT 24
Finished Aug 17 05:23:32 PM PDT 24
Peak memory 200616 kb
Host smart-24f74ad3-37fb-4752-9195-a45937ebed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694014778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3694014778
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2236043840
Short name T426
Test name
Test status
Simulation time 39356552853 ps
CPU time 14.06 seconds
Started Aug 17 05:23:17 PM PDT 24
Finished Aug 17 05:23:32 PM PDT 24
Peak memory 200640 kb
Host smart-78258340-0836-437d-9b96-f456e4749654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236043840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2236043840
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2307044540
Short name T858
Test name
Test status
Simulation time 170410896074 ps
CPU time 546.23 seconds
Started Aug 17 05:23:23 PM PDT 24
Finished Aug 17 05:32:29 PM PDT 24
Peak memory 200928 kb
Host smart-885a6f96-56a5-4dad-bccb-3744ae05ab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307044540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2307044540
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3028587250
Short name T683
Test name
Test status
Simulation time 205354204358 ps
CPU time 178.77 seconds
Started Aug 17 05:23:16 PM PDT 24
Finished Aug 17 05:26:15 PM PDT 24
Peak memory 199376 kb
Host smart-a2f80f23-caca-46a5-8d39-99afbe1c1368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028587250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3028587250
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.541994121
Short name T687
Test name
Test status
Simulation time 34921273 ps
CPU time 0.54 seconds
Started Aug 17 05:12:38 PM PDT 24
Finished Aug 17 05:12:38 PM PDT 24
Peak memory 195216 kb
Host smart-6e3902d8-e3d0-4534-835a-fadad5c72ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541994121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.541994121
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3615718713
Short name T741
Test name
Test status
Simulation time 19805452877 ps
CPU time 29.68 seconds
Started Aug 17 05:12:22 PM PDT 24
Finished Aug 17 05:12:52 PM PDT 24
Peak memory 200948 kb
Host smart-007e8b1d-b453-477f-9978-0243efed25d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615718713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3615718713
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.4058039707
Short name T744
Test name
Test status
Simulation time 184823643890 ps
CPU time 73.12 seconds
Started Aug 17 05:12:27 PM PDT 24
Finished Aug 17 05:13:40 PM PDT 24
Peak memory 200804 kb
Host smart-1f61f3d6-9e0f-4e44-a8e8-8d44e2ec065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058039707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4058039707
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.371505103
Short name T816
Test name
Test status
Simulation time 14296208590 ps
CPU time 17.11 seconds
Started Aug 17 05:12:23 PM PDT 24
Finished Aug 17 05:12:41 PM PDT 24
Peak memory 200832 kb
Host smart-fb9fb5a5-0d77-4ab2-9b4c-4d2757ebd294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371505103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.371505103
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1884492550
Short name T620
Test name
Test status
Simulation time 30541177093 ps
CPU time 47.17 seconds
Started Aug 17 05:12:24 PM PDT 24
Finished Aug 17 05:13:11 PM PDT 24
Peak memory 199872 kb
Host smart-79e5c43d-ffb3-465b-87f2-9856c852a544
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884492550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1884492550
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1953769552
Short name T603
Test name
Test status
Simulation time 131251811647 ps
CPU time 880.63 seconds
Started Aug 17 05:12:31 PM PDT 24
Finished Aug 17 05:27:12 PM PDT 24
Peak memory 200900 kb
Host smart-353aaa3f-58e6-433d-a91c-c3d75063e2e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953769552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1953769552
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3724043199
Short name T957
Test name
Test status
Simulation time 542136288 ps
CPU time 1.28 seconds
Started Aug 17 05:12:33 PM PDT 24
Finished Aug 17 05:12:34 PM PDT 24
Peak memory 199704 kb
Host smart-4965ca3f-354f-4edb-acf1-3f9b407c4051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724043199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3724043199
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.87585361
Short name T550
Test name
Test status
Simulation time 57277997377 ps
CPU time 95.56 seconds
Started Aug 17 05:12:22 PM PDT 24
Finished Aug 17 05:13:58 PM PDT 24
Peak memory 201156 kb
Host smart-87200cb4-0014-4781-9632-1b87cc27d760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87585361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.87585361
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.679571055
Short name T669
Test name
Test status
Simulation time 4874447496 ps
CPU time 88.97 seconds
Started Aug 17 05:12:30 PM PDT 24
Finished Aug 17 05:13:59 PM PDT 24
Peak memory 200952 kb
Host smart-fd4cbaad-1bdf-4ae0-b618-b1dd1287846b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679571055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.679571055
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3795987105
Short name T1059
Test name
Test status
Simulation time 6789813762 ps
CPU time 25.93 seconds
Started Aug 17 05:12:24 PM PDT 24
Finished Aug 17 05:12:50 PM PDT 24
Peak memory 200900 kb
Host smart-71ba650a-77d1-4f0d-9ff2-7cc93a02fdfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795987105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3795987105
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.271798801
Short name T782
Test name
Test status
Simulation time 91235724899 ps
CPU time 170.17 seconds
Started Aug 17 05:12:30 PM PDT 24
Finished Aug 17 05:15:20 PM PDT 24
Peak memory 200852 kb
Host smart-f108b1ef-2339-479d-9074-cafa065db240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271798801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.271798801
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2376290851
Short name T343
Test name
Test status
Simulation time 43515833599 ps
CPU time 70.17 seconds
Started Aug 17 05:12:23 PM PDT 24
Finished Aug 17 05:13:33 PM PDT 24
Peak memory 196992 kb
Host smart-55c9b203-1627-4029-a683-3e53f06e581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376290851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2376290851
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2577024056
Short name T51
Test name
Test status
Simulation time 5890036977 ps
CPU time 13.02 seconds
Started Aug 17 05:12:17 PM PDT 24
Finished Aug 17 05:12:30 PM PDT 24
Peak memory 200768 kb
Host smart-9c326bc7-2c48-4076-ab3e-e0874930c0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577024056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2577024056
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2171835352
Short name T919
Test name
Test status
Simulation time 14852273009 ps
CPU time 47.36 seconds
Started Aug 17 05:12:32 PM PDT 24
Finished Aug 17 05:13:19 PM PDT 24
Peak memory 216864 kb
Host smart-e72e9f38-976d-439c-9d09-2e6b63dc39c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171835352 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2171835352
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1691560230
Short name T736
Test name
Test status
Simulation time 2236167249 ps
CPU time 2.55 seconds
Started Aug 17 05:12:31 PM PDT 24
Finished Aug 17 05:12:34 PM PDT 24
Peak memory 199420 kb
Host smart-42f40b57-6c49-43b1-82d0-d2d36f713f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691560230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1691560230
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.790953143
Short name T950
Test name
Test status
Simulation time 158947144722 ps
CPU time 79.41 seconds
Started Aug 17 05:12:13 PM PDT 24
Finished Aug 17 05:13:32 PM PDT 24
Peak memory 200840 kb
Host smart-240803ea-c572-4be4-a6d8-1ade61e1c5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790953143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.790953143
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3728592821
Short name T239
Test name
Test status
Simulation time 19525660124 ps
CPU time 31.38 seconds
Started Aug 17 05:23:25 PM PDT 24
Finished Aug 17 05:23:56 PM PDT 24
Peak memory 200880 kb
Host smart-9eed9c73-91bc-4952-adf9-4b7826ea4b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728592821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3728592821
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1311644068
Short name T912
Test name
Test status
Simulation time 34735841963 ps
CPU time 28.39 seconds
Started Aug 17 05:23:23 PM PDT 24
Finished Aug 17 05:23:52 PM PDT 24
Peak memory 201100 kb
Host smart-4aac6b1f-ad69-4bed-9dcf-038c42c33f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311644068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1311644068
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1154921063
Short name T968
Test name
Test status
Simulation time 102814892264 ps
CPU time 79.33 seconds
Started Aug 17 05:23:25 PM PDT 24
Finished Aug 17 05:24:44 PM PDT 24
Peak memory 200768 kb
Host smart-65da4f70-a268-4c24-80b2-0c66060a590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154921063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1154921063
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1381713669
Short name T216
Test name
Test status
Simulation time 15149293874 ps
CPU time 25.11 seconds
Started Aug 17 05:23:26 PM PDT 24
Finished Aug 17 05:23:51 PM PDT 24
Peak memory 200892 kb
Host smart-8e12dcf4-31a4-43af-bf72-7e58a6c6ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381713669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1381713669
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2232710523
Short name T269
Test name
Test status
Simulation time 95898122582 ps
CPU time 35.41 seconds
Started Aug 17 05:23:25 PM PDT 24
Finished Aug 17 05:24:00 PM PDT 24
Peak memory 199392 kb
Host smart-d665a903-bbd1-4043-b6b0-ca0df9aa27c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232710523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2232710523
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3665458625
Short name T922
Test name
Test status
Simulation time 60775740359 ps
CPU time 37.37 seconds
Started Aug 17 05:23:25 PM PDT 24
Finished Aug 17 05:24:02 PM PDT 24
Peak memory 200936 kb
Host smart-464ffeec-bc83-487d-a073-0c06495e60f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665458625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3665458625
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2424734225
Short name T1005
Test name
Test status
Simulation time 50890848 ps
CPU time 0.54 seconds
Started Aug 17 05:12:55 PM PDT 24
Finished Aug 17 05:12:55 PM PDT 24
Peak memory 196256 kb
Host smart-beea5622-8fa0-4420-9202-bf2ee21eedc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424734225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2424734225
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1155416269
Short name T934
Test name
Test status
Simulation time 11596516984 ps
CPU time 18.8 seconds
Started Aug 17 05:12:38 PM PDT 24
Finished Aug 17 05:12:56 PM PDT 24
Peak memory 200916 kb
Host smart-e75c1441-181e-4baa-85da-2a4ac47b0598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155416269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1155416269
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2758238204
Short name T913
Test name
Test status
Simulation time 78426606368 ps
CPU time 56.18 seconds
Started Aug 17 05:12:37 PM PDT 24
Finished Aug 17 05:13:33 PM PDT 24
Peak memory 200956 kb
Host smart-14225021-9104-44ea-b922-cbdb606d3dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758238204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2758238204
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.2418404662
Short name T826
Test name
Test status
Simulation time 40691802881 ps
CPU time 62.89 seconds
Started Aug 17 05:12:47 PM PDT 24
Finished Aug 17 05:13:50 PM PDT 24
Peak memory 200956 kb
Host smart-8cf4b24c-d5e1-4764-8d22-439336e37ecd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418404662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2418404662
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.175103505
Short name T398
Test name
Test status
Simulation time 58180528648 ps
CPU time 232.74 seconds
Started Aug 17 05:12:48 PM PDT 24
Finished Aug 17 05:16:41 PM PDT 24
Peak memory 200872 kb
Host smart-451952e0-1f62-442e-aa46-180aa194a9d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175103505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.175103505
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.953133241
Short name T385
Test name
Test status
Simulation time 3239494695 ps
CPU time 2.46 seconds
Started Aug 17 05:12:50 PM PDT 24
Finished Aug 17 05:12:53 PM PDT 24
Peak memory 198856 kb
Host smart-a20a8faf-468f-42fc-9754-269eab62e109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953133241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.953133241
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1045824239
Short name T376
Test name
Test status
Simulation time 10886147007 ps
CPU time 15.56 seconds
Started Aug 17 05:12:47 PM PDT 24
Finished Aug 17 05:13:03 PM PDT 24
Peak memory 199088 kb
Host smart-be4a33e8-3da6-4c0f-b143-876a16bf5e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045824239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1045824239
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2832293694
Short name T693
Test name
Test status
Simulation time 6833275991 ps
CPU time 14.14 seconds
Started Aug 17 05:12:40 PM PDT 24
Finished Aug 17 05:12:54 PM PDT 24
Peak memory 198924 kb
Host smart-168fb088-f0e1-4596-b609-7af3888d39de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832293694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2832293694
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2139326287
Short name T304
Test name
Test status
Simulation time 49269387480 ps
CPU time 117.36 seconds
Started Aug 17 05:12:47 PM PDT 24
Finished Aug 17 05:14:45 PM PDT 24
Peak memory 200960 kb
Host smart-a416e2dd-1136-4ac1-af99-2a0dc130d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139326287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2139326287
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3980606821
Short name T511
Test name
Test status
Simulation time 649792313 ps
CPU time 1.25 seconds
Started Aug 17 05:12:47 PM PDT 24
Finished Aug 17 05:12:48 PM PDT 24
Peak memory 196392 kb
Host smart-07ce1c6c-8cf4-4c80-918b-84af5ec73d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980606821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3980606821
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.162653676
Short name T112
Test name
Test status
Simulation time 115211761 ps
CPU time 0.9 seconds
Started Aug 17 05:12:39 PM PDT 24
Finished Aug 17 05:12:40 PM PDT 24
Peak memory 198692 kb
Host smart-515ffdaf-82b6-4b8b-95a3-03b666d74da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162653676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.162653676
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2460401580
Short name T104
Test name
Test status
Simulation time 1549159665 ps
CPU time 15.47 seconds
Started Aug 17 05:12:47 PM PDT 24
Finished Aug 17 05:13:03 PM PDT 24
Peak memory 200948 kb
Host smart-625bd5eb-5645-489e-b59d-4be30be546dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460401580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2460401580
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.453629220
Short name T670
Test name
Test status
Simulation time 1346827465 ps
CPU time 2.75 seconds
Started Aug 17 05:12:49 PM PDT 24
Finished Aug 17 05:12:51 PM PDT 24
Peak memory 199864 kb
Host smart-d166d0ad-8989-45f6-bf3f-0e251293e157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453629220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.453629220
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.399389765
Short name T709
Test name
Test status
Simulation time 33608733641 ps
CPU time 18.53 seconds
Started Aug 17 05:12:38 PM PDT 24
Finished Aug 17 05:12:57 PM PDT 24
Peak memory 200928 kb
Host smart-9cbca5af-e5dc-4362-868f-15c5c9e2db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399389765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.399389765
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.811217552
Short name T932
Test name
Test status
Simulation time 174104420675 ps
CPU time 22.18 seconds
Started Aug 17 05:23:25 PM PDT 24
Finished Aug 17 05:23:47 PM PDT 24
Peak memory 200896 kb
Host smart-cff71bae-0384-43b4-9c5a-e43469d40be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811217552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.811217552
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.490136136
Short name T723
Test name
Test status
Simulation time 24297064662 ps
CPU time 21.85 seconds
Started Aug 17 05:23:24 PM PDT 24
Finished Aug 17 05:23:46 PM PDT 24
Peak memory 200948 kb
Host smart-41d620ea-2ff3-4eff-afd4-3435337c26d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490136136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.490136136
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.90457599
Short name T1028
Test name
Test status
Simulation time 10750218252 ps
CPU time 22.58 seconds
Started Aug 17 05:23:24 PM PDT 24
Finished Aug 17 05:23:47 PM PDT 24
Peak memory 200956 kb
Host smart-8f9d6e67-ea5d-4333-bff8-74445f0cc8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90457599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.90457599
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3003705121
Short name T174
Test name
Test status
Simulation time 89925095417 ps
CPU time 41.84 seconds
Started Aug 17 05:23:25 PM PDT 24
Finished Aug 17 05:24:07 PM PDT 24
Peak memory 200848 kb
Host smart-bc71e62b-5f83-4d4f-a7cd-6ac1c21633f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003705121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3003705121
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3814776416
Short name T227
Test name
Test status
Simulation time 62926506386 ps
CPU time 90.39 seconds
Started Aug 17 05:23:24 PM PDT 24
Finished Aug 17 05:24:55 PM PDT 24
Peak memory 200876 kb
Host smart-6280bb50-6d5c-478b-bef1-968d6aa72582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814776416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3814776416
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.651115157
Short name T430
Test name
Test status
Simulation time 75760162941 ps
CPU time 121.77 seconds
Started Aug 17 05:23:26 PM PDT 24
Finished Aug 17 05:25:28 PM PDT 24
Peak memory 200916 kb
Host smart-d3f8445e-7b19-44c2-ac1f-68f80c1c6e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651115157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.651115157
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2384952259
Short name T590
Test name
Test status
Simulation time 147447844909 ps
CPU time 70.7 seconds
Started Aug 17 05:23:32 PM PDT 24
Finished Aug 17 05:24:43 PM PDT 24
Peak memory 200848 kb
Host smart-c613e8af-8fef-4cf9-9a62-914c44afe3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384952259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2384952259
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2950059994
Short name T1018
Test name
Test status
Simulation time 14277991 ps
CPU time 0.59 seconds
Started Aug 17 05:13:12 PM PDT 24
Finished Aug 17 05:13:13 PM PDT 24
Peak memory 196276 kb
Host smart-f5a250bb-e6c4-472b-a2f3-757bab1c476e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950059994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2950059994
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3824370010
Short name T1145
Test name
Test status
Simulation time 38794934917 ps
CPU time 64.94 seconds
Started Aug 17 05:12:55 PM PDT 24
Finished Aug 17 05:14:00 PM PDT 24
Peak memory 200900 kb
Host smart-15fff8f9-1c20-49e9-a58c-4e381938b04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824370010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3824370010
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.739386627
Short name T202
Test name
Test status
Simulation time 88911823934 ps
CPU time 37.9 seconds
Started Aug 17 05:12:54 PM PDT 24
Finished Aug 17 05:13:32 PM PDT 24
Peak memory 200940 kb
Host smart-2815c689-0520-4bff-8c0f-0c534eec5f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739386627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.739386627
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2560106301
Short name T1129
Test name
Test status
Simulation time 80267445087 ps
CPU time 33.33 seconds
Started Aug 17 05:12:55 PM PDT 24
Finished Aug 17 05:13:29 PM PDT 24
Peak memory 200876 kb
Host smart-9b77b374-801f-4019-b477-c1ecbe4004f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560106301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2560106301
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1580601857
Short name T460
Test name
Test status
Simulation time 25745807350 ps
CPU time 19.55 seconds
Started Aug 17 05:12:57 PM PDT 24
Finished Aug 17 05:13:17 PM PDT 24
Peak memory 200640 kb
Host smart-091a3a15-5bf1-4075-b09b-770303d1fc31
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580601857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1580601857
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1118402416
Short name T577
Test name
Test status
Simulation time 54676108585 ps
CPU time 458.51 seconds
Started Aug 17 05:13:12 PM PDT 24
Finished Aug 17 05:20:51 PM PDT 24
Peak memory 200896 kb
Host smart-c31bc21b-8122-4a66-8d14-a5791f7cfdfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118402416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1118402416
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3695055965
Short name T570
Test name
Test status
Simulation time 11141629010 ps
CPU time 12.42 seconds
Started Aug 17 05:13:03 PM PDT 24
Finished Aug 17 05:13:16 PM PDT 24
Peak memory 200768 kb
Host smart-3bf25997-ea96-4f58-b564-f1912874fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695055965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3695055965
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2254149248
Short name T1118
Test name
Test status
Simulation time 293149921662 ps
CPU time 46.29 seconds
Started Aug 17 05:12:57 PM PDT 24
Finished Aug 17 05:13:43 PM PDT 24
Peak memory 200888 kb
Host smart-46876ebb-807a-4513-8f74-dcaa8310e9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254149248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2254149248
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2115634634
Short name T1124
Test name
Test status
Simulation time 17465305529 ps
CPU time 911.82 seconds
Started Aug 17 05:13:05 PM PDT 24
Finished Aug 17 05:28:17 PM PDT 24
Peak memory 200840 kb
Host smart-323d54dc-fea2-4b8c-81c7-17665622bf74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115634634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2115634634
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.4280772190
Short name T959
Test name
Test status
Simulation time 3292714395 ps
CPU time 6.28 seconds
Started Aug 17 05:12:56 PM PDT 24
Finished Aug 17 05:13:02 PM PDT 24
Peak memory 200072 kb
Host smart-22739b10-f071-4ba8-8e86-f83341d2d875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280772190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.4280772190
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.372778083
Short name T1142
Test name
Test status
Simulation time 42135893482 ps
CPU time 60.41 seconds
Started Aug 17 05:13:04 PM PDT 24
Finished Aug 17 05:14:04 PM PDT 24
Peak memory 200852 kb
Host smart-53221881-4013-44e9-8745-558ea0804271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372778083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.372778083
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3475562117
Short name T463
Test name
Test status
Simulation time 2203663901 ps
CPU time 1.48 seconds
Started Aug 17 05:13:04 PM PDT 24
Finished Aug 17 05:13:05 PM PDT 24
Peak memory 196472 kb
Host smart-5fec950b-2ae9-4046-9ca3-4cbbea8cd253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475562117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3475562117
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.26463732
Short name T759
Test name
Test status
Simulation time 126326311 ps
CPU time 0.9 seconds
Started Aug 17 05:12:57 PM PDT 24
Finished Aug 17 05:12:58 PM PDT 24
Peak memory 199292 kb
Host smart-1ab22de6-9e81-4650-8326-4331a501c4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26463732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.26463732
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.8914426
Short name T864
Test name
Test status
Simulation time 224763451509 ps
CPU time 385.79 seconds
Started Aug 17 05:13:11 PM PDT 24
Finished Aug 17 05:19:37 PM PDT 24
Peak memory 200960 kb
Host smart-574cdeab-2e8d-45a6-adc4-e23d6b298e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8914426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.8914426
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3289666031
Short name T707
Test name
Test status
Simulation time 1782108697 ps
CPU time 2.12 seconds
Started Aug 17 05:13:03 PM PDT 24
Finished Aug 17 05:13:06 PM PDT 24
Peak memory 199280 kb
Host smart-40d69ab4-392d-46dc-abbc-131081545dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289666031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3289666031
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3430950174
Short name T882
Test name
Test status
Simulation time 32933266270 ps
CPU time 50.6 seconds
Started Aug 17 05:12:54 PM PDT 24
Finished Aug 17 05:13:45 PM PDT 24
Peak memory 200860 kb
Host smart-4f5a4a1e-4441-489f-83e5-93331c06754c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430950174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3430950174
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.101283342
Short name T1126
Test name
Test status
Simulation time 424397663531 ps
CPU time 118.2 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:25:29 PM PDT 24
Peak memory 200972 kb
Host smart-c58e1a9f-f8a8-4623-acc3-22cc130072aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101283342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.101283342
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1425431620
Short name T321
Test name
Test status
Simulation time 88719324289 ps
CPU time 43.6 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:24:14 PM PDT 24
Peak memory 200904 kb
Host smart-f4dc7313-1573-41d7-9b29-b89b4eec3a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425431620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1425431620
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.741128907
Short name T1146
Test name
Test status
Simulation time 9650642983 ps
CPU time 17.28 seconds
Started Aug 17 05:23:32 PM PDT 24
Finished Aug 17 05:23:49 PM PDT 24
Peak memory 200876 kb
Host smart-1ed70588-211b-4682-ade5-55bcc4320f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741128907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.741128907
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2944539073
Short name T229
Test name
Test status
Simulation time 37067599174 ps
CPU time 15.21 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:23:46 PM PDT 24
Peak memory 200764 kb
Host smart-e6a43988-2eb9-4453-a66c-c1825f99b7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944539073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2944539073
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2043705485
Short name T677
Test name
Test status
Simulation time 11350545715 ps
CPU time 17.63 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:23:49 PM PDT 24
Peak memory 199452 kb
Host smart-9cfee252-daa8-4e75-9105-4fd3d7251c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043705485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2043705485
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3873933569
Short name T264
Test name
Test status
Simulation time 100903245763 ps
CPU time 28.74 seconds
Started Aug 17 05:23:33 PM PDT 24
Finished Aug 17 05:24:02 PM PDT 24
Peak memory 200876 kb
Host smart-15fc80f4-97e9-4526-a99b-d86d69858a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873933569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3873933569
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2315570425
Short name T711
Test name
Test status
Simulation time 37897590267 ps
CPU time 131.3 seconds
Started Aug 17 05:23:32 PM PDT 24
Finished Aug 17 05:25:43 PM PDT 24
Peak memory 200896 kb
Host smart-77eab9d5-7406-4d1e-b166-582f3f61396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315570425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2315570425
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2044577497
Short name T681
Test name
Test status
Simulation time 126369451133 ps
CPU time 84.39 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:24:55 PM PDT 24
Peak memory 200824 kb
Host smart-42b04ba0-2807-47bf-b855-93cfe8b38a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044577497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2044577497
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1471280349
Short name T446
Test name
Test status
Simulation time 20155323 ps
CPU time 0.55 seconds
Started Aug 17 05:13:30 PM PDT 24
Finished Aug 17 05:13:31 PM PDT 24
Peak memory 196252 kb
Host smart-76ff66fe-f32d-4381-82fa-1e413b96e86e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471280349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1471280349
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3123739928
Short name T315
Test name
Test status
Simulation time 44088309987 ps
CPU time 41.41 seconds
Started Aug 17 05:13:13 PM PDT 24
Finished Aug 17 05:13:54 PM PDT 24
Peak memory 200912 kb
Host smart-a6138b30-697b-4d69-80ca-7f9568f2634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123739928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3123739928
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2625265351
Short name T897
Test name
Test status
Simulation time 285716093201 ps
CPU time 231.56 seconds
Started Aug 17 05:13:13 PM PDT 24
Finished Aug 17 05:17:04 PM PDT 24
Peak memory 200864 kb
Host smart-9c12f090-eaf6-4050-9e95-e88f677395fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625265351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2625265351
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1440137566
Short name T967
Test name
Test status
Simulation time 29561395572 ps
CPU time 22.5 seconds
Started Aug 17 05:13:20 PM PDT 24
Finished Aug 17 05:13:43 PM PDT 24
Peak memory 200896 kb
Host smart-c87b392a-d337-43a7-bf20-b578774e2f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440137566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1440137566
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.528332690
Short name T113
Test name
Test status
Simulation time 16557101455 ps
CPU time 8.82 seconds
Started Aug 17 05:13:20 PM PDT 24
Finished Aug 17 05:13:29 PM PDT 24
Peak memory 200928 kb
Host smart-b41bdad8-5138-4ece-bb08-c41b08ac1f2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528332690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.528332690
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.862087374
Short name T796
Test name
Test status
Simulation time 146088900332 ps
CPU time 214.59 seconds
Started Aug 17 05:13:28 PM PDT 24
Finished Aug 17 05:17:03 PM PDT 24
Peak memory 200828 kb
Host smart-b91391f9-3632-4610-ba88-4670b332cb32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862087374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.862087374
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4035896316
Short name T1031
Test name
Test status
Simulation time 3318481608 ps
CPU time 2.31 seconds
Started Aug 17 05:13:28 PM PDT 24
Finished Aug 17 05:13:30 PM PDT 24
Peak memory 198960 kb
Host smart-6de6fa5b-4365-47b7-b95c-2e8061c127e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035896316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4035896316
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1876685578
Short name T940
Test name
Test status
Simulation time 190798686415 ps
CPU time 136.14 seconds
Started Aug 17 05:13:19 PM PDT 24
Finished Aug 17 05:15:35 PM PDT 24
Peak memory 200892 kb
Host smart-64e91f5e-60f9-47d9-ac90-5c1e11581c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876685578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1876685578
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3098997370
Short name T332
Test name
Test status
Simulation time 9069775399 ps
CPU time 124.14 seconds
Started Aug 17 05:13:28 PM PDT 24
Finished Aug 17 05:15:33 PM PDT 24
Peak memory 200948 kb
Host smart-6c47626a-d584-4af6-b56e-36a40ebfdaab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098997370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3098997370
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3872245004
Short name T19
Test name
Test status
Simulation time 6178997199 ps
CPU time 55.91 seconds
Started Aug 17 05:13:23 PM PDT 24
Finished Aug 17 05:14:19 PM PDT 24
Peak memory 198844 kb
Host smart-8fff254d-c9e9-4eaf-9c71-09cf41a7e2a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872245004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3872245004
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1821927753
Short name T345
Test name
Test status
Simulation time 6801301136 ps
CPU time 9.97 seconds
Started Aug 17 05:13:18 PM PDT 24
Finished Aug 17 05:13:28 PM PDT 24
Peak memory 200464 kb
Host smart-1735ef50-1f1d-44f0-905d-854ee95ef5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821927753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1821927753
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2138744081
Short name T786
Test name
Test status
Simulation time 3019643037 ps
CPU time 5.48 seconds
Started Aug 17 05:13:20 PM PDT 24
Finished Aug 17 05:13:26 PM PDT 24
Peak memory 197280 kb
Host smart-5498dc7a-fb47-4bd5-936c-2045b802eb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138744081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2138744081
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1223132735
Short name T1070
Test name
Test status
Simulation time 6095347158 ps
CPU time 22.68 seconds
Started Aug 17 05:13:14 PM PDT 24
Finished Aug 17 05:13:37 PM PDT 24
Peak memory 200840 kb
Host smart-a2fc572c-c4f2-45a0-9500-1de80ff692e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223132735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1223132735
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1897293616
Short name T943
Test name
Test status
Simulation time 142242875391 ps
CPU time 68.64 seconds
Started Aug 17 05:13:30 PM PDT 24
Finished Aug 17 05:14:38 PM PDT 24
Peak memory 200924 kb
Host smart-704b92df-82e5-466f-ac39-2a8c28bc7e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897293616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1897293616
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.978864498
Short name T855
Test name
Test status
Simulation time 2599142267 ps
CPU time 36.82 seconds
Started Aug 17 05:13:32 PM PDT 24
Finished Aug 17 05:14:09 PM PDT 24
Peak memory 216412 kb
Host smart-09b08925-fc2e-4ebc-bbfe-3e76e0990f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978864498 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.978864498
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2417033249
Short name T18
Test name
Test status
Simulation time 7984109949 ps
CPU time 15.38 seconds
Started Aug 17 05:13:28 PM PDT 24
Finished Aug 17 05:13:44 PM PDT 24
Peak memory 200848 kb
Host smart-598d1b73-e985-4c69-993c-3aa3a301357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417033249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2417033249
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2244770206
Short name T582
Test name
Test status
Simulation time 372245012407 ps
CPU time 43.21 seconds
Started Aug 17 05:13:12 PM PDT 24
Finished Aug 17 05:13:55 PM PDT 24
Peak memory 200948 kb
Host smart-d2c1132a-7e02-4a35-a140-3a9c8bf4fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244770206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2244770206
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2681433324
Short name T212
Test name
Test status
Simulation time 19891000251 ps
CPU time 32.95 seconds
Started Aug 17 05:23:32 PM PDT 24
Finished Aug 17 05:24:05 PM PDT 24
Peak memory 200744 kb
Host smart-277d67f9-4479-462a-aa95-35830a1d9d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681433324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2681433324
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2303803605
Short name T152
Test name
Test status
Simulation time 23303412763 ps
CPU time 35.46 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:24:07 PM PDT 24
Peak memory 200836 kb
Host smart-9329f9cb-6817-4875-84aa-729a6f7bd052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303803605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2303803605
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2930701774
Short name T1182
Test name
Test status
Simulation time 37883386041 ps
CPU time 50.22 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:24:22 PM PDT 24
Peak memory 200716 kb
Host smart-b4c6478b-0367-44c1-92ac-3333582f4362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930701774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2930701774
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2058496739
Short name T172
Test name
Test status
Simulation time 25328983593 ps
CPU time 10.91 seconds
Started Aug 17 05:23:31 PM PDT 24
Finished Aug 17 05:23:42 PM PDT 24
Peak memory 200924 kb
Host smart-3de36dc1-886b-48ab-b570-9c43c6f2e6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058496739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2058496739
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.763526693
Short name T537
Test name
Test status
Simulation time 218193884913 ps
CPU time 58.4 seconds
Started Aug 17 05:23:32 PM PDT 24
Finished Aug 17 05:24:30 PM PDT 24
Peak memory 200472 kb
Host smart-cd865837-8253-40f3-bd9e-35f98020b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763526693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.763526693
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1087569681
Short name T465
Test name
Test status
Simulation time 200762189631 ps
CPU time 39.67 seconds
Started Aug 17 05:23:33 PM PDT 24
Finished Aug 17 05:24:13 PM PDT 24
Peak memory 200940 kb
Host smart-6550f00b-7e74-46c8-8693-a88a138cb44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087569681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1087569681
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1131287402
Short name T176
Test name
Test status
Simulation time 48844291293 ps
CPU time 20.25 seconds
Started Aug 17 05:23:36 PM PDT 24
Finished Aug 17 05:23:56 PM PDT 24
Peak memory 200876 kb
Host smart-a9d21dfd-4c1c-44e1-8616-43a3f9f788bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131287402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1131287402
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3133303294
Short name T117
Test name
Test status
Simulation time 125417760015 ps
CPU time 180.56 seconds
Started Aug 17 05:23:41 PM PDT 24
Finished Aug 17 05:26:41 PM PDT 24
Peak memory 200876 kb
Host smart-c590bb76-2f09-47b4-8a76-08c75e132345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133303294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3133303294
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3558899091
Short name T955
Test name
Test status
Simulation time 90526346363 ps
CPU time 34.26 seconds
Started Aug 17 05:23:42 PM PDT 24
Finished Aug 17 05:24:16 PM PDT 24
Peak memory 200900 kb
Host smart-4109ccdc-5b52-43a8-92c4-95210f779f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558899091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3558899091
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.519899037
Short name T894
Test name
Test status
Simulation time 121150185378 ps
CPU time 93.79 seconds
Started Aug 17 05:23:45 PM PDT 24
Finished Aug 17 05:25:19 PM PDT 24
Peak memory 200852 kb
Host smart-0282dfa4-4e4b-4be7-8809-ecd3bdbdc0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519899037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.519899037
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1923941774
Short name T662
Test name
Test status
Simulation time 14634889 ps
CPU time 0.6 seconds
Started Aug 17 05:09:44 PM PDT 24
Finished Aug 17 05:09:45 PM PDT 24
Peak memory 196256 kb
Host smart-8483bd79-bcb0-4f10-8338-61d5385ddd01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923941774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1923941774
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2967604868
Short name T1166
Test name
Test status
Simulation time 175854317144 ps
CPU time 202.49 seconds
Started Aug 17 05:09:38 PM PDT 24
Finished Aug 17 05:13:00 PM PDT 24
Peak memory 200756 kb
Host smart-d59a9f47-cd7a-4f7a-9c15-a76b4530c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967604868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2967604868
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3819160535
Short name T318
Test name
Test status
Simulation time 46442144075 ps
CPU time 42.21 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:10:22 PM PDT 24
Peak memory 200836 kb
Host smart-0cd6e8a4-b3b7-47b2-930a-a041911f5937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819160535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3819160535
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.301550060
Short name T800
Test name
Test status
Simulation time 149127137664 ps
CPU time 106.55 seconds
Started Aug 17 05:09:42 PM PDT 24
Finished Aug 17 05:11:29 PM PDT 24
Peak memory 200700 kb
Host smart-572d723a-30de-4aaf-8715-ec094406b38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301550060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.301550060
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1029333261
Short name T1159
Test name
Test status
Simulation time 9054049018 ps
CPU time 8 seconds
Started Aug 17 05:09:38 PM PDT 24
Finished Aug 17 05:09:46 PM PDT 24
Peak memory 197956 kb
Host smart-4f35e04d-311b-4932-95e2-01a19faec92d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029333261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1029333261
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3861868162
Short name T699
Test name
Test status
Simulation time 74668247280 ps
CPU time 225.53 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:13:25 PM PDT 24
Peak memory 200888 kb
Host smart-9f87b502-9133-4531-8040-9de88571a716
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861868162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3861868162
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3204584148
Short name T821
Test name
Test status
Simulation time 11046229629 ps
CPU time 20.63 seconds
Started Aug 17 05:09:37 PM PDT 24
Finished Aug 17 05:09:58 PM PDT 24
Peak memory 200640 kb
Host smart-966c031e-fce8-4834-a3ea-c4bcda782ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204584148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3204584148
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2090260017
Short name T866
Test name
Test status
Simulation time 141867699799 ps
CPU time 92.92 seconds
Started Aug 17 05:09:38 PM PDT 24
Finished Aug 17 05:11:11 PM PDT 24
Peak memory 200228 kb
Host smart-d5dbd632-2365-4140-804c-cd0d9f824de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090260017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2090260017
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1744458120
Short name T1014
Test name
Test status
Simulation time 10641489483 ps
CPU time 594.86 seconds
Started Aug 17 05:09:41 PM PDT 24
Finished Aug 17 05:19:36 PM PDT 24
Peak memory 200952 kb
Host smart-fc12818d-592e-492f-b1ce-4b313ad0fe2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1744458120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1744458120
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2164958025
Short name T444
Test name
Test status
Simulation time 2329539027 ps
CPU time 13.3 seconds
Started Aug 17 05:09:38 PM PDT 24
Finished Aug 17 05:09:51 PM PDT 24
Peak memory 200104 kb
Host smart-229e56d5-4361-4373-99fd-0cf660d6dc8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164958025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2164958025
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3479804775
Short name T49
Test name
Test status
Simulation time 16049310075 ps
CPU time 53.04 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:10:32 PM PDT 24
Peak memory 200960 kb
Host smart-c8a0212f-9a9f-46bb-8e4a-9976043f4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479804775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3479804775
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.135778410
Short name T663
Test name
Test status
Simulation time 3870415008 ps
CPU time 3.93 seconds
Started Aug 17 05:09:38 PM PDT 24
Finished Aug 17 05:09:42 PM PDT 24
Peak memory 197388 kb
Host smart-489ffef8-32e4-4d87-91f8-6a2b6c476361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135778410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.135778410
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.2104373910
Short name T326
Test name
Test status
Simulation time 540922402 ps
CPU time 1.47 seconds
Started Aug 17 05:09:40 PM PDT 24
Finished Aug 17 05:09:41 PM PDT 24
Peak memory 199828 kb
Host smart-269a93ff-2fb2-4b11-a1cb-9cfcd4ac52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104373910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2104373910
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3770486569
Short name T532
Test name
Test status
Simulation time 398564082128 ps
CPU time 351.48 seconds
Started Aug 17 05:09:41 PM PDT 24
Finished Aug 17 05:15:33 PM PDT 24
Peak memory 217392 kb
Host smart-15d572cc-b182-4950-b32b-a315f1a2b512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770486569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3770486569
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.4280291255
Short name T1055
Test name
Test status
Simulation time 4639518387 ps
CPU time 103.35 seconds
Started Aug 17 05:09:40 PM PDT 24
Finished Aug 17 05:11:24 PM PDT 24
Peak memory 217384 kb
Host smart-8fc0314e-b0cb-4037-847c-c9f9f3031dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280291255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.4280291255
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3371999126
Short name T364
Test name
Test status
Simulation time 541927954 ps
CPU time 2.2 seconds
Started Aug 17 05:09:40 PM PDT 24
Finished Aug 17 05:09:42 PM PDT 24
Peak memory 199744 kb
Host smart-2d180bad-0973-4d96-b623-d2ace0f05e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371999126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3371999126
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4235855271
Short name T738
Test name
Test status
Simulation time 26230095007 ps
CPU time 41.07 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:10:20 PM PDT 24
Peak memory 200912 kb
Host smart-f1ca3bb4-394b-43be-83e1-489514eb9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235855271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4235855271
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.377967681
Short name T799
Test name
Test status
Simulation time 40258662 ps
CPU time 0.57 seconds
Started Aug 17 05:13:44 PM PDT 24
Finished Aug 17 05:13:45 PM PDT 24
Peak memory 196260 kb
Host smart-b3c24df9-0220-45b9-84c3-b2ad524d7936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377967681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.377967681
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2172730192
Short name T713
Test name
Test status
Simulation time 51532491777 ps
CPU time 27.12 seconds
Started Aug 17 05:13:37 PM PDT 24
Finished Aug 17 05:14:04 PM PDT 24
Peak memory 200920 kb
Host smart-44d98f1c-f81e-41cb-be09-50ae14913969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172730192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2172730192
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.4230666252
Short name T1130
Test name
Test status
Simulation time 103118900567 ps
CPU time 49.7 seconds
Started Aug 17 05:13:37 PM PDT 24
Finished Aug 17 05:14:27 PM PDT 24
Peak memory 200876 kb
Host smart-750e4259-23df-4664-acb8-a688d5d1ff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230666252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.4230666252
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2606453147
Short name T961
Test name
Test status
Simulation time 63289906625 ps
CPU time 34.88 seconds
Started Aug 17 05:13:37 PM PDT 24
Finished Aug 17 05:14:12 PM PDT 24
Peak memory 200928 kb
Host smart-11363b45-68bf-4451-adcf-4a5612790d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606453147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2606453147
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2856430062
Short name T808
Test name
Test status
Simulation time 240262277962 ps
CPU time 211.64 seconds
Started Aug 17 05:13:37 PM PDT 24
Finished Aug 17 05:17:09 PM PDT 24
Peak memory 200980 kb
Host smart-343e10de-78ed-4fb9-a2df-c64dcf5bfc59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856430062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2856430062
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3775118883
Short name T44
Test name
Test status
Simulation time 87713115889 ps
CPU time 293.01 seconds
Started Aug 17 05:13:44 PM PDT 24
Finished Aug 17 05:18:37 PM PDT 24
Peak memory 200940 kb
Host smart-6ddf990f-793a-4b6a-8790-bc62ecdfaf50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775118883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3775118883
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.491670734
Short name T1101
Test name
Test status
Simulation time 10675338919 ps
CPU time 12.15 seconds
Started Aug 17 05:13:45 PM PDT 24
Finished Aug 17 05:13:58 PM PDT 24
Peak memory 199384 kb
Host smart-2797f419-d961-414b-9363-c35d4d7309fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491670734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.491670734
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.917764247
Short name T461
Test name
Test status
Simulation time 40892466358 ps
CPU time 13.99 seconds
Started Aug 17 05:13:37 PM PDT 24
Finished Aug 17 05:13:51 PM PDT 24
Peak memory 196352 kb
Host smart-ce9f53a7-1145-48f9-8758-ed4bf5ab666d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917764247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.917764247
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1659028070
Short name T708
Test name
Test status
Simulation time 11688076989 ps
CPU time 340.93 seconds
Started Aug 17 05:13:54 PM PDT 24
Finished Aug 17 05:19:35 PM PDT 24
Peak memory 200928 kb
Host smart-01c43346-456b-4476-8271-1632f9c4d1a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659028070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1659028070
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2285402727
Short name T1009
Test name
Test status
Simulation time 2342156059 ps
CPU time 12.89 seconds
Started Aug 17 05:13:42 PM PDT 24
Finished Aug 17 05:13:55 PM PDT 24
Peak memory 200136 kb
Host smart-4d3b80f7-d3e6-4d9d-a6d6-9c08aa36cec3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2285402727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2285402727
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.41769347
Short name T1161
Test name
Test status
Simulation time 66895285360 ps
CPU time 107.3 seconds
Started Aug 17 05:13:36 PM PDT 24
Finished Aug 17 05:15:24 PM PDT 24
Peak memory 200880 kb
Host smart-c0af613a-6b66-4a50-962c-5d9cc79a11b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41769347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.41769347
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2176692650
Short name T440
Test name
Test status
Simulation time 5538827512 ps
CPU time 9.1 seconds
Started Aug 17 05:13:37 PM PDT 24
Finished Aug 17 05:13:46 PM PDT 24
Peak memory 197080 kb
Host smart-0f267fb3-1e97-4506-93a0-644d67155a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176692650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2176692650
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.799953901
Short name T480
Test name
Test status
Simulation time 5543662581 ps
CPU time 28.8 seconds
Started Aug 17 05:13:37 PM PDT 24
Finished Aug 17 05:14:06 PM PDT 24
Peak memory 200848 kb
Host smart-05193e92-7ea8-4de0-b652-4fe4ed322d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799953901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.799953901
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3786334412
Short name T771
Test name
Test status
Simulation time 1838174752 ps
CPU time 22.78 seconds
Started Aug 17 05:13:43 PM PDT 24
Finished Aug 17 05:14:06 PM PDT 24
Peak memory 209332 kb
Host smart-bdde4b75-48e6-44d8-a014-82052f2a89c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786334412 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3786334412
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1871968910
Short name T849
Test name
Test status
Simulation time 1106554593 ps
CPU time 1.67 seconds
Started Aug 17 05:13:43 PM PDT 24
Finished Aug 17 05:13:45 PM PDT 24
Peak memory 199424 kb
Host smart-6d5e64b0-b95a-4ff5-bfa7-314666b8bfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871968910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1871968910
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2772756265
Short name T1174
Test name
Test status
Simulation time 27051292654 ps
CPU time 8.65 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:23:49 PM PDT 24
Peak memory 200940 kb
Host smart-34fa817e-804e-4c79-a6b1-270bf2c0f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772756265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2772756265
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2598090108
Short name T1033
Test name
Test status
Simulation time 10783897430 ps
CPU time 11.06 seconds
Started Aug 17 05:23:41 PM PDT 24
Finished Aug 17 05:23:52 PM PDT 24
Peak memory 200780 kb
Host smart-b59f9c14-162a-4b28-8666-99c6cad6e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598090108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2598090108
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1423518651
Short name T262
Test name
Test status
Simulation time 91233869365 ps
CPU time 45.53 seconds
Started Aug 17 05:23:43 PM PDT 24
Finished Aug 17 05:24:28 PM PDT 24
Peak memory 200916 kb
Host smart-67a3caef-7643-40bc-b5d4-e2b4c3260959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423518651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1423518651
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2338516478
Short name T377
Test name
Test status
Simulation time 59054296344 ps
CPU time 88.19 seconds
Started Aug 17 05:23:41 PM PDT 24
Finished Aug 17 05:25:09 PM PDT 24
Peak memory 200816 kb
Host smart-65bcae77-c709-4131-a8df-9a8d782c7c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338516478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2338516478
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3946189407
Short name T481
Test name
Test status
Simulation time 50247053934 ps
CPU time 67.71 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:24:48 PM PDT 24
Peak memory 200928 kb
Host smart-ad5201ba-6aaa-4469-bda8-dcddfa530dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946189407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3946189407
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1490653676
Short name T1001
Test name
Test status
Simulation time 75192516146 ps
CPU time 132.86 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:25:53 PM PDT 24
Peak memory 200848 kb
Host smart-2a06601b-486b-4882-a5e6-6c15d74882b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490653676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1490653676
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3752575634
Short name T192
Test name
Test status
Simulation time 29770778537 ps
CPU time 24.86 seconds
Started Aug 17 05:23:42 PM PDT 24
Finished Aug 17 05:24:07 PM PDT 24
Peak memory 200920 kb
Host smart-ac5809ff-e76d-4236-8208-0d08534f3446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752575634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3752575634
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1194317037
Short name T1006
Test name
Test status
Simulation time 145448351924 ps
CPU time 54.05 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:24:34 PM PDT 24
Peak memory 200956 kb
Host smart-909e6d29-12ad-410b-accc-c5c8cb799067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194317037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1194317037
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.66588451
Short name T1088
Test name
Test status
Simulation time 74577778 ps
CPU time 0.58 seconds
Started Aug 17 05:14:09 PM PDT 24
Finished Aug 17 05:14:10 PM PDT 24
Peak memory 196216 kb
Host smart-7d024a85-5c2c-4da2-b06e-17e0750d5a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66588451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.66588451
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4046077723
Short name T633
Test name
Test status
Simulation time 113652939079 ps
CPU time 64.51 seconds
Started Aug 17 05:13:43 PM PDT 24
Finished Aug 17 05:14:48 PM PDT 24
Peak memory 200908 kb
Host smart-62683bf5-76ca-4db5-bfc1-33b51a6d47c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046077723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4046077723
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.389858565
Short name T568
Test name
Test status
Simulation time 16767307998 ps
CPU time 26.62 seconds
Started Aug 17 05:13:54 PM PDT 24
Finished Aug 17 05:14:21 PM PDT 24
Peak memory 200924 kb
Host smart-99736fcb-4f5c-4089-9fb8-7033b0c8b8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389858565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.389858565
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3510580863
Short name T288
Test name
Test status
Simulation time 34618788920 ps
CPU time 16.81 seconds
Started Aug 17 05:13:51 PM PDT 24
Finished Aug 17 05:14:08 PM PDT 24
Peak memory 200956 kb
Host smart-f62ad3c7-8483-4499-9361-d353a332e181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510580863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3510580863
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1285297980
Short name T888
Test name
Test status
Simulation time 30990510788 ps
CPU time 13.1 seconds
Started Aug 17 05:13:52 PM PDT 24
Finished Aug 17 05:14:05 PM PDT 24
Peak memory 199468 kb
Host smart-b123eb2a-9173-4399-b225-8567d16ac9ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285297980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1285297980
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.59875310
Short name T499
Test name
Test status
Simulation time 119999551089 ps
CPU time 565.3 seconds
Started Aug 17 05:14:09 PM PDT 24
Finished Aug 17 05:23:34 PM PDT 24
Peak memory 200908 kb
Host smart-02d37e4a-0f7a-44b7-8355-f83681f54585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59875310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.59875310
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1026878269
Short name T2
Test name
Test status
Simulation time 7001931892 ps
CPU time 7.28 seconds
Started Aug 17 05:14:01 PM PDT 24
Finished Aug 17 05:14:09 PM PDT 24
Peak memory 199672 kb
Host smart-3ac9a4d2-0c5f-4bee-842b-237f081cdce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026878269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1026878269
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.4048008020
Short name T973
Test name
Test status
Simulation time 113637533212 ps
CPU time 43.52 seconds
Started Aug 17 05:13:51 PM PDT 24
Finished Aug 17 05:14:35 PM PDT 24
Peak memory 201008 kb
Host smart-6ffa6537-5e8d-483f-ae3e-43cc95f1b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048008020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4048008020
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.458319753
Short name T429
Test name
Test status
Simulation time 26968134900 ps
CPU time 359.07 seconds
Started Aug 17 05:14:09 PM PDT 24
Finished Aug 17 05:20:08 PM PDT 24
Peak memory 200972 kb
Host smart-c7250ed5-0792-4f33-b74b-d03b74ce18b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458319753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.458319753
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.414332373
Short name T1152
Test name
Test status
Simulation time 6965159007 ps
CPU time 25.75 seconds
Started Aug 17 05:13:51 PM PDT 24
Finished Aug 17 05:14:17 PM PDT 24
Peak memory 199000 kb
Host smart-f265f147-72a6-4429-9ed6-35a203228a1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414332373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.414332373
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2790263598
Short name T763
Test name
Test status
Simulation time 4555716662 ps
CPU time 2.6 seconds
Started Aug 17 05:13:53 PM PDT 24
Finished Aug 17 05:13:56 PM PDT 24
Peak memory 197160 kb
Host smart-30dd4c20-308e-4316-ac1a-ce133bc67031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790263598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2790263598
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3840860526
Short name T471
Test name
Test status
Simulation time 803402662 ps
CPU time 4.61 seconds
Started Aug 17 05:13:46 PM PDT 24
Finished Aug 17 05:13:51 PM PDT 24
Peak memory 200412 kb
Host smart-27642f47-2348-4c1b-9459-bae5507dd8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840860526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3840860526
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3485778373
Short name T701
Test name
Test status
Simulation time 213515893971 ps
CPU time 216.35 seconds
Started Aug 17 05:14:03 PM PDT 24
Finished Aug 17 05:17:39 PM PDT 24
Peak memory 200868 kb
Host smart-c3430925-c1bf-4a74-824d-f57f4c0684f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485778373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3485778373
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.834494601
Short name T1019
Test name
Test status
Simulation time 4704940387 ps
CPU time 36.52 seconds
Started Aug 17 05:14:09 PM PDT 24
Finished Aug 17 05:14:45 PM PDT 24
Peak memory 216900 kb
Host smart-e31a70a0-ed52-445f-9c4a-2b701e8bf074
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834494601 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.834494601
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1268103126
Short name T1020
Test name
Test status
Simulation time 850658907 ps
CPU time 1.92 seconds
Started Aug 17 05:13:59 PM PDT 24
Finished Aug 17 05:14:01 PM PDT 24
Peak memory 199356 kb
Host smart-68043d46-7cb3-4c0c-a6b9-4e15c6ffae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268103126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1268103126
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.4236390259
Short name T464
Test name
Test status
Simulation time 27055026214 ps
CPU time 42.2 seconds
Started Aug 17 05:13:46 PM PDT 24
Finished Aug 17 05:14:28 PM PDT 24
Peak memory 200928 kb
Host smart-db13af44-d2ea-4a00-802e-57395bc7e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236390259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.4236390259
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1374061031
Short name T893
Test name
Test status
Simulation time 27100698612 ps
CPU time 21.62 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:24:02 PM PDT 24
Peak memory 200848 kb
Host smart-99729dcf-49dc-4cbf-a629-2c6ebdaa019d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374061031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1374061031
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.96409309
Short name T159
Test name
Test status
Simulation time 31158684380 ps
CPU time 14.75 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:23:55 PM PDT 24
Peak memory 200824 kb
Host smart-cbd0a782-405f-482d-901c-2248a73eff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96409309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.96409309
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1815110380
Short name T1039
Test name
Test status
Simulation time 130445085352 ps
CPU time 28.02 seconds
Started Aug 17 05:23:42 PM PDT 24
Finished Aug 17 05:24:10 PM PDT 24
Peak memory 200964 kb
Host smart-c849f6fd-b2b6-43fb-9387-9f16f48e2a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815110380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1815110380
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2751756343
Short name T1089
Test name
Test status
Simulation time 18876336864 ps
CPU time 27.66 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:24:08 PM PDT 24
Peak memory 200932 kb
Host smart-eeae9e88-3b83-452e-a276-6258caed7cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751756343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2751756343
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1875832306
Short name T1050
Test name
Test status
Simulation time 33282951009 ps
CPU time 45.57 seconds
Started Aug 17 05:23:43 PM PDT 24
Finished Aug 17 05:24:29 PM PDT 24
Peak memory 200956 kb
Host smart-a24f8200-78a7-41ba-b5cb-a20affcb19ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875832306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1875832306
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2397713739
Short name T969
Test name
Test status
Simulation time 22530215528 ps
CPU time 17.71 seconds
Started Aug 17 05:23:41 PM PDT 24
Finished Aug 17 05:23:59 PM PDT 24
Peak memory 200928 kb
Host smart-0116c787-ec49-48ee-8618-fe28dd225c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397713739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2397713739
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.466482870
Short name T169
Test name
Test status
Simulation time 18473402242 ps
CPU time 29.4 seconds
Started Aug 17 05:23:40 PM PDT 24
Finished Aug 17 05:24:10 PM PDT 24
Peak memory 200956 kb
Host smart-d75abdf6-6e45-48d9-946b-d48ca09de0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466482870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.466482870
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.697202996
Short name T1010
Test name
Test status
Simulation time 37862167295 ps
CPU time 46.1 seconds
Started Aug 17 05:23:42 PM PDT 24
Finished Aug 17 05:24:28 PM PDT 24
Peak memory 200912 kb
Host smart-ef2c6e60-34fe-470b-9cf7-346aac0a5b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697202996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.697202996
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2383029159
Short name T712
Test name
Test status
Simulation time 132521588608 ps
CPU time 114.73 seconds
Started Aug 17 05:23:49 PM PDT 24
Finished Aug 17 05:25:44 PM PDT 24
Peak memory 200964 kb
Host smart-241e1685-49a5-44f1-acfd-790e3905e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383029159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2383029159
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1596443085
Short name T729
Test name
Test status
Simulation time 13857342 ps
CPU time 0.57 seconds
Started Aug 17 05:14:23 PM PDT 24
Finished Aug 17 05:14:24 PM PDT 24
Peak memory 196540 kb
Host smart-6ea3eec7-707c-4e9a-bb51-58dedcfaac7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596443085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1596443085
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2906538770
Short name T335
Test name
Test status
Simulation time 143331078537 ps
CPU time 464.35 seconds
Started Aug 17 05:14:08 PM PDT 24
Finished Aug 17 05:21:52 PM PDT 24
Peak memory 200840 kb
Host smart-a16a4646-9fdb-4e0c-b66e-b7ae6285832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906538770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2906538770
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1384411284
Short name T190
Test name
Test status
Simulation time 55599037475 ps
CPU time 40.76 seconds
Started Aug 17 05:14:09 PM PDT 24
Finished Aug 17 05:14:50 PM PDT 24
Peak memory 200648 kb
Host smart-8af63d57-606a-4608-b3bb-84b322ed4f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384411284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1384411284
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.832002518
Short name T133
Test name
Test status
Simulation time 180262944570 ps
CPU time 175.04 seconds
Started Aug 17 05:14:11 PM PDT 24
Finished Aug 17 05:17:06 PM PDT 24
Peak memory 200948 kb
Host smart-9c38c576-5a8a-4c8c-b4b5-d8b90b54310e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832002518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.832002518
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3355424005
Short name T549
Test name
Test status
Simulation time 53206561756 ps
CPU time 33.79 seconds
Started Aug 17 05:14:08 PM PDT 24
Finished Aug 17 05:14:41 PM PDT 24
Peak memory 200956 kb
Host smart-98f37c2a-6d05-43cf-b033-26ff7f957c77
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355424005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3355424005
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2379931060
Short name T406
Test name
Test status
Simulation time 214483328760 ps
CPU time 291.36 seconds
Started Aug 17 05:14:16 PM PDT 24
Finished Aug 17 05:19:07 PM PDT 24
Peak memory 200892 kb
Host smart-723ac3b5-db58-4e5f-9901-49592683a296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2379931060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2379931060
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2431281802
Short name T1097
Test name
Test status
Simulation time 4548609494 ps
CPU time 3.61 seconds
Started Aug 17 05:14:21 PM PDT 24
Finished Aug 17 05:14:24 PM PDT 24
Peak memory 199584 kb
Host smart-3393cd8c-805c-4911-ac5e-58906c14fd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431281802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2431281802
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2369755008
Short name T362
Test name
Test status
Simulation time 49037591110 ps
CPU time 22.45 seconds
Started Aug 17 05:14:09 PM PDT 24
Finished Aug 17 05:14:32 PM PDT 24
Peak memory 200912 kb
Host smart-eaebd625-313c-407f-8228-8e4bdca0ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369755008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2369755008
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1879386606
Short name T42
Test name
Test status
Simulation time 20045372805 ps
CPU time 276.89 seconds
Started Aug 17 05:14:22 PM PDT 24
Finished Aug 17 05:18:59 PM PDT 24
Peak memory 200852 kb
Host smart-320ffde7-2140-4047-a8a9-5da2fbaa7b30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879386606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1879386606
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1096494287
Short name T717
Test name
Test status
Simulation time 6310113496 ps
CPU time 38.1 seconds
Started Aug 17 05:14:08 PM PDT 24
Finished Aug 17 05:14:47 PM PDT 24
Peak memory 199200 kb
Host smart-2078d8a8-a467-41fe-989a-5792c855d7ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096494287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1096494287
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.311953159
Short name T149
Test name
Test status
Simulation time 67444039182 ps
CPU time 28.44 seconds
Started Aug 17 05:14:16 PM PDT 24
Finished Aug 17 05:14:45 PM PDT 24
Peak memory 200932 kb
Host smart-54601811-8036-4560-84eb-b7632e71f92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311953159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.311953159
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1531401557
Short name T696
Test name
Test status
Simulation time 4615936169 ps
CPU time 7.53 seconds
Started Aug 17 05:14:09 PM PDT 24
Finished Aug 17 05:14:17 PM PDT 24
Peak memory 197776 kb
Host smart-d4282003-dad1-4775-8b49-3fe254b6090a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531401557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1531401557
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2446771693
Short name T393
Test name
Test status
Simulation time 297755410 ps
CPU time 1.16 seconds
Started Aug 17 05:14:08 PM PDT 24
Finished Aug 17 05:14:09 PM PDT 24
Peak memory 199624 kb
Host smart-e33b1e31-8bad-4227-9f42-6b29a5d94c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446771693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2446771693
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2743104502
Short name T739
Test name
Test status
Simulation time 9392917446 ps
CPU time 28.01 seconds
Started Aug 17 05:14:15 PM PDT 24
Finished Aug 17 05:14:44 PM PDT 24
Peak memory 217136 kb
Host smart-5b739d97-ba8f-466d-b4a3-d31b1b2b07a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743104502 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2743104502
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1411470106
Short name T389
Test name
Test status
Simulation time 384113953 ps
CPU time 1.51 seconds
Started Aug 17 05:14:14 PM PDT 24
Finished Aug 17 05:14:16 PM PDT 24
Peak memory 199204 kb
Host smart-0e5eab28-631f-40d6-8f8d-2a30f82b7bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411470106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1411470106
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4268175626
Short name T654
Test name
Test status
Simulation time 48980368260 ps
CPU time 18.02 seconds
Started Aug 17 05:14:08 PM PDT 24
Finished Aug 17 05:14:26 PM PDT 24
Peak memory 200948 kb
Host smart-226c5604-c450-4f5e-bc43-d93dd6cf9256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268175626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4268175626
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2657761701
Short name T685
Test name
Test status
Simulation time 9112124820 ps
CPU time 31.2 seconds
Started Aug 17 05:23:51 PM PDT 24
Finished Aug 17 05:24:23 PM PDT 24
Peak memory 200932 kb
Host smart-18f69df9-d656-49b0-9502-386169544f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657761701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2657761701
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.4047945766
Short name T520
Test name
Test status
Simulation time 49107025920 ps
CPU time 21.62 seconds
Started Aug 17 05:23:50 PM PDT 24
Finished Aug 17 05:24:12 PM PDT 24
Peak memory 200852 kb
Host smart-e125cfa6-b671-4b98-b498-6179e2cf688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047945766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.4047945766
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1142843948
Short name T274
Test name
Test status
Simulation time 30215969429 ps
CPU time 13.6 seconds
Started Aug 17 05:23:48 PM PDT 24
Finished Aug 17 05:24:02 PM PDT 24
Peak memory 200836 kb
Host smart-f96fcfae-1c8f-4793-9691-bc398b918bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142843948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1142843948
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.201876106
Short name T337
Test name
Test status
Simulation time 46194216216 ps
CPU time 12.39 seconds
Started Aug 17 05:23:52 PM PDT 24
Finished Aug 17 05:24:04 PM PDT 24
Peak memory 200716 kb
Host smart-5337c5ef-f5d4-4871-8249-03c3aab1c815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201876106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.201876106
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2344470380
Short name T213
Test name
Test status
Simulation time 70388553021 ps
CPU time 47.36 seconds
Started Aug 17 05:23:50 PM PDT 24
Finished Aug 17 05:24:37 PM PDT 24
Peak memory 200880 kb
Host smart-e768d786-94d0-4e67-a527-1e7c0ffdafe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344470380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2344470380
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1679619436
Short name T1078
Test name
Test status
Simulation time 232547119222 ps
CPU time 302.43 seconds
Started Aug 17 05:23:51 PM PDT 24
Finished Aug 17 05:28:54 PM PDT 24
Peak memory 200864 kb
Host smart-2d5f3738-49fd-4e44-aad7-fce319fffd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679619436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1679619436
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3274523517
Short name T680
Test name
Test status
Simulation time 26784308438 ps
CPU time 24.59 seconds
Started Aug 17 05:23:50 PM PDT 24
Finished Aug 17 05:24:15 PM PDT 24
Peak memory 200956 kb
Host smart-5e779821-549f-4289-98a3-4e8e4ba4618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274523517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3274523517
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.231396599
Short name T647
Test name
Test status
Simulation time 13907125830 ps
CPU time 63.05 seconds
Started Aug 17 05:23:51 PM PDT 24
Finished Aug 17 05:24:54 PM PDT 24
Peak memory 200904 kb
Host smart-75201fd4-454f-47c8-a1b5-595d826f1f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231396599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.231396599
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1194044461
Short name T363
Test name
Test status
Simulation time 101450769757 ps
CPU time 51.57 seconds
Started Aug 17 05:23:56 PM PDT 24
Finished Aug 17 05:24:47 PM PDT 24
Peak memory 200892 kb
Host smart-4f5bde2c-eee7-4ddb-88c1-a328072600a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194044461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1194044461
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1101545602
Short name T1111
Test name
Test status
Simulation time 117572697918 ps
CPU time 166.38 seconds
Started Aug 17 05:23:48 PM PDT 24
Finished Aug 17 05:26:35 PM PDT 24
Peak memory 200940 kb
Host smart-981929fa-15f2-471d-abf9-d0e975e8547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101545602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1101545602
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.689960125
Short name T705
Test name
Test status
Simulation time 26143973 ps
CPU time 0.58 seconds
Started Aug 17 05:14:42 PM PDT 24
Finished Aug 17 05:14:42 PM PDT 24
Peak memory 196552 kb
Host smart-a79b231e-b136-4f74-88ce-162a3169ecc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689960125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.689960125
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.188319436
Short name T308
Test name
Test status
Simulation time 140403983577 ps
CPU time 241.33 seconds
Started Aug 17 05:14:24 PM PDT 24
Finished Aug 17 05:18:26 PM PDT 24
Peak memory 200964 kb
Host smart-901d1618-9bd1-4c8f-9dff-10edcd1dfa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188319436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.188319436
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.571399297
Short name T204
Test name
Test status
Simulation time 22673810581 ps
CPU time 10.03 seconds
Started Aug 17 05:14:24 PM PDT 24
Finished Aug 17 05:14:34 PM PDT 24
Peak memory 200820 kb
Host smart-cd634dab-f96b-4a6a-ad92-f9072a91adb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571399297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.571399297
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4122463578
Short name T243
Test name
Test status
Simulation time 107309708690 ps
CPU time 165.78 seconds
Started Aug 17 05:14:36 PM PDT 24
Finished Aug 17 05:17:22 PM PDT 24
Peak memory 200956 kb
Host smart-2967c223-b20c-4267-beaf-2f7239af860b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122463578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4122463578
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1720333267
Short name T342
Test name
Test status
Simulation time 23528697575 ps
CPU time 3.53 seconds
Started Aug 17 05:14:33 PM PDT 24
Finished Aug 17 05:14:37 PM PDT 24
Peak memory 199256 kb
Host smart-fa49912b-37a4-45b6-aba2-10e8ac5fbbe4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720333267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1720333267
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_loopback.3375358739
Short name T109
Test name
Test status
Simulation time 6387414156 ps
CPU time 12.48 seconds
Started Aug 17 05:14:32 PM PDT 24
Finished Aug 17 05:14:45 PM PDT 24
Peak memory 200620 kb
Host smart-2beb51bb-d223-42cd-8a34-84e836a18457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375358739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3375358739
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2702363778
Short name T450
Test name
Test status
Simulation time 69138722376 ps
CPU time 84.92 seconds
Started Aug 17 05:14:33 PM PDT 24
Finished Aug 17 05:15:58 PM PDT 24
Peak memory 209344 kb
Host smart-312531b0-ae84-4195-a882-07a77e9bd88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702363778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2702363778
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2094850878
Short name T780
Test name
Test status
Simulation time 26946995352 ps
CPU time 507.98 seconds
Started Aug 17 05:14:32 PM PDT 24
Finished Aug 17 05:23:00 PM PDT 24
Peak memory 200916 kb
Host smart-b401a876-de5e-4585-808d-01972e2f3f4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2094850878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2094850878
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1658238692
Short name T819
Test name
Test status
Simulation time 2136146755 ps
CPU time 3.56 seconds
Started Aug 17 05:14:33 PM PDT 24
Finished Aug 17 05:14:37 PM PDT 24
Peak memory 198708 kb
Host smart-e12040d0-2be2-4b4c-a107-e46aa3408563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658238692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1658238692
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3094168705
Short name T585
Test name
Test status
Simulation time 51711454594 ps
CPU time 92.32 seconds
Started Aug 17 05:14:32 PM PDT 24
Finished Aug 17 05:16:04 PM PDT 24
Peak memory 200944 kb
Host smart-d31c39e2-3394-408a-a0d4-b425956ba8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094168705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3094168705
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.518741288
Short name T1048
Test name
Test status
Simulation time 4161636475 ps
CPU time 2.26 seconds
Started Aug 17 05:14:31 PM PDT 24
Finished Aug 17 05:14:34 PM PDT 24
Peak memory 197428 kb
Host smart-863abe66-0f4a-4071-acf4-e46868b95a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518741288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.518741288
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1324925936
Short name T990
Test name
Test status
Simulation time 455256777 ps
CPU time 1.85 seconds
Started Aug 17 05:14:23 PM PDT 24
Finished Aug 17 05:14:25 PM PDT 24
Peak memory 199420 kb
Host smart-ce28ceaa-f241-4770-9366-1074f95e2b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324925936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1324925936
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1451375518
Short name T999
Test name
Test status
Simulation time 5938478220 ps
CPU time 63.61 seconds
Started Aug 17 05:14:43 PM PDT 24
Finished Aug 17 05:15:47 PM PDT 24
Peak memory 209172 kb
Host smart-96587520-9708-4760-a511-52723f122af6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451375518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1451375518
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2737226424
Short name T775
Test name
Test status
Simulation time 563614459 ps
CPU time 1.67 seconds
Started Aug 17 05:14:35 PM PDT 24
Finished Aug 17 05:14:37 PM PDT 24
Peak memory 200768 kb
Host smart-6743321b-31a8-42c1-840d-ad5b71de7d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737226424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2737226424
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.932878852
Short name T286
Test name
Test status
Simulation time 69790610756 ps
CPU time 109.35 seconds
Started Aug 17 05:14:24 PM PDT 24
Finished Aug 17 05:16:13 PM PDT 24
Peak memory 200876 kb
Host smart-903cec5f-c855-475a-a89e-969ffed8a65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932878852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.932878852
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3094851900
Short name T1077
Test name
Test status
Simulation time 168745422963 ps
CPU time 37.77 seconds
Started Aug 17 05:23:50 PM PDT 24
Finished Aug 17 05:24:28 PM PDT 24
Peak memory 200752 kb
Host smart-de817397-8f23-422d-ad7e-cd56ca1620f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094851900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3094851900
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1418299754
Short name T1038
Test name
Test status
Simulation time 25850688949 ps
CPU time 31.89 seconds
Started Aug 17 05:23:47 PM PDT 24
Finished Aug 17 05:24:19 PM PDT 24
Peak memory 200932 kb
Host smart-b1f01910-bad9-45a0-a5ec-eedf8d6f7b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418299754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1418299754
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2262378736
Short name T926
Test name
Test status
Simulation time 228605146952 ps
CPU time 129.86 seconds
Started Aug 17 05:23:54 PM PDT 24
Finished Aug 17 05:26:04 PM PDT 24
Peak memory 200936 kb
Host smart-2391596b-59ff-4b15-8649-9105cf9449ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262378736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2262378736
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3768222791
Short name T397
Test name
Test status
Simulation time 120251253135 ps
CPU time 79.25 seconds
Started Aug 17 05:23:55 PM PDT 24
Finished Aug 17 05:25:14 PM PDT 24
Peak memory 200940 kb
Host smart-f859cbf8-e43b-476c-b008-5da2e16faa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768222791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3768222791
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.921914676
Short name T260
Test name
Test status
Simulation time 53397573086 ps
CPU time 9.55 seconds
Started Aug 17 05:23:48 PM PDT 24
Finished Aug 17 05:23:58 PM PDT 24
Peak memory 200916 kb
Host smart-6a655a44-a138-4cd3-9b55-fdc0a9a62144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921914676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.921914676
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.4258016304
Short name T224
Test name
Test status
Simulation time 182278624885 ps
CPU time 68.82 seconds
Started Aug 17 05:23:50 PM PDT 24
Finished Aug 17 05:24:59 PM PDT 24
Peak memory 200904 kb
Host smart-b137dc2f-20e9-40cd-b310-d9b81330eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258016304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.4258016304
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2238188034
Short name T178
Test name
Test status
Simulation time 89054788596 ps
CPU time 120.07 seconds
Started Aug 17 05:23:48 PM PDT 24
Finished Aug 17 05:25:48 PM PDT 24
Peak memory 200916 kb
Host smart-601808af-fe27-4755-929e-9b7d908d5990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238188034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2238188034
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.754375768
Short name T768
Test name
Test status
Simulation time 246246821361 ps
CPU time 30.73 seconds
Started Aug 17 05:23:49 PM PDT 24
Finished Aug 17 05:24:20 PM PDT 24
Peak memory 200880 kb
Host smart-cfbb2240-432a-48da-aca7-e20007e69b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754375768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.754375768
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.709523882
Short name T433
Test name
Test status
Simulation time 40691660 ps
CPU time 0.57 seconds
Started Aug 17 05:15:00 PM PDT 24
Finished Aug 17 05:15:01 PM PDT 24
Peak memory 196324 kb
Host smart-a7f27168-2fd5-4e49-8486-8af88198bc94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709523882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.709523882
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3508094815
Short name T634
Test name
Test status
Simulation time 58123234207 ps
CPU time 30.99 seconds
Started Aug 17 05:14:41 PM PDT 24
Finished Aug 17 05:15:12 PM PDT 24
Peak memory 200920 kb
Host smart-3c6b0499-819e-4e75-9c15-c24f68d38552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508094815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3508094815
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_intr.3149885616
Short name T927
Test name
Test status
Simulation time 58367038489 ps
CPU time 25.17 seconds
Started Aug 17 05:14:50 PM PDT 24
Finished Aug 17 05:15:15 PM PDT 24
Peak memory 200896 kb
Host smart-f3aaaff6-89e3-4f19-86dd-f0fd3b47b90b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149885616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3149885616
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1088710747
Short name T652
Test name
Test status
Simulation time 148558845306 ps
CPU time 118.12 seconds
Started Aug 17 05:14:57 PM PDT 24
Finished Aug 17 05:16:55 PM PDT 24
Peak memory 200916 kb
Host smart-e2ca0b4b-30fe-4fc6-974d-3cc72de0bc45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088710747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1088710747
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2979953027
Short name T659
Test name
Test status
Simulation time 5248472539 ps
CPU time 6.58 seconds
Started Aug 17 05:15:01 PM PDT 24
Finished Aug 17 05:15:07 PM PDT 24
Peak memory 200664 kb
Host smart-0e8d5484-7c15-443d-920a-b7adcda13865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979953027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2979953027
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.959278221
Short name T555
Test name
Test status
Simulation time 205271937631 ps
CPU time 36.78 seconds
Started Aug 17 05:14:52 PM PDT 24
Finished Aug 17 05:15:29 PM PDT 24
Peak memory 210356 kb
Host smart-dad33a2b-826c-4050-8a81-3e28fa9582cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959278221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.959278221
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2702200571
Short name T497
Test name
Test status
Simulation time 21869286478 ps
CPU time 94.44 seconds
Started Aug 17 05:14:58 PM PDT 24
Finished Aug 17 05:16:33 PM PDT 24
Peak memory 200912 kb
Host smart-c7748395-1fbc-48e6-838c-a4140493c378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702200571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2702200571
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1104489520
Short name T1141
Test name
Test status
Simulation time 2534869055 ps
CPU time 12.66 seconds
Started Aug 17 05:14:48 PM PDT 24
Finished Aug 17 05:15:01 PM PDT 24
Peak memory 199156 kb
Host smart-45ee36b8-495a-4189-8780-09b64fd88769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104489520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1104489520
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3074678228
Short name T194
Test name
Test status
Simulation time 109747684867 ps
CPU time 23.59 seconds
Started Aug 17 05:14:51 PM PDT 24
Finished Aug 17 05:15:15 PM PDT 24
Peak memory 200880 kb
Host smart-d09c0174-9f52-48dc-b3c8-04dca8a7a307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074678228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3074678228
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3823930185
Short name T338
Test name
Test status
Simulation time 43015224111 ps
CPU time 17.89 seconds
Started Aug 17 05:14:50 PM PDT 24
Finished Aug 17 05:15:08 PM PDT 24
Peak memory 197416 kb
Host smart-9c509f01-1b9e-4ab1-87c7-707963a7acd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823930185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3823930185
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.415827630
Short name T316
Test name
Test status
Simulation time 524755998 ps
CPU time 1.42 seconds
Started Aug 17 05:14:40 PM PDT 24
Finished Aug 17 05:14:41 PM PDT 24
Peak memory 200436 kb
Host smart-fa509ccb-e0df-4691-8a94-06affa6e8f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415827630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.415827630
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4133700729
Short name T954
Test name
Test status
Simulation time 3103822678 ps
CPU time 37.61 seconds
Started Aug 17 05:14:58 PM PDT 24
Finished Aug 17 05:15:35 PM PDT 24
Peak memory 217592 kb
Host smart-d2357f1e-94d6-4a2d-b1d1-491dcfe163eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133700729 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4133700729
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3906390387
Short name T751
Test name
Test status
Simulation time 10005411753 ps
CPU time 6.72 seconds
Started Aug 17 05:14:48 PM PDT 24
Finished Aug 17 05:14:55 PM PDT 24
Peak memory 200920 kb
Host smart-9d1fedc0-2cc2-42f3-84cc-b2c33de51eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906390387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3906390387
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1256016143
Short name T1169
Test name
Test status
Simulation time 26255455797 ps
CPU time 38.11 seconds
Started Aug 17 05:14:41 PM PDT 24
Finished Aug 17 05:15:19 PM PDT 24
Peak memory 200940 kb
Host smart-e57cd2b0-dc61-4fc2-ad30-d59d2d6b37cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256016143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1256016143
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2862414010
Short name T294
Test name
Test status
Simulation time 43113333372 ps
CPU time 9.05 seconds
Started Aug 17 05:23:52 PM PDT 24
Finished Aug 17 05:24:01 PM PDT 24
Peak memory 200960 kb
Host smart-88ee9625-cd8a-4bb0-bd7b-2d2a26f032d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862414010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2862414010
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1506046723
Short name T1103
Test name
Test status
Simulation time 108228744045 ps
CPU time 184.34 seconds
Started Aug 17 05:23:52 PM PDT 24
Finished Aug 17 05:26:56 PM PDT 24
Peak memory 200804 kb
Host smart-e12f07de-51ea-42b7-a9b5-f29fca5e5406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506046723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1506046723
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2190287781
Short name T609
Test name
Test status
Simulation time 24953204179 ps
CPU time 42.8 seconds
Started Aug 17 05:23:48 PM PDT 24
Finished Aug 17 05:24:31 PM PDT 24
Peak memory 200848 kb
Host smart-0b4f3571-2b23-472d-87c6-4edbad3fb064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190287781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2190287781
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4222733389
Short name T1012
Test name
Test status
Simulation time 48611244306 ps
CPU time 19.68 seconds
Started Aug 17 05:24:01 PM PDT 24
Finished Aug 17 05:24:20 PM PDT 24
Peak memory 200932 kb
Host smart-2ee94a76-9ab4-463b-b32a-b30e5788c851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222733389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4222733389
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3170637737
Short name T567
Test name
Test status
Simulation time 7012320738 ps
CPU time 11.36 seconds
Started Aug 17 05:24:00 PM PDT 24
Finished Aug 17 05:24:11 PM PDT 24
Peak memory 200880 kb
Host smart-ba64df56-3b41-40f9-bd00-7a666fefc81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170637737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3170637737
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3282193475
Short name T873
Test name
Test status
Simulation time 136363562458 ps
CPU time 66.38 seconds
Started Aug 17 05:23:59 PM PDT 24
Finished Aug 17 05:25:05 PM PDT 24
Peak memory 200940 kb
Host smart-0d3d10bc-4701-433a-8b98-a9e3be0680b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282193475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3282193475
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.496674527
Short name T1037
Test name
Test status
Simulation time 9989310185 ps
CPU time 15.1 seconds
Started Aug 17 05:24:01 PM PDT 24
Finished Aug 17 05:24:16 PM PDT 24
Peak memory 200808 kb
Host smart-7ae82f1c-7e60-47b9-a21d-f2dab0507792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496674527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.496674527
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1239349238
Short name T1093
Test name
Test status
Simulation time 47401363942 ps
CPU time 17.58 seconds
Started Aug 17 05:24:00 PM PDT 24
Finished Aug 17 05:24:18 PM PDT 24
Peak memory 200940 kb
Host smart-f15b4be1-07c2-46cd-9c26-4e39961e6d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239349238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1239349238
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.839310248
Short name T218
Test name
Test status
Simulation time 62158350673 ps
CPU time 29.33 seconds
Started Aug 17 05:23:59 PM PDT 24
Finished Aug 17 05:24:29 PM PDT 24
Peak memory 200956 kb
Host smart-e9601dd8-bbf7-41d2-9bb3-8f5e877b2c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839310248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.839310248
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3013439432
Short name T405
Test name
Test status
Simulation time 42117288 ps
CPU time 0.56 seconds
Started Aug 17 05:15:13 PM PDT 24
Finished Aug 17 05:15:14 PM PDT 24
Peak memory 196536 kb
Host smart-f3ba2323-d532-4827-a060-441f9c1bea85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013439432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3013439432
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.669516227
Short name T299
Test name
Test status
Simulation time 77587934419 ps
CPU time 168 seconds
Started Aug 17 05:14:57 PM PDT 24
Finished Aug 17 05:17:45 PM PDT 24
Peak memory 200832 kb
Host smart-962c8827-1747-4f52-bdf4-6befccd60af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669516227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.669516227
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1013449715
Short name T445
Test name
Test status
Simulation time 29361695464 ps
CPU time 53.4 seconds
Started Aug 17 05:15:05 PM PDT 24
Finished Aug 17 05:15:59 PM PDT 24
Peak memory 200852 kb
Host smart-8a28e441-6088-48f9-9e87-10dad0dc0983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013449715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1013449715
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3166099824
Short name T612
Test name
Test status
Simulation time 8799907671 ps
CPU time 14.32 seconds
Started Aug 17 05:15:05 PM PDT 24
Finished Aug 17 05:15:19 PM PDT 24
Peak memory 200700 kb
Host smart-54a8b8d1-a5f8-4d7e-b14c-9cd59d1b3d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166099824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3166099824
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.400370721
Short name T1168
Test name
Test status
Simulation time 37331544245 ps
CPU time 34.19 seconds
Started Aug 17 05:15:04 PM PDT 24
Finished Aug 17 05:15:39 PM PDT 24
Peak memory 200568 kb
Host smart-fd5f1471-5f7f-4281-b92f-c2b73a477b67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400370721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.400370721
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.229022138
Short name T810
Test name
Test status
Simulation time 72121911871 ps
CPU time 209.34 seconds
Started Aug 17 05:15:14 PM PDT 24
Finished Aug 17 05:18:44 PM PDT 24
Peak memory 200868 kb
Host smart-bcdb686b-9f2e-4354-82dd-a0c05d702c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229022138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.229022138
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3373367923
Short name T1052
Test name
Test status
Simulation time 7365597923 ps
CPU time 12.24 seconds
Started Aug 17 05:15:12 PM PDT 24
Finished Aug 17 05:15:25 PM PDT 24
Peak memory 199712 kb
Host smart-364b42b9-60e3-429b-9735-48eff712dc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373367923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3373367923
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2700283246
Short name T508
Test name
Test status
Simulation time 53673630312 ps
CPU time 38.57 seconds
Started Aug 17 05:15:05 PM PDT 24
Finished Aug 17 05:15:44 PM PDT 24
Peak memory 201080 kb
Host smart-ee0d1c30-9265-4655-b9f8-522e277f12e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700283246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2700283246
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2640226595
Short name T1002
Test name
Test status
Simulation time 15509700576 ps
CPU time 43.58 seconds
Started Aug 17 05:15:12 PM PDT 24
Finished Aug 17 05:15:56 PM PDT 24
Peak memory 200932 kb
Host smart-1f59cd69-2707-462c-81f7-4da192becc75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640226595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2640226595
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3869577176
Short name T6
Test name
Test status
Simulation time 4029300345 ps
CPU time 18.07 seconds
Started Aug 17 05:15:10 PM PDT 24
Finished Aug 17 05:15:28 PM PDT 24
Peak memory 199108 kb
Host smart-e5da4370-2413-4bc6-ac88-eb22948a1c75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869577176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3869577176
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1711069239
Short name T136
Test name
Test status
Simulation time 53092535002 ps
CPU time 77.5 seconds
Started Aug 17 05:15:05 PM PDT 24
Finished Aug 17 05:16:23 PM PDT 24
Peak memory 200960 kb
Host smart-40b836f6-3acf-40e5-9b3c-b5adced6c0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711069239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1711069239
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1419766363
Short name T949
Test name
Test status
Simulation time 1443686327 ps
CPU time 1.89 seconds
Started Aug 17 05:15:05 PM PDT 24
Finished Aug 17 05:15:07 PM PDT 24
Peak memory 196300 kb
Host smart-21239556-fddd-4aef-bdaa-c92ae845a688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419766363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1419766363
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1870653885
Short name T1104
Test name
Test status
Simulation time 252181236 ps
CPU time 1.18 seconds
Started Aug 17 05:14:57 PM PDT 24
Finished Aug 17 05:14:59 PM PDT 24
Peak memory 199416 kb
Host smart-4f6c0054-d673-485d-97c6-be574b8616bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870653885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1870653885
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3413396280
Short name T187
Test name
Test status
Simulation time 135949491957 ps
CPU time 549.56 seconds
Started Aug 17 05:15:14 PM PDT 24
Finished Aug 17 05:24:23 PM PDT 24
Peak memory 200896 kb
Host smart-f6f2c226-ccfa-4eac-8311-4c54c3436810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413396280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3413396280
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.702289387
Short name T984
Test name
Test status
Simulation time 1080501259 ps
CPU time 5.11 seconds
Started Aug 17 05:15:14 PM PDT 24
Finished Aug 17 05:15:19 PM PDT 24
Peak memory 216440 kb
Host smart-5fe78f95-1b55-447d-beb9-6353f2c814b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702289387 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.702289387
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.578384283
Short name T877
Test name
Test status
Simulation time 1309373438 ps
CPU time 1.42 seconds
Started Aug 17 05:15:04 PM PDT 24
Finished Aug 17 05:15:05 PM PDT 24
Peak memory 199268 kb
Host smart-b3fe7f26-fbb6-4e15-9795-d3490a261fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578384283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.578384283
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2221469220
Short name T660
Test name
Test status
Simulation time 20084249296 ps
CPU time 9.24 seconds
Started Aug 17 05:15:00 PM PDT 24
Finished Aug 17 05:15:09 PM PDT 24
Peak memory 200148 kb
Host smart-df460451-dc74-45ff-b9ab-b3ce773a669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221469220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2221469220
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2613300851
Short name T1177
Test name
Test status
Simulation time 117020345585 ps
CPU time 46.93 seconds
Started Aug 17 05:24:00 PM PDT 24
Finished Aug 17 05:24:47 PM PDT 24
Peak memory 200944 kb
Host smart-9b1293e9-3555-42d8-8778-81dba1fe0a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613300851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2613300851
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.53578968
Short name T4
Test name
Test status
Simulation time 93903076887 ps
CPU time 31.71 seconds
Started Aug 17 05:24:02 PM PDT 24
Finished Aug 17 05:24:34 PM PDT 24
Peak memory 199688 kb
Host smart-ffa9d017-d837-4ff5-8f60-22c07ffd3810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53578968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.53578968
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4275091465
Short name T167
Test name
Test status
Simulation time 10087780168 ps
CPU time 13.42 seconds
Started Aug 17 05:24:00 PM PDT 24
Finished Aug 17 05:24:14 PM PDT 24
Peak memory 200972 kb
Host smart-085ee742-b8e1-49ea-ad46-417d46ae24ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275091465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4275091465
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.424158464
Short name T231
Test name
Test status
Simulation time 15589133788 ps
CPU time 25.76 seconds
Started Aug 17 05:23:59 PM PDT 24
Finished Aug 17 05:24:25 PM PDT 24
Peak memory 200732 kb
Host smart-d096bba5-e3aa-4e18-b6f5-23756a23fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424158464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.424158464
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.108330755
Short name T292
Test name
Test status
Simulation time 143932655197 ps
CPU time 145.68 seconds
Started Aug 17 05:24:01 PM PDT 24
Finished Aug 17 05:26:27 PM PDT 24
Peak memory 200948 kb
Host smart-d1db5f43-0e23-47e8-b39a-030905619d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108330755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.108330755
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3231895961
Short name T960
Test name
Test status
Simulation time 80010057915 ps
CPU time 119.96 seconds
Started Aug 17 05:24:01 PM PDT 24
Finished Aug 17 05:26:01 PM PDT 24
Peak memory 200928 kb
Host smart-d03887b7-b811-4f00-986f-5e5faed13268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231895961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3231895961
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2326351186
Short name T613
Test name
Test status
Simulation time 26557421546 ps
CPU time 29.44 seconds
Started Aug 17 05:24:00 PM PDT 24
Finished Aug 17 05:24:30 PM PDT 24
Peak memory 200860 kb
Host smart-3bb2aff4-f151-4631-92e0-0bda9419873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326351186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2326351186
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.709286887
Short name T333
Test name
Test status
Simulation time 34671974600 ps
CPU time 8.91 seconds
Started Aug 17 05:23:59 PM PDT 24
Finished Aug 17 05:24:08 PM PDT 24
Peak memory 200960 kb
Host smart-74355d9c-cb28-4017-9af0-94d4f8c95eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709286887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.709286887
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1015703327
Short name T605
Test name
Test status
Simulation time 37613530184 ps
CPU time 17.97 seconds
Started Aug 17 05:24:00 PM PDT 24
Finished Aug 17 05:24:18 PM PDT 24
Peak memory 200876 kb
Host smart-0faf6674-a2a9-4be1-b0be-516573335cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015703327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1015703327
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2340468495
Short name T241
Test name
Test status
Simulation time 27470682985 ps
CPU time 44.48 seconds
Started Aug 17 05:24:02 PM PDT 24
Finished Aug 17 05:24:46 PM PDT 24
Peak memory 200836 kb
Host smart-a5df3d96-90eb-4765-acce-ee302ae1e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340468495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2340468495
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4015245795
Short name T524
Test name
Test status
Simulation time 35655539 ps
CPU time 0.57 seconds
Started Aug 17 05:15:31 PM PDT 24
Finished Aug 17 05:15:32 PM PDT 24
Peak memory 196184 kb
Host smart-f5567e2a-f3e7-4a04-8e51-34455976b0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015245795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4015245795
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.376394986
Short name T208
Test name
Test status
Simulation time 137428381080 ps
CPU time 52.07 seconds
Started Aug 17 05:15:26 PM PDT 24
Finished Aug 17 05:16:18 PM PDT 24
Peak memory 200932 kb
Host smart-c4259879-677f-4a4b-beef-8a7b84e55d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376394986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.376394986
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.476076708
Short name T1054
Test name
Test status
Simulation time 190156302944 ps
CPU time 33.91 seconds
Started Aug 17 05:15:23 PM PDT 24
Finished Aug 17 05:15:57 PM PDT 24
Peak memory 200932 kb
Host smart-0733e1e0-9946-4124-960c-75cf6da33b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476076708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.476076708
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1141336352
Short name T772
Test name
Test status
Simulation time 20737671616 ps
CPU time 21.88 seconds
Started Aug 17 05:15:23 PM PDT 24
Finished Aug 17 05:15:45 PM PDT 24
Peak memory 197888 kb
Host smart-c31ac4b9-225d-46e5-92bc-cd71e889f2e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141336352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1141336352
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1953312618
Short name T551
Test name
Test status
Simulation time 53849076435 ps
CPU time 154.4 seconds
Started Aug 17 05:15:31 PM PDT 24
Finished Aug 17 05:18:06 PM PDT 24
Peak memory 200880 kb
Host smart-f23b0509-1cce-4a8d-b595-daaeba820346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953312618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1953312618
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3358700071
Short name T507
Test name
Test status
Simulation time 5097518495 ps
CPU time 6.69 seconds
Started Aug 17 05:15:31 PM PDT 24
Finished Aug 17 05:15:38 PM PDT 24
Peak memory 200752 kb
Host smart-e6607274-c377-4e92-adf9-62f465968108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358700071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3358700071
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2527125880
Short name T283
Test name
Test status
Simulation time 39974699785 ps
CPU time 55.82 seconds
Started Aug 17 05:15:21 PM PDT 24
Finished Aug 17 05:16:17 PM PDT 24
Peak memory 209040 kb
Host smart-b06aa9cd-ef83-4efb-b98e-be5702944664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527125880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2527125880
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.4012236914
Short name T1025
Test name
Test status
Simulation time 10144047348 ps
CPU time 154.81 seconds
Started Aug 17 05:15:31 PM PDT 24
Finished Aug 17 05:18:06 PM PDT 24
Peak memory 200936 kb
Host smart-24862d7e-6e3d-48a3-9f59-ade14ce6e764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4012236914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4012236914
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4105538811
Short name T409
Test name
Test status
Simulation time 4811962678 ps
CPU time 42.11 seconds
Started Aug 17 05:15:23 PM PDT 24
Finished Aug 17 05:16:05 PM PDT 24
Peak memory 200060 kb
Host smart-7cf99e1b-0f24-4287-ad72-4bca540bdf93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105538811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4105538811
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3314811831
Short name T1057
Test name
Test status
Simulation time 141958001610 ps
CPU time 81.75 seconds
Started Aug 17 05:15:32 PM PDT 24
Finished Aug 17 05:16:54 PM PDT 24
Peak memory 200956 kb
Host smart-531cdc8b-3e34-4e44-ac9e-75c8caf911e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314811831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3314811831
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4236894928
Short name T432
Test name
Test status
Simulation time 560552774 ps
CPU time 0.84 seconds
Started Aug 17 05:15:22 PM PDT 24
Finished Aug 17 05:15:23 PM PDT 24
Peak memory 196596 kb
Host smart-0f4a94ed-c503-4c18-8478-08b36601dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236894928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4236894928
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.811026108
Short name T412
Test name
Test status
Simulation time 486192921 ps
CPU time 1.14 seconds
Started Aug 17 05:15:22 PM PDT 24
Finished Aug 17 05:15:23 PM PDT 24
Peak memory 199208 kb
Host smart-2161e4f6-bc60-40af-b676-9afd796a6dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811026108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.811026108
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1618643213
Short name T718
Test name
Test status
Simulation time 246331598359 ps
CPU time 426.64 seconds
Started Aug 17 05:15:31 PM PDT 24
Finished Aug 17 05:22:38 PM PDT 24
Peak memory 200944 kb
Host smart-08927395-08f2-4548-a0bd-47931903e9f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618643213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1618643213
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3551668588
Short name T978
Test name
Test status
Simulation time 6626227484 ps
CPU time 24.01 seconds
Started Aug 17 05:15:32 PM PDT 24
Finished Aug 17 05:15:57 PM PDT 24
Peak memory 209412 kb
Host smart-70d3b2aa-bbdd-4b66-b40e-6a47ddd6376b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551668588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3551668588
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.702725986
Short name T1136
Test name
Test status
Simulation time 978200173 ps
CPU time 3.6 seconds
Started Aug 17 05:15:32 PM PDT 24
Finished Aug 17 05:15:36 PM PDT 24
Peak memory 199688 kb
Host smart-c767b984-182e-4812-8db8-267f1b765769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702725986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.702725986
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1155063588
Short name T737
Test name
Test status
Simulation time 94659735222 ps
CPU time 38.63 seconds
Started Aug 17 05:15:22 PM PDT 24
Finished Aug 17 05:16:01 PM PDT 24
Peak memory 200964 kb
Host smart-9708bfc4-500b-4db4-8934-ba555133b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155063588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1155063588
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3140630728
Short name T182
Test name
Test status
Simulation time 20782096524 ps
CPU time 33.3 seconds
Started Aug 17 05:23:59 PM PDT 24
Finished Aug 17 05:24:32 PM PDT 24
Peak memory 200556 kb
Host smart-4f54ac40-8cf1-4343-8b68-8f98aae75499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140630728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3140630728
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2368840129
Short name T240
Test name
Test status
Simulation time 30287874009 ps
CPU time 41.63 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:24:49 PM PDT 24
Peak memory 200836 kb
Host smart-24155667-96a9-46c4-9c3d-629ad19a18ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368840129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2368840129
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3614170882
Short name T165
Test name
Test status
Simulation time 53952809233 ps
CPU time 17.7 seconds
Started Aug 17 05:24:09 PM PDT 24
Finished Aug 17 05:24:27 PM PDT 24
Peak memory 200520 kb
Host smart-de5471cd-be98-4364-a5f0-9ad65dc087df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614170882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3614170882
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1659276030
Short name T217
Test name
Test status
Simulation time 101180996240 ps
CPU time 96.18 seconds
Started Aug 17 05:24:13 PM PDT 24
Finished Aug 17 05:25:49 PM PDT 24
Peak memory 200948 kb
Host smart-a8737764-9ab9-4da0-b199-ecb3ffde40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659276030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1659276030
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1401121456
Short name T607
Test name
Test status
Simulation time 62148839522 ps
CPU time 201.74 seconds
Started Aug 17 05:24:07 PM PDT 24
Finished Aug 17 05:27:29 PM PDT 24
Peak memory 200856 kb
Host smart-7ef6c187-6a9c-4b4e-a4d7-5de410b9edf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401121456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1401121456
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2838522042
Short name T221
Test name
Test status
Simulation time 16593160274 ps
CPU time 26.51 seconds
Started Aug 17 05:24:09 PM PDT 24
Finished Aug 17 05:24:35 PM PDT 24
Peak memory 200852 kb
Host smart-7da34f49-bc14-4807-9659-a68cff6214ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838522042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2838522042
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3919213249
Short name T1092
Test name
Test status
Simulation time 33463941722 ps
CPU time 35.26 seconds
Started Aug 17 05:24:09 PM PDT 24
Finished Aug 17 05:24:44 PM PDT 24
Peak memory 200852 kb
Host smart-776ddb1a-6894-48a0-aada-38566ffe6c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919213249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3919213249
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2241135500
Short name T256
Test name
Test status
Simulation time 149811899163 ps
CPU time 30.67 seconds
Started Aug 17 05:24:10 PM PDT 24
Finished Aug 17 05:24:40 PM PDT 24
Peak memory 200956 kb
Host smart-f14407d9-6ced-4311-89cd-9087ba0cf026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241135500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2241135500
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4111538011
Short name T233
Test name
Test status
Simulation time 7422440884 ps
CPU time 7.53 seconds
Started Aug 17 05:24:11 PM PDT 24
Finished Aug 17 05:24:18 PM PDT 24
Peak memory 200908 kb
Host smart-6582151b-9c5e-4640-ab10-ece33b70ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111538011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4111538011
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4204585900
Short name T428
Test name
Test status
Simulation time 36280962 ps
CPU time 0.54 seconds
Started Aug 17 05:15:48 PM PDT 24
Finished Aug 17 05:15:49 PM PDT 24
Peak memory 196196 kb
Host smart-9a83acef-68c5-484f-9bab-4d718e9e0e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204585900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4204585900
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.573226985
Short name T861
Test name
Test status
Simulation time 129244450166 ps
CPU time 40.43 seconds
Started Aug 17 05:15:43 PM PDT 24
Finished Aug 17 05:16:23 PM PDT 24
Peak memory 200924 kb
Host smart-0e1eff95-1cb7-497b-ac2d-1a9cbee4d21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573226985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.573226985
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1878197991
Short name T637
Test name
Test status
Simulation time 33724863171 ps
CPU time 27.95 seconds
Started Aug 17 05:15:42 PM PDT 24
Finished Aug 17 05:16:10 PM PDT 24
Peak memory 200948 kb
Host smart-7665d564-b242-48e7-85d2-58b49d31e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878197991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1878197991
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2539912023
Short name T259
Test name
Test status
Simulation time 54330016716 ps
CPU time 22.98 seconds
Started Aug 17 05:15:40 PM PDT 24
Finished Aug 17 05:16:03 PM PDT 24
Peak memory 200952 kb
Host smart-c1e0d1da-a8e5-4677-9cde-e882c1edde94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539912023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2539912023
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3537319985
Short name T783
Test name
Test status
Simulation time 53475571442 ps
CPU time 103.29 seconds
Started Aug 17 05:15:42 PM PDT 24
Finished Aug 17 05:17:26 PM PDT 24
Peak memory 200936 kb
Host smart-6ffbb7f2-6a37-4818-a8c5-185f8889eceb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537319985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3537319985
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3666180869
Short name T502
Test name
Test status
Simulation time 193343672685 ps
CPU time 1211.71 seconds
Started Aug 17 05:15:49 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 200936 kb
Host smart-cfff4995-1540-478f-a848-2302e95f020b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666180869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3666180869
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.129226801
Short name T664
Test name
Test status
Simulation time 11897620517 ps
CPU time 8.68 seconds
Started Aug 17 05:15:48 PM PDT 24
Finished Aug 17 05:15:57 PM PDT 24
Peak memory 200508 kb
Host smart-7bda9f3b-5f84-49cc-9ac3-03393c556c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129226801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.129226801
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2854710135
Short name T334
Test name
Test status
Simulation time 88585401167 ps
CPU time 163.83 seconds
Started Aug 17 05:15:40 PM PDT 24
Finished Aug 17 05:18:24 PM PDT 24
Peak memory 209208 kb
Host smart-debd6847-901a-4e5a-b4fe-d295653954da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854710135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2854710135
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.4248728688
Short name T835
Test name
Test status
Simulation time 10564410699 ps
CPU time 293.41 seconds
Started Aug 17 05:15:46 PM PDT 24
Finished Aug 17 05:20:40 PM PDT 24
Peak memory 200912 kb
Host smart-288e98de-4c55-461b-adfc-a9a5bf546f5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4248728688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4248728688
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3422139413
Short name T629
Test name
Test status
Simulation time 6604915678 ps
CPU time 59.35 seconds
Started Aug 17 05:15:41 PM PDT 24
Finished Aug 17 05:16:41 PM PDT 24
Peak memory 200292 kb
Host smart-e04138b4-a28e-458e-83d3-e5f12ce68bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422139413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3422139413
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1545899121
Short name T1090
Test name
Test status
Simulation time 72780950782 ps
CPU time 49.87 seconds
Started Aug 17 05:15:53 PM PDT 24
Finished Aug 17 05:16:43 PM PDT 24
Peak memory 200812 kb
Host smart-96c25f1c-ec18-4b67-9554-ddf4e7959acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545899121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1545899121
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.4252630823
Short name T441
Test name
Test status
Simulation time 39924158853 ps
CPU time 52.91 seconds
Started Aug 17 05:15:48 PM PDT 24
Finished Aug 17 05:16:41 PM PDT 24
Peak memory 197468 kb
Host smart-9e5167a2-81d4-402a-acef-b18b7f295d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252630823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4252630823
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2595476534
Short name T640
Test name
Test status
Simulation time 315825013 ps
CPU time 1.28 seconds
Started Aug 17 05:15:42 PM PDT 24
Finished Aug 17 05:15:43 PM PDT 24
Peak memory 199788 kb
Host smart-fcd6d133-4b15-4920-8331-a44d3036dd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595476534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2595476534
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.135426419
Short name T900
Test name
Test status
Simulation time 108177523155 ps
CPU time 174.99 seconds
Started Aug 17 05:15:48 PM PDT 24
Finished Aug 17 05:18:43 PM PDT 24
Peak memory 200924 kb
Host smart-b97a0280-ef18-4feb-a832-121a5b98aea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135426419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.135426419
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3899238676
Short name T1083
Test name
Test status
Simulation time 1975828738 ps
CPU time 34.49 seconds
Started Aug 17 05:15:50 PM PDT 24
Finished Aug 17 05:16:25 PM PDT 24
Peak memory 209348 kb
Host smart-bfe80ba6-7c1a-4fe8-8293-7cba609a024c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899238676 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3899238676
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2936625674
Short name T992
Test name
Test status
Simulation time 4419887529 ps
CPU time 2.29 seconds
Started Aug 17 05:15:49 PM PDT 24
Finished Aug 17 05:15:51 PM PDT 24
Peak memory 200904 kb
Host smart-3c262415-8e45-4a18-8c8f-96f44b51868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936625674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2936625674
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1950965511
Short name T863
Test name
Test status
Simulation time 64695399464 ps
CPU time 141.2 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:26:30 PM PDT 24
Peak memory 200984 kb
Host smart-54688c11-da29-448c-9a67-5f7c0b358546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950965511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1950965511
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3330503019
Short name T1162
Test name
Test status
Simulation time 74508367354 ps
CPU time 60.08 seconds
Started Aug 17 05:24:10 PM PDT 24
Finished Aug 17 05:25:10 PM PDT 24
Peak memory 200800 kb
Host smart-48fbc731-aac5-4e0f-afa9-69286a636151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330503019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3330503019
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.697842524
Short name T344
Test name
Test status
Simulation time 132621355363 ps
CPU time 161.58 seconds
Started Aug 17 05:24:06 PM PDT 24
Finished Aug 17 05:26:48 PM PDT 24
Peak memory 200956 kb
Host smart-a5fca554-e869-42b7-b630-5f3f487f88d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697842524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.697842524
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3881668634
Short name T1045
Test name
Test status
Simulation time 84064526217 ps
CPU time 27.44 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:24:36 PM PDT 24
Peak memory 200952 kb
Host smart-8ae176dc-8021-433f-88be-2f7725c7af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881668634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3881668634
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1368556621
Short name T963
Test name
Test status
Simulation time 67793847116 ps
CPU time 34.42 seconds
Started Aug 17 05:24:13 PM PDT 24
Finished Aug 17 05:24:48 PM PDT 24
Peak memory 200948 kb
Host smart-a19a9b1a-23b3-4b50-973f-69bd78d416d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368556621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1368556621
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1371639016
Short name T498
Test name
Test status
Simulation time 15321563031 ps
CPU time 47.8 seconds
Started Aug 17 05:24:06 PM PDT 24
Finished Aug 17 05:24:54 PM PDT 24
Peak memory 200900 kb
Host smart-f0a7e859-59ee-4c19-9394-965e19dfb964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371639016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1371639016
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.467133721
Short name T297
Test name
Test status
Simulation time 31455522381 ps
CPU time 15.68 seconds
Started Aug 17 05:24:09 PM PDT 24
Finished Aug 17 05:24:25 PM PDT 24
Peak memory 200896 kb
Host smart-e633f75f-7971-455a-beee-5dc8c680ed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467133721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.467133721
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3715141624
Short name T694
Test name
Test status
Simulation time 117103697108 ps
CPU time 379.73 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:30:28 PM PDT 24
Peak memory 200888 kb
Host smart-186e2a78-c745-4d89-84ce-0cdbae68c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715141624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3715141624
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.22264877
Short name T994
Test name
Test status
Simulation time 8532764862 ps
CPU time 22.78 seconds
Started Aug 17 05:24:07 PM PDT 24
Finished Aug 17 05:24:30 PM PDT 24
Peak memory 200864 kb
Host smart-07229885-39e4-4736-b629-7ce6ff0772ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22264877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.22264877
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.773184284
Short name T120
Test name
Test status
Simulation time 217575979307 ps
CPU time 76.56 seconds
Started Aug 17 05:24:10 PM PDT 24
Finished Aug 17 05:25:27 PM PDT 24
Peak memory 200916 kb
Host smart-ea7c5b51-47f1-4c2b-9ab8-04953280bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773184284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.773184284
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3711394850
Short name T595
Test name
Test status
Simulation time 10828343 ps
CPU time 0.54 seconds
Started Aug 17 05:16:10 PM PDT 24
Finished Aug 17 05:16:11 PM PDT 24
Peak memory 195280 kb
Host smart-3cc44718-234f-4571-911b-ef57d284c705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711394850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3711394850
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1881285417
Short name T199
Test name
Test status
Simulation time 66531034074 ps
CPU time 38.19 seconds
Started Aug 17 05:15:56 PM PDT 24
Finished Aug 17 05:16:35 PM PDT 24
Peak memory 200784 kb
Host smart-358d1eb3-728b-4468-9c7e-49ab2e9c50a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881285417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1881285417
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1930032382
Short name T811
Test name
Test status
Simulation time 32050847736 ps
CPU time 53.46 seconds
Started Aug 17 05:15:58 PM PDT 24
Finished Aug 17 05:16:52 PM PDT 24
Peak memory 201120 kb
Host smart-46eb49c7-bfa6-4ae7-8097-d29895f3ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930032382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1930032382
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1286873029
Short name T937
Test name
Test status
Simulation time 110704629417 ps
CPU time 39.62 seconds
Started Aug 17 05:15:56 PM PDT 24
Finished Aug 17 05:16:36 PM PDT 24
Peak memory 200908 kb
Host smart-fa4b2b6a-21ed-4b8e-8cb6-f2d61efa312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286873029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1286873029
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4077129527
Short name T623
Test name
Test status
Simulation time 142936059425 ps
CPU time 374.49 seconds
Started Aug 17 05:15:58 PM PDT 24
Finished Aug 17 05:22:13 PM PDT 24
Peak memory 200856 kb
Host smart-a6f70457-fe92-40b8-985c-a1a83b507dd6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077129527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4077129527
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.881388020
Short name T328
Test name
Test status
Simulation time 150091878399 ps
CPU time 384.71 seconds
Started Aug 17 05:16:05 PM PDT 24
Finished Aug 17 05:22:30 PM PDT 24
Peak memory 200816 kb
Host smart-b6611c56-d477-4376-83cb-6b81d57be82b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881388020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.881388020
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2735758793
Short name T895
Test name
Test status
Simulation time 7756256726 ps
CPU time 4.58 seconds
Started Aug 17 05:16:06 PM PDT 24
Finished Aug 17 05:16:11 PM PDT 24
Peak memory 199964 kb
Host smart-513b0e19-30e4-4993-82c1-71c47ed32747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735758793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2735758793
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3609935628
Short name T880
Test name
Test status
Simulation time 72490274521 ps
CPU time 57.76 seconds
Started Aug 17 05:15:54 PM PDT 24
Finished Aug 17 05:16:52 PM PDT 24
Peak memory 209108 kb
Host smart-291750f0-7002-4212-ad4f-33cca0bb5c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609935628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3609935628
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3295916003
Short name T97
Test name
Test status
Simulation time 15202335887 ps
CPU time 88.45 seconds
Started Aug 17 05:16:04 PM PDT 24
Finished Aug 17 05:17:32 PM PDT 24
Peak memory 200876 kb
Host smart-9f289f18-005b-4dd9-a2de-ce64ccbe9c27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295916003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3295916003
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1676344996
Short name T566
Test name
Test status
Simulation time 1764641595 ps
CPU time 5.28 seconds
Started Aug 17 05:15:58 PM PDT 24
Finished Aug 17 05:16:03 PM PDT 24
Peak memory 198564 kb
Host smart-0f89fb5d-afa3-422d-b666-fc501351d9ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676344996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1676344996
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.248469268
Short name T184
Test name
Test status
Simulation time 26077479395 ps
CPU time 50.69 seconds
Started Aug 17 05:16:05 PM PDT 24
Finished Aug 17 05:16:55 PM PDT 24
Peak memory 200916 kb
Host smart-3458534c-60d4-422a-89af-f28ef4441753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248469268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.248469268
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1443773737
Short name T1066
Test name
Test status
Simulation time 4784450639 ps
CPU time 2.68 seconds
Started Aug 17 05:15:55 PM PDT 24
Finished Aug 17 05:15:57 PM PDT 24
Peak memory 197440 kb
Host smart-1ebbcf66-a421-4ef7-9388-b231b738145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443773737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1443773737
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2876230021
Short name T947
Test name
Test status
Simulation time 314981185 ps
CPU time 1.01 seconds
Started Aug 17 05:15:47 PM PDT 24
Finished Aug 17 05:15:48 PM PDT 24
Peak memory 199420 kb
Host smart-ec90cee9-fb94-48d1-a9e6-de80d139f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876230021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2876230021
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.734338135
Short name T494
Test name
Test status
Simulation time 179408697789 ps
CPU time 274.86 seconds
Started Aug 17 05:16:12 PM PDT 24
Finished Aug 17 05:20:47 PM PDT 24
Peak memory 200924 kb
Host smart-350b3498-a448-4ca0-a436-ce2413e94d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734338135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.734338135
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.329787500
Short name T742
Test name
Test status
Simulation time 8307878602 ps
CPU time 8.21 seconds
Started Aug 17 05:16:05 PM PDT 24
Finished Aug 17 05:16:13 PM PDT 24
Peak memory 200704 kb
Host smart-59e5362d-4923-4a3b-bb2f-818c98ec5165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329787500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.329787500
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1131364371
Short name T530
Test name
Test status
Simulation time 41322904990 ps
CPU time 16.74 seconds
Started Aug 17 05:15:55 PM PDT 24
Finished Aug 17 05:16:12 PM PDT 24
Peak memory 200684 kb
Host smart-326ceb6e-a79b-41f0-af7e-09e90698384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131364371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1131364371
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1829259552
Short name T416
Test name
Test status
Simulation time 26414864839 ps
CPU time 35.99 seconds
Started Aug 17 05:24:07 PM PDT 24
Finished Aug 17 05:24:43 PM PDT 24
Peak memory 200868 kb
Host smart-f30f11ea-8696-4e5b-8a4a-1ed23beb4b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829259552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1829259552
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2969768925
Short name T575
Test name
Test status
Simulation time 14838913320 ps
CPU time 20.33 seconds
Started Aug 17 05:24:11 PM PDT 24
Finished Aug 17 05:24:31 PM PDT 24
Peak memory 200960 kb
Host smart-5dbe61f0-39b2-44e6-99d3-b395c0c5244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969768925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2969768925
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3897450587
Short name T158
Test name
Test status
Simulation time 67104530966 ps
CPU time 51.51 seconds
Started Aug 17 05:24:09 PM PDT 24
Finished Aug 17 05:25:01 PM PDT 24
Peak memory 200764 kb
Host smart-0912e285-606a-4c99-9ccb-508412e21aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897450587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3897450587
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1737209554
Short name T278
Test name
Test status
Simulation time 40925533575 ps
CPU time 73.45 seconds
Started Aug 17 05:24:09 PM PDT 24
Finished Aug 17 05:25:23 PM PDT 24
Peak memory 200928 kb
Host smart-b7f6a341-8a00-48a8-9f16-d29ae0888c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737209554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1737209554
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2969607756
Short name T270
Test name
Test status
Simulation time 86832085215 ps
CPU time 34.83 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:24:43 PM PDT 24
Peak memory 200708 kb
Host smart-97d6522c-d19e-4ac1-a764-c6b18b555d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969607756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2969607756
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1118957920
Short name T526
Test name
Test status
Simulation time 113802419697 ps
CPU time 171 seconds
Started Aug 17 05:24:09 PM PDT 24
Finished Aug 17 05:27:00 PM PDT 24
Peak memory 200876 kb
Host smart-caab0fbc-a2c4-44e1-99f2-00a47484c559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118957920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1118957920
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1611136063
Short name T1016
Test name
Test status
Simulation time 163233480643 ps
CPU time 196.02 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:27:24 PM PDT 24
Peak memory 200824 kb
Host smart-dda2bc0f-4d38-48ef-b73f-8d3ef930cc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611136063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1611136063
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1356732922
Short name T468
Test name
Test status
Simulation time 54232500663 ps
CPU time 24.51 seconds
Started Aug 17 05:24:10 PM PDT 24
Finished Aug 17 05:24:34 PM PDT 24
Peak memory 200852 kb
Host smart-46085967-e425-4f14-8ef8-093f4ef7ad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356732922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1356732922
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3464285174
Short name T890
Test name
Test status
Simulation time 173966012526 ps
CPU time 112.17 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:26:01 PM PDT 24
Peak memory 200876 kb
Host smart-1f8c54cb-ea68-4ecb-aeb8-1e1221fde7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464285174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3464285174
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2113117826
Short name T434
Test name
Test status
Simulation time 57759970 ps
CPU time 0.56 seconds
Started Aug 17 05:16:27 PM PDT 24
Finished Aug 17 05:16:28 PM PDT 24
Peak memory 196216 kb
Host smart-1cb98e6d-295b-441d-a9ff-3df81e819a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113117826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2113117826
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.139359826
Short name T455
Test name
Test status
Simulation time 119449517245 ps
CPU time 184.93 seconds
Started Aug 17 05:16:12 PM PDT 24
Finished Aug 17 05:19:17 PM PDT 24
Peak memory 200868 kb
Host smart-fb3be70f-edab-4bd4-81c9-4606569d8e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139359826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.139359826
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3052775967
Short name T793
Test name
Test status
Simulation time 134010628824 ps
CPU time 101.05 seconds
Started Aug 17 05:16:11 PM PDT 24
Finished Aug 17 05:17:52 PM PDT 24
Peak memory 200544 kb
Host smart-bc97feb6-fb78-4e7c-a89e-a169c5cbf8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052775967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3052775967
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2231455718
Short name T177
Test name
Test status
Simulation time 58657137028 ps
CPU time 172.36 seconds
Started Aug 17 05:16:14 PM PDT 24
Finished Aug 17 05:19:07 PM PDT 24
Peak memory 200944 kb
Host smart-2b6b761a-b1db-4c83-b958-9198a3e0a5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231455718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2231455718
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1123840028
Short name T648
Test name
Test status
Simulation time 10184408589 ps
CPU time 17.94 seconds
Started Aug 17 05:16:19 PM PDT 24
Finished Aug 17 05:16:37 PM PDT 24
Peak memory 200872 kb
Host smart-fd38191d-93e8-41a6-a600-30ba505a78e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123840028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1123840028
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_loopback.1181219804
Short name T449
Test name
Test status
Simulation time 4659655028 ps
CPU time 3.41 seconds
Started Aug 17 05:16:27 PM PDT 24
Finished Aug 17 05:16:31 PM PDT 24
Peak memory 200516 kb
Host smart-b4e72f53-5184-44bd-a04f-8f867bbb3803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181219804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1181219804
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2080438803
Short name T1135
Test name
Test status
Simulation time 25804278810 ps
CPU time 45.07 seconds
Started Aug 17 05:16:17 PM PDT 24
Finished Aug 17 05:17:03 PM PDT 24
Peak memory 200596 kb
Host smart-67a4f6af-a79f-4b81-a4bb-f49fbec1152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080438803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2080438803
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3208125333
Short name T413
Test name
Test status
Simulation time 25189003850 ps
CPU time 199.53 seconds
Started Aug 17 05:16:29 PM PDT 24
Finished Aug 17 05:19:48 PM PDT 24
Peak memory 200796 kb
Host smart-a8c0c7f0-7d1d-41a9-811f-12d3293dc279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208125333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3208125333
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.255693488
Short name T690
Test name
Test status
Simulation time 4044579720 ps
CPU time 27.4 seconds
Started Aug 17 05:16:11 PM PDT 24
Finished Aug 17 05:16:38 PM PDT 24
Peak memory 199140 kb
Host smart-aca6dd88-b04a-469b-ab3a-c53a5fa8160d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255693488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.255693488
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3529844859
Short name T904
Test name
Test status
Simulation time 85609793158 ps
CPU time 166.77 seconds
Started Aug 17 05:16:20 PM PDT 24
Finished Aug 17 05:19:07 PM PDT 24
Peak memory 200904 kb
Host smart-4c9f046c-adea-477f-97c9-19b9b8dd289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529844859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3529844859
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2773836171
Short name T903
Test name
Test status
Simulation time 42691269665 ps
CPU time 12.73 seconds
Started Aug 17 05:16:19 PM PDT 24
Finished Aug 17 05:16:33 PM PDT 24
Peak memory 197204 kb
Host smart-f32e2d09-d6a1-4728-b2bc-86495a76fa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773836171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2773836171
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1363326636
Short name T781
Test name
Test status
Simulation time 171091981 ps
CPU time 0.77 seconds
Started Aug 17 05:16:11 PM PDT 24
Finished Aug 17 05:16:12 PM PDT 24
Peak memory 198012 kb
Host smart-6fd250c5-9871-4c84-8e4f-0a128c11eace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363326636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1363326636
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.646759132
Short name T436
Test name
Test status
Simulation time 1991683284 ps
CPU time 51.59 seconds
Started Aug 17 05:16:28 PM PDT 24
Finished Aug 17 05:17:19 PM PDT 24
Peak memory 209304 kb
Host smart-bb5e3021-4d58-40b9-ab80-93adb433b95c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646759132 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.646759132
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1997034603
Short name T871
Test name
Test status
Simulation time 6165365057 ps
CPU time 16.91 seconds
Started Aug 17 05:16:29 PM PDT 24
Finished Aug 17 05:16:46 PM PDT 24
Peak memory 200908 kb
Host smart-cf1728bf-911f-45da-bfb9-ebf6c2bf1b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997034603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1997034603
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1038735535
Short name T1106
Test name
Test status
Simulation time 75389742709 ps
CPU time 121.57 seconds
Started Aug 17 05:16:12 PM PDT 24
Finished Aug 17 05:18:13 PM PDT 24
Peak memory 200836 kb
Host smart-c9fda078-1e1a-4044-91c1-42b925d74a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038735535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1038735535
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.4284381942
Short name T277
Test name
Test status
Simulation time 395000617276 ps
CPU time 82.75 seconds
Started Aug 17 05:24:07 PM PDT 24
Finished Aug 17 05:25:30 PM PDT 24
Peak memory 200880 kb
Host smart-ad58abbe-bbd3-41fc-880c-1cc75a082674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284381942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.4284381942
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2666115833
Short name T331
Test name
Test status
Simulation time 21690651612 ps
CPU time 40.71 seconds
Started Aug 17 05:24:07 PM PDT 24
Finished Aug 17 05:24:48 PM PDT 24
Peak memory 200924 kb
Host smart-71be2e27-e180-4a1c-a393-30615d57959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666115833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2666115833
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.247320087
Short name T225
Test name
Test status
Simulation time 28668670595 ps
CPU time 101.48 seconds
Started Aug 17 05:24:11 PM PDT 24
Finished Aug 17 05:25:52 PM PDT 24
Peak memory 200884 kb
Host smart-f413a8f4-90c1-4c2f-ae8a-e8a697a2ce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247320087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.247320087
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2712499870
Short name T1157
Test name
Test status
Simulation time 176380949745 ps
CPU time 38.37 seconds
Started Aug 17 05:24:13 PM PDT 24
Finished Aug 17 05:24:52 PM PDT 24
Peak memory 200944 kb
Host smart-9d8df2a2-de08-4bdf-bfaa-930818890f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712499870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2712499870
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3513478780
Short name T906
Test name
Test status
Simulation time 43556720107 ps
CPU time 35.06 seconds
Started Aug 17 05:24:11 PM PDT 24
Finished Aug 17 05:24:46 PM PDT 24
Peak memory 200908 kb
Host smart-674e1bc6-c4be-48aa-aa46-0a42fdd18c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513478780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3513478780
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1463513744
Short name T695
Test name
Test status
Simulation time 39249362576 ps
CPU time 23.08 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:24:31 PM PDT 24
Peak memory 200952 kb
Host smart-64d47eb8-c2d2-4bcc-895c-c3be243f22e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463513744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1463513744
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.6532860
Short name T247
Test name
Test status
Simulation time 49841764774 ps
CPU time 69.99 seconds
Started Aug 17 05:24:08 PM PDT 24
Finished Aug 17 05:25:18 PM PDT 24
Peak memory 200748 kb
Host smart-79ddf17f-c997-4eff-a89a-7c5a7b717ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6532860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.6532860
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4232755732
Short name T769
Test name
Test status
Simulation time 18795735882 ps
CPU time 22.93 seconds
Started Aug 17 05:24:17 PM PDT 24
Finished Aug 17 05:24:40 PM PDT 24
Peak memory 200800 kb
Host smart-388f74fb-fbd3-4273-a93f-fa5bad16c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232755732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4232755732
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.4209945215
Short name T82
Test name
Test status
Simulation time 13768043 ps
CPU time 0.56 seconds
Started Aug 17 05:09:50 PM PDT 24
Finished Aug 17 05:09:51 PM PDT 24
Peak memory 195228 kb
Host smart-5667e692-288f-4f5d-801d-d7bcc0cdd84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209945215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4209945215
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.364512469
Short name T578
Test name
Test status
Simulation time 83693838518 ps
CPU time 72.54 seconds
Started Aug 17 05:09:41 PM PDT 24
Finished Aug 17 05:10:53 PM PDT 24
Peak memory 200884 kb
Host smart-e54a5406-d386-484d-88e6-34c7d946d96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364512469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.364512469
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.509557547
Short name T150
Test name
Test status
Simulation time 94999473824 ps
CPU time 408.52 seconds
Started Aug 17 05:09:44 PM PDT 24
Finished Aug 17 05:16:32 PM PDT 24
Peak memory 200816 kb
Host smart-3f9f369e-45f6-4c86-8baf-25253c108bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509557547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.509557547
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3529567483
Short name T230
Test name
Test status
Simulation time 17772133904 ps
CPU time 28.78 seconds
Started Aug 17 05:09:40 PM PDT 24
Finished Aug 17 05:10:09 PM PDT 24
Peak memory 200872 kb
Host smart-0fce45c1-0369-41be-ad2a-e1a2d4a33e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529567483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3529567483
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1285520219
Short name T1063
Test name
Test status
Simulation time 102480286792 ps
CPU time 433.94 seconds
Started Aug 17 05:09:47 PM PDT 24
Finished Aug 17 05:17:01 PM PDT 24
Peak memory 200936 kb
Host smart-d0ca03a1-0a17-42c7-bd48-e071e17f6531
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285520219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1285520219
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3097250000
Short name T437
Test name
Test status
Simulation time 3637254269 ps
CPU time 7.28 seconds
Started Aug 17 05:09:40 PM PDT 24
Finished Aug 17 05:09:48 PM PDT 24
Peak memory 199572 kb
Host smart-7b878be4-6106-4f1e-aa13-08e5e9a7d731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097250000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3097250000
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.970130363
Short name T1091
Test name
Test status
Simulation time 60535149355 ps
CPU time 109.73 seconds
Started Aug 17 05:09:44 PM PDT 24
Finished Aug 17 05:11:34 PM PDT 24
Peak memory 201024 kb
Host smart-c8552a97-f7e0-4f3a-8c3c-a335c61eecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970130363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.970130363
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.4203909923
Short name T987
Test name
Test status
Simulation time 11654689947 ps
CPU time 666.55 seconds
Started Aug 17 05:09:45 PM PDT 24
Finished Aug 17 05:20:52 PM PDT 24
Peak memory 200820 kb
Host smart-b25f85bd-1272-499b-b547-5a4d124e5af2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203909923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.4203909923
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.840521195
Short name T791
Test name
Test status
Simulation time 3402007831 ps
CPU time 13.9 seconds
Started Aug 17 05:09:42 PM PDT 24
Finished Aug 17 05:09:56 PM PDT 24
Peak memory 199636 kb
Host smart-1b581470-83f5-4674-9fd2-0dcf6474fb09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=840521195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.840521195
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3162360092
Short name T591
Test name
Test status
Simulation time 33057879120 ps
CPU time 46.27 seconds
Started Aug 17 05:09:40 PM PDT 24
Finished Aug 17 05:10:27 PM PDT 24
Peak memory 200724 kb
Host smart-06eb446f-91a6-467d-85d5-7bf733e8bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162360092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3162360092
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2839160383
Short name T857
Test name
Test status
Simulation time 27116447015 ps
CPU time 12.85 seconds
Started Aug 17 05:09:45 PM PDT 24
Finished Aug 17 05:09:58 PM PDT 24
Peak memory 197188 kb
Host smart-f66043a9-256c-42e5-84eb-5b1820bb5d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839160383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2839160383
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3659383117
Short name T90
Test name
Test status
Simulation time 50062625 ps
CPU time 0.78 seconds
Started Aug 17 05:09:49 PM PDT 24
Finished Aug 17 05:09:50 PM PDT 24
Peak memory 218912 kb
Host smart-71a37541-36a7-4f2a-b990-b4cdbaffcdd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659383117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3659383117
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1520247974
Short name T995
Test name
Test status
Simulation time 443660577 ps
CPU time 2.16 seconds
Started Aug 17 05:09:39 PM PDT 24
Finished Aug 17 05:09:41 PM PDT 24
Peak memory 199168 kb
Host smart-ad906add-992c-45af-9993-871d702c9e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520247974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1520247974
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3379327352
Short name T523
Test name
Test status
Simulation time 1963256593 ps
CPU time 17.85 seconds
Started Aug 17 05:09:48 PM PDT 24
Finished Aug 17 05:10:06 PM PDT 24
Peak memory 209348 kb
Host smart-b3bcf3bb-0ad0-4c55-8331-481dcd8a0804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379327352 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3379327352
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4118090364
Short name T1024
Test name
Test status
Simulation time 1891570878 ps
CPU time 2.24 seconds
Started Aug 17 05:09:41 PM PDT 24
Finished Aug 17 05:09:43 PM PDT 24
Peak memory 200600 kb
Host smart-edc1a382-6b1f-497a-9c49-e9f840597631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118090364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4118090364
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.4019915074
Short name T411
Test name
Test status
Simulation time 87276771836 ps
CPU time 12.08 seconds
Started Aug 17 05:09:40 PM PDT 24
Finished Aug 17 05:09:52 PM PDT 24
Peak memory 200868 kb
Host smart-b46492ad-e005-4fe3-88e0-aac8e3084375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019915074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.4019915074
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3244769558
Short name T587
Test name
Test status
Simulation time 43301393 ps
CPU time 0.57 seconds
Started Aug 17 05:16:45 PM PDT 24
Finished Aug 17 05:16:46 PM PDT 24
Peak memory 196456 kb
Host smart-5985c09d-446a-4285-a373-3d61c5acadb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244769558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3244769558
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2846679202
Short name T183
Test name
Test status
Simulation time 81905143307 ps
CPU time 49.08 seconds
Started Aug 17 05:16:35 PM PDT 24
Finished Aug 17 05:17:25 PM PDT 24
Peak memory 200884 kb
Host smart-6e7f5096-0705-4e79-9df0-92bfb6c232d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846679202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2846679202
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4166692648
Short name T918
Test name
Test status
Simulation time 10501539196 ps
CPU time 19.15 seconds
Started Aug 17 05:16:35 PM PDT 24
Finished Aug 17 05:16:54 PM PDT 24
Peak memory 200956 kb
Host smart-50d46835-85b2-4d92-bb26-4056dc8c6a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166692648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4166692648
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2131294112
Short name T929
Test name
Test status
Simulation time 83796144910 ps
CPU time 142.33 seconds
Started Aug 17 05:16:35 PM PDT 24
Finished Aug 17 05:18:58 PM PDT 24
Peak memory 200788 kb
Host smart-6af3620e-de80-4713-a3f6-bbe27f15e36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131294112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2131294112
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3296211579
Short name T622
Test name
Test status
Simulation time 58142555130 ps
CPU time 32.54 seconds
Started Aug 17 05:16:35 PM PDT 24
Finished Aug 17 05:17:08 PM PDT 24
Peak memory 200948 kb
Host smart-5eb9f69f-acdd-418f-b068-5d396bc3836e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296211579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3296211579
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3306299303
Short name T574
Test name
Test status
Simulation time 46364015933 ps
CPU time 259.32 seconds
Started Aug 17 05:16:42 PM PDT 24
Finished Aug 17 05:21:02 PM PDT 24
Peak memory 200872 kb
Host smart-1a16837b-040a-46fa-b396-396a306fe2bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306299303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3306299303
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1358299539
Short name T579
Test name
Test status
Simulation time 8178147929 ps
CPU time 12.32 seconds
Started Aug 17 05:16:43 PM PDT 24
Finished Aug 17 05:16:55 PM PDT 24
Peak memory 199684 kb
Host smart-2b003059-ac21-4593-b752-d7e9bfec7469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358299539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1358299539
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1585109023
Short name T431
Test name
Test status
Simulation time 32395363238 ps
CPU time 45.83 seconds
Started Aug 17 05:16:35 PM PDT 24
Finished Aug 17 05:17:21 PM PDT 24
Peak memory 199148 kb
Host smart-2c1d4541-3230-4427-a4cb-9fc0f99e4a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585109023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1585109023
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2098478534
Short name T592
Test name
Test status
Simulation time 11291390140 ps
CPU time 115.36 seconds
Started Aug 17 05:16:43 PM PDT 24
Finished Aug 17 05:18:38 PM PDT 24
Peak memory 200956 kb
Host smart-926449ef-6a54-4d50-a0fe-9ae61f86abf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098478534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2098478534
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2040439274
Short name T40
Test name
Test status
Simulation time 6063206505 ps
CPU time 16.35 seconds
Started Aug 17 05:16:38 PM PDT 24
Finished Aug 17 05:16:54 PM PDT 24
Peak memory 199200 kb
Host smart-818def62-4c58-4eca-ab96-be1658744a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040439274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2040439274
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2569507559
Short name T482
Test name
Test status
Simulation time 175410107167 ps
CPU time 60.85 seconds
Started Aug 17 05:16:43 PM PDT 24
Finished Aug 17 05:17:43 PM PDT 24
Peak memory 200880 kb
Host smart-3dc5ec1d-4b89-4de1-9317-017d576ed52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569507559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2569507559
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2894922037
Short name T329
Test name
Test status
Simulation time 34993953093 ps
CPU time 10.58 seconds
Started Aug 17 05:16:35 PM PDT 24
Finished Aug 17 05:16:46 PM PDT 24
Peak memory 197044 kb
Host smart-0a30cfd1-b58d-4608-8d0a-a845f378113c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894922037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2894922037
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3823057282
Short name T1022
Test name
Test status
Simulation time 733122737 ps
CPU time 1.55 seconds
Started Aug 17 05:16:37 PM PDT 24
Finished Aug 17 05:16:39 PM PDT 24
Peak memory 199816 kb
Host smart-a29e8ec5-a230-4155-89d2-99bb1d87621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823057282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3823057282
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1618320916
Short name T1049
Test name
Test status
Simulation time 105107295065 ps
CPU time 63.45 seconds
Started Aug 17 05:16:44 PM PDT 24
Finished Aug 17 05:17:47 PM PDT 24
Peak memory 200964 kb
Host smart-e149edd6-6ac5-48b2-be17-f5f852107eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618320916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1618320916
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2129749761
Short name T126
Test name
Test status
Simulation time 6042666844 ps
CPU time 26.28 seconds
Started Aug 17 05:16:49 PM PDT 24
Finished Aug 17 05:17:15 PM PDT 24
Peak memory 217384 kb
Host smart-1393647e-2186-4683-be52-b00942d1feb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129749761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2129749761
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3196306729
Short name T93
Test name
Test status
Simulation time 6200054939 ps
CPU time 1.98 seconds
Started Aug 17 05:16:44 PM PDT 24
Finished Aug 17 05:16:46 PM PDT 24
Peak memory 200312 kb
Host smart-90506627-d817-4933-a4c8-5200f117c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196306729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3196306729
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2822852840
Short name T1100
Test name
Test status
Simulation time 182077031706 ps
CPU time 53.73 seconds
Started Aug 17 05:16:35 PM PDT 24
Finished Aug 17 05:17:28 PM PDT 24
Peak memory 200948 kb
Host smart-750dd1de-9e13-4a55-8f95-50ad08a18192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822852840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2822852840
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3522583923
Short name T706
Test name
Test status
Simulation time 39492488 ps
CPU time 0.61 seconds
Started Aug 17 05:17:07 PM PDT 24
Finished Aug 17 05:17:08 PM PDT 24
Peak memory 195668 kb
Host smart-79105944-74b8-4bdc-aa18-088aaed13a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522583923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3522583923
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1789422062
Short name T854
Test name
Test status
Simulation time 44072166055 ps
CPU time 15.72 seconds
Started Aug 17 05:16:53 PM PDT 24
Finished Aug 17 05:17:09 PM PDT 24
Peak memory 200944 kb
Host smart-42abb5bc-d1c1-442e-b3fc-2fa5f72047cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789422062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1789422062
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1551437849
Short name T556
Test name
Test status
Simulation time 82889359092 ps
CPU time 38.61 seconds
Started Aug 17 05:16:50 PM PDT 24
Finished Aug 17 05:17:29 PM PDT 24
Peak memory 200984 kb
Host smart-043cd65f-0142-4e9d-9bed-abc72d21d316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551437849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1551437849
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.492563412
Short name T935
Test name
Test status
Simulation time 43979021073 ps
CPU time 59.28 seconds
Started Aug 17 05:16:58 PM PDT 24
Finished Aug 17 05:17:58 PM PDT 24
Peak memory 200876 kb
Host smart-879c27e2-0874-49e3-b6c9-2f1da7e1fade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492563412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.492563412
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3496433948
Short name T419
Test name
Test status
Simulation time 41080520942 ps
CPU time 69.2 seconds
Started Aug 17 05:17:02 PM PDT 24
Finished Aug 17 05:18:11 PM PDT 24
Peak memory 199752 kb
Host smart-4d3b1f7c-0999-4498-98b9-447dc8ec9463
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496433948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3496433948
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3477401858
Short name T540
Test name
Test status
Simulation time 280295934438 ps
CPU time 350.78 seconds
Started Aug 17 05:17:00 PM PDT 24
Finished Aug 17 05:22:51 PM PDT 24
Peak memory 200912 kb
Host smart-b0b9c247-9f41-425b-a2b9-5eab46252706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477401858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3477401858
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1102742968
Short name T732
Test name
Test status
Simulation time 1410876707 ps
CPU time 1.85 seconds
Started Aug 17 05:17:00 PM PDT 24
Finished Aug 17 05:17:02 PM PDT 24
Peak memory 196944 kb
Host smart-a425acd2-5673-4538-9ce8-b00ebf58bfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102742968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1102742968
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2144465358
Short name T23
Test name
Test status
Simulation time 87390576332 ps
CPU time 64.76 seconds
Started Aug 17 05:16:58 PM PDT 24
Finished Aug 17 05:18:03 PM PDT 24
Peak memory 201176 kb
Host smart-254f43e6-3ccf-42bd-baf5-6f1eae8dd193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144465358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2144465358
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3939580061
Short name T983
Test name
Test status
Simulation time 15161462466 ps
CPU time 219.54 seconds
Started Aug 17 05:17:00 PM PDT 24
Finished Aug 17 05:20:40 PM PDT 24
Peak memory 200832 kb
Host smart-f1d7525a-605d-4dfe-8c30-ea3eb39f365e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939580061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3939580061
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2848455166
Short name T645
Test name
Test status
Simulation time 5545056752 ps
CPU time 10.1 seconds
Started Aug 17 05:16:54 PM PDT 24
Finished Aug 17 05:17:04 PM PDT 24
Peak memory 200708 kb
Host smart-7b89a946-1541-478e-8030-2343e6a74869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2848455166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2848455166
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.659840175
Short name T676
Test name
Test status
Simulation time 23914206076 ps
CPU time 75.32 seconds
Started Aug 17 05:17:00 PM PDT 24
Finished Aug 17 05:18:15 PM PDT 24
Peak memory 200960 kb
Host smart-b8a867e4-6cc3-4a18-a094-6ef8fd689d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659840175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.659840175
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.778800889
Short name T655
Test name
Test status
Simulation time 3522480391 ps
CPU time 2.16 seconds
Started Aug 17 05:16:59 PM PDT 24
Finished Aug 17 05:17:01 PM PDT 24
Peak memory 197428 kb
Host smart-b4fd16ae-9f28-4c70-9938-a68c4a3b9d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778800889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.778800889
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3525232239
Short name T726
Test name
Test status
Simulation time 993529489 ps
CPU time 1.45 seconds
Started Aug 17 05:16:52 PM PDT 24
Finished Aug 17 05:16:53 PM PDT 24
Peak memory 199604 kb
Host smart-9c063b2e-114e-4df6-ab54-99b1b671d413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525232239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3525232239
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.862852693
Short name T944
Test name
Test status
Simulation time 297874031625 ps
CPU time 429.47 seconds
Started Aug 17 05:17:08 PM PDT 24
Finished Aug 17 05:24:17 PM PDT 24
Peak memory 201004 kb
Host smart-072c22ec-cdf9-402d-be64-a46287661a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862852693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.862852693
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3456198454
Short name T1123
Test name
Test status
Simulation time 7146900638 ps
CPU time 72.26 seconds
Started Aug 17 05:17:00 PM PDT 24
Finished Aug 17 05:18:12 PM PDT 24
Peak memory 209212 kb
Host smart-815afb82-b809-452f-b8a7-dfa09294ce9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456198454 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3456198454
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.215284242
Short name T770
Test name
Test status
Simulation time 1246294193 ps
CPU time 2.98 seconds
Started Aug 17 05:17:01 PM PDT 24
Finished Aug 17 05:17:04 PM PDT 24
Peak memory 200596 kb
Host smart-c028259b-1d51-4844-99ba-2b65847a6472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215284242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.215284242
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1439527659
Short name T745
Test name
Test status
Simulation time 25126037834 ps
CPU time 41.29 seconds
Started Aug 17 05:16:57 PM PDT 24
Finished Aug 17 05:17:38 PM PDT 24
Peak memory 200904 kb
Host smart-08fe9218-7486-4981-a7a1-bc1f08a6eb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439527659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1439527659
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.691148624
Short name T414
Test name
Test status
Simulation time 16351479 ps
CPU time 0.55 seconds
Started Aug 17 05:17:21 PM PDT 24
Finished Aug 17 05:17:22 PM PDT 24
Peak memory 196252 kb
Host smart-f76ca81f-c8f5-4f9e-8296-2717ce5d9c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691148624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.691148624
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2853946910
Short name T1140
Test name
Test status
Simulation time 124123644798 ps
CPU time 192.68 seconds
Started Aug 17 05:17:06 PM PDT 24
Finished Aug 17 05:20:19 PM PDT 24
Peak memory 200876 kb
Host smart-03f8d99d-88a9-4ca8-a798-9f7ab2bc3dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853946910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2853946910
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.4288568640
Short name T600
Test name
Test status
Simulation time 75922566077 ps
CPU time 126.07 seconds
Started Aug 17 05:17:17 PM PDT 24
Finished Aug 17 05:19:23 PM PDT 24
Peak memory 200864 kb
Host smart-3d6004ab-64b3-44a3-8825-663f93a45fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288568640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4288568640
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2940846304
Short name T220
Test name
Test status
Simulation time 20970637672 ps
CPU time 34.6 seconds
Started Aug 17 05:17:15 PM PDT 24
Finished Aug 17 05:17:50 PM PDT 24
Peak memory 200924 kb
Host smart-557274b9-ceaf-4e8b-b38d-c973f17f0299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940846304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2940846304
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2520304405
Short name T22
Test name
Test status
Simulation time 77608553251 ps
CPU time 60.98 seconds
Started Aug 17 05:17:15 PM PDT 24
Finished Aug 17 05:18:16 PM PDT 24
Peak memory 200960 kb
Host smart-99a9a416-6a36-4d86-b409-8d8ae7d3a275
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520304405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2520304405
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.31697833
Short name T1065
Test name
Test status
Simulation time 126610391564 ps
CPU time 161.03 seconds
Started Aug 17 05:17:23 PM PDT 24
Finished Aug 17 05:20:04 PM PDT 24
Peak memory 200864 kb
Host smart-8e563e0e-57a3-4ca8-a326-99dfa3ffd5d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31697833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.31697833
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1958696592
Short name T842
Test name
Test status
Simulation time 5782871035 ps
CPU time 2.87 seconds
Started Aug 17 05:17:23 PM PDT 24
Finished Aug 17 05:17:26 PM PDT 24
Peak memory 200432 kb
Host smart-b6f874bc-61c2-4ac5-9d62-755814055c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958696592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1958696592
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.645881444
Short name T474
Test name
Test status
Simulation time 50631995632 ps
CPU time 38.56 seconds
Started Aug 17 05:17:16 PM PDT 24
Finished Aug 17 05:17:54 PM PDT 24
Peak memory 201116 kb
Host smart-7c69f552-07e1-4505-a448-0e7cdda12e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645881444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.645881444
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.79354508
Short name T898
Test name
Test status
Simulation time 10740105403 ps
CPU time 489.33 seconds
Started Aug 17 05:17:28 PM PDT 24
Finished Aug 17 05:25:38 PM PDT 24
Peak memory 200832 kb
Host smart-24f71d67-6013-4ab3-aa06-32823d4d86ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79354508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.79354508
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2302037944
Short name T545
Test name
Test status
Simulation time 6483190878 ps
CPU time 14.72 seconds
Started Aug 17 05:17:15 PM PDT 24
Finished Aug 17 05:17:30 PM PDT 24
Peak memory 198932 kb
Host smart-b8751d6b-127e-45df-a1a7-84e06f7c72ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302037944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2302037944
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3360267848
Short name T679
Test name
Test status
Simulation time 47591791237 ps
CPU time 23.03 seconds
Started Aug 17 05:17:15 PM PDT 24
Finished Aug 17 05:17:39 PM PDT 24
Peak memory 200952 kb
Host smart-1aab2f75-1498-48f0-8f3e-375911146fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360267848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3360267848
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2535361428
Short name T78
Test name
Test status
Simulation time 3299553386 ps
CPU time 4.93 seconds
Started Aug 17 05:17:15 PM PDT 24
Finished Aug 17 05:17:20 PM PDT 24
Peak memory 197236 kb
Host smart-1ee5dc0d-ab08-4279-af95-0980f46502fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535361428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2535361428
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3640061495
Short name T518
Test name
Test status
Simulation time 514291714 ps
CPU time 1.63 seconds
Started Aug 17 05:17:06 PM PDT 24
Finished Aug 17 05:17:08 PM PDT 24
Peak memory 199228 kb
Host smart-33fea6f2-8a88-44a5-96df-c7c3bdfbd614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640061495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3640061495
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2530467483
Short name T123
Test name
Test status
Simulation time 2005627799 ps
CPU time 43.53 seconds
Started Aug 17 05:17:23 PM PDT 24
Finished Aug 17 05:18:06 PM PDT 24
Peak memory 200928 kb
Host smart-1baa262d-9a56-4532-915b-d802cecadbb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530467483 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2530467483
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.436413227
Short name T1067
Test name
Test status
Simulation time 7643718890 ps
CPU time 9.7 seconds
Started Aug 17 05:17:16 PM PDT 24
Finished Aug 17 05:17:26 PM PDT 24
Peak memory 200604 kb
Host smart-16565b03-3f24-44cd-919f-0af3fc218d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436413227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.436413227
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2235625261
Short name T822
Test name
Test status
Simulation time 20874428222 ps
CPU time 9.03 seconds
Started Aug 17 05:17:06 PM PDT 24
Finished Aug 17 05:17:15 PM PDT 24
Peak memory 200332 kb
Host smart-c2ed6841-a93b-4603-b453-e5d676611f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235625261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2235625261
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.403954082
Short name T1160
Test name
Test status
Simulation time 39634503 ps
CPU time 0.53 seconds
Started Aug 17 05:17:43 PM PDT 24
Finished Aug 17 05:17:43 PM PDT 24
Peak memory 195220 kb
Host smart-9eb66c90-c3cc-42f4-8042-545627e5b4eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403954082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.403954082
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.4176339988
Short name T325
Test name
Test status
Simulation time 79118666619 ps
CPU time 126.76 seconds
Started Aug 17 05:17:23 PM PDT 24
Finished Aug 17 05:19:30 PM PDT 24
Peak memory 200924 kb
Host smart-705127f9-46a9-472a-adcc-0ab39c979748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176339988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4176339988
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2930631819
Short name T147
Test name
Test status
Simulation time 129092122333 ps
CPU time 101.44 seconds
Started Aug 17 05:17:23 PM PDT 24
Finished Aug 17 05:19:05 PM PDT 24
Peak memory 200936 kb
Host smart-0fbe4e4a-174a-437d-8ba9-1157f9d035ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930631819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2930631819
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2663065107
Short name T1011
Test name
Test status
Simulation time 162900896225 ps
CPU time 255.41 seconds
Started Aug 17 05:17:24 PM PDT 24
Finished Aug 17 05:21:40 PM PDT 24
Peak memory 200972 kb
Host smart-64258eb3-8b25-492a-9749-4197b8346b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663065107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2663065107
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.542085138
Short name T1109
Test name
Test status
Simulation time 31170542916 ps
CPU time 49.81 seconds
Started Aug 17 05:17:29 PM PDT 24
Finished Aug 17 05:18:19 PM PDT 24
Peak memory 200940 kb
Host smart-e56111c6-7b8f-4acf-8401-a850b62e2dae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542085138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.542085138
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2723016701
Short name T443
Test name
Test status
Simulation time 152485315543 ps
CPU time 186.78 seconds
Started Aug 17 05:17:43 PM PDT 24
Finished Aug 17 05:20:50 PM PDT 24
Peak memory 200852 kb
Host smart-9723c1ae-7ba4-4bc7-89c1-a1b35e507b68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723016701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2723016701
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2388021554
Short name T665
Test name
Test status
Simulation time 2107129690 ps
CPU time 1.63 seconds
Started Aug 17 05:17:30 PM PDT 24
Finished Aug 17 05:17:32 PM PDT 24
Peak memory 197152 kb
Host smart-131b8ffb-2f8f-4870-aea6-eb9d30eca2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388021554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2388021554
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3021046780
Short name T1023
Test name
Test status
Simulation time 34929114330 ps
CPU time 52.39 seconds
Started Aug 17 05:17:29 PM PDT 24
Finished Aug 17 05:18:22 PM PDT 24
Peak memory 199980 kb
Host smart-3864034c-cc78-424e-8fc6-26d381922889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021046780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3021046780
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2287844831
Short name T734
Test name
Test status
Simulation time 6213357062 ps
CPU time 374.72 seconds
Started Aug 17 05:17:42 PM PDT 24
Finished Aug 17 05:23:57 PM PDT 24
Peak memory 200944 kb
Host smart-bee1dc1d-9fcc-407f-82ef-f3a3bd8a8825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287844831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2287844831
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2519419849
Short name T1003
Test name
Test status
Simulation time 3486808808 ps
CPU time 21.35 seconds
Started Aug 17 05:17:30 PM PDT 24
Finished Aug 17 05:17:51 PM PDT 24
Peak memory 200020 kb
Host smart-3ba25d6f-f898-4d4d-ad6a-3c2d648193a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519419849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2519419849
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.101853274
Short name T907
Test name
Test status
Simulation time 182603124364 ps
CPU time 85.47 seconds
Started Aug 17 05:17:30 PM PDT 24
Finished Aug 17 05:18:55 PM PDT 24
Peak memory 201056 kb
Host smart-9549d7fe-95b6-4ae7-b930-34a33d4a02f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101853274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.101853274
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1116004332
Short name T911
Test name
Test status
Simulation time 3067734402 ps
CPU time 5.29 seconds
Started Aug 17 05:17:30 PM PDT 24
Finished Aug 17 05:17:35 PM PDT 24
Peak memory 197320 kb
Host smart-5bbac480-97e9-4ea3-b8f2-6cbbb5f58a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116004332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1116004332
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3484429445
Short name T678
Test name
Test status
Simulation time 488687964 ps
CPU time 2.73 seconds
Started Aug 17 05:17:23 PM PDT 24
Finished Aug 17 05:17:25 PM PDT 24
Peak memory 199476 kb
Host smart-1201ffda-0959-4784-aa4b-825d1a717be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484429445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3484429445
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1936259095
Short name T209
Test name
Test status
Simulation time 259917594881 ps
CPU time 227.42 seconds
Started Aug 17 05:17:42 PM PDT 24
Finished Aug 17 05:21:29 PM PDT 24
Peak memory 209340 kb
Host smart-1cda0074-2609-4c48-bc3b-2e6ca34ef879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936259095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1936259095
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3019631175
Short name T764
Test name
Test status
Simulation time 6958179896 ps
CPU time 47.65 seconds
Started Aug 17 05:17:30 PM PDT 24
Finished Aug 17 05:18:17 PM PDT 24
Peak memory 200812 kb
Host smart-0d473989-ab2b-4f8a-83e0-c4ada3b8b9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019631175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3019631175
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1914027721
Short name T462
Test name
Test status
Simulation time 26908037554 ps
CPU time 13.9 seconds
Started Aug 17 05:17:30 PM PDT 24
Finished Aug 17 05:17:44 PM PDT 24
Peak memory 200596 kb
Host smart-870be794-a878-435f-848f-fae0c8fa6f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914027721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1914027721
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2217877211
Short name T740
Test name
Test status
Simulation time 25227200 ps
CPU time 0.56 seconds
Started Aug 17 05:17:56 PM PDT 24
Finished Aug 17 05:17:57 PM PDT 24
Peak memory 196236 kb
Host smart-b6c2ccb0-3b45-48f1-a39e-8258aed503a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217877211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2217877211
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1711063302
Short name T402
Test name
Test status
Simulation time 126472431282 ps
CPU time 51.18 seconds
Started Aug 17 05:17:52 PM PDT 24
Finished Aug 17 05:18:43 PM PDT 24
Peak memory 200848 kb
Host smart-05ef504a-601f-4fdb-8295-4f355fad03db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711063302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1711063302
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1166256737
Short name T933
Test name
Test status
Simulation time 147505123626 ps
CPU time 93.93 seconds
Started Aug 17 05:17:53 PM PDT 24
Finished Aug 17 05:19:27 PM PDT 24
Peak memory 200684 kb
Host smart-b64a448f-6a53-4d8d-95b5-04916d6b012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166256737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1166256737
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.291108426
Short name T319
Test name
Test status
Simulation time 23648268286 ps
CPU time 34.38 seconds
Started Aug 17 05:17:53 PM PDT 24
Finished Aug 17 05:18:28 PM PDT 24
Peak memory 200736 kb
Host smart-6d310659-0f7f-4181-abb6-2a480da35a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291108426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.291108426
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1233042256
Short name T598
Test name
Test status
Simulation time 36450787858 ps
CPU time 57.81 seconds
Started Aug 17 05:17:53 PM PDT 24
Finished Aug 17 05:18:51 PM PDT 24
Peak memory 200096 kb
Host smart-b7e7a5b3-cad2-4640-97e5-8f6023838a15
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233042256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1233042256
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3370965842
Short name T282
Test name
Test status
Simulation time 95408156662 ps
CPU time 420.74 seconds
Started Aug 17 05:17:51 PM PDT 24
Finished Aug 17 05:24:51 PM PDT 24
Peak memory 200832 kb
Host smart-468f287e-95ff-48c2-970c-c283851fd328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370965842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3370965842
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.864478737
Short name T492
Test name
Test status
Simulation time 6819314012 ps
CPU time 6.64 seconds
Started Aug 17 05:17:49 PM PDT 24
Finished Aug 17 05:17:56 PM PDT 24
Peak memory 199712 kb
Host smart-8628613e-c661-40a1-bc72-0a07dad2f860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864478737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.864478737
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.274199264
Short name T531
Test name
Test status
Simulation time 62386649695 ps
CPU time 29.45 seconds
Started Aug 17 05:17:50 PM PDT 24
Finished Aug 17 05:18:19 PM PDT 24
Peak memory 201064 kb
Host smart-fd4accc9-65fc-4ba9-bd25-e06849dff993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274199264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.274199264
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1204126760
Short name T306
Test name
Test status
Simulation time 11847016263 ps
CPU time 156.22 seconds
Started Aug 17 05:17:48 PM PDT 24
Finished Aug 17 05:20:24 PM PDT 24
Peak memory 200892 kb
Host smart-9c024dba-00e8-4b9d-9358-6b25c3fd5bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204126760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1204126760
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1531803656
Short name T1179
Test name
Test status
Simulation time 2309065119 ps
CPU time 15.12 seconds
Started Aug 17 05:17:49 PM PDT 24
Finished Aug 17 05:18:04 PM PDT 24
Peak memory 199040 kb
Host smart-167abefb-f6e6-43e6-b915-06412519fc0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531803656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1531803656
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3167613221
Short name T77
Test name
Test status
Simulation time 20797942710 ps
CPU time 11.16 seconds
Started Aug 17 05:17:51 PM PDT 24
Finished Aug 17 05:18:02 PM PDT 24
Peak memory 200860 kb
Host smart-c21d7e44-a17c-4c8f-b791-420cabfe91e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167613221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3167613221
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2333394382
Short name T674
Test name
Test status
Simulation time 3148125302 ps
CPU time 1.86 seconds
Started Aug 17 05:17:53 PM PDT 24
Finished Aug 17 05:17:55 PM PDT 24
Peak memory 197236 kb
Host smart-baf838e3-597f-455c-8034-86aca767d575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333394382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2333394382
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1902741401
Short name T501
Test name
Test status
Simulation time 531718887 ps
CPU time 1.2 seconds
Started Aug 17 05:17:42 PM PDT 24
Finished Aug 17 05:17:43 PM PDT 24
Peak memory 199560 kb
Host smart-39b66cd0-4049-48ff-888f-67f7071a2c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902741401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1902741401
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.4285228152
Short name T1131
Test name
Test status
Simulation time 693403118431 ps
CPU time 118.54 seconds
Started Aug 17 05:17:56 PM PDT 24
Finished Aug 17 05:19:54 PM PDT 24
Peak memory 200908 kb
Host smart-5fe08558-f683-4c79-968e-e56615e34e84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285228152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4285228152
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2093842035
Short name T35
Test name
Test status
Simulation time 6199048159 ps
CPU time 42.39 seconds
Started Aug 17 05:17:49 PM PDT 24
Finished Aug 17 05:18:31 PM PDT 24
Peak memory 201032 kb
Host smart-826c90c2-d1e9-4fae-92aa-5308a2eacbde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093842035 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2093842035
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2190313834
Short name T350
Test name
Test status
Simulation time 2999178342 ps
CPU time 3.14 seconds
Started Aug 17 05:17:53 PM PDT 24
Finished Aug 17 05:17:56 PM PDT 24
Peak memory 200872 kb
Host smart-cef6bf42-ca15-44e3-a1e5-6ff991469dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190313834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2190313834
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.551225492
Short name T425
Test name
Test status
Simulation time 90290426854 ps
CPU time 57.17 seconds
Started Aug 17 05:17:52 PM PDT 24
Finished Aug 17 05:18:49 PM PDT 24
Peak memory 200932 kb
Host smart-1c1d2e9c-26c7-4a03-89a6-590591071993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551225492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.551225492
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1351038362
Short name T746
Test name
Test status
Simulation time 17443394 ps
CPU time 0.52 seconds
Started Aug 17 05:18:12 PM PDT 24
Finished Aug 17 05:18:13 PM PDT 24
Peak memory 195232 kb
Host smart-24ec4a92-4012-4820-b645-049a7d00997b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351038362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1351038362
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.785054914
Short name T838
Test name
Test status
Simulation time 81307944527 ps
CPU time 22.24 seconds
Started Aug 17 05:17:57 PM PDT 24
Finished Aug 17 05:18:20 PM PDT 24
Peak memory 200840 kb
Host smart-bf637a62-f360-4e4a-87d7-a18009fd3ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785054914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.785054914
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.767424805
Short name T1164
Test name
Test status
Simulation time 115286798915 ps
CPU time 243.06 seconds
Started Aug 17 05:17:57 PM PDT 24
Finished Aug 17 05:22:00 PM PDT 24
Peak memory 200932 kb
Host smart-c027a9ad-0b6b-4e4f-bc2f-09fa9d60e970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767424805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.767424805
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1586473199
Short name T175
Test name
Test status
Simulation time 23800287382 ps
CPU time 36.24 seconds
Started Aug 17 05:18:04 PM PDT 24
Finished Aug 17 05:18:41 PM PDT 24
Peak memory 200940 kb
Host smart-4baa4e8b-321f-4306-9b93-746a6fad6bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586473199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1586473199
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.292972108
Short name T121
Test name
Test status
Simulation time 43448749849 ps
CPU time 21.56 seconds
Started Aug 17 05:18:04 PM PDT 24
Finished Aug 17 05:18:26 PM PDT 24
Peak memory 200896 kb
Host smart-2e2fd312-88f4-4a31-a853-926e5a42e389
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292972108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.292972108
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.479252891
Short name T301
Test name
Test status
Simulation time 122908265971 ps
CPU time 290.25 seconds
Started Aug 17 05:18:07 PM PDT 24
Finished Aug 17 05:22:57 PM PDT 24
Peak memory 200864 kb
Host smart-6efbbf71-2396-4729-aa3a-94f92aac1348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479252891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.479252891
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2347186511
Short name T1107
Test name
Test status
Simulation time 2519602535 ps
CPU time 5.82 seconds
Started Aug 17 05:18:05 PM PDT 24
Finished Aug 17 05:18:11 PM PDT 24
Peak memory 200820 kb
Host smart-1afbccb3-fd1d-47a9-b4c1-5e76e4c39fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347186511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2347186511
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.344308120
Short name T458
Test name
Test status
Simulation time 60269114104 ps
CPU time 127.99 seconds
Started Aug 17 05:18:09 PM PDT 24
Finished Aug 17 05:20:17 PM PDT 24
Peak memory 200788 kb
Host smart-6ed1176d-41b3-4554-bf6a-3fca614c2300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344308120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.344308120
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1695963871
Short name T1178
Test name
Test status
Simulation time 8466287793 ps
CPU time 434.28 seconds
Started Aug 17 05:18:05 PM PDT 24
Finished Aug 17 05:25:19 PM PDT 24
Peak memory 200932 kb
Host smart-29baa396-ebd1-4d75-9ab0-9b665accf204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695963871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1695963871
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3694375347
Short name T815
Test name
Test status
Simulation time 4537919259 ps
CPU time 37.49 seconds
Started Aug 17 05:18:05 PM PDT 24
Finished Aug 17 05:18:43 PM PDT 24
Peak memory 200896 kb
Host smart-8f6cca4e-6a24-40ab-8b0b-e7ff8f426e47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694375347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3694375347
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.764259319
Short name T641
Test name
Test status
Simulation time 33756764504 ps
CPU time 56.19 seconds
Started Aug 17 05:18:08 PM PDT 24
Finished Aug 17 05:19:05 PM PDT 24
Peak memory 200924 kb
Host smart-a1ac8ad8-74d0-4ad0-93ec-8f06c95a13cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764259319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.764259319
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3752448902
Short name T876
Test name
Test status
Simulation time 5109102096 ps
CPU time 2.51 seconds
Started Aug 17 05:18:09 PM PDT 24
Finished Aug 17 05:18:11 PM PDT 24
Peak memory 197256 kb
Host smart-fee3a295-c3e1-47c7-98c9-004ceb759de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752448902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3752448902
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1157811482
Short name T630
Test name
Test status
Simulation time 515854702 ps
CPU time 1.64 seconds
Started Aug 17 05:17:56 PM PDT 24
Finished Aug 17 05:17:58 PM PDT 24
Peak memory 199200 kb
Host smart-2593f9a9-9440-40d3-9a9b-0a9132e1f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157811482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1157811482
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.292048009
Short name T642
Test name
Test status
Simulation time 652311990000 ps
CPU time 446.55 seconds
Started Aug 17 05:18:14 PM PDT 24
Finished Aug 17 05:25:40 PM PDT 24
Peak memory 200900 kb
Host smart-86e5215b-2985-4272-8b05-d82d2ff17ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292048009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.292048009
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1971483133
Short name T931
Test name
Test status
Simulation time 2203521251 ps
CPU time 28.86 seconds
Started Aug 17 05:18:17 PM PDT 24
Finished Aug 17 05:18:46 PM PDT 24
Peak memory 209644 kb
Host smart-adbe8f15-1acd-48a7-95fa-27735463a6c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971483133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1971483133
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.861578509
Short name T483
Test name
Test status
Simulation time 963568526 ps
CPU time 3.08 seconds
Started Aug 17 05:18:06 PM PDT 24
Finished Aug 17 05:18:09 PM PDT 24
Peak memory 200516 kb
Host smart-30a8a30e-ce0a-463a-afa0-04cf2aebf89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861578509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.861578509
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2322164651
Short name T359
Test name
Test status
Simulation time 34217889117 ps
CPU time 16.59 seconds
Started Aug 17 05:17:56 PM PDT 24
Finished Aug 17 05:18:13 PM PDT 24
Peak memory 200844 kb
Host smart-89f65a50-3339-4984-bbf4-a2dd6c7053b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322164651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2322164651
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3871254666
Short name T24
Test name
Test status
Simulation time 35399126 ps
CPU time 0.56 seconds
Started Aug 17 05:18:37 PM PDT 24
Finished Aug 17 05:18:38 PM PDT 24
Peak memory 196536 kb
Host smart-de4ab6bf-4f8a-43e2-a4da-4717445aa23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871254666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3871254666
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2938290095
Short name T584
Test name
Test status
Simulation time 69742907132 ps
CPU time 59.75 seconds
Started Aug 17 05:18:08 PM PDT 24
Finished Aug 17 05:19:08 PM PDT 24
Peak memory 200912 kb
Host smart-1b824d8e-3eb1-4de9-8139-705c48a12891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938290095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2938290095
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.4168667043
Short name T534
Test name
Test status
Simulation time 57555760412 ps
CPU time 78.31 seconds
Started Aug 17 05:18:33 PM PDT 24
Finished Aug 17 05:19:51 PM PDT 24
Peak memory 200892 kb
Host smart-e43e7561-9974-4aec-bd67-c85e67508e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168667043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.4168667043
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1807009116
Short name T773
Test name
Test status
Simulation time 131238031100 ps
CPU time 55.3 seconds
Started Aug 17 05:18:21 PM PDT 24
Finished Aug 17 05:19:16 PM PDT 24
Peak memory 200864 kb
Host smart-23024d4a-a1a7-4e15-a232-53638649d561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807009116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1807009116
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.193480932
Short name T1163
Test name
Test status
Simulation time 17375280596 ps
CPU time 14.99 seconds
Started Aug 17 05:18:19 PM PDT 24
Finished Aug 17 05:18:34 PM PDT 24
Peak memory 198652 kb
Host smart-cc78a78d-ea20-48ae-8ff2-0214938fd8d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193480932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.193480932
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2083730189
Short name T1058
Test name
Test status
Simulation time 76216879020 ps
CPU time 75.7 seconds
Started Aug 17 05:18:30 PM PDT 24
Finished Aug 17 05:19:45 PM PDT 24
Peak memory 200976 kb
Host smart-5ff42606-5b51-47d4-9e0e-2f7772371291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083730189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2083730189
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.428335280
Short name T563
Test name
Test status
Simulation time 6348275752 ps
CPU time 14.19 seconds
Started Aug 17 05:18:30 PM PDT 24
Finished Aug 17 05:18:45 PM PDT 24
Peak memory 200612 kb
Host smart-d0bead22-1110-4c5a-b2ee-120aad01d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428335280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.428335280
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3656554252
Short name T881
Test name
Test status
Simulation time 133962164110 ps
CPU time 56.3 seconds
Started Aug 17 05:18:33 PM PDT 24
Finished Aug 17 05:19:29 PM PDT 24
Peak memory 199260 kb
Host smart-2f5985d2-5e7c-4acf-9b43-9353b4a3e01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656554252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3656554252
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.81394848
Short name T475
Test name
Test status
Simulation time 15667062734 ps
CPU time 983.12 seconds
Started Aug 17 05:18:28 PM PDT 24
Finished Aug 17 05:34:51 PM PDT 24
Peak memory 200812 kb
Host smart-11516ea0-6958-4f5d-87aa-e906e3630989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81394848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.81394848
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1469041716
Short name T561
Test name
Test status
Simulation time 4912308762 ps
CPU time 10.44 seconds
Started Aug 17 05:18:21 PM PDT 24
Finished Aug 17 05:18:31 PM PDT 24
Peak memory 200336 kb
Host smart-a4087b03-71db-4d7f-9956-1efaab121088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469041716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1469041716
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.594698689
Short name T820
Test name
Test status
Simulation time 112051331457 ps
CPU time 68.18 seconds
Started Aug 17 05:18:30 PM PDT 24
Finished Aug 17 05:19:38 PM PDT 24
Peak memory 200996 kb
Host smart-cb082ee7-e8a0-4304-a56a-2a8aff99a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594698689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.594698689
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3873986191
Short name T756
Test name
Test status
Simulation time 38512706236 ps
CPU time 14.35 seconds
Started Aug 17 05:18:33 PM PDT 24
Finished Aug 17 05:18:47 PM PDT 24
Peak memory 196692 kb
Host smart-8d027035-729f-4d1f-9b56-b5bb81a3ca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873986191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3873986191
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3564585909
Short name T795
Test name
Test status
Simulation time 523238277 ps
CPU time 1.31 seconds
Started Aug 17 05:18:12 PM PDT 24
Finished Aug 17 05:18:13 PM PDT 24
Peak memory 199556 kb
Host smart-761e4c98-3443-446b-88aa-5ec631fd399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564585909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3564585909
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4258373939
Short name T248
Test name
Test status
Simulation time 291821361876 ps
CPU time 472.65 seconds
Started Aug 17 05:18:30 PM PDT 24
Finished Aug 17 05:26:22 PM PDT 24
Peak memory 200832 kb
Host smart-d4d7b0ce-b4fe-4182-88e0-e591f5cee5d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258373939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4258373939
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3726535311
Short name T1138
Test name
Test status
Simulation time 1569043477 ps
CPU time 19.65 seconds
Started Aug 17 05:18:30 PM PDT 24
Finished Aug 17 05:18:50 PM PDT 24
Peak memory 217316 kb
Host smart-458c8c08-b452-4e20-b33f-7df3c647405f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726535311 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3726535311
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.803744075
Short name T1064
Test name
Test status
Simulation time 971412665 ps
CPU time 2.15 seconds
Started Aug 17 05:18:32 PM PDT 24
Finished Aug 17 05:18:34 PM PDT 24
Peak memory 199760 kb
Host smart-eef5a5da-0aab-448d-878b-8d152239ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803744075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.803744075
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3059968678
Short name T346
Test name
Test status
Simulation time 80170558969 ps
CPU time 58.1 seconds
Started Aug 17 05:18:12 PM PDT 24
Finished Aug 17 05:19:10 PM PDT 24
Peak memory 200944 kb
Host smart-12faa5a7-2b74-4af7-a504-168146a25761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059968678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3059968678
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2119313116
Short name T1068
Test name
Test status
Simulation time 10580013 ps
CPU time 0.55 seconds
Started Aug 17 05:18:56 PM PDT 24
Finished Aug 17 05:18:56 PM PDT 24
Peak memory 195912 kb
Host smart-ed01c540-33f0-4778-8718-0de2fd5b31ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119313116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2119313116
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.233262369
Short name T135
Test name
Test status
Simulation time 27897259616 ps
CPU time 41.44 seconds
Started Aug 17 05:18:37 PM PDT 24
Finished Aug 17 05:19:18 PM PDT 24
Peak memory 200924 kb
Host smart-3deb3203-1213-451f-bb01-2bd89e96d387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233262369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.233262369
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3860446386
Short name T851
Test name
Test status
Simulation time 166323396368 ps
CPU time 206.56 seconds
Started Aug 17 05:18:38 PM PDT 24
Finished Aug 17 05:22:04 PM PDT 24
Peak memory 200936 kb
Host smart-cc1509d8-c4a4-4598-bc62-015e51458ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860446386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3860446386
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1650924196
Short name T794
Test name
Test status
Simulation time 110983461814 ps
CPU time 31.26 seconds
Started Aug 17 05:18:38 PM PDT 24
Finished Aug 17 05:19:09 PM PDT 24
Peak memory 200788 kb
Host smart-866f3ea5-b84b-4d90-959a-92a82121677f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650924196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1650924196
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3210391965
Short name T1176
Test name
Test status
Simulation time 10246370067 ps
CPU time 2.8 seconds
Started Aug 17 05:18:36 PM PDT 24
Finished Aug 17 05:18:39 PM PDT 24
Peak memory 197440 kb
Host smart-6ca7fd29-9b12-440b-89b0-41dc09c632a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210391965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3210391965
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2773440970
Short name T986
Test name
Test status
Simulation time 63174986057 ps
CPU time 605.04 seconds
Started Aug 17 05:18:47 PM PDT 24
Finished Aug 17 05:28:52 PM PDT 24
Peak memory 200960 kb
Host smart-c365ffc1-d544-457a-a4bf-b0d91e31491a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773440970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2773440970
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.4007601891
Short name T572
Test name
Test status
Simulation time 9562871106 ps
CPU time 39.42 seconds
Started Aug 17 05:18:46 PM PDT 24
Finished Aug 17 05:19:26 PM PDT 24
Peak memory 200896 kb
Host smart-90bfa4b8-4936-4cfa-acbe-bdaed82b9a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007601891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4007601891
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2059177097
Short name T1029
Test name
Test status
Simulation time 28774132592 ps
CPU time 44.87 seconds
Started Aug 17 05:18:40 PM PDT 24
Finished Aug 17 05:19:25 PM PDT 24
Peak memory 201108 kb
Host smart-187b3090-0d25-479f-bf09-22692b7f5062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059177097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2059177097
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4103963153
Short name T724
Test name
Test status
Simulation time 11693174998 ps
CPU time 118.29 seconds
Started Aug 17 05:18:46 PM PDT 24
Finished Aug 17 05:20:44 PM PDT 24
Peak memory 200860 kb
Host smart-3c15fd4f-a455-46cb-8ff2-8c4a1ce36b6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103963153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4103963153
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2274733805
Short name T400
Test name
Test status
Simulation time 5446321146 ps
CPU time 46.67 seconds
Started Aug 17 05:18:37 PM PDT 24
Finished Aug 17 05:19:24 PM PDT 24
Peak memory 200108 kb
Host smart-e02aa080-f6f8-460a-a8e4-81562195e90b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274733805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2274733805
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2004293640
Short name T702
Test name
Test status
Simulation time 73444170190 ps
CPU time 28.28 seconds
Started Aug 17 05:18:48 PM PDT 24
Finished Aug 17 05:19:17 PM PDT 24
Peak memory 200960 kb
Host smart-1b23eb56-2fa8-4ef9-8041-727a1731c25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004293640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2004293640
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2492947018
Short name T358
Test name
Test status
Simulation time 55067108865 ps
CPU time 91.77 seconds
Started Aug 17 05:18:48 PM PDT 24
Finished Aug 17 05:20:20 PM PDT 24
Peak memory 197628 kb
Host smart-c1a3d470-3f41-4c7c-a95b-6c61e4bd46b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492947018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2492947018
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.127688194
Short name T956
Test name
Test status
Simulation time 6040297704 ps
CPU time 5.07 seconds
Started Aug 17 05:18:37 PM PDT 24
Finished Aug 17 05:18:43 PM PDT 24
Peak memory 200472 kb
Host smart-1e014155-938f-4987-90be-fbf51a1f75f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127688194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.127688194
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3552851622
Short name T1150
Test name
Test status
Simulation time 3446702478 ps
CPU time 21.83 seconds
Started Aug 17 05:18:44 PM PDT 24
Finished Aug 17 05:19:06 PM PDT 24
Peak memory 217176 kb
Host smart-da6150fc-3892-4d66-97fa-d950db396184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552851622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3552851622
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4136792923
Short name T638
Test name
Test status
Simulation time 9798408849 ps
CPU time 6.03 seconds
Started Aug 17 05:18:47 PM PDT 24
Finished Aug 17 05:18:53 PM PDT 24
Peak memory 200496 kb
Host smart-4d4da928-a3e5-48cf-b200-3a9b45d60dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136792923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4136792923
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1440218350
Short name T348
Test name
Test status
Simulation time 27622924946 ps
CPU time 28.18 seconds
Started Aug 17 05:18:37 PM PDT 24
Finished Aug 17 05:19:06 PM PDT 24
Peak memory 200924 kb
Host smart-ff3465b2-cce5-4c59-9334-9d966b7b0266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440218350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1440218350
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3874553769
Short name T477
Test name
Test status
Simulation time 11654416 ps
CPU time 0.57 seconds
Started Aug 17 05:19:01 PM PDT 24
Finished Aug 17 05:19:02 PM PDT 24
Peak memory 196184 kb
Host smart-d250f728-a6e3-4a31-b83d-f63f86b9869f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874553769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3874553769
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.4009378663
Short name T689
Test name
Test status
Simulation time 29982686673 ps
CPU time 23.48 seconds
Started Aug 17 05:18:56 PM PDT 24
Finished Aug 17 05:19:19 PM PDT 24
Peak memory 200964 kb
Host smart-ab30e881-4c9f-4a2c-a608-c71b13525c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009378663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4009378663
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3551052278
Short name T453
Test name
Test status
Simulation time 6368778257 ps
CPU time 10 seconds
Started Aug 17 05:18:54 PM PDT 24
Finished Aug 17 05:19:04 PM PDT 24
Peak memory 200768 kb
Host smart-8a798785-288b-4d66-939e-8c97e68233d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551052278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3551052278
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1311051611
Short name T356
Test name
Test status
Simulation time 23888551391 ps
CPU time 45.6 seconds
Started Aug 17 05:18:55 PM PDT 24
Finished Aug 17 05:19:40 PM PDT 24
Peak memory 200780 kb
Host smart-e764c085-a786-4230-904b-aa7b5bbd53de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311051611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1311051611
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3742261986
Short name T1046
Test name
Test status
Simulation time 49243588310 ps
CPU time 85.67 seconds
Started Aug 17 05:18:56 PM PDT 24
Finished Aug 17 05:20:21 PM PDT 24
Peak memory 200928 kb
Host smart-4fafe063-ce27-41be-8050-b4d193238ea7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742261986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3742261986
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1269138525
Short name T583
Test name
Test status
Simulation time 71121825891 ps
CPU time 452.31 seconds
Started Aug 17 05:19:05 PM PDT 24
Finished Aug 17 05:26:37 PM PDT 24
Peak memory 200920 kb
Host smart-01b67003-c681-456f-aa29-76fc53a92eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269138525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1269138525
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3705353404
Short name T408
Test name
Test status
Simulation time 5891225018 ps
CPU time 10.96 seconds
Started Aug 17 05:19:02 PM PDT 24
Finished Aug 17 05:19:13 PM PDT 24
Peak memory 200404 kb
Host smart-bdb923ce-d453-47de-aef1-f6a3d3638ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705353404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3705353404
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3958720448
Short name T317
Test name
Test status
Simulation time 88740505316 ps
CPU time 143.24 seconds
Started Aug 17 05:19:02 PM PDT 24
Finished Aug 17 05:21:25 PM PDT 24
Peak memory 200968 kb
Host smart-2be790b4-acba-45cf-a21a-7fb3fd8c26ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958720448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3958720448
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3888854424
Short name T870
Test name
Test status
Simulation time 12015071971 ps
CPU time 551.21 seconds
Started Aug 17 05:19:01 PM PDT 24
Finished Aug 17 05:28:12 PM PDT 24
Peak memory 200944 kb
Host smart-aeb489c4-0806-4b9b-a705-3138f8422a96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888854424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3888854424
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.853606606
Short name T384
Test name
Test status
Simulation time 2543580647 ps
CPU time 3.77 seconds
Started Aug 17 05:18:55 PM PDT 24
Finished Aug 17 05:18:59 PM PDT 24
Peak memory 199340 kb
Host smart-7221f4e8-57fd-4e1b-872f-3ddb6f03f254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853606606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.853606606
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1157968564
Short name T915
Test name
Test status
Simulation time 39099557268 ps
CPU time 16.98 seconds
Started Aug 17 05:19:00 PM PDT 24
Finished Aug 17 05:19:17 PM PDT 24
Peak memory 200720 kb
Host smart-a9bfac87-cc5d-4209-a891-f109cc2d9f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157968564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1157968564
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.712587187
Short name T993
Test name
Test status
Simulation time 701388188 ps
CPU time 1.46 seconds
Started Aug 17 05:19:01 PM PDT 24
Finished Aug 17 05:19:02 PM PDT 24
Peak memory 196448 kb
Host smart-a4d76fe3-4e98-4121-8eb4-e657f958044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712587187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.712587187
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2366683595
Short name T491
Test name
Test status
Simulation time 112756702 ps
CPU time 0.8 seconds
Started Aug 17 05:18:53 PM PDT 24
Finished Aug 17 05:18:54 PM PDT 24
Peak memory 197860 kb
Host smart-9b71af95-d59f-4375-9746-e3d786709342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366683595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2366683595
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1503613626
Short name T846
Test name
Test status
Simulation time 936106177 ps
CPU time 4.09 seconds
Started Aug 17 05:19:02 PM PDT 24
Finished Aug 17 05:19:06 PM PDT 24
Peak memory 200960 kb
Host smart-cfce78ac-281f-4e14-826e-bd91288ddc17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503613626 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1503613626
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3023603847
Short name T1061
Test name
Test status
Simulation time 4408409787 ps
CPU time 1.83 seconds
Started Aug 17 05:19:01 PM PDT 24
Finished Aug 17 05:19:02 PM PDT 24
Peak memory 199620 kb
Host smart-b7636f56-d620-4cfd-a692-49a1465b7d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023603847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3023603847
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3995301326
Short name T615
Test name
Test status
Simulation time 7834984637 ps
CPU time 12.91 seconds
Started Aug 17 05:18:55 PM PDT 24
Finished Aug 17 05:19:08 PM PDT 24
Peak memory 200932 kb
Host smart-a8483eae-b89c-406a-8b5f-ced8764b0112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995301326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3995301326
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.108655314
Short name T653
Test name
Test status
Simulation time 13159918 ps
CPU time 0.57 seconds
Started Aug 17 05:19:27 PM PDT 24
Finished Aug 17 05:19:27 PM PDT 24
Peak memory 196536 kb
Host smart-6c0a50b8-e56b-486f-a2b4-5a797de33c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108655314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.108655314
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1467299449
Short name T193
Test name
Test status
Simulation time 120254997337 ps
CPU time 48.42 seconds
Started Aug 17 05:19:08 PM PDT 24
Finished Aug 17 05:19:57 PM PDT 24
Peak memory 200868 kb
Host smart-ef6f5edb-6135-4884-9187-f9b3c1238ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467299449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1467299449
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1701858346
Short name T46
Test name
Test status
Simulation time 19486856313 ps
CPU time 16.55 seconds
Started Aug 17 05:19:08 PM PDT 24
Finished Aug 17 05:19:25 PM PDT 24
Peak memory 200916 kb
Host smart-975547f3-b0eb-4208-9640-f5c3bc5a1839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701858346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1701858346
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3822596575
Short name T1171
Test name
Test status
Simulation time 34596900493 ps
CPU time 78.17 seconds
Started Aug 17 05:19:19 PM PDT 24
Finished Aug 17 05:20:37 PM PDT 24
Peak memory 200884 kb
Host smart-cc2c7972-a616-428f-b5cd-ceebd3a5c733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822596575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3822596575
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3092029907
Short name T760
Test name
Test status
Simulation time 73099534926 ps
CPU time 25.65 seconds
Started Aug 17 05:19:19 PM PDT 24
Finished Aug 17 05:19:44 PM PDT 24
Peak memory 200900 kb
Host smart-78be9e94-70e8-473c-80ac-db58373324bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092029907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3092029907
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1675086200
Short name T1114
Test name
Test status
Simulation time 93463262391 ps
CPU time 224.65 seconds
Started Aug 17 05:19:26 PM PDT 24
Finished Aug 17 05:23:11 PM PDT 24
Peak memory 200960 kb
Host smart-c28bcbb6-c964-4009-b4eb-6ee3910e0b62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675086200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1675086200
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1092158712
Short name T817
Test name
Test status
Simulation time 8717368377 ps
CPU time 19.45 seconds
Started Aug 17 05:19:29 PM PDT 24
Finished Aug 17 05:19:48 PM PDT 24
Peak memory 200832 kb
Host smart-cb4dbb69-5960-432e-87ad-0e30a40a5870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092158712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1092158712
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3019035243
Short name T569
Test name
Test status
Simulation time 24135239678 ps
CPU time 11.25 seconds
Started Aug 17 05:19:18 PM PDT 24
Finished Aug 17 05:19:29 PM PDT 24
Peak memory 195544 kb
Host smart-a171d059-3c9e-48e5-b219-e43012f75fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019035243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3019035243
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.104277876
Short name T628
Test name
Test status
Simulation time 8016973057 ps
CPU time 398.29 seconds
Started Aug 17 05:19:27 PM PDT 24
Finished Aug 17 05:26:06 PM PDT 24
Peak memory 200956 kb
Host smart-9c39e1ed-8fae-4774-bfab-c835b3e83bc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104277876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.104277876
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2224464957
Short name T1074
Test name
Test status
Simulation time 3369876133 ps
CPU time 11.99 seconds
Started Aug 17 05:19:17 PM PDT 24
Finished Aug 17 05:19:30 PM PDT 24
Peak memory 199324 kb
Host smart-ab5efeb7-1cac-4b05-8c28-cd1d87068665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224464957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2224464957
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3171751593
Short name T1134
Test name
Test status
Simulation time 26621000897 ps
CPU time 28.13 seconds
Started Aug 17 05:19:19 PM PDT 24
Finished Aug 17 05:19:47 PM PDT 24
Peak memory 200920 kb
Host smart-aed40325-a9f6-4eed-a026-89a6a9cc17fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171751593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3171751593
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1980992754
Short name T617
Test name
Test status
Simulation time 1250846055 ps
CPU time 2.46 seconds
Started Aug 17 05:19:17 PM PDT 24
Finished Aug 17 05:19:20 PM PDT 24
Peak memory 196416 kb
Host smart-6b1dfcb3-b55f-405d-9cc7-85acf351f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980992754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1980992754
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1708525649
Short name T671
Test name
Test status
Simulation time 5872906150 ps
CPU time 12.55 seconds
Started Aug 17 05:19:09 PM PDT 24
Finished Aug 17 05:19:21 PM PDT 24
Peak memory 200852 kb
Host smart-0320855f-81b3-4afd-a40d-1ef9c1321b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708525649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1708525649
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2355561806
Short name T761
Test name
Test status
Simulation time 12156563201 ps
CPU time 13.77 seconds
Started Aug 17 05:19:28 PM PDT 24
Finished Aug 17 05:19:42 PM PDT 24
Peak memory 200964 kb
Host smart-e4048faf-c04b-4215-8dd2-c7e05049ddb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355561806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2355561806
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4268886588
Short name T614
Test name
Test status
Simulation time 5439119638 ps
CPU time 94.4 seconds
Started Aug 17 05:19:26 PM PDT 24
Finished Aug 17 05:21:00 PM PDT 24
Peak memory 217584 kb
Host smart-fc8c0b6d-9691-4e09-8bae-774e41e4bfcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268886588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4268886588
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3258052006
Short name T885
Test name
Test status
Simulation time 1694306111 ps
CPU time 2.74 seconds
Started Aug 17 05:19:17 PM PDT 24
Finished Aug 17 05:19:20 PM PDT 24
Peak memory 200852 kb
Host smart-5c625914-1cc8-475f-a5ce-739ba5b8f9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258052006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3258052006
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.4077843054
Short name T94
Test name
Test status
Simulation time 142048791598 ps
CPU time 53.21 seconds
Started Aug 17 05:19:08 PM PDT 24
Finished Aug 17 05:20:02 PM PDT 24
Peak memory 200936 kb
Host smart-0de8d0ab-3ccc-4c18-a15e-8dd287003f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077843054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4077843054
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2017403658
Short name T522
Test name
Test status
Simulation time 115546466 ps
CPU time 0.57 seconds
Started Aug 17 05:09:57 PM PDT 24
Finished Aug 17 05:09:57 PM PDT 24
Peak memory 196560 kb
Host smart-c6dafc75-7976-464b-852c-ca2897c14b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017403658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2017403658
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1427745562
Short name T719
Test name
Test status
Simulation time 60107841354 ps
CPU time 130.66 seconds
Started Aug 17 05:09:50 PM PDT 24
Finished Aug 17 05:12:01 PM PDT 24
Peak memory 200896 kb
Host smart-2027f9a7-a6f8-4b33-ad54-5dfc5b3f5067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427745562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1427745562
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3909489599
Short name T977
Test name
Test status
Simulation time 62631250716 ps
CPU time 10.57 seconds
Started Aug 17 05:09:50 PM PDT 24
Finished Aug 17 05:10:01 PM PDT 24
Peak memory 200896 kb
Host smart-e5c72236-2fe3-4ee0-a770-5898b975fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909489599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3909489599
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2034639936
Short name T832
Test name
Test status
Simulation time 15415009645 ps
CPU time 27.89 seconds
Started Aug 17 05:09:49 PM PDT 24
Finished Aug 17 05:10:17 PM PDT 24
Peak memory 200864 kb
Host smart-1d4d7278-ca5b-4700-a873-33b4a48ec614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034639936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2034639936
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2111128421
Short name T98
Test name
Test status
Simulation time 21821149013 ps
CPU time 9.52 seconds
Started Aug 17 05:09:47 PM PDT 24
Finished Aug 17 05:09:57 PM PDT 24
Peak memory 200952 kb
Host smart-1fe1ae64-1e85-4f88-a4dd-0c8eaecef909
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111128421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2111128421
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2177162981
Short name T785
Test name
Test status
Simulation time 142552428971 ps
CPU time 766.17 seconds
Started Aug 17 05:09:48 PM PDT 24
Finished Aug 17 05:22:35 PM PDT 24
Peak memory 200944 kb
Host smart-0b63889a-c239-4b12-94c1-038df7b19228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177162981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2177162981
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2968229686
Short name T529
Test name
Test status
Simulation time 1661719870 ps
CPU time 1.9 seconds
Started Aug 17 05:09:47 PM PDT 24
Finished Aug 17 05:09:49 PM PDT 24
Peak memory 200804 kb
Host smart-b4213c10-6dd5-4eb4-aa8f-29fa909e183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968229686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2968229686
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.4279175555
Short name T293
Test name
Test status
Simulation time 79929928710 ps
CPU time 127.32 seconds
Started Aug 17 05:09:49 PM PDT 24
Finished Aug 17 05:11:56 PM PDT 24
Peak memory 209292 kb
Host smart-152801f1-4498-46b4-aa92-8b56e4a21206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279175555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.4279175555
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1623762184
Short name T850
Test name
Test status
Simulation time 12385332834 ps
CPU time 535.66 seconds
Started Aug 17 05:09:49 PM PDT 24
Finished Aug 17 05:18:45 PM PDT 24
Peak memory 200956 kb
Host smart-96618d50-77b6-48b8-beb1-c21a4a536973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1623762184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1623762184
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1712247088
Short name T942
Test name
Test status
Simulation time 3677520751 ps
CPU time 6.07 seconds
Started Aug 17 05:09:49 PM PDT 24
Finished Aug 17 05:09:55 PM PDT 24
Peak memory 199836 kb
Host smart-69d489a2-46cf-462d-8bac-cf4f336c75e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712247088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1712247088
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2928504006
Short name T1155
Test name
Test status
Simulation time 109069171769 ps
CPU time 163.06 seconds
Started Aug 17 05:09:48 PM PDT 24
Finished Aug 17 05:12:31 PM PDT 24
Peak memory 201120 kb
Host smart-b23b9230-54fa-405a-b797-59b3336c90bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928504006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2928504006
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1716294553
Short name T596
Test name
Test status
Simulation time 1782270789 ps
CPU time 2.05 seconds
Started Aug 17 05:09:49 PM PDT 24
Finished Aug 17 05:09:51 PM PDT 24
Peak memory 196348 kb
Host smart-2cb84c84-a677-4e08-82d1-5932489dd1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716294553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1716294553
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.29220678
Short name T91
Test name
Test status
Simulation time 140920156 ps
CPU time 0.78 seconds
Started Aug 17 05:09:55 PM PDT 24
Finished Aug 17 05:09:56 PM PDT 24
Peak memory 218992 kb
Host smart-6057199f-2d19-4eac-b137-8352150504d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29220678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.29220678
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2789079269
Short name T1154
Test name
Test status
Simulation time 5681064416 ps
CPU time 3.26 seconds
Started Aug 17 05:09:48 PM PDT 24
Finished Aug 17 05:09:52 PM PDT 24
Peak memory 200152 kb
Host smart-2047cd14-4431-4035-8299-c92156b6fe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789079269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2789079269
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1785502239
Short name T1053
Test name
Test status
Simulation time 365957183008 ps
CPU time 503.91 seconds
Started Aug 17 05:09:57 PM PDT 24
Finished Aug 17 05:18:21 PM PDT 24
Peak memory 200960 kb
Host smart-1e273bb2-97cf-4387-af50-abccad50054b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785502239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1785502239
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3317966443
Short name T834
Test name
Test status
Simulation time 1157892046 ps
CPU time 5.07 seconds
Started Aug 17 05:09:48 PM PDT 24
Finished Aug 17 05:09:53 PM PDT 24
Peak memory 200808 kb
Host smart-90bc9ac8-8873-4c4b-a5c5-3d6b75bccca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317966443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3317966443
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.340595929
Short name T928
Test name
Test status
Simulation time 21114505170 ps
CPU time 28.54 seconds
Started Aug 17 05:09:47 PM PDT 24
Finished Aug 17 05:10:16 PM PDT 24
Peak memory 200164 kb
Host smart-2f1367e2-c439-4f1a-8d22-927a5af2ac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340595929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.340595929
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2992429156
Short name T636
Test name
Test status
Simulation time 14602809 ps
CPU time 0.57 seconds
Started Aug 17 05:19:52 PM PDT 24
Finished Aug 17 05:19:52 PM PDT 24
Peak memory 196428 kb
Host smart-1f42cf1d-5b87-4ef0-9e1f-e3bed68487fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992429156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2992429156
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3404033671
Short name T700
Test name
Test status
Simulation time 237643205242 ps
CPU time 380.24 seconds
Started Aug 17 05:19:25 PM PDT 24
Finished Aug 17 05:25:45 PM PDT 24
Peak memory 200948 kb
Host smart-32dbfbf6-eee6-443d-ab52-ec1620c66a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404033671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3404033671
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2132565711
Short name T721
Test name
Test status
Simulation time 49523946761 ps
CPU time 19.69 seconds
Started Aug 17 05:19:26 PM PDT 24
Finished Aug 17 05:19:46 PM PDT 24
Peak memory 200920 kb
Host smart-736de682-099e-4af8-b7f5-ded77a59f407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132565711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2132565711
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.4243116872
Short name T415
Test name
Test status
Simulation time 11678404003 ps
CPU time 2.65 seconds
Started Aug 17 05:19:33 PM PDT 24
Finished Aug 17 05:19:36 PM PDT 24
Peak memory 197136 kb
Host smart-0eff487f-5b95-46a3-85a1-42686a7b9398
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243116872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.4243116872
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1666110821
Short name T457
Test name
Test status
Simulation time 103803555595 ps
CPU time 752.36 seconds
Started Aug 17 05:19:40 PM PDT 24
Finished Aug 17 05:32:13 PM PDT 24
Peak memory 200812 kb
Host smart-0c15f0dd-5ae2-413c-b690-9e348c0ac99b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666110821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1666110821
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2776973099
Short name T519
Test name
Test status
Simulation time 83249140 ps
CPU time 0.6 seconds
Started Aug 17 05:19:41 PM PDT 24
Finished Aug 17 05:19:42 PM PDT 24
Peak memory 196756 kb
Host smart-06ef1c30-8994-48ab-a66c-84d57284c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776973099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2776973099
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.701488883
Short name T704
Test name
Test status
Simulation time 196017599623 ps
CPU time 110.02 seconds
Started Aug 17 05:19:34 PM PDT 24
Finished Aug 17 05:21:24 PM PDT 24
Peak memory 209312 kb
Host smart-96b1a795-9979-4c76-baa8-5ecd381a3400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701488883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.701488883
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2149655138
Short name T472
Test name
Test status
Simulation time 23930009645 ps
CPU time 1440.18 seconds
Started Aug 17 05:19:41 PM PDT 24
Finished Aug 17 05:43:41 PM PDT 24
Peak memory 200968 kb
Host smart-2b2287a8-edac-4290-a2ba-21e8a034b748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149655138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2149655138
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2708843321
Short name T1183
Test name
Test status
Simulation time 2221840513 ps
CPU time 3.5 seconds
Started Aug 17 05:19:33 PM PDT 24
Finished Aug 17 05:19:37 PM PDT 24
Peak memory 199492 kb
Host smart-deec6ddc-c0fc-4e08-b281-854e96d22310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708843321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2708843321
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.4235709765
Short name T388
Test name
Test status
Simulation time 34150114237 ps
CPU time 12.72 seconds
Started Aug 17 05:19:32 PM PDT 24
Finished Aug 17 05:19:45 PM PDT 24
Peak memory 196860 kb
Host smart-b1a80397-f655-41af-ae21-c7c8e7b77efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235709765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.4235709765
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3961862487
Short name T1172
Test name
Test status
Simulation time 484371285 ps
CPU time 2.41 seconds
Started Aug 17 05:19:29 PM PDT 24
Finished Aug 17 05:19:31 PM PDT 24
Peak memory 199592 kb
Host smart-7dbc2739-70dd-4588-a375-1be7e404256c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961862487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3961862487
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2260808489
Short name T1170
Test name
Test status
Simulation time 392784482866 ps
CPU time 1443.75 seconds
Started Aug 17 05:19:41 PM PDT 24
Finished Aug 17 05:43:45 PM PDT 24
Peak memory 200940 kb
Host smart-0d58ac7a-4627-4364-a515-c8f7fde65354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260808489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2260808489
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2204332866
Short name T886
Test name
Test status
Simulation time 2719772554 ps
CPU time 32.08 seconds
Started Aug 17 05:19:41 PM PDT 24
Finished Aug 17 05:20:14 PM PDT 24
Peak memory 209380 kb
Host smart-0194fbbe-e2db-4604-87b4-541ae04924b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204332866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2204332866
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.474166577
Short name T779
Test name
Test status
Simulation time 8115874497 ps
CPU time 11.73 seconds
Started Aug 17 05:19:41 PM PDT 24
Finished Aug 17 05:19:53 PM PDT 24
Peak memory 200800 kb
Host smart-1ae0d750-3826-4cdc-bcbb-5e2948561c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474166577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.474166577
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1484696735
Short name T324
Test name
Test status
Simulation time 34185342123 ps
CPU time 26.59 seconds
Started Aug 17 05:19:27 PM PDT 24
Finished Aug 17 05:19:54 PM PDT 24
Peak memory 200988 kb
Host smart-0694391b-8bd9-4d0c-9c7d-bb663714b805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484696735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1484696735
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1568971623
Short name T53
Test name
Test status
Simulation time 15113610 ps
CPU time 0.55 seconds
Started Aug 17 05:20:00 PM PDT 24
Finished Aug 17 05:20:01 PM PDT 24
Peak memory 195236 kb
Host smart-3394e086-d8ee-4c5f-b832-e30b41738844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568971623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1568971623
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.4023239201
Short name T668
Test name
Test status
Simulation time 42326489421 ps
CPU time 66.46 seconds
Started Aug 17 05:19:50 PM PDT 24
Finished Aug 17 05:20:57 PM PDT 24
Peak memory 200828 kb
Host smart-ea1b7d79-0898-47a8-ab0e-caf41f62a01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023239201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4023239201
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2097047173
Short name T160
Test name
Test status
Simulation time 16777270668 ps
CPU time 27.71 seconds
Started Aug 17 05:19:52 PM PDT 24
Finished Aug 17 05:20:20 PM PDT 24
Peak memory 200884 kb
Host smart-02088969-4919-4a5e-8172-6fc19c8c5cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097047173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2097047173
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3966973952
Short name T1051
Test name
Test status
Simulation time 207847411204 ps
CPU time 43.46 seconds
Started Aug 17 05:19:51 PM PDT 24
Finished Aug 17 05:20:35 PM PDT 24
Peak memory 200952 kb
Host smart-c341e0d9-4610-4886-83af-a9525acdeaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966973952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3966973952
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2096563780
Short name T14
Test name
Test status
Simulation time 45732363035 ps
CPU time 17.33 seconds
Started Aug 17 05:19:50 PM PDT 24
Finished Aug 17 05:20:08 PM PDT 24
Peak memory 200092 kb
Host smart-a37dcc87-0cea-4c33-be4a-b5da2aa49607
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096563780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2096563780
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.883448246
Short name T837
Test name
Test status
Simulation time 58208030260 ps
CPU time 146.2 seconds
Started Aug 17 05:19:57 PM PDT 24
Finished Aug 17 05:22:23 PM PDT 24
Peak memory 200920 kb
Host smart-4a3818b6-8caf-43f2-a732-a5f026c88225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883448246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.883448246
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.67366541
Short name T586
Test name
Test status
Simulation time 435165001 ps
CPU time 0.9 seconds
Started Aug 17 05:19:59 PM PDT 24
Finished Aug 17 05:20:00 PM PDT 24
Peak memory 196384 kb
Host smart-0d8eb501-016e-488b-8370-46c970b9267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67366541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.67366541
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2490516653
Short name T814
Test name
Test status
Simulation time 41045995449 ps
CPU time 64.82 seconds
Started Aug 17 05:19:51 PM PDT 24
Finished Aug 17 05:20:56 PM PDT 24
Peak memory 201064 kb
Host smart-81712a3d-c5e8-4baa-8ec5-0e09393b19cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490516653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2490516653
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.514523218
Short name T831
Test name
Test status
Simulation time 20053161519 ps
CPU time 280.64 seconds
Started Aug 17 05:19:58 PM PDT 24
Finished Aug 17 05:24:39 PM PDT 24
Peak memory 200912 kb
Host smart-a7a9232c-9a0c-45e9-a90c-acf88c92173d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514523218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.514523218
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.255038191
Short name T1144
Test name
Test status
Simulation time 4131445064 ps
CPU time 4.17 seconds
Started Aug 17 05:19:51 PM PDT 24
Finished Aug 17 05:19:56 PM PDT 24
Peak memory 199260 kb
Host smart-17251c1e-d7fe-43bd-a8dc-3cb9717607ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255038191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.255038191
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2154357268
Short name T588
Test name
Test status
Simulation time 153737422584 ps
CPU time 270.55 seconds
Started Aug 17 05:19:52 PM PDT 24
Finished Aug 17 05:24:22 PM PDT 24
Peak memory 200824 kb
Host smart-29c05255-eba9-4643-96de-21075315d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154357268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2154357268
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.408728496
Short name T766
Test name
Test status
Simulation time 6064625109 ps
CPU time 10.01 seconds
Started Aug 17 05:19:50 PM PDT 24
Finished Aug 17 05:20:01 PM PDT 24
Peak memory 197444 kb
Host smart-8071fac1-0432-45e4-b387-eee81e540bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408728496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.408728496
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1593731885
Short name T825
Test name
Test status
Simulation time 472000316 ps
CPU time 2.25 seconds
Started Aug 17 05:19:50 PM PDT 24
Finished Aug 17 05:19:52 PM PDT 24
Peak memory 199788 kb
Host smart-a238a6e3-f9ef-420e-9ee6-e432aced23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593731885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1593731885
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.537026703
Short name T658
Test name
Test status
Simulation time 9982606897 ps
CPU time 30.79 seconds
Started Aug 17 05:20:00 PM PDT 24
Finished Aug 17 05:20:30 PM PDT 24
Peak memory 209400 kb
Host smart-2ea28fdf-4cf2-4925-a70b-d7d77da72682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537026703 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.537026703
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2828049236
Short name T401
Test name
Test status
Simulation time 1093371087 ps
CPU time 4.6 seconds
Started Aug 17 05:19:51 PM PDT 24
Finished Aug 17 05:19:55 PM PDT 24
Peak memory 200284 kb
Host smart-f6253ae2-448a-4d71-8f6b-c25ac53eb038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828049236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2828049236
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1679597754
Short name T290
Test name
Test status
Simulation time 217088752075 ps
CPU time 45.24 seconds
Started Aug 17 05:19:50 PM PDT 24
Finished Aug 17 05:20:35 PM PDT 24
Peak memory 200880 kb
Host smart-98988d22-4217-4386-a046-77759b1834d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679597754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1679597754
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1340216817
Short name T865
Test name
Test status
Simulation time 14407524 ps
CPU time 0.55 seconds
Started Aug 17 05:20:12 PM PDT 24
Finished Aug 17 05:20:13 PM PDT 24
Peak memory 196244 kb
Host smart-c664bcd2-2c2d-465b-8863-f0b7c7ca43bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340216817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1340216817
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.892717736
Short name T841
Test name
Test status
Simulation time 93372944506 ps
CPU time 156.41 seconds
Started Aug 17 05:20:00 PM PDT 24
Finished Aug 17 05:22:36 PM PDT 24
Peak memory 200968 kb
Host smart-9db46f59-325a-4ab5-b8dc-0d543d84e492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892717736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.892717736
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2308070828
Short name T1116
Test name
Test status
Simulation time 38320124969 ps
CPU time 76.02 seconds
Started Aug 17 05:20:00 PM PDT 24
Finished Aug 17 05:21:16 PM PDT 24
Peak memory 200956 kb
Host smart-75a4a007-a9a0-4b1c-897c-2a3fb12c0dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308070828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2308070828
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1457453716
Short name T921
Test name
Test status
Simulation time 80261572746 ps
CPU time 31.41 seconds
Started Aug 17 05:20:01 PM PDT 24
Finished Aug 17 05:20:32 PM PDT 24
Peak memory 200856 kb
Host smart-525022de-9a7e-4a38-ac6a-7b7a01f5cd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457453716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1457453716
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1367237583
Short name T1115
Test name
Test status
Simulation time 29287013831 ps
CPU time 52.27 seconds
Started Aug 17 05:20:08 PM PDT 24
Finished Aug 17 05:21:00 PM PDT 24
Peak memory 200928 kb
Host smart-059e7f45-a8fc-48f1-852b-4a02efda7c11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367237583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1367237583
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.984113717
Short name T727
Test name
Test status
Simulation time 48395419167 ps
CPU time 363.64 seconds
Started Aug 17 05:20:07 PM PDT 24
Finished Aug 17 05:26:11 PM PDT 24
Peak memory 200932 kb
Host smart-f45711ad-8ab3-4f13-9d99-53d8baba626e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984113717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.984113717
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1984348126
Short name T1132
Test name
Test status
Simulation time 10869407375 ps
CPU time 17.11 seconds
Started Aug 17 05:20:09 PM PDT 24
Finished Aug 17 05:20:26 PM PDT 24
Peak memory 200484 kb
Host smart-4fdbc8c8-d9d3-4460-9309-a893b5ce175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984348126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1984348126
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3625948501
Short name T1042
Test name
Test status
Simulation time 57928223683 ps
CPU time 26.58 seconds
Started Aug 17 05:20:05 PM PDT 24
Finished Aug 17 05:20:32 PM PDT 24
Peak memory 200480 kb
Host smart-9633ac7f-9b0d-452a-a173-af0c942d6080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625948501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3625948501
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1731176363
Short name T1062
Test name
Test status
Simulation time 2585862333 ps
CPU time 154.52 seconds
Started Aug 17 05:20:08 PM PDT 24
Finished Aug 17 05:22:42 PM PDT 24
Peak memory 200824 kb
Host smart-5a6a4814-1e87-4dea-815a-cef72c401cc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731176363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1731176363
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.4077137533
Short name T99
Test name
Test status
Simulation time 1593545470 ps
CPU time 4.67 seconds
Started Aug 17 05:19:59 PM PDT 24
Finished Aug 17 05:20:04 PM PDT 24
Peak memory 198900 kb
Host smart-ffe615cd-95d6-4452-9d70-f5c67016cbe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077137533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.4077137533
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1535550592
Short name T998
Test name
Test status
Simulation time 136100419453 ps
CPU time 100.58 seconds
Started Aug 17 05:20:07 PM PDT 24
Finished Aug 17 05:21:48 PM PDT 24
Peak memory 200844 kb
Host smart-a0b68e19-3fc7-4eb5-a354-3828f7a65642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535550592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1535550592
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2313990033
Short name T352
Test name
Test status
Simulation time 52931119814 ps
CPU time 22 seconds
Started Aug 17 05:20:09 PM PDT 24
Finished Aug 17 05:20:31 PM PDT 24
Peak memory 197260 kb
Host smart-5be447b4-eab8-4deb-9d4e-2c13e1aacab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313990033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2313990033
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3122648649
Short name T469
Test name
Test status
Simulation time 265926732 ps
CPU time 1.46 seconds
Started Aug 17 05:19:58 PM PDT 24
Finished Aug 17 05:19:59 PM PDT 24
Peak memory 200392 kb
Host smart-fd813b9c-4a04-4ef5-8306-13278bdee52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122648649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3122648649
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.670730429
Short name T924
Test name
Test status
Simulation time 552982096596 ps
CPU time 646.66 seconds
Started Aug 17 05:20:07 PM PDT 24
Finished Aug 17 05:30:54 PM PDT 24
Peak memory 200788 kb
Host smart-030fb979-e53a-452d-beae-a191a0278bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670730429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.670730429
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3700679903
Short name T951
Test name
Test status
Simulation time 9671834328 ps
CPU time 73.09 seconds
Started Aug 17 05:20:07 PM PDT 24
Finished Aug 17 05:21:20 PM PDT 24
Peak memory 209412 kb
Host smart-1edad170-3bf9-4968-bdef-8939febb313f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700679903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3700679903
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1111982773
Short name T1069
Test name
Test status
Simulation time 820548271 ps
CPU time 2.55 seconds
Started Aug 17 05:20:09 PM PDT 24
Finished Aug 17 05:20:12 PM PDT 24
Peak memory 199484 kb
Host smart-44ea1be2-57df-4135-ae59-9132d2551574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111982773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1111982773
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4222848296
Short name T525
Test name
Test status
Simulation time 43562533790 ps
CPU time 14.5 seconds
Started Aug 17 05:19:59 PM PDT 24
Finished Aug 17 05:20:14 PM PDT 24
Peak memory 197876 kb
Host smart-0fc88953-9aa9-412e-8165-7cdd0064a57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222848296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4222848296
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1305103953
Short name T548
Test name
Test status
Simulation time 11877054 ps
CPU time 0.56 seconds
Started Aug 17 05:20:21 PM PDT 24
Finished Aug 17 05:20:21 PM PDT 24
Peak memory 196252 kb
Host smart-5a8dd2fb-be8b-46af-b998-68ddb1ace1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305103953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1305103953
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3917610001
Short name T161
Test name
Test status
Simulation time 26580524440 ps
CPU time 19.91 seconds
Started Aug 17 05:20:13 PM PDT 24
Finished Aug 17 05:20:33 PM PDT 24
Peak memory 200824 kb
Host smart-733bc0d8-04ef-45fe-8c7e-5b62c4bc6adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917610001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3917610001
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1105079305
Short name T313
Test name
Test status
Simulation time 141988335052 ps
CPU time 40.64 seconds
Started Aug 17 05:20:15 PM PDT 24
Finished Aug 17 05:20:56 PM PDT 24
Peak memory 200940 kb
Host smart-15aea6b2-7e97-47bc-b04e-238f0e9ae761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105079305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1105079305
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.555202808
Short name T604
Test name
Test status
Simulation time 32340657145 ps
CPU time 52.43 seconds
Started Aug 17 05:20:14 PM PDT 24
Finished Aug 17 05:21:06 PM PDT 24
Peak memory 200908 kb
Host smart-91a6a405-f122-474a-84d1-a9c69e94bd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555202808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.555202808
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1883239199
Short name T684
Test name
Test status
Simulation time 27604830770 ps
CPU time 20.38 seconds
Started Aug 17 05:20:13 PM PDT 24
Finished Aug 17 05:20:34 PM PDT 24
Peak memory 200936 kb
Host smart-04046a87-accf-4b4a-a7ff-4b79e0434525
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883239199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1883239199
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4124925913
Short name T527
Test name
Test status
Simulation time 102793408127 ps
CPU time 342.68 seconds
Started Aug 17 05:20:20 PM PDT 24
Finished Aug 17 05:26:03 PM PDT 24
Peak memory 200936 kb
Host smart-54acf718-33b6-4df1-9d39-b7ba44ce2199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124925913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4124925913
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2625662306
Short name T830
Test name
Test status
Simulation time 3972197308 ps
CPU time 7.12 seconds
Started Aug 17 05:20:22 PM PDT 24
Finished Aug 17 05:20:29 PM PDT 24
Peak memory 199360 kb
Host smart-5843afe2-37ad-4588-ab1f-29f94f9ec53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625662306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2625662306
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3689088723
Short name T1080
Test name
Test status
Simulation time 73882279945 ps
CPU time 58.1 seconds
Started Aug 17 05:20:16 PM PDT 24
Finished Aug 17 05:21:14 PM PDT 24
Peak memory 209312 kb
Host smart-0bd7ec9d-da55-49c6-b4f5-12ed4aaccb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689088723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3689088723
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1323785304
Short name T422
Test name
Test status
Simulation time 17348469248 ps
CPU time 917.23 seconds
Started Aug 17 05:20:22 PM PDT 24
Finished Aug 17 05:35:39 PM PDT 24
Peak memory 200960 kb
Host smart-b5e84949-6bb4-4ee7-ae73-fce9763317ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323785304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1323785304
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3524767357
Short name T829
Test name
Test status
Simulation time 6368610267 ps
CPU time 18.08 seconds
Started Aug 17 05:20:13 PM PDT 24
Finished Aug 17 05:20:32 PM PDT 24
Peak memory 199116 kb
Host smart-114d1497-afe0-4c7e-b967-a4e8a93bbc5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524767357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3524767357
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.94419085
Short name T309
Test name
Test status
Simulation time 26828880521 ps
CPU time 15.4 seconds
Started Aug 17 05:20:16 PM PDT 24
Finished Aug 17 05:20:31 PM PDT 24
Peak memory 200936 kb
Host smart-90c2b2e8-c2a2-42c4-952f-c2ef8d7abd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94419085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.94419085
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.597031663
Short name T1032
Test name
Test status
Simulation time 2736973170 ps
CPU time 1.75 seconds
Started Aug 17 05:20:14 PM PDT 24
Finished Aug 17 05:20:15 PM PDT 24
Peak memory 197448 kb
Host smart-6259d6af-81af-4632-89ec-c00368dadff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597031663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.597031663
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1909993147
Short name T1007
Test name
Test status
Simulation time 459962809 ps
CPU time 2.11 seconds
Started Aug 17 05:20:13 PM PDT 24
Finished Aug 17 05:20:16 PM PDT 24
Peak memory 200820 kb
Host smart-da1d0a35-3fe6-47da-9c42-d9c99cd9ad2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909993147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1909993147
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.33371062
Short name T862
Test name
Test status
Simulation time 332916854593 ps
CPU time 580.4 seconds
Started Aug 17 05:20:21 PM PDT 24
Finished Aug 17 05:30:01 PM PDT 24
Peak memory 200872 kb
Host smart-609eb7cb-ddd2-4b19-9f8f-61e8a07c4525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33371062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.33371062
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.290014636
Short name T21
Test name
Test status
Simulation time 3501894396 ps
CPU time 54.92 seconds
Started Aug 17 05:20:22 PM PDT 24
Finished Aug 17 05:21:17 PM PDT 24
Peak memory 200988 kb
Host smart-3bb54516-1844-47a0-9977-df0da7e02259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290014636 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.290014636
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1442887317
Short name T327
Test name
Test status
Simulation time 7128409133 ps
CPU time 21.77 seconds
Started Aug 17 05:20:22 PM PDT 24
Finished Aug 17 05:20:44 PM PDT 24
Peak memory 200748 kb
Host smart-f93db55c-c0f5-47f4-b2c2-8e76089f9521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442887317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1442887317
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2039239074
Short name T378
Test name
Test status
Simulation time 8883058484 ps
CPU time 17.09 seconds
Started Aug 17 05:20:13 PM PDT 24
Finished Aug 17 05:20:31 PM PDT 24
Peak memory 200944 kb
Host smart-748e5d79-41c5-4ef6-82c4-5685cbc358bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039239074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2039239074
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.316086849
Short name T25
Test name
Test status
Simulation time 40778800 ps
CPU time 0.58 seconds
Started Aug 17 05:20:39 PM PDT 24
Finished Aug 17 05:20:40 PM PDT 24
Peak memory 196264 kb
Host smart-7c56c852-536c-4221-8bcb-2f555d825d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316086849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.316086849
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1554735756
Short name T505
Test name
Test status
Simulation time 19033934979 ps
CPU time 15.53 seconds
Started Aug 17 05:20:24 PM PDT 24
Finished Aug 17 05:20:40 PM PDT 24
Peak memory 200924 kb
Host smart-e03d4176-1a35-404b-beb6-3aa2f7bd4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554735756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1554735756
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2609914652
Short name T610
Test name
Test status
Simulation time 45555625855 ps
CPU time 24.38 seconds
Started Aug 17 05:20:31 PM PDT 24
Finished Aug 17 05:20:56 PM PDT 24
Peak memory 200952 kb
Host smart-850a961e-dee6-4912-9b09-91ce2024b2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609914652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2609914652
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.1718485411
Short name T1072
Test name
Test status
Simulation time 4148983857 ps
CPU time 6.37 seconds
Started Aug 17 05:20:31 PM PDT 24
Finished Aug 17 05:20:38 PM PDT 24
Peak memory 200828 kb
Host smart-0b9f4341-6a7b-470b-8a23-a96bc622074f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718485411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1718485411
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3379005615
Short name T593
Test name
Test status
Simulation time 213626840202 ps
CPU time 203.76 seconds
Started Aug 17 05:20:48 PM PDT 24
Finished Aug 17 05:24:12 PM PDT 24
Peak memory 200952 kb
Host smart-d98dfb5e-998d-4248-b3fc-d531c3d233bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3379005615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3379005615
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3530768095
Short name T490
Test name
Test status
Simulation time 8050094848 ps
CPU time 9.89 seconds
Started Aug 17 05:20:38 PM PDT 24
Finished Aug 17 05:20:48 PM PDT 24
Peak memory 200476 kb
Host smart-7ec19ed5-e574-46aa-8eb5-db56e5cc8778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530768095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3530768095
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3800867761
Short name T945
Test name
Test status
Simulation time 142658978607 ps
CPU time 245.75 seconds
Started Aug 17 05:20:30 PM PDT 24
Finished Aug 17 05:24:36 PM PDT 24
Peak memory 199860 kb
Host smart-5f1fb22f-fdc4-435e-9e4e-52956120985d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800867761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3800867761
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2657530985
Short name T37
Test name
Test status
Simulation time 14327743717 ps
CPU time 449.93 seconds
Started Aug 17 05:20:41 PM PDT 24
Finished Aug 17 05:28:11 PM PDT 24
Peak memory 200800 kb
Host smart-08bc1220-347c-42df-b220-06723a97a2dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657530985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2657530985
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1819825578
Short name T1110
Test name
Test status
Simulation time 4619461745 ps
CPU time 9.15 seconds
Started Aug 17 05:20:30 PM PDT 24
Finished Aug 17 05:20:40 PM PDT 24
Peak memory 198980 kb
Host smart-00799702-68a4-4e0a-9896-ce4dbce23217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819825578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1819825578
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2105000334
Short name T714
Test name
Test status
Simulation time 128800621203 ps
CPU time 180.23 seconds
Started Aug 17 05:20:30 PM PDT 24
Finished Aug 17 05:23:31 PM PDT 24
Peak memory 200876 kb
Host smart-9419fbb0-5027-4553-ad55-925a2b6e0a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105000334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2105000334
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1411369868
Short name T581
Test name
Test status
Simulation time 6028256137 ps
CPU time 1.98 seconds
Started Aug 17 05:20:30 PM PDT 24
Finished Aug 17 05:20:32 PM PDT 24
Peak memory 197420 kb
Host smart-a4e6e415-9844-4cab-ab86-474fd790f9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411369868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1411369868
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1845369544
Short name T1156
Test name
Test status
Simulation time 528532742 ps
CPU time 1.65 seconds
Started Aug 17 05:20:23 PM PDT 24
Finished Aug 17 05:20:25 PM PDT 24
Peak memory 199256 kb
Host smart-a20be54c-fb82-4d80-b99a-981dee801fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845369544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1845369544
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2501410292
Short name T833
Test name
Test status
Simulation time 129269695391 ps
CPU time 235.39 seconds
Started Aug 17 05:20:38 PM PDT 24
Finished Aug 17 05:24:34 PM PDT 24
Peak memory 200812 kb
Host smart-47866252-d2f8-4642-8b53-984edb562407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501410292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2501410292
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.10227224
Short name T106
Test name
Test status
Simulation time 3734939570 ps
CPU time 37.56 seconds
Started Aug 17 05:20:39 PM PDT 24
Finished Aug 17 05:21:16 PM PDT 24
Peak memory 216408 kb
Host smart-4805693a-3252-454c-a0c1-95e4289603d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10227224 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.10227224
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3678695816
Short name T470
Test name
Test status
Simulation time 1285690578 ps
CPU time 1.64 seconds
Started Aug 17 05:20:40 PM PDT 24
Finished Aug 17 05:20:42 PM PDT 24
Peak memory 199312 kb
Host smart-6cb2799a-56fd-4f0a-9d2b-5b613a652e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678695816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3678695816
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.265753804
Short name T1071
Test name
Test status
Simulation time 192928775379 ps
CPU time 32.67 seconds
Started Aug 17 05:20:22 PM PDT 24
Finished Aug 17 05:20:55 PM PDT 24
Peak memory 200948 kb
Host smart-23a17aef-c342-4785-b787-20c77445ebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265753804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.265753804
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.852829648
Short name T798
Test name
Test status
Simulation time 20931768 ps
CPU time 0.57 seconds
Started Aug 17 05:21:03 PM PDT 24
Finished Aug 17 05:21:03 PM PDT 24
Peak memory 196500 kb
Host smart-4b2327e9-4863-44d1-8947-0b220e50a16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852829648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.852829648
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3210099526
Short name T982
Test name
Test status
Simulation time 149227046511 ps
CPU time 157.46 seconds
Started Aug 17 05:20:48 PM PDT 24
Finished Aug 17 05:23:26 PM PDT 24
Peak memory 200936 kb
Host smart-3eb108c2-fb61-4abb-b8b4-d5f6a6ce8e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210099526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3210099526
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.739123128
Short name T533
Test name
Test status
Simulation time 175286831654 ps
CPU time 74.86 seconds
Started Aug 17 05:20:47 PM PDT 24
Finished Aug 17 05:22:02 PM PDT 24
Peak memory 200836 kb
Host smart-1e0b644f-7df0-4af9-9aed-f01f78cfec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739123128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.739123128
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1269323076
Short name T884
Test name
Test status
Simulation time 17630767101 ps
CPU time 30.22 seconds
Started Aug 17 05:20:47 PM PDT 24
Finished Aug 17 05:21:17 PM PDT 24
Peak memory 200756 kb
Host smart-81af455e-2ad0-42f7-9cb9-ae365352944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269323076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1269323076
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3808161853
Short name T611
Test name
Test status
Simulation time 44056269684 ps
CPU time 29.81 seconds
Started Aug 17 05:20:48 PM PDT 24
Finished Aug 17 05:21:18 PM PDT 24
Peak memory 200936 kb
Host smart-5cb84905-cf29-4785-88df-7c91c8326020
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808161853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3808161853
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3679363588
Short name T594
Test name
Test status
Simulation time 182356779120 ps
CPU time 370.13 seconds
Started Aug 17 05:20:56 PM PDT 24
Finished Aug 17 05:27:07 PM PDT 24
Peak memory 200904 kb
Host smart-cff4b552-f644-46a5-8dc8-addade6ed2de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679363588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3679363588
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1500024742
Short name T1125
Test name
Test status
Simulation time 2980232580 ps
CPU time 10.07 seconds
Started Aug 17 05:20:58 PM PDT 24
Finished Aug 17 05:21:08 PM PDT 24
Peak memory 199760 kb
Host smart-918f146e-f296-4172-847b-af617ec5b796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500024742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1500024742
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1159336085
Short name T442
Test name
Test status
Simulation time 47314786447 ps
CPU time 33.09 seconds
Started Aug 17 05:20:47 PM PDT 24
Finished Aug 17 05:21:21 PM PDT 24
Peak memory 209324 kb
Host smart-6a11e7bd-769f-4b0b-8465-186c1c846579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159336085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1159336085
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1737612614
Short name T809
Test name
Test status
Simulation time 11294263419 ps
CPU time 132.57 seconds
Started Aug 17 05:20:56 PM PDT 24
Finished Aug 17 05:23:08 PM PDT 24
Peak memory 200852 kb
Host smart-80ef304f-bd82-4978-a2c9-8b5c39147f02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737612614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1737612614
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.165429606
Short name T639
Test name
Test status
Simulation time 5988517192 ps
CPU time 49.5 seconds
Started Aug 17 05:20:46 PM PDT 24
Finished Aug 17 05:21:36 PM PDT 24
Peak memory 200080 kb
Host smart-9baf32fe-46ed-411c-a372-08cae90fd902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165429606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.165429606
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1627322289
Short name T646
Test name
Test status
Simulation time 52256074550 ps
CPU time 23.41 seconds
Started Aug 17 05:21:00 PM PDT 24
Finished Aug 17 05:21:24 PM PDT 24
Peak memory 200872 kb
Host smart-a1e3adf3-8c17-4654-9ed1-9a8008417ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627322289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1627322289
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4146774274
Short name T528
Test name
Test status
Simulation time 40143072265 ps
CPU time 10.6 seconds
Started Aug 17 05:20:58 PM PDT 24
Finished Aug 17 05:21:09 PM PDT 24
Peak memory 196988 kb
Host smart-65d73319-8d2d-4aa6-bd02-32d692cd8d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146774274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4146774274
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.474171143
Short name T716
Test name
Test status
Simulation time 715746818 ps
CPU time 4.33 seconds
Started Aug 17 05:20:38 PM PDT 24
Finished Aug 17 05:20:42 PM PDT 24
Peak memory 199828 kb
Host smart-64c6e43a-19f1-4784-8309-ed039d38a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474171143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.474171143
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2350054728
Short name T340
Test name
Test status
Simulation time 185479611919 ps
CPU time 212.47 seconds
Started Aug 17 05:20:57 PM PDT 24
Finished Aug 17 05:24:29 PM PDT 24
Peak memory 209280 kb
Host smart-037f88a8-43b1-42a7-8d03-4f2825a25eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350054728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2350054728
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2750899177
Short name T7
Test name
Test status
Simulation time 1322513239 ps
CPU time 17.67 seconds
Started Aug 17 05:21:00 PM PDT 24
Finished Aug 17 05:21:18 PM PDT 24
Peak memory 209344 kb
Host smart-f2537dc9-6d8c-41fc-bf0b-eb3b6c004e09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750899177 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2750899177
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.4075870923
Short name T789
Test name
Test status
Simulation time 689133670 ps
CPU time 1.69 seconds
Started Aug 17 05:20:58 PM PDT 24
Finished Aug 17 05:21:00 PM PDT 24
Peak memory 199552 kb
Host smart-4b85f9e3-3147-497b-971f-d80f54c9c977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075870923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4075870923
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.962611875
Short name T675
Test name
Test status
Simulation time 62282389627 ps
CPU time 110.22 seconds
Started Aug 17 05:20:39 PM PDT 24
Finished Aug 17 05:22:29 PM PDT 24
Peak memory 200872 kb
Host smart-89c29370-e4f6-450d-b586-fd096131aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962611875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.962611875
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.106991546
Short name T1165
Test name
Test status
Simulation time 14826627 ps
CPU time 0.59 seconds
Started Aug 17 05:21:13 PM PDT 24
Finished Aug 17 05:21:14 PM PDT 24
Peak memory 196300 kb
Host smart-5070855c-bda3-4c9e-845c-a2b362886bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106991546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.106991546
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1993144677
Short name T1117
Test name
Test status
Simulation time 124227024481 ps
CPU time 23.81 seconds
Started Aug 17 05:20:57 PM PDT 24
Finished Aug 17 05:21:21 PM PDT 24
Peak memory 200888 kb
Host smart-291fd2de-8b1f-41ea-a5fc-a87f8dc54f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993144677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1993144677
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1850155741
Short name T606
Test name
Test status
Simulation time 151666259090 ps
CPU time 123.69 seconds
Started Aug 17 05:21:07 PM PDT 24
Finished Aug 17 05:23:11 PM PDT 24
Peak memory 200936 kb
Host smart-28aed742-6003-436b-860f-aca74a319f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850155741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1850155741
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.2148850755
Short name T11
Test name
Test status
Simulation time 215579065731 ps
CPU time 70.11 seconds
Started Aug 17 05:21:06 PM PDT 24
Finished Aug 17 05:22:16 PM PDT 24
Peak memory 198160 kb
Host smart-46391f43-c059-4858-9886-d3768f8d7e20
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148850755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2148850755
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.329496618
Short name T643
Test name
Test status
Simulation time 59376479171 ps
CPU time 274.89 seconds
Started Aug 17 05:21:13 PM PDT 24
Finished Aug 17 05:25:48 PM PDT 24
Peak memory 200892 kb
Host smart-a7382ca4-e32c-44d2-b24a-178e40b49dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329496618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.329496618
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2350729344
Short name T373
Test name
Test status
Simulation time 7063690694 ps
CPU time 5.51 seconds
Started Aug 17 05:21:15 PM PDT 24
Finished Aug 17 05:21:20 PM PDT 24
Peak memory 199532 kb
Host smart-505a1817-2024-4622-a4b1-58a3577c6709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350729344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2350729344
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3650565925
Short name T421
Test name
Test status
Simulation time 11607163137 ps
CPU time 18.08 seconds
Started Aug 17 05:21:05 PM PDT 24
Finished Aug 17 05:21:23 PM PDT 24
Peak memory 200876 kb
Host smart-a61d15b9-d1aa-4852-a618-674467285870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650565925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3650565925
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1106371400
Short name T1013
Test name
Test status
Simulation time 6900482701 ps
CPU time 69.65 seconds
Started Aug 17 05:21:13 PM PDT 24
Finished Aug 17 05:22:22 PM PDT 24
Peak memory 200944 kb
Host smart-d016dc60-60e0-4e8e-a88e-ba6a558e319e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106371400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1106371400
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2185921343
Short name T438
Test name
Test status
Simulation time 6688219534 ps
CPU time 27.35 seconds
Started Aug 17 05:21:07 PM PDT 24
Finished Aug 17 05:21:34 PM PDT 24
Peak memory 200412 kb
Host smart-35940099-5635-4100-bba1-851ebeee4bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185921343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2185921343
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3316515321
Short name T506
Test name
Test status
Simulation time 162531964987 ps
CPU time 16.07 seconds
Started Aug 17 05:21:05 PM PDT 24
Finished Aug 17 05:21:21 PM PDT 24
Peak memory 200836 kb
Host smart-e3856202-5547-4672-b6c5-3d5f69f1a586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316515321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3316515321
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.923876726
Short name T624
Test name
Test status
Simulation time 2277039630 ps
CPU time 2.56 seconds
Started Aug 17 05:21:09 PM PDT 24
Finished Aug 17 05:21:11 PM PDT 24
Peak memory 196436 kb
Host smart-43f682be-0b5f-4c8e-8941-0503765ac83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923876726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.923876726
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2551219354
Short name T720
Test name
Test status
Simulation time 450199801 ps
CPU time 2.14 seconds
Started Aug 17 05:20:56 PM PDT 24
Finished Aug 17 05:20:58 PM PDT 24
Peak memory 200796 kb
Host smart-31f3448c-e831-4a90-b54f-ce4858b062e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551219354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2551219354
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.411746394
Short name T618
Test name
Test status
Simulation time 202584584231 ps
CPU time 330.16 seconds
Started Aug 17 05:21:14 PM PDT 24
Finished Aug 17 05:26:44 PM PDT 24
Peak memory 209216 kb
Host smart-4ba4a7b2-7c4e-4379-89c4-cf9f2f563d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411746394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.411746394
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1729555273
Short name T1180
Test name
Test status
Simulation time 4510932228 ps
CPU time 57.77 seconds
Started Aug 17 05:21:14 PM PDT 24
Finished Aug 17 05:22:12 PM PDT 24
Peak memory 217596 kb
Host smart-932b9360-d174-4d83-8fff-07e9827043a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729555273 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1729555273
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3811850615
Short name T649
Test name
Test status
Simulation time 7262527173 ps
CPU time 11.4 seconds
Started Aug 17 05:21:14 PM PDT 24
Finished Aug 17 05:21:26 PM PDT 24
Peak memory 200256 kb
Host smart-b7ab616c-95f1-4415-a6eb-c698dc7bbbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811850615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3811850615
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1435497311
Short name T310
Test name
Test status
Simulation time 142516315602 ps
CPU time 293.3 seconds
Started Aug 17 05:20:57 PM PDT 24
Finished Aug 17 05:25:50 PM PDT 24
Peak memory 200964 kb
Host smart-236a2ec0-7fa5-467f-8916-8c0ca87d3d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435497311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1435497311
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1923089978
Short name T879
Test name
Test status
Simulation time 12287098 ps
CPU time 0.62 seconds
Started Aug 17 05:21:31 PM PDT 24
Finished Aug 17 05:21:32 PM PDT 24
Peak memory 196276 kb
Host smart-6d5eb962-8d53-4379-93dc-5ec15524fdfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923089978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1923089978
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.4176385662
Short name T185
Test name
Test status
Simulation time 38497471836 ps
CPU time 16.2 seconds
Started Aug 17 05:21:24 PM PDT 24
Finished Aug 17 05:21:40 PM PDT 24
Peak memory 200872 kb
Host smart-0ae7d935-0540-4071-97c5-daac0d9b21e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176385662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4176385662
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.349871170
Short name T991
Test name
Test status
Simulation time 156302665966 ps
CPU time 13.65 seconds
Started Aug 17 05:21:25 PM PDT 24
Finished Aug 17 05:21:38 PM PDT 24
Peak memory 200896 kb
Host smart-2d4fba86-d978-4344-b42f-bc114002094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349871170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.349871170
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1844222282
Short name T1094
Test name
Test status
Simulation time 51779002573 ps
CPU time 47.59 seconds
Started Aug 17 05:21:25 PM PDT 24
Finished Aug 17 05:22:12 PM PDT 24
Peak memory 200956 kb
Host smart-7792e4b0-cd71-461d-8868-096da1cd8d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844222282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1844222282
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3447979375
Short name T339
Test name
Test status
Simulation time 29899513849 ps
CPU time 25.62 seconds
Started Aug 17 05:21:23 PM PDT 24
Finished Aug 17 05:21:48 PM PDT 24
Peak memory 200812 kb
Host smart-e0cb448c-d1d1-45ce-bbb1-042f682f0a1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447979375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3447979375
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2344480397
Short name T666
Test name
Test status
Simulation time 58539680460 ps
CPU time 302.62 seconds
Started Aug 17 05:21:30 PM PDT 24
Finished Aug 17 05:26:33 PM PDT 24
Peak memory 200876 kb
Host smart-27786e8f-781a-4272-b3bb-e9011d60d8fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344480397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2344480397
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.61593070
Short name T827
Test name
Test status
Simulation time 1229971326 ps
CPU time 2.43 seconds
Started Aug 17 05:21:24 PM PDT 24
Finished Aug 17 05:21:27 PM PDT 24
Peak memory 197124 kb
Host smart-e9a90491-9aad-40bf-8405-281d75835592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61593070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.61593070
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.848081783
Short name T1015
Test name
Test status
Simulation time 134619642231 ps
CPU time 89.75 seconds
Started Aug 17 05:21:24 PM PDT 24
Finished Aug 17 05:22:54 PM PDT 24
Peak memory 200572 kb
Host smart-518a5a5b-28dd-4ece-a657-885def3a9016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848081783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.848081783
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1552294171
Short name T392
Test name
Test status
Simulation time 4101821442 ps
CPU time 172.69 seconds
Started Aug 17 05:21:29 PM PDT 24
Finished Aug 17 05:24:22 PM PDT 24
Peak memory 200952 kb
Host smart-36915eb1-3a81-444a-b7a2-4b04d60087b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552294171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1552294171
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3549152613
Short name T1021
Test name
Test status
Simulation time 6104785045 ps
CPU time 25.51 seconds
Started Aug 17 05:21:24 PM PDT 24
Finished Aug 17 05:21:49 PM PDT 24
Peak memory 199768 kb
Host smart-a8f4e347-ee0e-4232-ab22-f8f5e6b242b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549152613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3549152613
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1788706423
Short name T843
Test name
Test status
Simulation time 40836253292 ps
CPU time 10.43 seconds
Started Aug 17 05:21:23 PM PDT 24
Finished Aug 17 05:21:34 PM PDT 24
Peak memory 200960 kb
Host smart-3182dd16-2c97-4c38-8137-de5c4d02c058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788706423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1788706423
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1517924866
Short name T5
Test name
Test status
Simulation time 1592488628 ps
CPU time 3.03 seconds
Started Aug 17 05:21:24 PM PDT 24
Finished Aug 17 05:21:27 PM PDT 24
Peak memory 196424 kb
Host smart-ae83ab6b-27a4-4d32-aa11-2d38e7264a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517924866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1517924866
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.53703368
Short name T387
Test name
Test status
Simulation time 273815646 ps
CPU time 1.14 seconds
Started Aug 17 05:21:13 PM PDT 24
Finished Aug 17 05:21:14 PM PDT 24
Peak memory 199436 kb
Host smart-5f3ec0b0-5079-4053-9c2a-6311b11e4074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53703368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.53703368
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2357079157
Short name T435
Test name
Test status
Simulation time 25095560118 ps
CPU time 334.93 seconds
Started Aug 17 05:21:30 PM PDT 24
Finished Aug 17 05:27:05 PM PDT 24
Peak memory 200940 kb
Host smart-b5ae8bdc-ee7e-4f04-8526-2828dd24225b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357079157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2357079157
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1304842862
Short name T758
Test name
Test status
Simulation time 1941988124 ps
CPU time 21.05 seconds
Started Aug 17 05:21:28 PM PDT 24
Finished Aug 17 05:21:49 PM PDT 24
Peak memory 216416 kb
Host smart-c98a0758-d5f3-4851-8076-dd248d1f2467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304842862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1304842862
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3936717941
Short name T557
Test name
Test status
Simulation time 725502511 ps
CPU time 2.95 seconds
Started Aug 17 05:21:23 PM PDT 24
Finished Aug 17 05:21:26 PM PDT 24
Peak memory 199984 kb
Host smart-db14bdc1-dd2c-4ff0-8a5e-5e6ff0d85fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936717941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3936717941
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1944515171
Short name T644
Test name
Test status
Simulation time 65438468707 ps
CPU time 205.29 seconds
Started Aug 17 05:21:28 PM PDT 24
Finished Aug 17 05:24:53 PM PDT 24
Peak memory 200936 kb
Host smart-7f0639cf-3d87-4963-863e-bd880ada11eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944515171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1944515171
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3560349347
Short name T553
Test name
Test status
Simulation time 65316504 ps
CPU time 0.55 seconds
Started Aug 17 05:21:45 PM PDT 24
Finished Aug 17 05:21:45 PM PDT 24
Peak memory 196148 kb
Host smart-ec75af86-7f8f-47ce-be63-9334a2e404ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560349347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3560349347
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.841469239
Short name T395
Test name
Test status
Simulation time 166089857267 ps
CPU time 60.35 seconds
Started Aug 17 05:21:29 PM PDT 24
Finished Aug 17 05:22:29 PM PDT 24
Peak memory 200888 kb
Host smart-27a66aeb-ab5e-4b27-8833-581457c98677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841469239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.841469239
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2680867654
Short name T560
Test name
Test status
Simulation time 48296347709 ps
CPU time 47.66 seconds
Started Aug 17 05:21:36 PM PDT 24
Finished Aug 17 05:22:24 PM PDT 24
Peak memory 200900 kb
Host smart-1dfdcfa4-4627-4109-9a3f-05b8452b2020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680867654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2680867654
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.472952286
Short name T748
Test name
Test status
Simulation time 34958875680 ps
CPU time 33.24 seconds
Started Aug 17 05:21:37 PM PDT 24
Finished Aug 17 05:22:10 PM PDT 24
Peak memory 200900 kb
Host smart-edea3449-ace1-483f-8972-206df8bc0e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472952286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.472952286
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1815021956
Short name T374
Test name
Test status
Simulation time 68766526186 ps
CPU time 30.58 seconds
Started Aug 17 05:21:37 PM PDT 24
Finished Aug 17 05:22:07 PM PDT 24
Peak memory 200896 kb
Host smart-3fd7feca-8021-4329-abaa-dd3613fd450e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815021956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1815021956
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.577771323
Short name T509
Test name
Test status
Simulation time 301861678674 ps
CPU time 544.88 seconds
Started Aug 17 05:21:47 PM PDT 24
Finished Aug 17 05:30:52 PM PDT 24
Peak memory 200856 kb
Host smart-b5521f72-1a05-4094-82c5-bd84ea5dcd5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577771323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.577771323
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4093987540
Short name T403
Test name
Test status
Simulation time 1282971998 ps
CPU time 1.07 seconds
Started Aug 17 05:21:36 PM PDT 24
Finished Aug 17 05:21:37 PM PDT 24
Peak memory 196360 kb
Host smart-a8f15c7f-2e2e-4596-b2ed-6721b661769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093987540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4093987540
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3264895143
Short name T360
Test name
Test status
Simulation time 170016647203 ps
CPU time 78.94 seconds
Started Aug 17 05:21:37 PM PDT 24
Finished Aug 17 05:22:56 PM PDT 24
Peak memory 209332 kb
Host smart-001c490d-fe45-4ede-8c5f-a828f0d0fe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264895143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3264895143
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3264190569
Short name T95
Test name
Test status
Simulation time 5138865436 ps
CPU time 309.07 seconds
Started Aug 17 05:21:38 PM PDT 24
Finished Aug 17 05:26:47 PM PDT 24
Peak memory 200864 kb
Host smart-4a9cbf75-e610-43e1-8f23-3fcd9c7b8780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264190569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3264190569
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1571953917
Short name T856
Test name
Test status
Simulation time 5458695789 ps
CPU time 12.2 seconds
Started Aug 17 05:21:36 PM PDT 24
Finished Aug 17 05:21:48 PM PDT 24
Peak memory 199180 kb
Host smart-e542dd0e-f625-4847-a21d-a535d4a1d976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571953917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1571953917
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3863240158
Short name T790
Test name
Test status
Simulation time 97258685015 ps
CPU time 162.46 seconds
Started Aug 17 05:21:37 PM PDT 24
Finished Aug 17 05:24:20 PM PDT 24
Peak memory 200996 kb
Host smart-44f8d0e4-de05-405c-bc00-bb0fdd48b4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863240158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3863240158
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.4134551627
Short name T564
Test name
Test status
Simulation time 1985656280 ps
CPU time 1.38 seconds
Started Aug 17 05:21:36 PM PDT 24
Finished Aug 17 05:21:38 PM PDT 24
Peak memory 196416 kb
Host smart-284d7fa1-2574-4cd9-bfcd-218070884f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134551627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.4134551627
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3907563762
Short name T953
Test name
Test status
Simulation time 5757679254 ps
CPU time 5.99 seconds
Started Aug 17 05:21:31 PM PDT 24
Finished Aug 17 05:21:37 PM PDT 24
Peak memory 200296 kb
Host smart-85ac5b98-eedf-4b95-834b-4f30760e7d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907563762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3907563762
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.371833424
Short name T892
Test name
Test status
Simulation time 293754738491 ps
CPU time 786.91 seconds
Started Aug 17 05:21:45 PM PDT 24
Finished Aug 17 05:34:52 PM PDT 24
Peak memory 200860 kb
Host smart-f1e24199-1b70-400d-96fa-68ad95167ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371833424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.371833424
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1647394879
Short name T852
Test name
Test status
Simulation time 2264024968 ps
CPU time 32.62 seconds
Started Aug 17 05:21:45 PM PDT 24
Finished Aug 17 05:22:18 PM PDT 24
Peak memory 209376 kb
Host smart-8c180d94-1b49-4d5d-af32-9e5fe0229d61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647394879 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1647394879
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1348939262
Short name T952
Test name
Test status
Simulation time 1684776013 ps
CPU time 2.27 seconds
Started Aug 17 05:21:38 PM PDT 24
Finished Aug 17 05:21:40 PM PDT 24
Peak memory 199460 kb
Host smart-7d0e9563-3c07-4228-a4d3-26504a31aee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348939262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1348939262
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1853917933
Short name T1034
Test name
Test status
Simulation time 53688482366 ps
CPU time 43.71 seconds
Started Aug 17 05:21:31 PM PDT 24
Finished Aug 17 05:22:14 PM PDT 24
Peak memory 200916 kb
Host smart-68032c42-4619-4dd4-9ae0-8f20ba187df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853917933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1853917933
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.907169672
Short name T896
Test name
Test status
Simulation time 30076206 ps
CPU time 0.54 seconds
Started Aug 17 05:22:03 PM PDT 24
Finished Aug 17 05:22:04 PM PDT 24
Peak memory 196232 kb
Host smart-3946c446-dc2c-4be2-89cb-6f349541209c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907169672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.907169672
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1648721289
Short name T459
Test name
Test status
Simulation time 140767812637 ps
CPU time 133.57 seconds
Started Aug 17 05:22:00 PM PDT 24
Finished Aug 17 05:24:14 PM PDT 24
Peak memory 200872 kb
Host smart-54979815-66b4-42d6-b19d-6bae4f11ac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648721289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1648721289
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3373739561
Short name T920
Test name
Test status
Simulation time 72348735774 ps
CPU time 130.73 seconds
Started Aug 17 05:21:56 PM PDT 24
Finished Aug 17 05:24:07 PM PDT 24
Peak memory 200848 kb
Host smart-153a5af1-1135-402d-be1b-3383c42715e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373739561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3373739561
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.594516409
Short name T860
Test name
Test status
Simulation time 2702268044 ps
CPU time 5.89 seconds
Started Aug 17 05:21:57 PM PDT 24
Finished Aug 17 05:22:03 PM PDT 24
Peak memory 200204 kb
Host smart-e0831317-b5e4-4463-aaf1-37965295b282
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594516409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.594516409
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1659529451
Short name T487
Test name
Test status
Simulation time 174477115731 ps
CPU time 1092.35 seconds
Started Aug 17 05:22:03 PM PDT 24
Finished Aug 17 05:40:15 PM PDT 24
Peak memory 200932 kb
Host smart-3c9a6aba-ddbd-44cb-9038-fcc975b6de08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659529451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1659529451
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2667975925
Short name T1073
Test name
Test status
Simulation time 4110284879 ps
CPU time 7.45 seconds
Started Aug 17 05:22:05 PM PDT 24
Finished Aug 17 05:22:13 PM PDT 24
Peak memory 200716 kb
Host smart-8299256f-2495-4c53-99e1-06a7f61c6c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667975925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2667975925
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1373786495
Short name T936
Test name
Test status
Simulation time 73109123123 ps
CPU time 110.88 seconds
Started Aug 17 05:22:00 PM PDT 24
Finished Aug 17 05:23:51 PM PDT 24
Peak memory 200688 kb
Host smart-8f2fec26-a18b-494c-8957-cefc6dc510be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373786495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1373786495
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1254276416
Short name T552
Test name
Test status
Simulation time 1896804032 ps
CPU time 22.84 seconds
Started Aug 17 05:22:05 PM PDT 24
Finished Aug 17 05:22:27 PM PDT 24
Peak memory 200612 kb
Host smart-ea91cb99-d4a8-41a3-9554-015033fc1838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254276416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1254276416
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1668660155
Short name T1
Test name
Test status
Simulation time 7384827527 ps
CPU time 65.11 seconds
Started Aug 17 05:22:00 PM PDT 24
Finished Aug 17 05:23:05 PM PDT 24
Peak memory 199576 kb
Host smart-c9994888-7dea-44e3-bdbd-441531f31a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1668660155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1668660155
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3392123234
Short name T295
Test name
Test status
Simulation time 42486981719 ps
CPU time 41.1 seconds
Started Aug 17 05:21:55 PM PDT 24
Finished Aug 17 05:22:37 PM PDT 24
Peak memory 200936 kb
Host smart-3b664afe-4811-4475-99d6-a246630411a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392123234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3392123234
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.623154399
Short name T651
Test name
Test status
Simulation time 3762197139 ps
CPU time 1.18 seconds
Started Aug 17 05:21:56 PM PDT 24
Finished Aug 17 05:21:57 PM PDT 24
Peak memory 197428 kb
Host smart-45778a3d-9963-49fa-85ea-0fbff18b3add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623154399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.623154399
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3775194947
Short name T981
Test name
Test status
Simulation time 886950555 ps
CPU time 2.86 seconds
Started Aug 17 05:21:45 PM PDT 24
Finished Aug 17 05:21:48 PM PDT 24
Peak memory 199660 kb
Host smart-49ee69b0-43f8-4773-a154-bce5fe952198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775194947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3775194947
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1665647883
Short name T341
Test name
Test status
Simulation time 230624217912 ps
CPU time 1415.19 seconds
Started Aug 17 05:22:03 PM PDT 24
Finished Aug 17 05:45:38 PM PDT 24
Peak memory 200872 kb
Host smart-b172090b-e689-4985-8ee8-7625245c4a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665647883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1665647883
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1227293912
Short name T688
Test name
Test status
Simulation time 2791992328 ps
CPU time 50.45 seconds
Started Aug 17 05:22:03 PM PDT 24
Finished Aug 17 05:22:53 PM PDT 24
Peak memory 217360 kb
Host smart-e3f38db8-f2ce-42a5-a288-6a36997b6423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227293912 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1227293912
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4210213860
Short name T632
Test name
Test status
Simulation time 1000016400 ps
CPU time 3.54 seconds
Started Aug 17 05:22:03 PM PDT 24
Finished Aug 17 05:22:07 PM PDT 24
Peak memory 200712 kb
Host smart-23566afb-9455-4e24-9676-e3668adbf229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210213860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4210213860
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.4091771544
Short name T423
Test name
Test status
Simulation time 157841954501 ps
CPU time 68.55 seconds
Started Aug 17 05:21:55 PM PDT 24
Finished Aug 17 05:23:04 PM PDT 24
Peak memory 200964 kb
Host smart-03dd1822-ea72-4b45-9ced-05615ad8a584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091771544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.4091771544
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.4197568201
Short name T682
Test name
Test status
Simulation time 50667916 ps
CPU time 0.57 seconds
Started Aug 17 05:09:58 PM PDT 24
Finished Aug 17 05:09:58 PM PDT 24
Peak memory 196248 kb
Host smart-ab28a46d-7f91-4f84-93ec-503e5f322425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197568201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.4197568201
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1302107063
Short name T848
Test name
Test status
Simulation time 57656978781 ps
CPU time 48.6 seconds
Started Aug 17 05:09:56 PM PDT 24
Finished Aug 17 05:10:45 PM PDT 24
Peak memory 200940 kb
Host smart-43249315-eb1f-4222-ae43-a9f66facd049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302107063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1302107063
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3044025803
Short name T186
Test name
Test status
Simulation time 9333925155 ps
CPU time 7.69 seconds
Started Aug 17 05:09:57 PM PDT 24
Finished Aug 17 05:10:05 PM PDT 24
Peak memory 200896 kb
Host smart-c93745b4-a253-4a2e-a2d1-b51462ee1355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044025803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3044025803
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3682799443
Short name T479
Test name
Test status
Simulation time 12019021490 ps
CPU time 20.4 seconds
Started Aug 17 05:09:55 PM PDT 24
Finished Aug 17 05:10:16 PM PDT 24
Peak memory 200852 kb
Host smart-730bef25-af6d-423a-875e-357144d27bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682799443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3682799443
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1059894903
Short name T1030
Test name
Test status
Simulation time 27157471502 ps
CPU time 19.74 seconds
Started Aug 17 05:09:57 PM PDT 24
Finished Aug 17 05:10:17 PM PDT 24
Peak memory 200880 kb
Host smart-424c722e-63f9-4204-924e-318240b4efde
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059894903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1059894903
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.634028184
Short name T311
Test name
Test status
Simulation time 115274141703 ps
CPU time 1201.04 seconds
Started Aug 17 05:10:01 PM PDT 24
Finished Aug 17 05:30:02 PM PDT 24
Peak memory 200868 kb
Host smart-fc5f330e-4624-4cb2-9429-ed3089e20677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634028184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.634028184
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.140996491
Short name T20
Test name
Test status
Simulation time 1913168730 ps
CPU time 3.94 seconds
Started Aug 17 05:09:58 PM PDT 24
Finished Aug 17 05:10:02 PM PDT 24
Peak memory 198592 kb
Host smart-412b79c3-0ee6-404e-ac3d-75fe2fc20d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140996491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.140996491
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1907547943
Short name T869
Test name
Test status
Simulation time 133461527495 ps
CPU time 63.67 seconds
Started Aug 17 05:09:57 PM PDT 24
Finished Aug 17 05:11:01 PM PDT 24
Peak memory 201052 kb
Host smart-5361198c-4583-4548-bd7c-b804b6f0e45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907547943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1907547943
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.239061714
Short name T917
Test name
Test status
Simulation time 9224732974 ps
CPU time 353.28 seconds
Started Aug 17 05:09:59 PM PDT 24
Finished Aug 17 05:15:52 PM PDT 24
Peak memory 200852 kb
Host smart-3f86153f-dc67-48c6-8499-0c1b4a609596
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239061714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.239061714
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.300989951
Short name T107
Test name
Test status
Simulation time 5267542233 ps
CPU time 7.63 seconds
Started Aug 17 05:09:59 PM PDT 24
Finished Aug 17 05:10:07 PM PDT 24
Peak memory 199776 kb
Host smart-3cc472f3-23bf-4049-8d77-16a736f3a0db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300989951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.300989951
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.4065857706
Short name T818
Test name
Test status
Simulation time 66568168401 ps
CPU time 33.67 seconds
Started Aug 17 05:09:59 PM PDT 24
Finished Aug 17 05:10:32 PM PDT 24
Peak memory 200836 kb
Host smart-4c4ee61b-e811-4dbf-a2bb-30d59d4eca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065857706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4065857706
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2815510016
Short name T1153
Test name
Test status
Simulation time 2963396778 ps
CPU time 5.02 seconds
Started Aug 17 05:09:59 PM PDT 24
Finished Aug 17 05:10:04 PM PDT 24
Peak memory 197504 kb
Host smart-0f997dba-143c-462a-9464-66bc7d161508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815510016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2815510016
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3921396608
Short name T691
Test name
Test status
Simulation time 690920907 ps
CPU time 2.93 seconds
Started Aug 17 05:09:56 PM PDT 24
Finished Aug 17 05:09:59 PM PDT 24
Peak memory 199672 kb
Host smart-e4a9bfeb-2d71-4821-89e5-9d93ad25f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921396608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3921396608
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3641631784
Short name T788
Test name
Test status
Simulation time 17086055944 ps
CPU time 39.18 seconds
Started Aug 17 05:09:57 PM PDT 24
Finished Aug 17 05:10:37 PM PDT 24
Peak memory 217376 kb
Host smart-e8ca49e1-428e-4090-af74-1057d046027e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641631784 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3641631784
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.819701783
Short name T925
Test name
Test status
Simulation time 1379911415 ps
CPU time 3.95 seconds
Started Aug 17 05:09:57 PM PDT 24
Finished Aug 17 05:10:01 PM PDT 24
Peak memory 199844 kb
Host smart-68bf413e-9152-43ca-a113-e6ad1c9c6cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819701783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.819701783
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3381183272
Short name T749
Test name
Test status
Simulation time 6580355960 ps
CPU time 10.57 seconds
Started Aug 17 05:09:54 PM PDT 24
Finished Aug 17 05:10:05 PM PDT 24
Peak memory 200676 kb
Host smart-38cb9f1d-543a-4f22-a7ec-7e63a9d60560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381183272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3381183272
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.551199287
Short name T302
Test name
Test status
Simulation time 49533660676 ps
CPU time 113.11 seconds
Started Aug 17 05:22:09 PM PDT 24
Finished Aug 17 05:24:02 PM PDT 24
Peak memory 200868 kb
Host smart-0338d6d7-20fc-4a61-a2a7-e8614aa92cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551199287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.551199287
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3819610160
Short name T875
Test name
Test status
Simulation time 5302696112 ps
CPU time 39.66 seconds
Started Aug 17 05:22:03 PM PDT 24
Finished Aug 17 05:22:43 PM PDT 24
Peak memory 209196 kb
Host smart-faad45c9-d650-4308-981e-a50cbca28c57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819610160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3819610160
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1198303466
Short name T267
Test name
Test status
Simulation time 16226966783 ps
CPU time 31.46 seconds
Started Aug 17 05:22:01 PM PDT 24
Finished Aug 17 05:22:33 PM PDT 24
Peak memory 200972 kb
Host smart-83b36a60-9ab8-4f11-af09-5aff76a07124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198303466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1198303466
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.394022036
Short name T34
Test name
Test status
Simulation time 5522704605 ps
CPU time 46.68 seconds
Started Aug 17 05:22:09 PM PDT 24
Finished Aug 17 05:22:56 PM PDT 24
Peak memory 217388 kb
Host smart-60cfc899-c6ec-46c0-996a-074e5ad63e78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394022036 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.394022036
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2576506726
Short name T228
Test name
Test status
Simulation time 107349317558 ps
CPU time 41.25 seconds
Started Aug 17 05:22:07 PM PDT 24
Finished Aug 17 05:22:49 PM PDT 24
Peak memory 200880 kb
Host smart-fdc56e3c-0ce3-496b-bfc9-89a0f2bc3dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576506726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2576506726
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1261155000
Short name T1149
Test name
Test status
Simulation time 49892965207 ps
CPU time 98.53 seconds
Started Aug 17 05:22:12 PM PDT 24
Finished Aug 17 05:23:50 PM PDT 24
Peak memory 200896 kb
Host smart-f628c6c5-08d2-41e7-892c-ab87fa07924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261155000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1261155000
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.361437123
Short name T941
Test name
Test status
Simulation time 3525405133 ps
CPU time 36.81 seconds
Started Aug 17 05:22:12 PM PDT 24
Finished Aug 17 05:22:49 PM PDT 24
Peak memory 216528 kb
Host smart-55f0da11-3fcc-44b1-a194-903bf5329ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361437123 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.361437123
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1876458953
Short name T244
Test name
Test status
Simulation time 14501571652 ps
CPU time 23.77 seconds
Started Aug 17 05:22:13 PM PDT 24
Finished Aug 17 05:22:37 PM PDT 24
Peak memory 199392 kb
Host smart-1beacb26-7dd7-4e40-a0f8-297e6eebc52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876458953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1876458953
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3655228393
Short name T33
Test name
Test status
Simulation time 2786752695 ps
CPU time 27.72 seconds
Started Aug 17 05:22:10 PM PDT 24
Finished Aug 17 05:22:38 PM PDT 24
Peak memory 200956 kb
Host smart-9b517742-b403-4ffa-80b5-2e9edc360e3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655228393 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3655228393
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.670614426
Short name T1127
Test name
Test status
Simulation time 140963730319 ps
CPU time 116.82 seconds
Started Aug 17 05:22:12 PM PDT 24
Finished Aug 17 05:24:09 PM PDT 24
Peak memory 200876 kb
Host smart-460d3ab4-44a5-4f08-9f41-373381851eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670614426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.670614426
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3671943506
Short name T367
Test name
Test status
Simulation time 7443938759 ps
CPU time 45.63 seconds
Started Aug 17 05:22:11 PM PDT 24
Finished Aug 17 05:22:57 PM PDT 24
Peak memory 217552 kb
Host smart-c3518228-1c33-4b50-a400-9d0f725f0bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671943506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3671943506
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.4211369992
Short name T289
Test name
Test status
Simulation time 94008939406 ps
CPU time 40.17 seconds
Started Aug 17 05:22:12 PM PDT 24
Finished Aug 17 05:22:52 PM PDT 24
Peak memory 200828 kb
Host smart-5b244368-e899-48c2-8ee9-dc46eac7d5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211369992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.4211369992
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.718827581
Short name T767
Test name
Test status
Simulation time 4753337703 ps
CPU time 144.14 seconds
Started Aug 17 05:22:11 PM PDT 24
Finished Aug 17 05:24:35 PM PDT 24
Peak memory 217188 kb
Host smart-babac440-22c5-47b7-8331-935529cd9be7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718827581 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.718827581
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.4129304544
Short name T171
Test name
Test status
Simulation time 29229646507 ps
CPU time 21.21 seconds
Started Aug 17 05:22:11 PM PDT 24
Finished Aug 17 05:22:32 PM PDT 24
Peak memory 200944 kb
Host smart-dfd7a812-1abb-421b-a025-a350d812e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129304544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.4129304544
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2098407794
Short name T30
Test name
Test status
Simulation time 21535164108 ps
CPU time 57.62 seconds
Started Aug 17 05:22:12 PM PDT 24
Finished Aug 17 05:23:09 PM PDT 24
Peak memory 209348 kb
Host smart-d2dcfaa9-7a91-445f-ba9d-c578e3a2c714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098407794 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2098407794
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2988296752
Short name T988
Test name
Test status
Simulation time 91101858678 ps
CPU time 65.34 seconds
Started Aug 17 05:22:12 PM PDT 24
Finished Aug 17 05:23:17 PM PDT 24
Peak memory 200916 kb
Host smart-96cc3d80-2dc7-411e-99cf-6c4d546e1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988296752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2988296752
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3273841752
Short name T1158
Test name
Test status
Simulation time 1962796022 ps
CPU time 22.85 seconds
Started Aug 17 05:22:10 PM PDT 24
Finished Aug 17 05:22:33 PM PDT 24
Peak memory 209128 kb
Host smart-1fbaa415-c6a3-4393-a0fd-a23388b0e1e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273841752 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3273841752
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2026119428
Short name T52
Test name
Test status
Simulation time 45340566876 ps
CPU time 84.4 seconds
Started Aug 17 05:22:13 PM PDT 24
Finished Aug 17 05:23:38 PM PDT 24
Peak memory 199316 kb
Host smart-08b51969-abe5-4c27-adf9-cbbd8af8cb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026119428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2026119428
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3262840196
Short name T868
Test name
Test status
Simulation time 14150931278 ps
CPU time 66.42 seconds
Started Aug 17 05:22:11 PM PDT 24
Finished Aug 17 05:23:18 PM PDT 24
Peak memory 217532 kb
Host smart-68720884-8483-4ca0-a687-4fe672ec932f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262840196 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3262840196
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1592826668
Short name T747
Test name
Test status
Simulation time 11354118 ps
CPU time 0.54 seconds
Started Aug 17 05:10:07 PM PDT 24
Finished Aug 17 05:10:08 PM PDT 24
Peak memory 196216 kb
Host smart-ee783f49-b50b-42bc-bd3b-3f3f4ad7649f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592826668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1592826668
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.250209420
Short name T203
Test name
Test status
Simulation time 32620921646 ps
CPU time 14.04 seconds
Started Aug 17 05:10:02 PM PDT 24
Finished Aug 17 05:10:16 PM PDT 24
Peak memory 200824 kb
Host smart-c8947928-59d5-43bc-a906-6a32fedbcb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250209420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.250209420
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.21517532
Short name T536
Test name
Test status
Simulation time 79919248302 ps
CPU time 59.07 seconds
Started Aug 17 05:10:01 PM PDT 24
Finished Aug 17 05:11:00 PM PDT 24
Peak memory 200332 kb
Host smart-dd0378ee-4c5c-4bcb-ab1b-14fca2b062e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21517532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.21517532
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1989801089
Short name T1082
Test name
Test status
Simulation time 82698424638 ps
CPU time 117.48 seconds
Started Aug 17 05:10:04 PM PDT 24
Finished Aug 17 05:12:01 PM PDT 24
Peak memory 200880 kb
Host smart-c9f9ed83-a6d0-4518-b3c8-4ecd902f5b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989801089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1989801089
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2034584559
Short name T1086
Test name
Test status
Simulation time 92311047867 ps
CPU time 32.63 seconds
Started Aug 17 05:10:03 PM PDT 24
Finished Aug 17 05:10:35 PM PDT 24
Peak memory 200948 kb
Host smart-8a3bf705-bb8b-4ab7-925c-94659edf323c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034584559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2034584559
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3775152767
Short name T538
Test name
Test status
Simulation time 91962485509 ps
CPU time 681.37 seconds
Started Aug 17 05:10:07 PM PDT 24
Finished Aug 17 05:21:28 PM PDT 24
Peak memory 200864 kb
Host smart-7f5145fb-51d8-43af-a138-3879ced1e1b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775152767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3775152767
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3562360835
Short name T510
Test name
Test status
Simulation time 4768338772 ps
CPU time 2.6 seconds
Started Aug 17 05:10:11 PM PDT 24
Finished Aug 17 05:10:13 PM PDT 24
Peak memory 200716 kb
Host smart-fd848d1e-d343-454b-a54b-2fd8d08577d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562360835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3562360835
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3428576170
Short name T979
Test name
Test status
Simulation time 296421129874 ps
CPU time 201.44 seconds
Started Aug 17 05:10:05 PM PDT 24
Finished Aug 17 05:13:27 PM PDT 24
Peak memory 209188 kb
Host smart-1f33427f-80ac-437f-9db1-1d3887198792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428576170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3428576170
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3059424457
Short name T722
Test name
Test status
Simulation time 9170762689 ps
CPU time 547.58 seconds
Started Aug 17 05:10:05 PM PDT 24
Finished Aug 17 05:19:13 PM PDT 24
Peak memory 200900 kb
Host smart-3eadea63-d9da-4640-99ed-33c164eaab57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3059424457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3059424457
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3834663575
Short name T743
Test name
Test status
Simulation time 2591081770 ps
CPU time 1.51 seconds
Started Aug 17 05:10:01 PM PDT 24
Finished Aug 17 05:10:03 PM PDT 24
Peak memory 199164 kb
Host smart-47002c0c-b89d-48ee-827b-30e51cca8d83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834663575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3834663575
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.103360664
Short name T493
Test name
Test status
Simulation time 105744099284 ps
CPU time 170.14 seconds
Started Aug 17 05:10:06 PM PDT 24
Finished Aug 17 05:12:57 PM PDT 24
Peak memory 200864 kb
Host smart-12f0c8f7-cbb3-4f49-ab96-a997fb8d9e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103360664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.103360664
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2372046239
Short name T48
Test name
Test status
Simulation time 2835095844 ps
CPU time 3.74 seconds
Started Aug 17 05:10:05 PM PDT 24
Finished Aug 17 05:10:09 PM PDT 24
Peak memory 196872 kb
Host smart-55380513-ef8f-42a4-be5e-ea5617f77417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372046239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2372046239
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.73196312
Short name T404
Test name
Test status
Simulation time 306916897 ps
CPU time 2.41 seconds
Started Aug 17 05:10:00 PM PDT 24
Finished Aug 17 05:10:02 PM PDT 24
Peak memory 199840 kb
Host smart-09436715-3ee5-44dd-8cda-7eafe182dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73196312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.73196312
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2908469183
Short name T1119
Test name
Test status
Simulation time 374398295256 ps
CPU time 47.45 seconds
Started Aug 17 05:10:06 PM PDT 24
Finished Aug 17 05:10:54 PM PDT 24
Peak memory 200948 kb
Host smart-22574b91-8ee1-48d0-9635-e3ced9dd366b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908469183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2908469183
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1055505934
Short name T883
Test name
Test status
Simulation time 484383672 ps
CPU time 8.92 seconds
Started Aug 17 05:10:08 PM PDT 24
Finished Aug 17 05:10:17 PM PDT 24
Peak memory 201084 kb
Host smart-3eadd345-36ce-4514-b263-023baa64f316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055505934 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1055505934
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.603640028
Short name T535
Test name
Test status
Simulation time 4951758092 ps
CPU time 1.79 seconds
Started Aug 17 05:10:07 PM PDT 24
Finished Aug 17 05:10:09 PM PDT 24
Peak memory 200160 kb
Host smart-90250880-2e4e-4671-8c35-3b28544d613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603640028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.603640028
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4128366642
Short name T10
Test name
Test status
Simulation time 59845622590 ps
CPU time 14.62 seconds
Started Aug 17 05:22:10 PM PDT 24
Finished Aug 17 05:22:25 PM PDT 24
Peak memory 200936 kb
Host smart-3b8ebf20-485a-4cd0-a433-a91be79a924b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128366642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4128366642
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.583612479
Short name T1081
Test name
Test status
Simulation time 9464788230 ps
CPU time 37.21 seconds
Started Aug 17 05:22:12 PM PDT 24
Finished Aug 17 05:22:50 PM PDT 24
Peak memory 209540 kb
Host smart-1c56dcee-a9ed-4634-9452-75232d2252fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583612479 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.583612479
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.431716740
Short name T801
Test name
Test status
Simulation time 58515569491 ps
CPU time 14.39 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:22:34 PM PDT 24
Peak memory 200896 kb
Host smart-f9408737-c3ca-4666-b64b-da95a9fb9fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431716740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.431716740
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.615738015
Short name T562
Test name
Test status
Simulation time 13580149119 ps
CPU time 46.19 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:23:06 PM PDT 24
Peak memory 217540 kb
Host smart-426db41e-457f-476d-813a-98fdc54d1251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615738015 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.615738015
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3248690981
Short name T238
Test name
Test status
Simulation time 98799895525 ps
CPU time 151.76 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:24:51 PM PDT 24
Peak memory 200892 kb
Host smart-13b15383-32a6-492d-86e9-0bd871712a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248690981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3248690981
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3117555659
Short name T698
Test name
Test status
Simulation time 2318149657 ps
CPU time 33.55 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:22:53 PM PDT 24
Peak memory 217520 kb
Host smart-8f4c6e42-888d-46c5-ba5f-c95f8fd18cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117555659 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3117555659
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2904805859
Short name T180
Test name
Test status
Simulation time 60868859904 ps
CPU time 25.74 seconds
Started Aug 17 05:22:21 PM PDT 24
Finished Aug 17 05:22:46 PM PDT 24
Peak memory 200848 kb
Host smart-f32fff23-70ee-4633-b161-eb1c0cd84c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904805859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2904805859
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.470805235
Short name T354
Test name
Test status
Simulation time 2420611545 ps
CPU time 29.22 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:22:48 PM PDT 24
Peak memory 217080 kb
Host smart-c03af571-f362-47b1-81a0-c08b1dd3d2bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470805235 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.470805235
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.942158443
Short name T1102
Test name
Test status
Simulation time 158601583801 ps
CPU time 51.91 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:23:19 PM PDT 24
Peak memory 200888 kb
Host smart-ea6182ea-3482-48a4-ae3e-2a3c0a4b2702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942158443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.942158443
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.4173617792
Short name T730
Test name
Test status
Simulation time 31142074420 ps
CPU time 33.08 seconds
Started Aug 17 05:22:21 PM PDT 24
Finished Aug 17 05:22:54 PM PDT 24
Peak memory 200268 kb
Host smart-5188b3f8-506f-4ab5-988c-8131bf55f217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173617792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4173617792
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3873342331
Short name T631
Test name
Test status
Simulation time 4764973406 ps
CPU time 30.47 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:22:50 PM PDT 24
Peak memory 217464 kb
Host smart-82b015e0-13ca-4d6a-9791-ac4fdf3e9bad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873342331 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3873342331
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.12892248
Short name T597
Test name
Test status
Simulation time 218071024198 ps
CPU time 55.4 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:23:14 PM PDT 24
Peak memory 200968 kb
Host smart-6bebe7ae-bf44-444e-95ee-3f0d86af1dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12892248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.12892248
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2577742508
Short name T368
Test name
Test status
Simulation time 8755038427 ps
CPU time 57.37 seconds
Started Aug 17 05:22:17 PM PDT 24
Finished Aug 17 05:23:15 PM PDT 24
Peak memory 217588 kb
Host smart-b08689d5-6a9a-4696-960a-2f16dc3bce17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577742508 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2577742508
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1860500359
Short name T382
Test name
Test status
Simulation time 34217830523 ps
CPU time 17.97 seconds
Started Aug 17 05:22:21 PM PDT 24
Finished Aug 17 05:22:39 PM PDT 24
Peak memory 200956 kb
Host smart-dd58af6a-b10d-4803-95ce-5a89dcb5cd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860500359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1860500359
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3395969250
Short name T1017
Test name
Test status
Simulation time 12069140060 ps
CPU time 71.19 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:23:30 PM PDT 24
Peak memory 217596 kb
Host smart-e2f19d11-5707-4eee-acfd-a55fbb1b4f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395969250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3395969250
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.660813875
Short name T608
Test name
Test status
Simulation time 129514851157 ps
CPU time 51.98 seconds
Started Aug 17 05:22:17 PM PDT 24
Finished Aug 17 05:23:09 PM PDT 24
Peak memory 200848 kb
Host smart-46665be8-66d5-4ee5-bfaa-3b34db68620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660813875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.660813875
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2015145491
Short name T366
Test name
Test status
Simulation time 3047926887 ps
CPU time 38.75 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:22:57 PM PDT 24
Peak memory 216812 kb
Host smart-77de58ec-6a6f-497f-863d-4f949b52c186
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015145491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2015145491
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.663262492
Short name T972
Test name
Test status
Simulation time 16769946 ps
CPU time 0.56 seconds
Started Aug 17 05:10:23 PM PDT 24
Finished Aug 17 05:10:23 PM PDT 24
Peak memory 196196 kb
Host smart-bfe5ad47-b05d-4e86-9e99-084155598abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663262492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.663262492
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.4039560229
Short name T1113
Test name
Test status
Simulation time 83640950303 ps
CPU time 41.86 seconds
Started Aug 17 05:10:08 PM PDT 24
Finished Aug 17 05:10:50 PM PDT 24
Peak memory 200952 kb
Host smart-ab751639-283d-43df-b110-3dc01fd71fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039560229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.4039560229
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.94110594
Short name T1139
Test name
Test status
Simulation time 26589070379 ps
CPU time 46.51 seconds
Started Aug 17 05:10:09 PM PDT 24
Finished Aug 17 05:10:55 PM PDT 24
Peak memory 200916 kb
Host smart-4f75a9b5-a3cf-4ef8-83c5-d81c318690a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94110594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.94110594
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1607650284
Short name T513
Test name
Test status
Simulation time 36674495828 ps
CPU time 31.42 seconds
Started Aug 17 05:10:16 PM PDT 24
Finished Aug 17 05:10:47 PM PDT 24
Peak memory 200864 kb
Host smart-402ad169-a63d-4a9f-82d7-26354aa9f739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607650284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1607650284
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1427896189
Short name T1121
Test name
Test status
Simulation time 177113838051 ps
CPU time 290.09 seconds
Started Aug 17 05:10:12 PM PDT 24
Finished Aug 17 05:15:02 PM PDT 24
Peak memory 198240 kb
Host smart-7afa53bf-b7c9-4c11-aa90-8494fb2b9220
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427896189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1427896189
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.874683067
Short name T964
Test name
Test status
Simulation time 194166696071 ps
CPU time 915.26 seconds
Started Aug 17 05:10:18 PM PDT 24
Finished Aug 17 05:25:33 PM PDT 24
Peak memory 200808 kb
Host smart-5030d0c6-644e-46f3-8d31-b911f748a0a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874683067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.874683067
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3416977489
Short name T974
Test name
Test status
Simulation time 2248043814 ps
CPU time 1.63 seconds
Started Aug 17 05:10:14 PM PDT 24
Finished Aug 17 05:10:15 PM PDT 24
Peak memory 199596 kb
Host smart-b632fc2d-dee7-4566-be9d-6ee31244a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416977489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3416977489
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1978465095
Short name T840
Test name
Test status
Simulation time 38851712691 ps
CPU time 67.71 seconds
Started Aug 17 05:10:10 PM PDT 24
Finished Aug 17 05:11:18 PM PDT 24
Peak memory 200596 kb
Host smart-ef765350-f706-4eba-82a0-01d2b800593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978465095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1978465095
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3804194035
Short name T1026
Test name
Test status
Simulation time 17701135674 ps
CPU time 214.46 seconds
Started Aug 17 05:10:23 PM PDT 24
Finished Aug 17 05:13:58 PM PDT 24
Peak memory 200892 kb
Host smart-02a9b202-b6ed-47f5-81d0-7374e748ea82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804194035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3804194035
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3559592659
Short name T656
Test name
Test status
Simulation time 3677373909 ps
CPU time 32.09 seconds
Started Aug 17 05:10:16 PM PDT 24
Finished Aug 17 05:10:48 PM PDT 24
Peak memory 199316 kb
Host smart-3b5df228-e467-4d6f-b0c0-53b591c29318
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559592659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3559592659
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2724784137
Short name T1000
Test name
Test status
Simulation time 42969023315 ps
CPU time 15.97 seconds
Started Aug 17 05:10:10 PM PDT 24
Finished Aug 17 05:10:26 PM PDT 24
Peak memory 200272 kb
Host smart-52a79c5e-6497-41c6-b5a8-160829dab886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724784137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2724784137
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3104958880
Short name T353
Test name
Test status
Simulation time 4782828875 ps
CPU time 5.37 seconds
Started Aug 17 05:10:16 PM PDT 24
Finished Aug 17 05:10:21 PM PDT 24
Peak memory 196980 kb
Host smart-f540d5bb-fa40-4067-a406-2df38857e1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104958880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3104958880
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1807198912
Short name T12
Test name
Test status
Simulation time 927696536 ps
CPU time 3.31 seconds
Started Aug 17 05:10:10 PM PDT 24
Finished Aug 17 05:10:14 PM PDT 24
Peak memory 200828 kb
Host smart-15917c3d-b2cd-4e9a-b523-36d9368ad3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807198912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1807198912
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.4294551301
Short name T1133
Test name
Test status
Simulation time 270856242294 ps
CPU time 565.4 seconds
Started Aug 17 05:10:15 PM PDT 24
Finished Aug 17 05:19:41 PM PDT 24
Peak memory 200912 kb
Host smart-47958233-b517-483f-819d-3eee4b1e6030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294551301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.4294551301
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.168876753
Short name T486
Test name
Test status
Simulation time 3646840549 ps
CPU time 62.27 seconds
Started Aug 17 05:10:23 PM PDT 24
Finished Aug 17 05:11:25 PM PDT 24
Peak memory 210476 kb
Host smart-a6771797-ce76-4892-abb3-519fa4f1a423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168876753 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.168876753
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3055925858
Short name T1076
Test name
Test status
Simulation time 6107108094 ps
CPU time 16.78 seconds
Started Aug 17 05:10:13 PM PDT 24
Finished Aug 17 05:10:30 PM PDT 24
Peak memory 200836 kb
Host smart-7d7778cb-df9d-4fd5-918f-a568efa527fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055925858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3055925858
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1506379887
Short name T1085
Test name
Test status
Simulation time 24141209567 ps
CPU time 35.35 seconds
Started Aug 17 05:10:07 PM PDT 24
Finished Aug 17 05:10:42 PM PDT 24
Peak memory 200896 kb
Host smart-d69250d3-f941-4d11-b658-1a0554de607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506379887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1506379887
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.4038476451
Short name T196
Test name
Test status
Simulation time 58332600951 ps
CPU time 29.6 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:22:49 PM PDT 24
Peak memory 200904 kb
Host smart-b316e024-f9b2-4152-8bee-3f2c509bca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038476451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.4038476451
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3576386668
Short name T910
Test name
Test status
Simulation time 13533106179 ps
CPU time 44.34 seconds
Started Aug 17 05:22:19 PM PDT 24
Finished Aug 17 05:23:03 PM PDT 24
Peak memory 216028 kb
Host smart-15a7140e-c2df-4cdf-88e3-00b789c4b0ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576386668 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3576386668
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3308896554
Short name T1122
Test name
Test status
Simulation time 79670102837 ps
CPU time 62.61 seconds
Started Aug 17 05:22:28 PM PDT 24
Finished Aug 17 05:23:31 PM PDT 24
Peak memory 200980 kb
Host smart-ad8790a3-18cf-49e4-8816-566d20573555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308896554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3308896554
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3822662476
Short name T369
Test name
Test status
Simulation time 3488315551 ps
CPU time 45.51 seconds
Started Aug 17 05:22:28 PM PDT 24
Finished Aug 17 05:23:13 PM PDT 24
Peak memory 209424 kb
Host smart-85faa2d9-4f85-45e6-adbf-2b099e339237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822662476 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3822662476
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2618480836
Short name T372
Test name
Test status
Simulation time 3602191943 ps
CPU time 34.37 seconds
Started Aug 17 05:22:26 PM PDT 24
Finished Aug 17 05:23:01 PM PDT 24
Peak memory 217372 kb
Host smart-813502de-3b80-4ff9-b5c6-6e1660f7c2c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618480836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2618480836
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2355533587
Short name T226
Test name
Test status
Simulation time 21995639983 ps
CPU time 39.82 seconds
Started Aug 17 05:22:40 PM PDT 24
Finished Aug 17 05:23:19 PM PDT 24
Peak memory 200972 kb
Host smart-fa1da01b-ac88-4c0e-b34a-685cb35a92bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355533587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2355533587
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3011126799
Short name T844
Test name
Test status
Simulation time 17293787570 ps
CPU time 48.14 seconds
Started Aug 17 05:22:26 PM PDT 24
Finished Aug 17 05:23:14 PM PDT 24
Peak memory 210412 kb
Host smart-d41f9432-3568-4199-8729-881fdf8a51ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011126799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3011126799
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2467965987
Short name T54
Test name
Test status
Simulation time 4147663780 ps
CPU time 11.75 seconds
Started Aug 17 05:22:26 PM PDT 24
Finished Aug 17 05:22:38 PM PDT 24
Peak memory 217044 kb
Host smart-8ce5050d-afba-47fa-93ee-ea128a06bbd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467965987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2467965987
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1081580941
Short name T381
Test name
Test status
Simulation time 40105409567 ps
CPU time 103.73 seconds
Started Aug 17 05:22:28 PM PDT 24
Finished Aug 17 05:24:11 PM PDT 24
Peak memory 200896 kb
Host smart-2306b1bd-1650-4dfb-9b98-0be4c39a77bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081580941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1081580941
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.376393702
Short name T16
Test name
Test status
Simulation time 2165695333 ps
CPU time 28.57 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:22:56 PM PDT 24
Peak memory 209356 kb
Host smart-b138c600-b7d0-412e-b4ce-934d27e3eadf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376393702 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.376393702
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1756052985
Short name T145
Test name
Test status
Simulation time 308762708022 ps
CPU time 45.48 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:23:13 PM PDT 24
Peak memory 200888 kb
Host smart-06a6ed3d-bb31-4695-b2ff-2e2b9c01d438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756052985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1756052985
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1755987676
Short name T980
Test name
Test status
Simulation time 20464191719 ps
CPU time 31.28 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:22:59 PM PDT 24
Peak memory 216752 kb
Host smart-b4cf0a43-376c-4eca-bcad-8cd2155a7fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755987676 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1755987676
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3590188380
Short name T162
Test name
Test status
Simulation time 67302503229 ps
CPU time 31.88 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:22:59 PM PDT 24
Peak memory 200964 kb
Host smart-b822eedd-6b26-4056-b02f-451ee26b88b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590188380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3590188380
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1113230514
Short name T1036
Test name
Test status
Simulation time 17711059973 ps
CPU time 41.52 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:23:08 PM PDT 24
Peak memory 217508 kb
Host smart-fddc8571-4f6e-4229-aa04-96a4bdf8320d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113230514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1113230514
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3319180614
Short name T170
Test name
Test status
Simulation time 236060323672 ps
CPU time 29.24 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:22:57 PM PDT 24
Peak memory 200904 kb
Host smart-510f59bd-1ce9-400e-a0e9-63ea5eccf8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319180614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3319180614
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.682766900
Short name T905
Test name
Test status
Simulation time 6475258550 ps
CPU time 40.09 seconds
Started Aug 17 05:22:28 PM PDT 24
Finished Aug 17 05:23:09 PM PDT 24
Peak memory 217556 kb
Host smart-f586035c-f92b-49f1-abd7-6af423a7a4ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682766900 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.682766900
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3625665605
Short name T521
Test name
Test status
Simulation time 8100085974 ps
CPU time 52.68 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:23:20 PM PDT 24
Peak memory 217240 kb
Host smart-2497f670-1a14-4d56-86b1-988b3815d9b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625665605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3625665605
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.4066846845
Short name T619
Test name
Test status
Simulation time 14092162 ps
CPU time 0.54 seconds
Started Aug 17 05:10:28 PM PDT 24
Finished Aug 17 05:10:29 PM PDT 24
Peak memory 196252 kb
Host smart-e99828a2-6284-4c1d-8e21-77e1cc12eaf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066846845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4066846845
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.887500763
Short name T872
Test name
Test status
Simulation time 64021295737 ps
CPU time 100.81 seconds
Started Aug 17 05:10:21 PM PDT 24
Finished Aug 17 05:12:02 PM PDT 24
Peak memory 200872 kb
Host smart-58af18f3-7abc-466e-9a15-e301bf81b231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887500763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.887500763
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.241666876
Short name T602
Test name
Test status
Simulation time 49003945084 ps
CPU time 38.41 seconds
Started Aug 17 05:10:14 PM PDT 24
Finished Aug 17 05:10:53 PM PDT 24
Peak memory 200924 kb
Host smart-07de3ea8-f11f-489d-abce-8887c119f340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241666876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.241666876
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1428312040
Short name T938
Test name
Test status
Simulation time 208513189789 ps
CPU time 465.69 seconds
Started Aug 17 05:10:21 PM PDT 24
Finished Aug 17 05:18:07 PM PDT 24
Peak memory 200552 kb
Host smart-a51ff7fe-3580-4d1c-b402-8e166f79f674
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428312040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1428312040
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.528452809
Short name T300
Test name
Test status
Simulation time 122364180666 ps
CPU time 592.03 seconds
Started Aug 17 05:10:19 PM PDT 24
Finished Aug 17 05:20:11 PM PDT 24
Peak memory 200856 kb
Host smart-e6f67ee5-57c6-417c-9ff6-787879d6c467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528452809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.528452809
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1614524354
Short name T420
Test name
Test status
Simulation time 4452465462 ps
CPU time 2.84 seconds
Started Aug 17 05:10:21 PM PDT 24
Finished Aug 17 05:10:24 PM PDT 24
Peak memory 198304 kb
Host smart-50a23b22-38f3-432a-92f7-c6fb43f8f31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614524354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1614524354
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2688124289
Short name T710
Test name
Test status
Simulation time 27786209479 ps
CPU time 20.93 seconds
Started Aug 17 05:10:19 PM PDT 24
Finished Aug 17 05:10:40 PM PDT 24
Peak memory 199824 kb
Host smart-8b0d6aeb-0837-44ee-918b-24e78deddeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688124289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2688124289
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.20949231
Short name T320
Test name
Test status
Simulation time 8622479486 ps
CPU time 318 seconds
Started Aug 17 05:10:20 PM PDT 24
Finished Aug 17 05:15:38 PM PDT 24
Peak memory 200864 kb
Host smart-0a7bdd0e-0440-49a0-94a3-66e7852b2ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20949231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.20949231
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3696896833
Short name T466
Test name
Test status
Simulation time 7250013934 ps
CPU time 67.47 seconds
Started Aug 17 05:10:18 PM PDT 24
Finished Aug 17 05:11:25 PM PDT 24
Peak memory 198996 kb
Host smart-f6105d57-d491-40bc-a35c-ec39e6b494df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3696896833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3696896833
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3486904742
Short name T298
Test name
Test status
Simulation time 22353304656 ps
CPU time 19.98 seconds
Started Aug 17 05:10:19 PM PDT 24
Finished Aug 17 05:10:39 PM PDT 24
Peak memory 200896 kb
Host smart-0c54ee20-40b8-46b5-a024-b9aabca544f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486904742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3486904742
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1688491596
Short name T296
Test name
Test status
Simulation time 1484216255 ps
CPU time 1.24 seconds
Started Aug 17 05:10:24 PM PDT 24
Finished Aug 17 05:10:25 PM PDT 24
Peak memory 196364 kb
Host smart-d023e21c-e6a0-4563-b19f-db2af672b323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688491596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1688491596
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3176615155
Short name T323
Test name
Test status
Simulation time 5999921252 ps
CPU time 15.95 seconds
Started Aug 17 05:10:23 PM PDT 24
Finished Aug 17 05:10:39 PM PDT 24
Peak memory 200564 kb
Host smart-a3d7f4ed-8486-4762-a548-8d6bdd6acad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176615155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3176615155
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.248133780
Short name T807
Test name
Test status
Simulation time 611181680254 ps
CPU time 354.33 seconds
Started Aug 17 05:10:29 PM PDT 24
Finished Aug 17 05:16:24 PM PDT 24
Peak memory 200956 kb
Host smart-a560dd18-630b-4514-8819-f7c9c0af4895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248133780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.248133780
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2310617394
Short name T105
Test name
Test status
Simulation time 1601641691 ps
CPU time 16.59 seconds
Started Aug 17 05:10:28 PM PDT 24
Finished Aug 17 05:10:45 PM PDT 24
Peak memory 217304 kb
Host smart-6786e87b-c8b5-4fb2-b392-96073d621cde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310617394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2310617394
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2526249664
Short name T484
Test name
Test status
Simulation time 1221511452 ps
CPU time 3.9 seconds
Started Aug 17 05:10:19 PM PDT 24
Finished Aug 17 05:10:23 PM PDT 24
Peak memory 199392 kb
Host smart-0b7985ff-1982-476a-8229-45cc3486e807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526249664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2526249664
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.664306350
Short name T1128
Test name
Test status
Simulation time 97846189743 ps
CPU time 206.8 seconds
Started Aug 17 05:10:12 PM PDT 24
Finished Aug 17 05:13:39 PM PDT 24
Peak memory 200860 kb
Host smart-632e98fd-2ac6-4de2-bcec-564e09410e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664306350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.664306350
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1538503226
Short name T448
Test name
Test status
Simulation time 67374966442 ps
CPU time 165.53 seconds
Started Aug 17 05:22:27 PM PDT 24
Finished Aug 17 05:25:12 PM PDT 24
Peak memory 200820 kb
Host smart-70dc3be7-00a8-42b1-a743-88def8174735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538503226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1538503226
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1334932631
Short name T1040
Test name
Test status
Simulation time 9319730285 ps
CPU time 39.33 seconds
Started Aug 17 05:22:29 PM PDT 24
Finished Aug 17 05:23:08 PM PDT 24
Peak memory 217396 kb
Host smart-e76530a0-5beb-4a0e-b78c-d3b599a95263
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334932631 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1334932631
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1758239778
Short name T250
Test name
Test status
Simulation time 135819091922 ps
CPU time 321.97 seconds
Started Aug 17 05:22:29 PM PDT 24
Finished Aug 17 05:27:51 PM PDT 24
Peak memory 200948 kb
Host smart-59b2cbb8-7e6c-4c35-bbd7-c753e69b6f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758239778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1758239778
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2092888445
Short name T371
Test name
Test status
Simulation time 2334567527 ps
CPU time 17.87 seconds
Started Aug 17 05:22:26 PM PDT 24
Finished Aug 17 05:22:44 PM PDT 24
Peak memory 216488 kb
Host smart-680ade4c-1c73-401a-aaa9-ae468fc6abec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092888445 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2092888445
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1905332859
Short name T189
Test name
Test status
Simulation time 34783320327 ps
CPU time 72.87 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:23:49 PM PDT 24
Peak memory 200872 kb
Host smart-50fc890e-aa9d-4ac2-a17b-1b34f141b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905332859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1905332859
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2125361099
Short name T45
Test name
Test status
Simulation time 15396400586 ps
CPU time 55.71 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:23:31 PM PDT 24
Peak memory 217584 kb
Host smart-a1646a8e-9a31-400f-8094-8e63abb24008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125361099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2125361099
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2295852628
Short name T559
Test name
Test status
Simulation time 33666539446 ps
CPU time 17.8 seconds
Started Aug 17 05:22:39 PM PDT 24
Finished Aug 17 05:22:56 PM PDT 24
Peak memory 200876 kb
Host smart-c78bd669-16ce-467d-87ea-34e46ee1ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295852628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2295852628
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2976935429
Short name T100
Test name
Test status
Simulation time 3039028047 ps
CPU time 8.16 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:22:45 PM PDT 24
Peak memory 201072 kb
Host smart-56e4420c-0e29-480c-b4a0-dee09db656ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976935429 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2976935429
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.638352184
Short name T287
Test name
Test status
Simulation time 64838029193 ps
CPU time 141.95 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:24:58 PM PDT 24
Peak memory 200944 kb
Host smart-460106d0-b9a9-45c5-b323-88321e59fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638352184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.638352184
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1946400776
Short name T125
Test name
Test status
Simulation time 21294933831 ps
CPU time 88.97 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:24:05 PM PDT 24
Peak memory 209848 kb
Host smart-35cf7c61-fcf3-48ce-a3cf-bf984d4e71e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946400776 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1946400776
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1325128138
Short name T314
Test name
Test status
Simulation time 15013198681 ps
CPU time 12.17 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:22:48 PM PDT 24
Peak memory 200888 kb
Host smart-a9c7757f-8657-4882-be65-9c65e79afe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325128138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1325128138
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1651592053
Short name T966
Test name
Test status
Simulation time 56171511433 ps
CPU time 66.04 seconds
Started Aug 17 05:22:38 PM PDT 24
Finished Aug 17 05:23:44 PM PDT 24
Peak memory 212196 kb
Host smart-5e70a5bf-f67f-408b-b2b1-85e72657d793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651592053 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1651592053
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1732780170
Short name T731
Test name
Test status
Simulation time 20177876753 ps
CPU time 31.53 seconds
Started Aug 17 05:22:37 PM PDT 24
Finished Aug 17 05:23:09 PM PDT 24
Peak memory 200904 kb
Host smart-a0b9c356-296c-4e58-84b0-32cb39105b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732780170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1732780170
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3122465488
Short name T1148
Test name
Test status
Simulation time 4387137624 ps
CPU time 61.94 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:23:38 PM PDT 24
Peak memory 217368 kb
Host smart-0875c566-bc72-4bfb-8332-846727e2510a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122465488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3122465488
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3885775300
Short name T1096
Test name
Test status
Simulation time 19929327686 ps
CPU time 41.96 seconds
Started Aug 17 05:22:35 PM PDT 24
Finished Aug 17 05:23:17 PM PDT 24
Peak memory 200952 kb
Host smart-ed2b0a14-21f7-440b-aa00-4abc7daf37df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885775300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3885775300
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1436250342
Short name T813
Test name
Test status
Simulation time 8045238981 ps
CPU time 49.41 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:23:25 PM PDT 24
Peak memory 209396 kb
Host smart-528abe7b-3b09-406e-a426-4d127f07eb7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436250342 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1436250342
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.931787666
Short name T139
Test name
Test status
Simulation time 129639050340 ps
CPU time 93.45 seconds
Started Aug 17 05:22:36 PM PDT 24
Finished Aug 17 05:24:10 PM PDT 24
Peak memory 200900 kb
Host smart-b5bc6e19-61e5-4e5b-a023-537780a275a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931787666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.931787666
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3706486474
Short name T806
Test name
Test status
Simulation time 48605968862 ps
CPU time 77.05 seconds
Started Aug 17 05:22:42 PM PDT 24
Finished Aug 17 05:23:59 PM PDT 24
Peak memory 217572 kb
Host smart-d8fa5f61-9ec2-47cb-a77b-dda4f7a25594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706486474 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3706486474
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.607856682
Short name T31
Test name
Test status
Simulation time 4263758971 ps
CPU time 30.19 seconds
Started Aug 17 05:22:42 PM PDT 24
Finished Aug 17 05:23:13 PM PDT 24
Peak memory 209396 kb
Host smart-e30d4463-e1c5-4a98-b910-33bee267c28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607856682 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.607856682
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.825597844
Short name T504
Test name
Test status
Simulation time 12935899 ps
CPU time 0.63 seconds
Started Aug 17 05:10:44 PM PDT 24
Finished Aug 17 05:10:44 PM PDT 24
Peak memory 196168 kb
Host smart-c4d19019-eabd-4e67-9521-ad291aa3b91d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825597844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.825597844
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3049609445
Short name T914
Test name
Test status
Simulation time 64494895969 ps
CPU time 65.5 seconds
Started Aug 17 05:10:27 PM PDT 24
Finished Aug 17 05:11:33 PM PDT 24
Peak memory 200800 kb
Host smart-c0d84a2b-f2c8-4653-b9a3-989fc61a2612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049609445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3049609445
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2490989438
Short name T96
Test name
Test status
Simulation time 103468394810 ps
CPU time 38.62 seconds
Started Aug 17 05:10:30 PM PDT 24
Finished Aug 17 05:11:09 PM PDT 24
Peak memory 200884 kb
Host smart-e30ea625-4497-46fc-a342-9c797daca396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490989438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2490989438
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1304989137
Short name T650
Test name
Test status
Simulation time 71901006667 ps
CPU time 115.47 seconds
Started Aug 17 05:10:28 PM PDT 24
Finished Aug 17 05:12:24 PM PDT 24
Peak memory 200936 kb
Host smart-e8cb7b8c-c168-4afd-ab80-55fe509b19ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304989137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1304989137
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2485874976
Short name T485
Test name
Test status
Simulation time 25275878735 ps
CPU time 9.28 seconds
Started Aug 17 05:10:35 PM PDT 24
Finished Aug 17 05:10:45 PM PDT 24
Peak memory 199300 kb
Host smart-50bc5514-9d56-492e-a7eb-455542bf5804
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485874976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2485874976
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2926962122
Short name T859
Test name
Test status
Simulation time 235739707065 ps
CPU time 552.8 seconds
Started Aug 17 05:10:43 PM PDT 24
Finished Aug 17 05:19:56 PM PDT 24
Peak memory 200832 kb
Host smart-b86190be-522e-45eb-ac39-58b09c7b563e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926962122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2926962122
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.630033167
Short name T467
Test name
Test status
Simulation time 184108365 ps
CPU time 0.78 seconds
Started Aug 17 05:10:38 PM PDT 24
Finished Aug 17 05:10:39 PM PDT 24
Peak memory 197740 kb
Host smart-f7bd847a-57c2-4311-a09d-d281fb068160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630033167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.630033167
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.514787427
Short name T1105
Test name
Test status
Simulation time 206862221074 ps
CPU time 513.48 seconds
Started Aug 17 05:10:35 PM PDT 24
Finished Aug 17 05:19:08 PM PDT 24
Peak memory 209336 kb
Host smart-28b979f6-a9df-4881-9401-0aac5914a645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514787427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.514787427
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1681343063
Short name T1056
Test name
Test status
Simulation time 11726640897 ps
CPU time 644.89 seconds
Started Aug 17 05:10:42 PM PDT 24
Finished Aug 17 05:21:27 PM PDT 24
Peak memory 200936 kb
Host smart-1b750224-9e55-4d06-988c-eb27d965d1d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681343063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1681343063
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1904712096
Short name T757
Test name
Test status
Simulation time 2001919221 ps
CPU time 3.65 seconds
Started Aug 17 05:10:30 PM PDT 24
Finished Aug 17 05:10:34 PM PDT 24
Peak memory 199672 kb
Host smart-f489226f-5e9c-4a51-958b-90942bb29307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904712096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1904712096
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.234393160
Short name T725
Test name
Test status
Simulation time 83010558676 ps
CPU time 134.09 seconds
Started Aug 17 05:10:35 PM PDT 24
Finished Aug 17 05:12:49 PM PDT 24
Peak memory 200876 kb
Host smart-44b42473-ff00-4e9b-ae51-ef146ee7a1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234393160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.234393160
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3238586332
Short name T902
Test name
Test status
Simulation time 41649536751 ps
CPU time 4.19 seconds
Started Aug 17 05:10:36 PM PDT 24
Finished Aug 17 05:10:41 PM PDT 24
Peak memory 196992 kb
Host smart-c9898fe1-a282-41c6-97f9-5c64a9468a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238586332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3238586332
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3929000398
Short name T307
Test name
Test status
Simulation time 320728310 ps
CPU time 1.18 seconds
Started Aug 17 05:10:29 PM PDT 24
Finished Aug 17 05:10:30 PM PDT 24
Peak memory 199732 kb
Host smart-489f009b-392e-4e7f-a59c-2c78338f7a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929000398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3929000398
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2216417390
Short name T370
Test name
Test status
Simulation time 12692329203 ps
CPU time 34.92 seconds
Started Aug 17 05:10:43 PM PDT 24
Finished Aug 17 05:11:18 PM PDT 24
Peak memory 209204 kb
Host smart-e26f8084-c5f4-4f84-868f-ce1f3a7755f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216417390 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2216417390
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3499856139
Short name T489
Test name
Test status
Simulation time 7082406986 ps
CPU time 8.79 seconds
Started Aug 17 05:10:35 PM PDT 24
Finished Aug 17 05:10:44 PM PDT 24
Peak memory 200404 kb
Host smart-59fbbc99-e4e7-4baf-bc8a-833d6519282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499856139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3499856139
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1792280297
Short name T488
Test name
Test status
Simulation time 137998256244 ps
CPU time 26.17 seconds
Started Aug 17 05:10:27 PM PDT 24
Finished Aug 17 05:10:54 PM PDT 24
Peak memory 200956 kb
Host smart-4fdced58-c67b-4ac7-9a00-04ff11de38fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792280297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1792280297
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2869237411
Short name T148
Test name
Test status
Simulation time 27640591627 ps
CPU time 42.23 seconds
Started Aug 17 05:22:42 PM PDT 24
Finished Aug 17 05:23:24 PM PDT 24
Peak memory 200872 kb
Host smart-44e1d76b-0ac1-4c39-be45-d699ad561b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869237411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2869237411
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.854739942
Short name T32
Test name
Test status
Simulation time 18214419079 ps
CPU time 57.19 seconds
Started Aug 17 05:22:42 PM PDT 24
Finished Aug 17 05:23:39 PM PDT 24
Peak memory 217380 kb
Host smart-2efc5842-07da-4534-bf62-84a2df9b6379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854739942 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.854739942
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1787034090
Short name T179
Test name
Test status
Simulation time 75266829131 ps
CPU time 29.88 seconds
Started Aug 17 05:22:42 PM PDT 24
Finished Aug 17 05:23:12 PM PDT 24
Peak memory 200896 kb
Host smart-a1fb791f-3546-43fb-8cfa-db8ffb6aa2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787034090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1787034090
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2698371596
Short name T101
Test name
Test status
Simulation time 9907842710 ps
CPU time 22.52 seconds
Started Aug 17 05:22:44 PM PDT 24
Finished Aug 17 05:23:06 PM PDT 24
Peak memory 216704 kb
Host smart-79fe7cce-3614-47f4-bf85-338af780c3c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698371596 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2698371596
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3759630093
Short name T312
Test name
Test status
Simulation time 94775127738 ps
CPU time 42.53 seconds
Started Aug 17 05:22:43 PM PDT 24
Finished Aug 17 05:23:26 PM PDT 24
Peak memory 200888 kb
Host smart-733feafe-803b-46b5-868e-2f575cb7c639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759630093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3759630093
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2025129806
Short name T454
Test name
Test status
Simulation time 3564423834 ps
CPU time 13.62 seconds
Started Aug 17 05:22:45 PM PDT 24
Finished Aug 17 05:22:58 PM PDT 24
Peak memory 200996 kb
Host smart-20800d23-f1dc-40ad-81d1-2461ae55ab9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025129806 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2025129806
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.828400592
Short name T276
Test name
Test status
Simulation time 134708453495 ps
CPU time 58.31 seconds
Started Aug 17 05:22:43 PM PDT 24
Finished Aug 17 05:23:42 PM PDT 24
Peak memory 200900 kb
Host smart-488c796b-c2b9-4dd2-be25-3cf5196d4d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828400592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.828400592
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1965478706
Short name T424
Test name
Test status
Simulation time 1254194069 ps
CPU time 13.65 seconds
Started Aug 17 05:22:45 PM PDT 24
Finished Aug 17 05:22:58 PM PDT 24
Peak memory 209256 kb
Host smart-da2e77e4-6455-4de3-9aa3-ab17876e2116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965478706 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1965478706
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4077937575
Short name T996
Test name
Test status
Simulation time 64025020578 ps
CPU time 161.72 seconds
Started Aug 17 05:22:43 PM PDT 24
Finished Aug 17 05:25:25 PM PDT 24
Peak memory 200956 kb
Host smart-d4ad9b57-e724-4f8b-b9cf-09efc115fa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077937575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4077937575
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.4024795880
Short name T673
Test name
Test status
Simulation time 6656846855 ps
CPU time 131.91 seconds
Started Aug 17 05:22:43 PM PDT 24
Finished Aug 17 05:24:55 PM PDT 24
Peak memory 209536 kb
Host smart-34891ed3-292e-4ec1-8ded-538b6dcfe42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024795880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4024795880
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3236869512
Short name T803
Test name
Test status
Simulation time 155699835564 ps
CPU time 166.08 seconds
Started Aug 17 05:22:42 PM PDT 24
Finished Aug 17 05:25:29 PM PDT 24
Peak memory 200808 kb
Host smart-db0b94db-f32e-41a3-905b-f01d3d387542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236869512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3236869512
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.303392246
Short name T349
Test name
Test status
Simulation time 3619425130 ps
CPU time 28.97 seconds
Started Aug 17 05:22:45 PM PDT 24
Finished Aug 17 05:23:14 PM PDT 24
Peak memory 217380 kb
Host smart-b5dc5a41-db90-40f6-a56c-3d175d39f1cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303392246 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.303392246
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.161375960
Short name T1043
Test name
Test status
Simulation time 25623111590 ps
CPU time 54.27 seconds
Started Aug 17 05:22:44 PM PDT 24
Finished Aug 17 05:23:39 PM PDT 24
Peak memory 200896 kb
Host smart-ac594e4e-6ab7-4451-9a26-19165f36dcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161375960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.161375960
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2318497438
Short name T1027
Test name
Test status
Simulation time 6496519062 ps
CPU time 22.82 seconds
Started Aug 17 05:22:44 PM PDT 24
Finished Aug 17 05:23:06 PM PDT 24
Peak memory 209320 kb
Host smart-2c2ef161-c7e3-4c12-b3d0-d7cd5d052c6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318497438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2318497438
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.160239000
Short name T836
Test name
Test status
Simulation time 57171456275 ps
CPU time 21.38 seconds
Started Aug 17 05:22:43 PM PDT 24
Finished Aug 17 05:23:05 PM PDT 24
Peak memory 200976 kb
Host smart-b05b9e6b-fcc5-42b1-83aa-c6d5223f9310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160239000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.160239000
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3614307600
Short name T989
Test name
Test status
Simulation time 17526090043 ps
CPU time 63.3 seconds
Started Aug 17 05:22:43 PM PDT 24
Finished Aug 17 05:23:47 PM PDT 24
Peak memory 217560 kb
Host smart-2c2532e2-98c9-43c1-bcaa-88aa8d6bf375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614307600 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3614307600
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4162955201
Short name T379
Test name
Test status
Simulation time 32361333800 ps
CPU time 22.77 seconds
Started Aug 17 05:22:43 PM PDT 24
Finished Aug 17 05:23:05 PM PDT 24
Peak memory 200884 kb
Host smart-c29fd185-66fa-4180-a2db-2f2186528813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162955201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4162955201
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.381237650
Short name T901
Test name
Test status
Simulation time 1923371583 ps
CPU time 34.11 seconds
Started Aug 17 05:22:51 PM PDT 24
Finished Aug 17 05:23:25 PM PDT 24
Peak memory 209352 kb
Host smart-4ac3b48d-8c2f-4d74-b5dc-41bd5a7360c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381237650 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.381237650
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.618535053
Short name T137
Test name
Test status
Simulation time 12428603663 ps
CPU time 13.24 seconds
Started Aug 17 05:22:51 PM PDT 24
Finished Aug 17 05:23:04 PM PDT 24
Peak memory 200912 kb
Host smart-bf7a2927-6598-4274-be23-cabd1a56cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618535053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.618535053
Directory /workspace/99.uart_fifo_reset/latest
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