Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	84646	1			T1	22		T2	19		T3	12
all_values[1]	84646	1			T1	22		T2	19		T3	12
all_values[2]	84646	1			T1	22		T2	19		T3	12
all_values[3]	84646	1			T1	22		T2	19		T3	12
all_values[4]	84646	1			T1	22		T2	19		T3	12
all_values[5]	84646	1			T1	22		T2	19		T3	12
all_values[6]	84646	1			T1	22		T2	19		T3	12
all_values[7]	84646	1			T1	22		T2	19		T3	12
all_values[8]	84646	1			T1	22		T2	19		T3	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

385322

1

T1

98

T2

113

T3

40

auto[1]

376492

1

T1

100

T2

58

T3

68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694670

1

T1

180

T2

132

T3

93

auto[1]

67144

1

T1

18

T2

39

T3

15

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27206	1			T1	2		T2	5		T3	4
all_values[0]	auto[0]	auto[1]	17159	1			T1	7		T2	14		T3	1
all_values[0]	auto[1]	auto[0]	24076	1			T1	8		T3	1		T4	1
all_values[0]	auto[1]	auto[1]	16205	1			T1	5		T3	6		T4	42
all_values[1]	auto[0]	auto[0]	39292	1			T1	4		T3	8		T5	24
all_values[1]	auto[0]	auto[1]	1283	1			T7	2		T36	3		T14	4
all_values[1]	auto[1]	auto[0]	42728	1			T1	18		T2	11		T3	4
all_values[1]	auto[1]	auto[1]	1343	1			T2	8		T4	4		T37	2
all_values[2]	auto[0]	auto[0]	38437	1			T1	7		T2	14		T3	4
all_values[2]	auto[0]	auto[1]	2364	1			T1	1		T2	3		T5	5
all_values[2]	auto[1]	auto[0]	41688	1			T1	14		T2	2		T3	7
all_values[2]	auto[1]	auto[1]	2157	1			T3	1		T5	9		T7	2
all_values[3]	auto[0]	auto[0]	40870	1			T1	12		T2	19		T3	3
all_values[3]	auto[0]	auto[1]	296	1			T11	4		T12	1		T64	4
all_values[3]	auto[1]	auto[0]	43203	1			T1	10		T3	9		T4	43
all_values[3]	auto[1]	auto[1]	277	1			T13	2		T90	2		T15	2
all_values[4]	auto[0]	auto[0]	44608	1			T1	22		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	336	1			T4	8		T13	11		T15	2
all_values[4]	auto[1]	auto[0]	39364	1			T2	17		T3	9		T5	4
all_values[4]	auto[1]	auto[1]	338	1			T14	6		T15	6		T23	4
all_values[5]	auto[0]	auto[0]	42511	1			T1	14		T2	19		T3	2
all_values[5]	auto[0]	auto[1]	159	1			T15	4		T18	1		T30	1
all_values[5]	auto[1]	auto[0]	41817	1			T1	8		T3	10		T5	44
all_values[5]	auto[1]	auto[1]	159	1			T15	2		T23	2		T18	2
all_values[6]	auto[0]	auto[0]	43173	1			T1	14		T2	18		T3	3
all_values[6]	auto[0]	auto[1]	153	1			T15	6		T23	1		T31	5
all_values[6]	auto[1]	auto[0]	41183	1			T1	8		T2	1		T3	9
all_values[6]	auto[1]	auto[1]	137	1			T15	1		T23	1		T31	4
all_values[7]	auto[0]	auto[0]	43764	1			T1	8		T2	16		T3	10
all_values[7]	auto[0]	auto[1]	303	1			T4	1		T13	1		T15	4
all_values[7]	auto[1]	auto[0]	40332	1			T1	14		T2	3		T3	2
all_values[7]	auto[1]	auto[1]	247	1			T30	2		T115	1		T31	5
all_values[8]	auto[0]	auto[0]	29844	1			T1	3		T2	2		T5	14
all_values[8]	auto[0]	auto[1]	13564	1			T1	4		T2	1		T3	2
all_values[8]	auto[1]	auto[0]	30574	1			T1	14		T2	3		T3	5
all_values[8]	auto[1]	auto[1]	10664	1			T1	1		T2	13		T3	5