Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2676

1

T1

6

T2

1

T3

11

auto[UartRx]

2676

1

T1

6

T2

1

T3

11

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4631	1			T1	10		T2	2		T3	9
values[1]	53	1			T3	1		T21	1		T15	1
values[2]	57	1			T1	1		T3	3		T15	2
values[3]	47	1			T21	2		T18	2		T32	1
values[4]	52	1			T3	1		T30	1		T31	1
values[5]	73	1			T21	1		T30	2		T32	1
values[6]	61	1			T21	2		T15	2		T18	2
values[7]	76	1			T3	1		T15	1		T18	1
values[8]	72	1			T1	1		T3	5		T21	1
values[9]	74	1			T32	1		T33	1		T319	3
values[10]	106	1			T3	2		T18	2		T30	3

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2410	1			T1	5		T2	1		T3	6
auto[UartTx]	values[1]	14	1			T21	1		T320	1		T85	1
auto[UartTx]	values[2]	22	1			T3	1		T15	1		T96	1
auto[UartTx]	values[3]	27	1			T21	1		T18	1		T32	1
auto[UartTx]	values[4]	13	1			T3	1		T309	1		T215	1
auto[UartTx]	values[5]	35	1			T30	1		T32	1		T34	2
auto[UartTx]	values[6]	23	1			T21	1		T15	1		T18	1
auto[UartTx]	values[7]	26	1			T30	2		T31	1		T34	1
auto[UartTx]	values[8]	25	1			T1	1		T3	3		T21	1
auto[UartTx]	values[9]	23	1			T33	1		T319	1		T321	1
auto[UartTx]	values[10]	42	1			T18	1		T30	2		T32	1
auto[UartRx]	values[0]	2221	1			T1	5		T2	1		T3	3
auto[UartRx]	values[1]	39	1			T3	1		T15	1		T30	1
auto[UartRx]	values[2]	35	1			T1	1		T3	2		T15	1
auto[UartRx]	values[3]	20	1			T21	1		T18	1		T34	1
auto[UartRx]	values[4]	39	1			T30	1		T31	1		T322	2
auto[UartRx]	values[5]	38	1			T21	1		T30	1		T322	1
auto[UartRx]	values[6]	38	1			T21	1		T15	1		T18	1
auto[UartRx]	values[7]	50	1			T3	1		T15	1		T18	1
auto[UartRx]	values[8]	47	1			T3	2		T15	2		T30	1
auto[UartRx]	values[9]	51	1			T32	1		T319	2		T96	1
auto[UartRx]	values[10]	64	1			T3	2		T18	1		T30	1