Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1896	1			T2	1		T3	3		T5	1
auto[BaudRate115200]	1580	1			T3	4		T5	2		T8	2
auto[BaudRate230400]	1447	1			T1	1		T3	9		T4	1
auto[BaudRate128Kbps]	1563	1			T1	1		T2	1		T3	1
auto[BaudRate256Kbps]	1798	1			T1	4		T2	2		T3	7
auto[BaudRate1Mbps]	1440	1			T1	2		T2	1		T3	6
auto[BaudRate1p5Mbps]	1063	1			T5	1		T8	1		T10	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1235	1			T8	5		T37	10		T11	8
freqs[25]	845	1			T1	8		T43	8		T18	25
freqs[48]	319	1			T35	6		T38	10		T100	10
freqs[50]	570	1			T5	9		T255	2		T106	7
freqs[100]	1149	1			T81	8		T13	34		T17	18

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	217	1			T11	1		T286	1		T66	4
auto[BaudRate9600]	freqs[25]	177	1			T18	6		T252	1		T323	3
auto[BaudRate9600]	freqs[48]	83	1			T35	1		T100	2		T15	3
auto[BaudRate9600]	freqs[50]	78	1			T5	1		T106	1		T324	1
auto[BaudRate9600]	freqs[100]	207	1			T13	2		T41	3		T256	1
auto[BaudRate115200]	freqs[24]	174	1			T8	2		T37	4		T11	1
auto[BaudRate115200]	freqs[25]	132	1			T43	4		T18	2		T119	1
auto[BaudRate115200]	freqs[48]	35	1			T35	1		T38	1		T15	3
auto[BaudRate115200]	freqs[50]	83	1			T5	2		T106	1		T166	1
auto[BaudRate115200]	freqs[100]	150	1			T13	4		T64	1		T256	3
auto[BaudRate230400]	freqs[24]	176	1			T37	2		T11	1		T238	2
auto[BaudRate230400]	freqs[25]	100	1			T1	1		T43	2		T119	4
auto[BaudRate230400]	freqs[48]	39	1			T35	2		T38	1		T100	6
auto[BaudRate230400]	freqs[50]	56	1			T5	1		T106	1		T166	3
auto[BaudRate230400]	freqs[100]	121	1			T81	3		T13	3		T41	2
auto[BaudRate128Kbps]	freqs[24]	171	1			T8	1		T238	1		T115	1
auto[BaudRate128Kbps]	freqs[25]	117	1			T1	1		T43	2		T18	2
auto[BaudRate128Kbps]	freqs[48]	27	1			T38	2		T92	2		T321	2
auto[BaudRate128Kbps]	freqs[50]	86	1			T5	1		T255	1		T106	1
auto[BaudRate128Kbps]	freqs[100]	164	1			T81	2		T13	4		T17	6
auto[BaudRate256Kbps]	freqs[24]	215	1			T37	2		T238	2		T286	1
auto[BaudRate256Kbps]	freqs[25]	123	1			T1	4		T18	6		T119	1
auto[BaudRate256Kbps]	freqs[48]	63	1			T35	1		T38	1		T15	2
auto[BaudRate256Kbps]	freqs[50]	100	1			T255	1		T106	2		T166	1
auto[BaudRate256Kbps]	freqs[100]	151	1			T81	1		T13	9		T41	1
auto[BaudRate1Mbps]	freqs[24]	206	1			T8	1		T37	2		T11	3
auto[BaudRate1Mbps]	freqs[25]	139	1			T1	2		T18	9		T119	1
auto[BaudRate1Mbps]	freqs[48]	31	1			T38	3		T100	2		T15	2
auto[BaudRate1Mbps]	freqs[50]	74	1			T5	3		T166	2		T144	1
auto[BaudRate1Mbps]	freqs[100]	186	1			T81	2		T13	8		T17	9
auto[BaudRate1p5Mbps]	freqs[25]	57	1			T119	2		T113	1		T32	6
auto[BaudRate1p5Mbps]	freqs[48]	41	1			T35	1		T38	2		T15	4
auto[BaudRate1p5Mbps]	freqs[50]	93	1			T5	1		T106	1		T102	2
auto[BaudRate1p5Mbps]	freqs[100]	170	1			T13	4		T17	3		T41	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded