Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.88	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	16	114	87.69

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	16	114	87.69	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	24336425	1			T1	1203		T2	64		T3	28
all_levels[1]	157042	1			T1	70		T2	33		T3	1
all_levels[2]	2232	1			T2	16		T5	25		T7	5
all_levels[3]	925	1			T2	4		T5	8		T7	1
all_levels[4]	627	1			T5	2		T6	2		T7	1
all_levels[5]	399	1			T2	1		T36	3		T11	1
all_levels[6]	351	1			T5	2		T36	1		T12	2
all_levels[7]	288	1			T6	1		T12	3		T13	2
all_levels[8]	240	1			T8	1		T65	1		T90	1
all_levels[9]	194	1			T7	1		T8	1		T11	1
all_levels[10]	147	1			T37	1		T11	1		T13	1
all_levels[11]	155	1			T98	1		T23	2		T91	1
all_levels[12]	136	1			T99	1		T41	2		T23	2
all_levels[13]	135	1			T2	1		T37	1		T41	1
all_levels[14]	106	1			T2	1		T41	1		T100	1
all_levels[15]	80	1			T2	1		T91	1		T92	1
all_levels[16]	74	1			T41	1		T101	1		T102	1
all_levels[17]	75	1			T13	1		T91	2		T92	1
all_levels[18]	71	1			T11	1		T13	1		T91	1
all_levels[19]	60	1			T11	1		T23	1		T103	1
all_levels[20]	53	1			T11	1		T13	2		T91	1
all_levels[21]	33	1			T37	1		T13	2		T64	1
all_levels[22]	55	1			T37	1		T13	2		T90	1
all_levels[23]	54	1			T7	1		T13	1		T90	1
all_levels[24]	46	1			T90	1		T104	2		T105	2
all_levels[25]	61	1			T106	2		T107	2		T108	2
all_levels[26]	31	1			T109	1		T110	1		T111	1
all_levels[27]	26	1			T91	1		T106	1		T110	1
all_levels[28]	37	1			T90	1		T91	1		T92	2
all_levels[29]	29	1			T106	1		T112	1		T113	1
all_levels[30]	27	1			T13	1		T91	1		T114	2
all_levels[31]	26	1			T65	1		T115	1		T116	1
all_levels[32]	36	1			T2	1		T41	1		T117	3
all_levels[33]	26	1			T11	1		T118	3		T92	3
all_levels[34]	21	1			T2	1		T8	1		T118	1
all_levels[35]	27	1			T41	1		T119	3		T120	1
all_levels[36]	20	1			T41	1		T108	1		T121	1
all_levels[37]	19	1			T1	1		T91	1		T102	1
all_levels[38]	10	1			T8	1		T91	1		T104	1
all_levels[39]	22	1			T64	1		T93	1		T106	2
all_levels[40]	16	1			T112	1		T122	1		T123	1
all_levels[41]	13	1			T1	1		T64	1		T124	1
all_levels[42]	13	1			T125	1		T126	4		T127	1
all_levels[43]	7	1			T91	1		T115	1		T128	1
all_levels[44]	15	1			T121	1		T129	1		T96	1
all_levels[45]	13	1			T93	1		T130	1		T111	1
all_levels[46]	9	1			T113	1		T131	1		T132	1
all_levels[47]	10	1			T92	4		T131	1		T133	1
all_levels[48]	6	1			T93	1		T134	1		T135	1
all_levels[49]	6	1			T92	1		T134	1		T136	1
all_levels[50]	15	1			T92	1		T137	1		T138	1
all_levels[51]	11	1			T13	1		T91	1		T139	3
all_levels[52]	7	1			T37	2		T140	1		T132	1
all_levels[53]	9	1			T141	1		T142	1		T122	1
all_levels[54]	1	1			T143	1		-	-		-	-
all_levels[55]	9	1			T41	1		T92	1		T107	1
all_levels[56]	9	1			T144	2		T145	1		T146	1
all_levels[57]	3	1			T146	1		T147	1		T148	1
all_levels[58]	7	1			T92	1		T96	2		T149	2
all_levels[59]	4	1			T150	1		T151	1		T152	1
all_levels[60]	9	1			T111	1		T146	1		T153	1
all_levels[61]	6	1			T99	1		T91	1		T131	1
all_levels[62]	2	1			T154	1		T155	1		-	-
all_levels[63]	6	1			T144	1		T156	1		T157	1
all_levels[64]	93	1			T12	1		T64	2		T65	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24497026

1

T1

1275

T2

120

T3

26

auto[1]

3694

1

T2

3

T3

3

T4

11

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	16	114	87.69	16

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[21]]	[auto[1]]	0	1	1
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[45] , all_levels[46]]	[auto[1]]	--	--	2
[all_levels[49] , all_levels[50]]	[auto[1]]	--	--	2
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[59] , all_levels[60] , all_levels[61] , all_levels[62] , all_levels[63]]	[auto[1]]	--	--	5

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	24333165	1			T1	1203		T2	61		T3	25
all_levels[0]	auto[1]	3260	1			T2	3		T3	3		T4	11
all_levels[1]	auto[0]	156961	1			T1	70		T2	33		T3	1
all_levels[1]	auto[1]	81	1			T65	2		T158	1		T159	1
all_levels[2]	auto[0]	2191	1			T2	16		T5	25		T7	5
all_levels[2]	auto[1]	41	1			T91	2		T160	1		T161	1
all_levels[3]	auto[0]	902	1			T2	4		T5	8		T7	1
all_levels[3]	auto[1]	23	1			T158	1		T162	2		T163	4
all_levels[4]	auto[0]	608	1			T5	2		T6	2		T7	1
all_levels[4]	auto[1]	19	1			T103	2		T164	1		T165	1
all_levels[5]	auto[0]	385	1			T2	1		T36	3		T11	1
all_levels[5]	auto[1]	14	1			T139	1		T166	1		T167	3
all_levels[6]	auto[0]	340	1			T5	2		T36	1		T12	2
all_levels[6]	auto[1]	11	1			T168	1		T169	1		T170	1
all_levels[7]	auto[0]	273	1			T6	1		T12	3		T13	2
all_levels[7]	auto[1]	15	1			T103	1		T168	1		T167	2
all_levels[8]	auto[0]	236	1			T8	1		T65	1		T90	1
all_levels[8]	auto[1]	4	1			T171	1		T172	1		T173	1
all_levels[9]	auto[0]	184	1			T7	1		T8	1		T11	1
all_levels[9]	auto[1]	10	1			T117	1		T174	1		T161	1
all_levels[10]	auto[0]	132	1			T37	1		T11	1		T13	1
all_levels[10]	auto[1]	15	1			T175	1		T176	6		T177	1
all_levels[11]	auto[0]	145	1			T98	1		T23	2		T91	1
all_levels[11]	auto[1]	10	1			T178	1		T176	1		T179	1
all_levels[12]	auto[0]	123	1			T99	1		T41	2		T23	2
all_levels[12]	auto[1]	13	1			T180	1		T181	1		T182	3
all_levels[13]	auto[0]	124	1			T2	1		T37	1		T41	1
all_levels[13]	auto[1]	11	1			T183	5		T144	1		T184	1
all_levels[14]	auto[0]	98	1			T2	1		T41	1		T100	1
all_levels[14]	auto[1]	8	1			T111	1		T185	1		T186	1
all_levels[15]	auto[0]	69	1			T2	1		T91	1		T92	1
all_levels[15]	auto[1]	11	1			T187	1		T188	1		T189	3
all_levels[16]	auto[0]	73	1			T41	1		T101	1		T102	1
all_levels[16]	auto[1]	1	1			T190	1		-	-		-	-
all_levels[17]	auto[0]	66	1			T13	1		T91	2		T92	1
all_levels[17]	auto[1]	9	1			T191	1		T161	1		T192	1
all_levels[18]	auto[0]	69	1			T11	1		T13	1		T91	1
all_levels[18]	auto[1]	2	1			T193	1		T194	1		-	-
all_levels[19]	auto[0]	50	1			T11	1		T23	1		T103	1
all_levels[19]	auto[1]	10	1			T195	1		T196	2		T197	2
all_levels[20]	auto[0]	44	1			T11	1		T13	2		T91	1
all_levels[20]	auto[1]	9	1			T198	1		T199	1		T200	2
all_levels[21]	auto[0]	33	1			T37	1		T13	2		T64	1
all_levels[22]	auto[0]	50	1			T37	1		T13	2		T90	1
all_levels[22]	auto[1]	5	1			T159	2		T201	2		T202	1
all_levels[23]	auto[0]	46	1			T7	1		T13	1		T90	1
all_levels[23]	auto[1]	8	1			T91	1		T193	1		T203	1
all_levels[24]	auto[0]	42	1			T90	1		T104	2		T105	1
all_levels[24]	auto[1]	4	1			T105	1		T140	1		T196	1
all_levels[25]	auto[0]	49	1			T106	2		T107	2		T108	1
all_levels[25]	auto[1]	12	1			T108	1		T204	1		T205	1
all_levels[26]	auto[0]	27	1			T109	1		T110	1		T111	1
all_levels[26]	auto[1]	4	1			T206	1		T207	1		T208	1
all_levels[27]	auto[0]	20	1			T91	1		T106	1		T110	1
all_levels[27]	auto[1]	6	1			T209	2		T199	1		T210	1
all_levels[28]	auto[0]	32	1			T90	1		T91	1		T92	1
all_levels[28]	auto[1]	5	1			T92	1		T171	1		T211	1
all_levels[29]	auto[0]	27	1			T106	1		T112	1		T113	1
all_levels[29]	auto[1]	2	1			T135	1		T212	1		-	-
all_levels[30]	auto[0]	23	1			T13	1		T91	1		T114	1
all_levels[30]	auto[1]	4	1			T114	1		T213	1		T214	1
all_levels[31]	auto[0]	22	1			T65	1		T115	1		T116	1
all_levels[31]	auto[1]	4	1			T215	1		T216	2		T217	1
all_levels[32]	auto[0]	30	1			T2	1		T41	1		T117	1
all_levels[32]	auto[1]	6	1			T117	2		T218	1		T219	2
all_levels[33]	auto[0]	21	1			T11	1		T118	1		T92	2
all_levels[33]	auto[1]	5	1			T118	2		T92	1		T117	2
all_levels[34]	auto[0]	16	1			T2	1		T8	1		T118	1
all_levels[34]	auto[1]	5	1			T136	1		T220	1		T221	1
all_levels[35]	auto[0]	22	1			T41	1		T119	1		T120	1
all_levels[35]	auto[1]	5	1			T119	2		T222	2		T223	1
all_levels[36]	auto[0]	19	1			T41	1		T108	1		T121	1
all_levels[36]	auto[1]	1	1			T224	1		-	-		-	-
all_levels[37]	auto[0]	16	1			T1	1		T91	1		T102	1
all_levels[37]	auto[1]	3	1			T108	2		T225	1		-	-
all_levels[38]	auto[0]	10	1			T8	1		T91	1		T104	1
all_levels[39]	auto[0]	21	1			T64	1		T93	1		T106	2
all_levels[39]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[40]	auto[0]	13	1			T112	1		T122	1		T123	1
all_levels[40]	auto[1]	3	1			T226	1		T227	2		-	-
all_levels[41]	auto[0]	12	1			T1	1		T64	1		T124	1
all_levels[41]	auto[1]	1	1			T228	1		-	-		-	-
all_levels[42]	auto[0]	11	1			T125	1		T126	2		T127	1
all_levels[42]	auto[1]	2	1			T126	2		-	-		-	-
all_levels[43]	auto[0]	7	1			T91	1		T115	1		T128	1
all_levels[44]	auto[0]	12	1			T121	1		T129	1		T96	1
all_levels[44]	auto[1]	3	1			T189	1		T229	1		T230	1
all_levels[45]	auto[0]	13	1			T93	1		T130	1		T111	1
all_levels[46]	auto[0]	9	1			T113	1		T131	1		T132	1
all_levels[47]	auto[0]	7	1			T92	1		T131	1		T133	1
all_levels[47]	auto[1]	3	1			T92	3		-	-		-	-
all_levels[48]	auto[0]	4	1			T93	1		T134	1		T135	1
all_levels[48]	auto[1]	2	1			T231	2		-	-		-	-
all_levels[49]	auto[0]	6	1			T92	1		T134	1		T136	1
all_levels[50]	auto[0]	15	1			T92	1		T137	1		T138	1
all_levels[51]	auto[0]	9	1			T13	1		T91	1		T139	1
all_levels[51]	auto[1]	2	1			T139	2		-	-		-	-
all_levels[52]	auto[0]	7	1			T37	2		T140	1		T132	1
all_levels[53]	auto[0]	8	1			T141	1		T142	1		T122	1
all_levels[53]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[54]	auto[0]	1	1			T143	1		-	-		-	-
all_levels[55]	auto[0]	9	1			T41	1		T92	1		T107	1
all_levels[56]	auto[0]	7	1			T144	1		T145	1		T146	1
all_levels[56]	auto[1]	2	1			T144	1		T182	1		-	-
all_levels[57]	auto[0]	3	1			T146	1		T147	1		T148	1
all_levels[58]	auto[0]	6	1			T92	1		T96	1		T149	2
all_levels[58]	auto[1]	1	1			T96	1		-	-		-	-
all_levels[59]	auto[0]	4	1			T150	1		T151	1		T152	1
all_levels[60]	auto[0]	9	1			T111	1		T146	1		T153	1
all_levels[61]	auto[0]	6	1			T99	1		T91	1		T131	1
all_levels[62]	auto[0]	2	1			T154	1		T155	1		-	-
all_levels[63]	auto[0]	6	1			T144	1		T156	1		T157	1
all_levels[64]	auto[0]	76	1			T12	1		T64	2		T65	1
all_levels[64]	auto[1]	17	1			T65	1		T119	2		T233	1