Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 1 7 87.50 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 1 7 87.50


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1283 1 T7 2 T36 3 T63 2
all_levels[1] 556 1 T2 8 T11 3 T90 8
all_levels[2] 295 1 T79 3 T13 24 T90 5
all_levels[3] 193 1 T37 2 T91 10 T34 2
all_levels[4] 173 1 T4 4 T14 4 T20 4
all_levels[5] 73 1 T13 8 T92 2 T93 1
all_levels[6] 46 1 T14 6 T94 6 T95 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%