Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	84646	1			T1	22		T2	19		T3	12
all_pins[1]	84646	1			T1	22		T2	19		T3	12
all_pins[2]	84646	1			T1	22		T2	19		T3	12
all_pins[3]	84646	1			T1	22		T2	19		T3	12
all_pins[4]	84646	1			T1	22		T2	19		T3	12
all_pins[5]	84646	1			T1	22		T2	19		T3	12
all_pins[6]	84646	1			T1	22		T2	19		T3	12
all_pins[7]	84646	1			T1	22		T2	19		T3	12
all_pins[8]	84646	1			T1	22		T2	19		T3	12

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	729551	1			T1	192		T2	150		T3	96
values[0x1]	32263	1			T1	6		T2	21		T3	12
transitions[0x0=>0x1]	26761	1			T1	6		T2	21		T3	8
transitions[0x1=>0x0]	26554	1			T1	6		T2	21		T3	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	68392	1			T1	17		T2	19		T3	6
all_pins[0]	values[0x1]	16254	1			T1	5		T3	6		T4	42
all_pins[0]	transitions[0x0=>0x1]	15888	1			T1	5		T3	6		T4	38
all_pins[0]	transitions[0x1=>0x0]	972	1			T2	8		T37	2		T11	3
all_pins[1]	values[0x0]	83308	1			T1	22		T2	11		T3	12
all_pins[1]	values[0x1]	1338	1			T2	8		T4	4		T37	2
all_pins[1]	transitions[0x0=>0x1]	1237	1			T2	8		T4	4		T37	2
all_pins[1]	transitions[0x1=>0x0]	2092	1			T3	1		T4	2		T5	9
all_pins[2]	values[0x0]	82453	1			T1	22		T2	19		T3	11
all_pins[2]	values[0x1]	2193	1			T3	1		T4	2		T5	9
all_pins[2]	transitions[0x0=>0x1]	2134	1			T3	1		T4	2		T5	9
all_pins[2]	transitions[0x1=>0x0]	218	1			T13	2		T90	2		T15	1
all_pins[3]	values[0x0]	84369	1			T1	22		T2	19		T3	12
all_pins[3]	values[0x1]	277	1			T13	2		T90	2		T15	2
all_pins[3]	transitions[0x0=>0x1]	246	1			T13	2		T90	2		T15	1
all_pins[3]	transitions[0x1=>0x0]	307	1			T14	6		T15	5		T23	3
all_pins[4]	values[0x0]	84308	1			T1	22		T2	19		T3	12
all_pins[4]	values[0x1]	338	1			T14	6		T15	6		T23	4
all_pins[4]	transitions[0x0=>0x1]	291	1			T14	6		T15	5		T23	2
all_pins[4]	transitions[0x1=>0x0]	133	1			T13	2		T15	1		T236	1
all_pins[5]	values[0x0]	84466	1			T1	22		T2	19		T3	12
all_pins[5]	values[0x1]	180	1			T13	2		T15	2		T23	2
all_pins[5]	transitions[0x0=>0x1]	142	1			T13	2		T15	2		T23	2
all_pins[5]	transitions[0x1=>0x0]	686	1			T7	3		T36	2		T11	1
all_pins[6]	values[0x0]	83922	1			T1	22		T2	19		T3	12
all_pins[6]	values[0x1]	724	1			T7	3		T36	2		T11	1
all_pins[6]	transitions[0x0=>0x1]	694	1			T7	3		T36	2		T11	1
all_pins[6]	transitions[0x1=>0x0]	217	1			T30	2		T115	1		T31	4
all_pins[7]	values[0x0]	84399	1			T1	22		T2	19		T3	12
all_pins[7]	values[0x1]	247	1			T30	2		T115	1		T31	5
all_pins[7]	transitions[0x0=>0x1]	132	1			T30	1		T115	1		T31	1
all_pins[7]	transitions[0x1=>0x0]	10597	1			T1	1		T2	13		T3	5
all_pins[8]	values[0x0]	73934	1			T1	21		T2	6		T3	7
all_pins[8]	values[0x1]	10712	1			T1	1		T2	13		T3	5
all_pins[8]	transitions[0x0=>0x1]	5997	1			T1	1		T2	13		T3	1
all_pins[8]	transitions[0x1=>0x0]	11332	1			T1	5		T3	2		T4	2