Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	4657903	1			T1	4		T2	46		T3	9
all_levels[1]	2086473	1			T2	10		T5	10		T6	4
all_levels[2]	310283	1			T2	1		T5	8		T8	1
all_levels[3]	155801	1			T2	3		T5	8		T10	164
all_levels[4]	176242	1			T2	4		T5	8		T7	6
all_levels[5]	199560	1			T1	2		T2	2		T5	3
all_levels[6]	149109	1			T1	1		T2	3		T5	3
all_levels[7]	324736	1			T2	3		T5	9		T7	6
all_levels[8]	194957	1			T2	3		T3	1		T5	5
all_levels[9]	174577	1			T3	1		T5	5		T7	1
all_levels[10]	265998	1			T1	1		T2	1		T3	3
all_levels[11]	150645	1			T1	1		T2	2		T5	6
all_levels[12]	152148	1			T2	3		T5	6		T10	151
all_levels[13]	146508	1			T2	2		T3	1		T5	4
all_levels[14]	258816	1			T2	2		T5	1		T7	10
all_levels[15]	194171	1			T2	1		T5	2		T9	36
all_levels[16]	193469	1			T2	1		T5	4		T10	186
all_levels[17]	546071	1			T1	1		T2	5		T3	1
all_levels[18]	425675	1			T2	6		T3	1		T5	1
all_levels[19]	149306	1			T2	5		T5	3		T10	171
all_levels[20]	178006	1			T2	3		T5	2		T10	163
all_levels[21]	139644	1			T1	1		T2	2		T10	158
all_levels[22]	203695	1			T2	6		T3	1		T5	2
all_levels[23]	179202	1			T5	1		T10	158		T21	110
all_levels[24]	159227	1			T2	3		T5	1		T7	15
all_levels[25]	203403	1			T2	1		T3	1		T5	2
all_levels[26]	136051	1			T2	2		T5	2		T8	2
all_levels[27]	178991	1			T2	1		T5	3		T10	168
all_levels[28]	267429	1			T2	4		T5	1		T10	165
all_levels[29]	231097	1			T1	1		T5	4		T10	175
all_levels[30]	128530	1			T5	1		T10	172		T21	2651
all_levels[31]	427944	1			T1	107		T5	2		T10	4948
all_levels[32]	11154894	1			T1	1156		T3	7		T5	7

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24497026

1

T1

1275

T2

120

T3

26

auto[1]

3535

1

T2

5

T4

9

T5

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	4655933	1			T1	4		T2	43		T3	9
all_levels[0]	auto[1]	1970	1			T2	3		T4	9		T5	2
all_levels[1]	auto[0]	2086189	1			T2	8		T5	7		T6	4
all_levels[1]	auto[1]	284	1			T2	2		T5	3		T7	1
all_levels[2]	auto[0]	310246	1			T2	1		T5	8		T8	1
all_levels[2]	auto[1]	37	1			T40	2		T90	2		T93	1
all_levels[3]	auto[0]	155734	1			T2	3		T5	8		T10	164
all_levels[3]	auto[1]	67	1			T159	1		T89	5		T290	1
all_levels[4]	auto[0]	176206	1			T2	4		T5	8		T7	6
all_levels[4]	auto[1]	36	1			T138	1		T145	1		T326	1
all_levels[5]	auto[0]	199535	1			T1	2		T2	2		T5	3
all_levels[5]	auto[1]	25	1			T35	1		T291	1		T105	1
all_levels[6]	auto[0]	149079	1			T1	1		T2	3		T5	3
all_levels[6]	auto[1]	30	1			T12	1		T171	5		T261	1
all_levels[7]	auto[0]	324669	1			T2	3		T5	9		T7	6
all_levels[7]	auto[1]	67	1			T20	2		T251	1		T159	2
all_levels[8]	auto[0]	194931	1			T2	3		T3	1		T5	5
all_levels[8]	auto[1]	26	1			T256	1		T254	2		T168	1
all_levels[9]	auto[0]	174547	1			T3	1		T5	4		T7	1
all_levels[9]	auto[1]	30	1			T5	1		T175	1		T91	2
all_levels[10]	auto[0]	265963	1			T1	1		T2	1		T3	3
all_levels[10]	auto[1]	35	1			T327	1		T124	4		T300	1
all_levels[11]	auto[0]	150627	1			T1	1		T2	2		T5	6
all_levels[11]	auto[1]	18	1			T42	1		T15	1		T23	1
all_levels[12]	auto[0]	152105	1			T2	3		T5	6		T10	151
all_levels[12]	auto[1]	43	1			T36	1		T11	1		T113	1
all_levels[13]	auto[0]	146480	1			T2	2		T3	1		T5	4
all_levels[13]	auto[1]	28	1			T100	4		T211	1		T136	2
all_levels[14]	auto[0]	258786	1			T2	2		T5	1		T7	10
all_levels[14]	auto[1]	30	1			T12	1		T23	1		T260	1
all_levels[15]	auto[0]	194080	1			T2	1		T5	2		T9	36
all_levels[15]	auto[1]	91	1			T14	4		T257	5		T316	31
all_levels[16]	auto[0]	193448	1			T2	1		T5	4		T10	186
all_levels[16]	auto[1]	21	1			T108	1		T296	1		T160	1
all_levels[17]	auto[0]	546053	1			T1	1		T2	5		T3	1
all_levels[17]	auto[1]	18	1			T119	1		T154	1		T328	2
all_levels[18]	auto[0]	425652	1			T2	6		T3	1		T5	1
all_levels[18]	auto[1]	23	1			T9	1		T93	3		T166	1
all_levels[19]	auto[0]	149293	1			T2	5		T5	1		T10	171
all_levels[19]	auto[1]	13	1			T5	2		T329	2		T330	1
all_levels[20]	auto[0]	177990	1			T2	3		T5	2		T10	163
all_levels[20]	auto[1]	16	1			T267	2		T170	1		T331	2
all_levels[21]	auto[0]	139635	1			T1	1		T2	2		T10	158
all_levels[21]	auto[1]	9	1			T118	1		T215	1		T293	1
all_levels[22]	auto[0]	203677	1			T2	6		T3	1		T5	2
all_levels[22]	auto[1]	18	1			T102	1		T253	1		T160	3
all_levels[23]	auto[0]	179182	1			T5	1		T10	158		T21	110
all_levels[23]	auto[1]	20	1			T171	1		T110	2		T89	1
all_levels[24]	auto[0]	159220	1			T2	3		T5	1		T7	15
all_levels[24]	auto[1]	7	1			T23	1		T175	1		T140	1
all_levels[25]	auto[0]	203394	1			T2	1		T3	1		T5	2
all_levels[25]	auto[1]	9	1			T165	2		T332	1		T147	1
all_levels[26]	auto[0]	136042	1			T2	2		T5	2		T8	2
all_levels[26]	auto[1]	9	1			T249	1		T174	1		T333	1
all_levels[27]	auto[0]	178964	1			T2	1		T5	3		T10	168
all_levels[27]	auto[1]	27	1			T40	3		T91	3		T334	1
all_levels[28]	auto[0]	267409	1			T2	4		T5	1		T10	165
all_levels[28]	auto[1]	20	1			T40	1		T327	1		T246	1
all_levels[29]	auto[0]	231084	1			T1	1		T5	4		T10	175
all_levels[29]	auto[1]	13	1			T91	1		T252	2		T314	1
all_levels[30]	auto[0]	128518	1			T5	1		T10	172		T21	2651
all_levels[30]	auto[1]	12	1			T40	1		T159	1		T335	1
all_levels[31]	auto[0]	427933	1			T1	107		T5	2		T10	4948
all_levels[31]	auto[1]	11	1			T140	1		T199	1		T220	1
all_levels[32]	auto[0]	11154422	1			T1	1156		T3	7		T5	6
all_levels[32]	auto[1]	472	1			T5	1		T7	2		T37	1