Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	712	1			T15	11		T23	7		T18	4
all_values[1]	712	1			T15	11		T23	7		T18	4
all_values[2]	712	1			T15	11		T23	7		T18	4
all_values[3]	712	1			T15	11		T23	7		T18	4
all_values[4]	712	1			T15	11		T23	7		T18	4
all_values[5]	712	1			T15	11		T23	7		T18	4
all_values[6]	712	1			T15	11		T23	7		T18	4
all_values[7]	712	1			T15	11		T23	7		T18	4
all_values[8]	712	1			T15	11		T23	7		T18	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3467

1

T15

60

T23

36

T18

21

auto[1]

2941

1

T15

39

T23

27

T18

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2089

1

T15

22

T23

19

T18

15

auto[1]

4319

1

T15

77

T23

44

T18

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3762

1

T15

55

T23

35

T18

23

auto[1]

2646

1

T15

44

T23

28

T18

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	224	1			T15	5		T23	1		T30	1
all_values[0]	auto[0]	auto[1]	auto[1]	196	1			T15	1		T23	3		T18	1
all_values[0]	auto[1]	auto[0]	auto[1]	164	1			T15	3		T23	2		T18	2
all_values[0]	auto[1]	auto[1]	auto[1]	128	1			T15	2		T23	1		T18	1
all_values[1]	auto[0]	auto[0]	auto[0]	234	1			T15	2		T23	2		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	193	1			T15	4		T18	1		T30	1
all_values[1]	auto[1]	auto[0]	auto[1]	151	1			T15	1		T23	3		T30	1
all_values[1]	auto[1]	auto[1]	auto[1]	134	1			T15	4		T23	2		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	153	1			T15	2		T18	1		T30	1
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T15	2		T30	1		T34	1
all_values[2]	auto[0]	auto[1]	auto[0]	124	1			T23	2		T18	2		T31	4
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T15	4		T23	1		T31	2
all_values[2]	auto[1]	auto[0]	auto[1]	166	1			T15	3		T23	2		T30	2
all_values[2]	auto[1]	auto[1]	auto[1]	122	1			T23	2		T18	1		T31	3
all_values[3]	auto[0]	auto[0]	auto[0]	137	1			T15	2		T23	1		T18	1
all_values[3]	auto[0]	auto[0]	auto[1]	67	1			T23	2		T30	1		T31	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T15	2		T18	2		T31	2
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T15	1		T31	1		T82	2
all_values[3]	auto[1]	auto[0]	auto[1]	187	1			T15	4		T23	3		T30	2
all_values[3]	auto[1]	auto[1]	auto[1]	125	1			T15	2		T23	1		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	157	1			T15	1		T18	2		T30	1
all_values[4]	auto[0]	auto[0]	auto[1]	63	1			T15	2		T23	1		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	119	1			T23	1		T31	5		T82	1
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T15	4		T23	1		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	164	1			T15	2		T23	1		T18	1
all_values[4]	auto[1]	auto[1]	auto[1]	133	1			T15	2		T23	3		T31	3
all_values[5]	auto[0]	auto[0]	auto[0]	147	1			T15	2		T23	3		T18	1
all_values[5]	auto[0]	auto[0]	auto[1]	68	1			T15	2		T18	1		T30	1
all_values[5]	auto[0]	auto[1]	auto[0]	126	1			T23	1		T30	1		T34	1
all_values[5]	auto[0]	auto[1]	auto[1]	71	1			T15	2		T23	1		T18	1
all_values[5]	auto[1]	auto[0]	auto[1]	165	1			T15	3		T23	1		T18	1
all_values[5]	auto[1]	auto[1]	auto[1]	135	1			T15	2		T23	1		T31	1
all_values[6]	auto[0]	auto[0]	auto[0]	156	1			T15	2		T23	3		T18	3
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T15	3		T23	1		T31	2
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T15	1		T23	1		T18	1
all_values[6]	auto[0]	auto[1]	auto[1]	56	1			T31	3		T82	1		T96	1
all_values[6]	auto[1]	auto[0]	auto[1]	162	1			T15	4		T23	2		T31	5
all_values[6]	auto[1]	auto[1]	auto[1]	117	1			T15	1		T31	1		T34	2
all_values[7]	auto[0]	auto[0]	auto[0]	141	1			T15	2		T23	4		T31	7
all_values[7]	auto[0]	auto[0]	auto[1]	88	1			T15	2		T18	1		T31	1
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T15	2		T23	1		T31	1
all_values[7]	auto[0]	auto[1]	auto[1]	60	1			T30	3		T31	1		T97	1
all_values[7]	auto[1]	auto[0]	auto[1]	163	1			T15	3		T23	2		T18	3
all_values[7]	auto[1]	auto[1]	auto[1]	130	1			T15	2		T31	3		T34	1
all_values[8]	auto[0]	auto[0]	auto[1]	204	1			T15	3		T23	2		T18	2
all_values[8]	auto[0]	auto[1]	auto[1]	208	1			T15	2		T23	3		T18	1
all_values[8]	auto[1]	auto[0]	auto[1]	154	1			T15	5		T18	1		T30	1
all_values[8]	auto[1]	auto[1]	auto[1]	146	1			T15	1		T23	2		T30	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal