Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.10 97.65 100.00 98.38 100.00 99.41


Total test records in report: 1319
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T1259 /workspace/coverage/cover_reg_top/49.uart_intr_test.1835057271 Aug 18 04:44:45 PM PDT 24 Aug 18 04:44:46 PM PDT 24 13669200 ps
T1260 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2262911222 Aug 18 04:44:43 PM PDT 24 Aug 18 04:44:44 PM PDT 24 179757255 ps
T1261 /workspace/coverage/cover_reg_top/30.uart_intr_test.2522216291 Aug 18 04:44:46 PM PDT 24 Aug 18 04:44:47 PM PDT 24 146450716 ps
T1262 /workspace/coverage/cover_reg_top/34.uart_intr_test.3528854655 Aug 18 04:44:36 PM PDT 24 Aug 18 04:44:37 PM PDT 24 112266501 ps
T1263 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3484926496 Aug 18 04:44:30 PM PDT 24 Aug 18 04:44:31 PM PDT 24 216295285 ps
T1264 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3796578520 Aug 18 04:44:41 PM PDT 24 Aug 18 04:44:42 PM PDT 24 12618368 ps
T73 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2550056682 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:53 PM PDT 24 82372612 ps
T1265 /workspace/coverage/cover_reg_top/43.uart_intr_test.4017012708 Aug 18 04:44:38 PM PDT 24 Aug 18 04:44:39 PM PDT 24 83088537 ps
T1266 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3231091066 Aug 18 04:44:50 PM PDT 24 Aug 18 04:44:50 PM PDT 24 66522782 ps
T49 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4072545473 Aug 18 04:44:45 PM PDT 24 Aug 18 04:44:46 PM PDT 24 46868310 ps
T1267 /workspace/coverage/cover_reg_top/38.uart_intr_test.281342295 Aug 18 04:44:45 PM PDT 24 Aug 18 04:44:45 PM PDT 24 29538825 ps
T1268 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1363314909 Aug 18 04:44:55 PM PDT 24 Aug 18 04:44:56 PM PDT 24 112641393 ps
T1269 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2412162956 Aug 18 04:44:32 PM PDT 24 Aug 18 04:44:33 PM PDT 24 85759651 ps
T1270 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1456616084 Aug 18 04:44:23 PM PDT 24 Aug 18 04:44:24 PM PDT 24 16625721 ps
T1271 /workspace/coverage/cover_reg_top/42.uart_intr_test.2641048588 Aug 18 04:44:34 PM PDT 24 Aug 18 04:44:35 PM PDT 24 16876308 ps
T1272 /workspace/coverage/cover_reg_top/18.uart_intr_test.1367286191 Aug 18 04:44:49 PM PDT 24 Aug 18 04:44:49 PM PDT 24 28483790 ps
T1273 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3349214984 Aug 18 04:44:48 PM PDT 24 Aug 18 04:44:50 PM PDT 24 134718365 ps
T1274 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3623417030 Aug 18 04:44:26 PM PDT 24 Aug 18 04:44:26 PM PDT 24 45100486 ps
T1275 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1254509570 Aug 18 04:44:38 PM PDT 24 Aug 18 04:44:39 PM PDT 24 89386692 ps
T1276 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.315867034 Aug 18 04:44:45 PM PDT 24 Aug 18 04:44:46 PM PDT 24 17630330 ps
T1277 /workspace/coverage/cover_reg_top/13.uart_intr_test.3187042397 Aug 18 04:44:43 PM PDT 24 Aug 18 04:44:44 PM PDT 24 54714702 ps
T1278 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1473912718 Aug 18 04:44:26 PM PDT 24 Aug 18 04:44:26 PM PDT 24 119956622 ps
T1279 /workspace/coverage/cover_reg_top/20.uart_intr_test.2073413731 Aug 18 04:44:44 PM PDT 24 Aug 18 04:44:45 PM PDT 24 11561065 ps
T1280 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.341372119 Aug 18 04:44:26 PM PDT 24 Aug 18 04:44:27 PM PDT 24 337793188 ps
T1281 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3075215886 Aug 18 04:44:41 PM PDT 24 Aug 18 04:44:43 PM PDT 24 64460188 ps
T1282 /workspace/coverage/cover_reg_top/11.uart_intr_test.2314397982 Aug 18 04:44:45 PM PDT 24 Aug 18 04:44:46 PM PDT 24 91479255 ps
T1283 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.435903805 Aug 18 04:44:37 PM PDT 24 Aug 18 04:44:38 PM PDT 24 37047265 ps
T1284 /workspace/coverage/cover_reg_top/27.uart_intr_test.2401985360 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:53 PM PDT 24 28486320 ps
T1285 /workspace/coverage/cover_reg_top/26.uart_intr_test.3080405808 Aug 18 04:44:47 PM PDT 24 Aug 18 04:44:48 PM PDT 24 24580540 ps
T1286 /workspace/coverage/cover_reg_top/29.uart_intr_test.4026796073 Aug 18 04:44:43 PM PDT 24 Aug 18 04:44:44 PM PDT 24 87287281 ps
T50 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2549897561 Aug 18 04:44:26 PM PDT 24 Aug 18 04:44:27 PM PDT 24 18691884 ps
T1287 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1352762408 Aug 18 04:44:30 PM PDT 24 Aug 18 04:44:31 PM PDT 24 203511998 ps
T1288 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.503863441 Aug 18 04:44:28 PM PDT 24 Aug 18 04:44:28 PM PDT 24 23416081 ps
T1289 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2816293217 Aug 18 04:44:37 PM PDT 24 Aug 18 04:44:38 PM PDT 24 324410805 ps
T1290 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3991821747 Aug 18 04:44:25 PM PDT 24 Aug 18 04:44:27 PM PDT 24 329010874 ps
T1291 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.518870839 Aug 18 04:44:27 PM PDT 24 Aug 18 04:44:28 PM PDT 24 48526836 ps
T235 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.248072948 Aug 18 04:44:35 PM PDT 24 Aug 18 04:44:36 PM PDT 24 77634204 ps
T1292 /workspace/coverage/cover_reg_top/25.uart_intr_test.318467389 Aug 18 04:44:54 PM PDT 24 Aug 18 04:44:55 PM PDT 24 47004111 ps
T1293 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3545809784 Aug 18 04:44:31 PM PDT 24 Aug 18 04:44:32 PM PDT 24 28231656 ps
T1294 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1097884039 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:53 PM PDT 24 53241547 ps
T1295 /workspace/coverage/cover_reg_top/4.uart_intr_test.3824996657 Aug 18 04:44:31 PM PDT 24 Aug 18 04:44:32 PM PDT 24 13587558 ps
T1296 /workspace/coverage/cover_reg_top/5.uart_intr_test.3148236218 Aug 18 04:44:37 PM PDT 24 Aug 18 04:44:37 PM PDT 24 45579770 ps
T76 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.554113364 Aug 18 04:44:41 PM PDT 24 Aug 18 04:44:42 PM PDT 24 285886905 ps
T1297 /workspace/coverage/cover_reg_top/15.uart_intr_test.2663712964 Aug 18 04:44:49 PM PDT 24 Aug 18 04:44:50 PM PDT 24 49598743 ps
T1298 /workspace/coverage/cover_reg_top/35.uart_intr_test.4244357012 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:53 PM PDT 24 55286846 ps
T1299 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.280122823 Aug 18 04:44:47 PM PDT 24 Aug 18 04:44:48 PM PDT 24 64906965 ps
T1300 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3477130353 Aug 18 04:44:25 PM PDT 24 Aug 18 04:44:26 PM PDT 24 68620751 ps
T1301 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2337970567 Aug 18 04:44:34 PM PDT 24 Aug 18 04:44:37 PM PDT 24 123500125 ps
T1302 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1550953310 Aug 18 04:44:31 PM PDT 24 Aug 18 04:44:32 PM PDT 24 64575697 ps
T1303 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.266291613 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:54 PM PDT 24 101413974 ps
T1304 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1097987356 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:54 PM PDT 24 16329134 ps
T1305 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1509441464 Aug 18 04:44:24 PM PDT 24 Aug 18 04:44:25 PM PDT 24 373196115 ps
T1306 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3352479168 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:54 PM PDT 24 100250449 ps
T1307 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1975376803 Aug 18 04:44:30 PM PDT 24 Aug 18 04:44:30 PM PDT 24 41106946 ps
T51 /workspace/coverage/cover_reg_top/6.uart_csr_rw.849892178 Aug 18 04:44:28 PM PDT 24 Aug 18 04:44:28 PM PDT 24 18224549 ps
T1308 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.248087786 Aug 18 04:44:36 PM PDT 24 Aug 18 04:44:38 PM PDT 24 573666193 ps
T1309 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1378168518 Aug 18 04:44:44 PM PDT 24 Aug 18 04:44:45 PM PDT 24 36877638 ps
T1310 /workspace/coverage/cover_reg_top/24.uart_intr_test.680858451 Aug 18 04:44:37 PM PDT 24 Aug 18 04:44:38 PM PDT 24 51169542 ps
T53 /workspace/coverage/cover_reg_top/14.uart_csr_rw.21225706 Aug 18 04:44:23 PM PDT 24 Aug 18 04:44:24 PM PDT 24 14825008 ps
T1311 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2416132066 Aug 18 04:44:32 PM PDT 24 Aug 18 04:44:34 PM PDT 24 342420984 ps
T1312 /workspace/coverage/cover_reg_top/2.uart_intr_test.614310507 Aug 18 04:44:28 PM PDT 24 Aug 18 04:44:29 PM PDT 24 16492126 ps
T1313 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.464392266 Aug 18 04:44:27 PM PDT 24 Aug 18 04:44:28 PM PDT 24 49709879 ps
T1314 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2752306807 Aug 18 04:44:23 PM PDT 24 Aug 18 04:44:24 PM PDT 24 24098470 ps
T1315 /workspace/coverage/cover_reg_top/17.uart_intr_test.1084043069 Aug 18 04:44:36 PM PDT 24 Aug 18 04:44:36 PM PDT 24 16197841 ps
T1316 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2191811611 Aug 18 04:44:50 PM PDT 24 Aug 18 04:44:51 PM PDT 24 61012736 ps
T52 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2203222851 Aug 18 04:44:28 PM PDT 24 Aug 18 04:44:29 PM PDT 24 1097727320 ps
T1317 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4178106477 Aug 18 04:44:31 PM PDT 24 Aug 18 04:44:32 PM PDT 24 45347214 ps
T1318 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4198796663 Aug 18 04:44:28 PM PDT 24 Aug 18 04:44:29 PM PDT 24 38780887 ps
T1319 /workspace/coverage/cover_reg_top/37.uart_intr_test.4159004885 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:52 PM PDT 24 16607810 ps

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1660331706
Short name T3
Test name
Test status
Simulation time 8279770779 ps
CPU time 25.47 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:43 PM PDT 24
Peak memory 216600 kb
Host smart-f4529365-16b6-4e83-be9a-f49ce1d59307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660331706 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1660331706
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all.2351062565
Short name T13
Test name
Test status
Simulation time 348749840034 ps
CPU time 1406.74 seconds
Started Aug 18 05:59:50 PM PDT 24
Finished Aug 18 06:23:17 PM PDT 24
Peak memory 200892 kb
Host smart-656f0e04-0096-43ef-b1a7-15eed8264624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351062565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2351062565
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all.4075096216
Short name T23
Test name
Test status
Simulation time 583746703616 ps
CPU time 108.7 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 06:00:32 PM PDT 24
Peak memory 209352 kb
Host smart-33e962a5-942a-4dd0-b26f-211d23474744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075096216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.4075096216
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2561950482
Short name T10
Test name
Test status
Simulation time 94501074212 ps
CPU time 753.81 seconds
Started Aug 18 05:59:48 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 200880 kb
Host smart-44bc4467-bd7d-4383-987e-0e4baf74823a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561950482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2561950482
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_stress_all.3831543375
Short name T104
Test name
Test status
Simulation time 254286100093 ps
CPU time 427.23 seconds
Started Aug 18 05:59:41 PM PDT 24
Finished Aug 18 06:06:49 PM PDT 24
Peak memory 209260 kb
Host smart-f5ad2dd7-a4c7-4c5d-a06a-ae3952c4050a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831543375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3831543375
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all.2573021914
Short name T107
Test name
Test status
Simulation time 352217209284 ps
CPU time 555.56 seconds
Started Aug 18 05:59:00 PM PDT 24
Finished Aug 18 06:08:15 PM PDT 24
Peak memory 200952 kb
Host smart-0f62482d-0fa5-41af-b14b-7ff985d14dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573021914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2573021914
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3261470140
Short name T247
Test name
Test status
Simulation time 145603977819 ps
CPU time 335.21 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:07:04 PM PDT 24
Peak memory 200892 kb
Host smart-d402368b-d12d-4f66-ab89-0d05b0afc8e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261470140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3261470140
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_stress_all.2940550359
Short name T93
Test name
Test status
Simulation time 258836445155 ps
CPU time 133.14 seconds
Started Aug 18 06:01:27 PM PDT 24
Finished Aug 18 06:03:41 PM PDT 24
Peak memory 200940 kb
Host smart-f51456ca-f623-4971-a902-fe68a3a2bc42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940550359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2940550359
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_sec_cm.867501514
Short name T27
Test name
Test status
Simulation time 81256633 ps
CPU time 0.88 seconds
Started Aug 18 05:57:36 PM PDT 24
Finished Aug 18 05:57:37 PM PDT 24
Peak memory 219012 kb
Host smart-238ccc5b-ce27-46b7-941c-83b4f93b7518
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867501514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.867501514
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.766525410
Short name T37
Test name
Test status
Simulation time 35236922954 ps
CPU time 20.47 seconds
Started Aug 18 05:58:41 PM PDT 24
Finished Aug 18 05:59:02 PM PDT 24
Peak memory 200836 kb
Host smart-f20d805d-a251-4888-be76-4b8935cad563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766525410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.766525410
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.4160531606
Short name T115
Test name
Test status
Simulation time 210115915746 ps
CPU time 95.58 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 06:00:09 PM PDT 24
Peak memory 200944 kb
Host smart-cbc757b1-4d7b-4ed0-995a-900bb0a81044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160531606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4160531606
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1601494968
Short name T175
Test name
Test status
Simulation time 129254661409 ps
CPU time 257.28 seconds
Started Aug 18 06:02:43 PM PDT 24
Finished Aug 18 06:07:00 PM PDT 24
Peak memory 200908 kb
Host smart-daba5c11-d1f1-4f7a-b4b2-e58037c2bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601494968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1601494968
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3585327405
Short name T44
Test name
Test status
Simulation time 15846271 ps
CPU time 0.79 seconds
Started Aug 18 04:44:38 PM PDT 24
Finished Aug 18 04:44:39 PM PDT 24
Peak memory 196404 kb
Host smart-9b8ba867-86a0-47c1-b649-f700e635d9f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585327405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3585327405
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/default/4.uart_stress_all.4081067514
Short name T146
Test name
Test status
Simulation time 270352628302 ps
CPU time 441.8 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 06:05:06 PM PDT 24
Peak memory 200888 kb
Host smart-b3e10aa3-dcaa-48c0-9945-38fc0065d915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081067514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4081067514
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1927877751
Short name T158
Test name
Test status
Simulation time 86366156912 ps
CPU time 239.04 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:06:01 PM PDT 24
Peak memory 200940 kb
Host smart-25c995bc-c0f4-4638-8853-bd6dbffbba59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927877751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1927877751
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.2113172162
Short name T290
Test name
Test status
Simulation time 418326467519 ps
CPU time 200.25 seconds
Started Aug 18 06:01:22 PM PDT 24
Finished Aug 18 06:04:43 PM PDT 24
Peak memory 209264 kb
Host smart-c87d2baa-77d6-4749-a1db-2afe241f4c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113172162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2113172162
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all.1162083012
Short name T138
Test name
Test status
Simulation time 253212031347 ps
CPU time 104.97 seconds
Started Aug 18 05:59:51 PM PDT 24
Finished Aug 18 06:01:36 PM PDT 24
Peak memory 216620 kb
Host smart-d0ef9a59-2a38-4c6e-a2c4-3041502f2d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162083012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1162083012
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1455222370
Short name T71
Test name
Test status
Simulation time 89252248 ps
CPU time 1.22 seconds
Started Aug 18 04:44:24 PM PDT 24
Finished Aug 18 04:44:25 PM PDT 24
Peak memory 199412 kb
Host smart-c47ec1d3-3d61-4c2a-a7ac-4d066329bc4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455222370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1455222370
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/19.uart_noise_filter.822716094
Short name T264
Test name
Test status
Simulation time 596839957143 ps
CPU time 103.98 seconds
Started Aug 18 05:58:59 PM PDT 24
Finished Aug 18 06:00:43 PM PDT 24
Peak memory 217464 kb
Host smart-4ef863bb-45c0-4062-b24b-2c80dfdde9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822716094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.822716094
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1272428052
Short name T36
Test name
Test status
Simulation time 53509048430 ps
CPU time 48.38 seconds
Started Aug 18 06:01:29 PM PDT 24
Finished Aug 18 06:02:17 PM PDT 24
Peak memory 201132 kb
Host smart-09c24b26-6b6d-4141-8a70-d5536a2261e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272428052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1272428052
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_alert_test.3258874353
Short name T336
Test name
Test status
Simulation time 12153579 ps
CPU time 0.56 seconds
Started Aug 18 05:57:29 PM PDT 24
Finished Aug 18 05:57:30 PM PDT 24
Peak memory 196244 kb
Host smart-2f7e1ebf-d687-4f54-801b-789bf2a06fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258874353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3258874353
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.570651587
Short name T106
Test name
Test status
Simulation time 70194376654 ps
CPU time 49.11 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 06:00:29 PM PDT 24
Peak memory 200868 kb
Host smart-ba4dff61-dba4-4a0a-bdfc-9040f609dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570651587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.570651587
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2128435801
Short name T92
Test name
Test status
Simulation time 54158414317 ps
CPU time 45.93 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:03:45 PM PDT 24
Peak memory 200852 kb
Host smart-b450f71d-498b-4132-abac-a65578c12573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128435801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2128435801
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.294688209
Short name T18
Test name
Test status
Simulation time 6160837482 ps
CPU time 22.98 seconds
Started Aug 18 06:01:23 PM PDT 24
Finished Aug 18 06:01:46 PM PDT 24
Peak memory 209472 kb
Host smart-7714a1c5-fea4-4c5b-beee-1b3e6303d1d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294688209 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.294688209
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.459872544
Short name T129
Test name
Test status
Simulation time 198206033722 ps
CPU time 98.07 seconds
Started Aug 18 06:01:42 PM PDT 24
Finished Aug 18 06:03:21 PM PDT 24
Peak memory 200828 kb
Host smart-836fcfb8-bea5-4466-aa89-e62d37497873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459872544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.459872544
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all.2921381339
Short name T279
Test name
Test status
Simulation time 147922938271 ps
CPU time 1170.14 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 06:19:05 PM PDT 24
Peak memory 217576 kb
Host smart-1e5410a4-4972-4f7b-99eb-55a154eb737f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921381339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2921381339
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1962954898
Short name T111
Test name
Test status
Simulation time 119970465889 ps
CPU time 136.14 seconds
Started Aug 18 06:01:35 PM PDT 24
Finished Aug 18 06:03:52 PM PDT 24
Peak memory 200880 kb
Host smart-c22546e0-f487-4ad9-8ee0-deae73c8c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962954898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1962954898
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.548592089
Short name T143
Test name
Test status
Simulation time 273060970917 ps
CPU time 591.14 seconds
Started Aug 18 06:01:37 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 200940 kb
Host smart-d4441334-30df-49a1-ba2a-12829ab93a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548592089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.548592089
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3574924666
Short name T56
Test name
Test status
Simulation time 29403405 ps
CPU time 0.59 seconds
Started Aug 18 04:44:32 PM PDT 24
Finished Aug 18 04:44:33 PM PDT 24
Peak memory 195592 kb
Host smart-1edffb86-4bf7-4de2-b586-f3494af808b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574924666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3574924666
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1425532375
Short name T5
Test name
Test status
Simulation time 127704379398 ps
CPU time 231.49 seconds
Started Aug 18 05:58:35 PM PDT 24
Finished Aug 18 06:02:26 PM PDT 24
Peak memory 200852 kb
Host smart-f1857908-181e-454b-bcda-b78795c80796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425532375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1425532375
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.254916391
Short name T196
Test name
Test status
Simulation time 113319397721 ps
CPU time 79.5 seconds
Started Aug 18 06:03:02 PM PDT 24
Finished Aug 18 06:04:21 PM PDT 24
Peak memory 200944 kb
Host smart-0417a42d-0292-4a0e-bd49-959f6904a6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254916391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.254916391
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3931188840
Short name T171
Test name
Test status
Simulation time 112377517171 ps
CPU time 38.63 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:56 PM PDT 24
Peak memory 200864 kb
Host smart-4c68a07c-a73c-4b5b-842c-2bbe153f948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931188840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3931188840
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2229414709
Short name T215
Test name
Test status
Simulation time 18140658395 ps
CPU time 56.31 seconds
Started Aug 18 05:58:42 PM PDT 24
Finished Aug 18 05:59:38 PM PDT 24
Peak memory 209028 kb
Host smart-8868658b-6d5d-4ba2-8a33-3a54b0512d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229414709 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2229414709
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.4088759182
Short name T149
Test name
Test status
Simulation time 149947086054 ps
CPU time 483.38 seconds
Started Aug 18 05:57:38 PM PDT 24
Finished Aug 18 06:05:41 PM PDT 24
Peak memory 200908 kb
Host smart-38eb2229-a9eb-4617-abe8-18db6143081b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088759182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4088759182
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2710741660
Short name T113
Test name
Test status
Simulation time 42482787586 ps
CPU time 17.39 seconds
Started Aug 18 05:59:15 PM PDT 24
Finished Aug 18 05:59:32 PM PDT 24
Peak memory 200924 kb
Host smart-3e444171-43fe-42b3-a45b-10d908714c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710741660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2710741660
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.826557740
Short name T91
Test name
Test status
Simulation time 20841922800 ps
CPU time 32.09 seconds
Started Aug 18 06:03:02 PM PDT 24
Finished Aug 18 06:03:34 PM PDT 24
Peak memory 200940 kb
Host smart-c0b898c0-d4ca-4f49-8bfd-ca780c4be48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826557740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.826557740
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3071527345
Short name T161
Test name
Test status
Simulation time 195092027058 ps
CPU time 299.63 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:08:11 PM PDT 24
Peak memory 200880 kb
Host smart-f289f21c-d7f1-481c-8ebb-d1bd717feacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071527345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3071527345
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2411002142
Short name T300
Test name
Test status
Simulation time 22303461147 ps
CPU time 16.32 seconds
Started Aug 18 06:03:19 PM PDT 24
Finished Aug 18 06:03:35 PM PDT 24
Peak memory 200908 kb
Host smart-c884a486-f727-40ed-bd20-c07c95ea4795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411002142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2411002142
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.3175866412
Short name T209
Test name
Test status
Simulation time 193868019068 ps
CPU time 177.36 seconds
Started Aug 18 06:00:53 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 209184 kb
Host smart-4a5f43dd-1b33-42b7-82c3-c2853bf59087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175866412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3175866412
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3340984095
Short name T96
Test name
Test status
Simulation time 15358943574 ps
CPU time 96.73 seconds
Started Aug 18 06:02:00 PM PDT 24
Finished Aug 18 06:03:37 PM PDT 24
Peak memory 209092 kb
Host smart-5155de24-0ecb-41a3-8abe-40ff16162bbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340984095 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3340984095
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1920548107
Short name T230
Test name
Test status
Simulation time 66094260353 ps
CPU time 25.57 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:03:37 PM PDT 24
Peak memory 200808 kb
Host smart-98b949d6-3729-485b-9d85-e2aa91f8390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920548107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1920548107
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.2888487772
Short name T147
Test name
Test status
Simulation time 227724438582 ps
CPU time 554.26 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 06:07:15 PM PDT 24
Peak memory 200928 kb
Host smart-06fc5c9b-9067-44ae-b688-66f0e3a2b236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888487772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2888487772
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_intr.2701280155
Short name T14
Test name
Test status
Simulation time 46020323859 ps
CPU time 27.15 seconds
Started Aug 18 05:58:19 PM PDT 24
Finished Aug 18 05:58:46 PM PDT 24
Peak memory 200792 kb
Host smart-56ef9456-e087-46f1-aaff-bc256ce124b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701280155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2701280155
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2420789757
Short name T144
Test name
Test status
Simulation time 25191659201 ps
CPU time 20.07 seconds
Started Aug 18 06:02:19 PM PDT 24
Finished Aug 18 06:02:39 PM PDT 24
Peak memory 200864 kb
Host smart-c1852b60-4188-4cbe-b85b-62e09a52f7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420789757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2420789757
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2085532696
Short name T173
Test name
Test status
Simulation time 47411968834 ps
CPU time 47.88 seconds
Started Aug 18 06:02:27 PM PDT 24
Finished Aug 18 06:03:15 PM PDT 24
Peak memory 200864 kb
Host smart-6eb7d56c-5ac5-4649-b159-93c67f115227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085532696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2085532696
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.162227257
Short name T227
Test name
Test status
Simulation time 109274612505 ps
CPU time 45.24 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 06:00:17 PM PDT 24
Peak memory 200836 kb
Host smart-272b68e7-cb00-4dd5-8924-225d3b44cd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162227257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.162227257
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3636964945
Short name T100
Test name
Test status
Simulation time 135921394060 ps
CPU time 102.22 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:03:11 PM PDT 24
Peak memory 200752 kb
Host smart-44756e83-2a5d-4a5f-a8ce-36c0f894a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636964945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3636964945
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1694330718
Short name T154
Test name
Test status
Simulation time 20423232786 ps
CPU time 15.23 seconds
Started Aug 18 06:02:18 PM PDT 24
Finished Aug 18 06:02:34 PM PDT 24
Peak memory 200888 kb
Host smart-9006a2b3-8b08-490d-ab3c-efa85ccdf96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694330718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1694330718
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.366540804
Short name T159
Test name
Test status
Simulation time 79307629880 ps
CPU time 126.84 seconds
Started Aug 18 06:02:42 PM PDT 24
Finished Aug 18 06:04:49 PM PDT 24
Peak memory 200704 kb
Host smart-02a3b65b-e3c1-4188-bb6a-37bf6f66ebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366540804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.366540804
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1321252927
Short name T541
Test name
Test status
Simulation time 5229888169 ps
CPU time 76.57 seconds
Started Aug 18 05:59:49 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 217572 kb
Host smart-594d4fcf-5a2e-48c6-980a-397b6788adca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321252927 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1321252927
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1151040166
Short name T2
Test name
Test status
Simulation time 90437811303 ps
CPU time 64.23 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:04:16 PM PDT 24
Peak memory 200872 kb
Host smart-42be3cb8-5348-4a99-83e7-dbc4ae17914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151040166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1151040166
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1093098731
Short name T179
Test name
Test status
Simulation time 51221100138 ps
CPU time 86.25 seconds
Started Aug 18 05:57:29 PM PDT 24
Finished Aug 18 05:58:55 PM PDT 24
Peak memory 200920 kb
Host smart-22572cfc-5029-4855-b1f9-1d9a729f85b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093098731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1093098731
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3205052417
Short name T199
Test name
Test status
Simulation time 16657980678 ps
CPU time 32.08 seconds
Started Aug 18 06:02:20 PM PDT 24
Finished Aug 18 06:02:52 PM PDT 24
Peak memory 200820 kb
Host smart-2293f060-7234-455b-9ac9-c07c59a96aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205052417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3205052417
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.479088127
Short name T207
Test name
Test status
Simulation time 51548259525 ps
CPU time 123.68 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:05:13 PM PDT 24
Peak memory 200928 kb
Host smart-f951ad5c-0576-4948-9b1e-cc020d22f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479088127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.479088127
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2170951515
Short name T267
Test name
Test status
Simulation time 83644543607 ps
CPU time 74.71 seconds
Started Aug 18 06:03:09 PM PDT 24
Finished Aug 18 06:04:24 PM PDT 24
Peak memory 200828 kb
Host smart-8500c081-0bbd-4a60-99ed-fedcff95d24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170951515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2170951515
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4237525740
Short name T117
Test name
Test status
Simulation time 80420959084 ps
CPU time 32.78 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 200872 kb
Host smart-056efb36-1238-4a09-a668-6d9be35170e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237525740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4237525740
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.43637801
Short name T213
Test name
Test status
Simulation time 109263399385 ps
CPU time 136.58 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:02:12 PM PDT 24
Peak memory 200928 kb
Host smart-e62c1edd-c4b4-4080-8e19-4d394f712e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43637801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.43637801
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.3797738405
Short name T440
Test name
Test status
Simulation time 421749920519 ps
CPU time 199.59 seconds
Started Aug 18 05:57:50 PM PDT 24
Finished Aug 18 06:01:10 PM PDT 24
Peak memory 200884 kb
Host smart-e487e170-ec28-46fd-8e64-8ed182c97cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797738405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3797738405
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.554113364
Short name T76
Test name
Test status
Simulation time 285886905 ps
CPU time 1.34 seconds
Started Aug 18 04:44:41 PM PDT 24
Finished Aug 18 04:44:42 PM PDT 24
Peak memory 199468 kb
Host smart-bfd5fe81-1db2-4630-b735-45c63c14ae69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554113364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.554113364
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3350347587
Short name T139
Test name
Test status
Simulation time 123426884632 ps
CPU time 137.07 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:04:34 PM PDT 24
Peak memory 200868 kb
Host smart-fcca9b5f-9485-4c65-8a80-493bd5edb505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350347587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3350347587
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.4225382391
Short name T231
Test name
Test status
Simulation time 44716377313 ps
CPU time 17.45 seconds
Started Aug 18 06:02:20 PM PDT 24
Finished Aug 18 06:02:38 PM PDT 24
Peak memory 200936 kb
Host smart-22736f05-d0e0-4910-856e-5e82929427c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225382391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.4225382391
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all.4035726975
Short name T134
Test name
Test status
Simulation time 185290044376 ps
CPU time 311.03 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 06:03:42 PM PDT 24
Peak memory 200956 kb
Host smart-31a71c97-3ad8-4976-b1fd-f193911fd64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035726975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4035726975
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3565332034
Short name T190
Test name
Test status
Simulation time 42399311372 ps
CPU time 35.76 seconds
Started Aug 18 06:02:28 PM PDT 24
Finished Aug 18 06:03:04 PM PDT 24
Peak memory 200896 kb
Host smart-9f95511a-8735-46e7-bbce-fa61d030b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565332034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3565332034
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3735366669
Short name T126
Test name
Test status
Simulation time 133225822120 ps
CPU time 186.03 seconds
Started Aug 18 06:02:29 PM PDT 24
Finished Aug 18 06:05:35 PM PDT 24
Peak memory 200908 kb
Host smart-d8b205d1-8008-4d1a-b6c7-12ccc7e08453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735366669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3735366669
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3348747059
Short name T189
Test name
Test status
Simulation time 29985718799 ps
CPU time 51.06 seconds
Started Aug 18 06:02:26 PM PDT 24
Finished Aug 18 06:03:17 PM PDT 24
Peak memory 200832 kb
Host smart-c431907f-2afe-4832-8bc6-06b48021f863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348747059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3348747059
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3096801061
Short name T232
Test name
Test status
Simulation time 17883916477 ps
CPU time 23.61 seconds
Started Aug 18 06:02:31 PM PDT 24
Finished Aug 18 06:02:55 PM PDT 24
Peak memory 200896 kb
Host smart-83295290-7ea9-4f6e-a045-fc5169310863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096801061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3096801061
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1053905857
Short name T135
Test name
Test status
Simulation time 120631083810 ps
CPU time 69.37 seconds
Started Aug 18 06:02:34 PM PDT 24
Finished Aug 18 06:03:44 PM PDT 24
Peak memory 200864 kb
Host smart-30ca74fa-0781-44bc-8794-cd08fa0f89c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053905857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1053905857
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2846899022
Short name T119
Test name
Test status
Simulation time 66215761735 ps
CPU time 24.83 seconds
Started Aug 18 06:02:36 PM PDT 24
Finished Aug 18 06:03:01 PM PDT 24
Peak memory 200936 kb
Host smart-5e4a1361-e9c2-45d0-aa6c-d96db550cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846899022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2846899022
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3824409169
Short name T220
Test name
Test status
Simulation time 138674447605 ps
CPU time 791.29 seconds
Started Aug 18 06:02:36 PM PDT 24
Finished Aug 18 06:15:47 PM PDT 24
Peak memory 200836 kb
Host smart-9ee6dcb3-3d8b-41b7-8473-cfa523cb0326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824409169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3824409169
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3499455104
Short name T321
Test name
Test status
Simulation time 4182138499 ps
CPU time 29.83 seconds
Started Aug 18 05:59:09 PM PDT 24
Finished Aug 18 05:59:39 PM PDT 24
Peak memory 209144 kb
Host smart-853886f6-ee65-49af-b49a-a3ee22acac91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499455104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3499455104
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.276102091
Short name T193
Test name
Test status
Simulation time 48959464326 ps
CPU time 74.88 seconds
Started Aug 18 06:03:00 PM PDT 24
Finished Aug 18 06:04:15 PM PDT 24
Peak memory 200876 kb
Host smart-0c9d08b4-4727-4fe0-9f03-e20ddf093f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276102091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.276102091
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3305300625
Short name T108
Test name
Test status
Simulation time 15611989915 ps
CPU time 13.59 seconds
Started Aug 18 06:03:19 PM PDT 24
Finished Aug 18 06:03:33 PM PDT 24
Peak memory 200940 kb
Host smart-2c309b26-a932-44aa-a158-662e244a4fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305300625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3305300625
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all.3296238907
Short name T224
Test name
Test status
Simulation time 184908870488 ps
CPU time 458 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:08:40 PM PDT 24
Peak memory 216444 kb
Host smart-176d0c41-1917-4516-b813-3bf6c373cd7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296238907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3296238907
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3880682043
Short name T228
Test name
Test status
Simulation time 39425498855 ps
CPU time 58.48 seconds
Started Aug 18 06:01:57 PM PDT 24
Finished Aug 18 06:02:56 PM PDT 24
Peak memory 200888 kb
Host smart-b344c729-cfae-4ed3-a721-9976ef04e7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880682043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3880682043
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3106747019
Short name T226
Test name
Test status
Simulation time 91327494751 ps
CPU time 80.9 seconds
Started Aug 18 06:02:10 PM PDT 24
Finished Aug 18 06:03:31 PM PDT 24
Peak memory 200924 kb
Host smart-7d08f89f-6be1-4dae-ba97-c8b353e7e114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106747019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3106747019
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1037490555
Short name T1187
Test name
Test status
Simulation time 172033638 ps
CPU time 2.41 seconds
Started Aug 18 04:44:27 PM PDT 24
Finished Aug 18 04:44:34 PM PDT 24
Peak memory 197824 kb
Host smart-c0d69336-7ea1-4bf8-8d55-c742e14a99ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037490555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1037490555
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3623417030
Short name T1274
Test name
Test status
Simulation time 45100486 ps
CPU time 0.56 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:26 PM PDT 24
Peak memory 195484 kb
Host smart-d0d42d1a-fdc3-4f2a-a1ed-33e4d06fde8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623417030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3623417030
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1509441464
Short name T1305
Test name
Test status
Simulation time 373196115 ps
CPU time 0.77 seconds
Started Aug 18 04:44:24 PM PDT 24
Finished Aug 18 04:44:25 PM PDT 24
Peak memory 199668 kb
Host smart-54ac121c-8822-4cc2-bd6a-a8d0e24be8be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509441464 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1509441464
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.448202298
Short name T1195
Test name
Test status
Simulation time 43450348 ps
CPU time 0.62 seconds
Started Aug 18 04:44:19 PM PDT 24
Finished Aug 18 04:44:20 PM PDT 24
Peak memory 194216 kb
Host smart-14cb5f9f-ce1f-4735-bdae-ec4a25b66577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448202298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.448202298
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.503863441
Short name T1288
Test name
Test status
Simulation time 23416081 ps
CPU time 0.69 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 196724 kb
Host smart-ad0eb43e-1347-4c4d-aded-22648169d5a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503863441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.503863441
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3237525815
Short name T1202
Test name
Test status
Simulation time 109230614 ps
CPU time 1.58 seconds
Started Aug 18 04:44:22 PM PDT 24
Finished Aug 18 04:44:24 PM PDT 24
Peak memory 200272 kb
Host smart-a1d74655-83bf-4a59-9ee6-8b469d29db6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237525815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3237525815
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3868124725
Short name T1255
Test name
Test status
Simulation time 141807506 ps
CPU time 0.79 seconds
Started Aug 18 04:44:12 PM PDT 24
Finished Aug 18 04:44:13 PM PDT 24
Peak memory 196524 kb
Host smart-a2e7fafe-b53b-4bd8-8474-29daebbf46c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868124725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3868124725
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2287542464
Short name T1241
Test name
Test status
Simulation time 1201936824 ps
CPU time 1.5 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 197740 kb
Host smart-ff9f6f2a-0a67-4774-bb5d-b0059d236660
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287542464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2287542464
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2203222851
Short name T52
Test name
Test status
Simulation time 1097727320 ps
CPU time 0.87 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 195528 kb
Host smart-a80ee32f-6f06-40f7-be23-69908dcd18d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203222851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2203222851
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2816293217
Short name T1289
Test name
Test status
Simulation time 324410805 ps
CPU time 0.77 seconds
Started Aug 18 04:44:37 PM PDT 24
Finished Aug 18 04:44:38 PM PDT 24
Peak memory 198792 kb
Host smart-5344ee6c-9370-489f-bf11-dfcda382997a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816293217 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2816293217
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3087774911
Short name T1223
Test name
Test status
Simulation time 36048825 ps
CPU time 0.64 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:25 PM PDT 24
Peak memory 195344 kb
Host smart-e2475ad8-b59d-489a-8b24-6bde09fd38f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087774911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3087774911
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3125038947
Short name T1221
Test name
Test status
Simulation time 56790452 ps
CPU time 0.56 seconds
Started Aug 18 04:44:15 PM PDT 24
Finished Aug 18 04:44:15 PM PDT 24
Peak memory 194496 kb
Host smart-714f0aeb-9bc6-4152-a5e2-705350f75fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125038947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3125038947
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2889493567
Short name T1254
Test name
Test status
Simulation time 12894723 ps
CPU time 0.65 seconds
Started Aug 18 04:44:29 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 196668 kb
Host smart-692aa4e2-7f91-4f41-a563-e07b7e2a5bc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889493567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2889493567
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.709147365
Short name T1206
Test name
Test status
Simulation time 147456166 ps
CPU time 2.14 seconds
Started Aug 18 04:44:35 PM PDT 24
Finished Aug 18 04:44:38 PM PDT 24
Peak memory 200028 kb
Host smart-ee55badb-3eb2-4155-9577-9e0549f51db7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709147365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.709147365
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.248072948
Short name T235
Test name
Test status
Simulation time 77634204 ps
CPU time 1.25 seconds
Started Aug 18 04:44:35 PM PDT 24
Finished Aug 18 04:44:36 PM PDT 24
Peak memory 199296 kb
Host smart-5b8c18e7-30fb-4b36-ac9d-dad8dc8eefbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248072948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.248072948
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1378168518
Short name T1309
Test name
Test status
Simulation time 36877638 ps
CPU time 0.87 seconds
Started Aug 18 04:44:44 PM PDT 24
Finished Aug 18 04:44:45 PM PDT 24
Peak memory 199868 kb
Host smart-74e773e1-3042-425b-b0f3-65913e275964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378168518 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1378168518
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3011729533
Short name T1252
Test name
Test status
Simulation time 40786564 ps
CPU time 0.63 seconds
Started Aug 18 04:44:37 PM PDT 24
Finished Aug 18 04:44:38 PM PDT 24
Peak memory 195488 kb
Host smart-d081e9a9-02a2-4fd8-bfe6-4ef0f112b4cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011729533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3011729533
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3216529006
Short name T1237
Test name
Test status
Simulation time 45616683 ps
CPU time 0.58 seconds
Started Aug 18 04:44:49 PM PDT 24
Finished Aug 18 04:44:49 PM PDT 24
Peak memory 194456 kb
Host smart-10f9f57a-aeb2-4a5a-b9eb-6d687488fd98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216529006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3216529006
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2622501442
Short name T1253
Test name
Test status
Simulation time 64257903 ps
CPU time 0.71 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 197060 kb
Host smart-c7ae3e3c-542e-4aa0-b010-a8de5713eed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622501442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2622501442
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3513784860
Short name T1235
Test name
Test status
Simulation time 98640949 ps
CPU time 1.29 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 200140 kb
Host smart-3a0164d4-c71f-4712-869c-eec8d7374704
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513784860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3513784860
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2951709680
Short name T1234
Test name
Test status
Simulation time 25005044 ps
CPU time 0.64 seconds
Started Aug 18 04:44:34 PM PDT 24
Finished Aug 18 04:44:35 PM PDT 24
Peak memory 197472 kb
Host smart-c2eb6a5e-f350-43dc-a7fb-ef7eabf8d8da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951709680 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2951709680
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2020678781
Short name T1214
Test name
Test status
Simulation time 15427167 ps
CPU time 0.64 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:26 PM PDT 24
Peak memory 195444 kb
Host smart-044e5ad0-4f5e-4bf6-9c71-16158254f947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020678781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2020678781
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2314397982
Short name T1282
Test name
Test status
Simulation time 91479255 ps
CPU time 0.6 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:46 PM PDT 24
Peak memory 194408 kb
Host smart-830755ed-5391-412d-a0b1-fe10a2633805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314397982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2314397982
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4098046951
Short name T60
Test name
Test status
Simulation time 17755660 ps
CPU time 0.63 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 195652 kb
Host smart-3909f2b7-4afe-43ec-a6d9-d48c5b2cc07b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098046951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.4098046951
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3991821747
Short name T1290
Test name
Test status
Simulation time 329010874 ps
CPU time 1.91 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 200176 kb
Host smart-bec13fcc-bf03-4626-83ea-92aa7a491f64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991821747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3991821747
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.353511284
Short name T68
Test name
Test status
Simulation time 70494271 ps
CPU time 1.28 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:30 PM PDT 24
Peak memory 199464 kb
Host smart-c1cb90f6-2ffe-4297-a742-ec6a0e0c8193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353511284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.353511284
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.315867034
Short name T1276
Test name
Test status
Simulation time 17630330 ps
CPU time 0.68 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:46 PM PDT 24
Peak memory 197616 kb
Host smart-87a8ef11-760c-42c5-a96d-cef6db97a9cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315867034 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.315867034
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2140760464
Short name T1219
Test name
Test status
Simulation time 57875016 ps
CPU time 0.6 seconds
Started Aug 18 04:44:29 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 195456 kb
Host smart-3e980574-fb35-4810-9132-ba97660adcd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140760464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2140760464
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1489643965
Short name T1242
Test name
Test status
Simulation time 11413457 ps
CPU time 0.58 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 194412 kb
Host smart-39816e3c-c6b1-449f-9424-07f60597f313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489643965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1489643965
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2044576567
Short name T62
Test name
Test status
Simulation time 376344050 ps
CPU time 0.74 seconds
Started Aug 18 04:44:34 PM PDT 24
Finished Aug 18 04:44:35 PM PDT 24
Peak memory 197656 kb
Host smart-8ab22562-3d0f-478e-ab78-cc81e91b1683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044576567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2044576567
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2408599620
Short name T1218
Test name
Test status
Simulation time 39830463 ps
CPU time 1.94 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 200260 kb
Host smart-6142fea3-f502-405d-ad58-50dda6b4eb9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408599620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2408599620
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2697668357
Short name T72
Test name
Test status
Simulation time 84603596 ps
CPU time 1.24 seconds
Started Aug 18 04:44:48 PM PDT 24
Finished Aug 18 04:44:49 PM PDT 24
Peak memory 199288 kb
Host smart-9d66e2a9-6396-4740-a32e-68a6b88c058a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697668357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2697668357
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1550953310
Short name T1302
Test name
Test status
Simulation time 64575697 ps
CPU time 0.97 seconds
Started Aug 18 04:44:31 PM PDT 24
Finished Aug 18 04:44:32 PM PDT 24
Peak memory 199984 kb
Host smart-ce5ad5fa-9898-4c06-813a-ad0f4996c1a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550953310 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1550953310
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3580527458
Short name T1258
Test name
Test status
Simulation time 15428005 ps
CPU time 0.58 seconds
Started Aug 18 04:44:50 PM PDT 24
Finished Aug 18 04:44:51 PM PDT 24
Peak memory 195484 kb
Host smart-7b0eb828-f132-4f06-ba36-ffc476420a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580527458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3580527458
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3187042397
Short name T1277
Test name
Test status
Simulation time 54714702 ps
CPU time 0.59 seconds
Started Aug 18 04:44:43 PM PDT 24
Finished Aug 18 04:44:44 PM PDT 24
Peak memory 194532 kb
Host smart-61c01485-bc0f-4ea6-a955-0c0cfa1a640b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187042397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3187042397
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.178489792
Short name T1230
Test name
Test status
Simulation time 41934039 ps
CPU time 0.73 seconds
Started Aug 18 04:44:23 PM PDT 24
Finished Aug 18 04:44:24 PM PDT 24
Peak memory 197756 kb
Host smart-f739a2c1-2330-4e47-9ec1-9ffeb8bc4b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178489792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.178489792
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.516903916
Short name T1246
Test name
Test status
Simulation time 80426692 ps
CPU time 1.13 seconds
Started Aug 18 04:44:41 PM PDT 24
Finished Aug 18 04:44:42 PM PDT 24
Peak memory 199944 kb
Host smart-3e8007e6-4e4b-4b22-bddb-72dca0e4c027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516903916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.516903916
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4178106477
Short name T1317
Test name
Test status
Simulation time 45347214 ps
CPU time 0.95 seconds
Started Aug 18 04:44:31 PM PDT 24
Finished Aug 18 04:44:32 PM PDT 24
Peak memory 199256 kb
Host smart-7897cea6-b79d-41bc-991b-50dcb8ec0e70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178106477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.4178106477
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.870465390
Short name T1249
Test name
Test status
Simulation time 32470204 ps
CPU time 1.49 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 200264 kb
Host smart-9dd90f97-3ac1-4ab8-9c1e-6f7e46ec75a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870465390 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.870465390
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.21225706
Short name T53
Test name
Test status
Simulation time 14825008 ps
CPU time 0.6 seconds
Started Aug 18 04:44:23 PM PDT 24
Finished Aug 18 04:44:24 PM PDT 24
Peak memory 195512 kb
Host smart-5bcd031c-3188-49cc-9142-047212abd200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21225706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.21225706
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.4073447687
Short name T1193
Test name
Test status
Simulation time 34477417 ps
CPU time 0.6 seconds
Started Aug 18 04:44:44 PM PDT 24
Finished Aug 18 04:44:45 PM PDT 24
Peak memory 194444 kb
Host smart-7a277c93-0185-4645-8d0b-38b7a490e6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073447687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.4073447687
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.886664094
Short name T1228
Test name
Test status
Simulation time 32444299 ps
CPU time 0.8 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 197272 kb
Host smart-12c861b2-d83f-42e5-81a0-5eb6c61468da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886664094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.886664094
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3247578299
Short name T1198
Test name
Test status
Simulation time 63513413 ps
CPU time 1.26 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 200072 kb
Host smart-927b2ab0-d86f-4e1b-bb16-5def9a5541ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247578299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3247578299
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.607684373
Short name T1236
Test name
Test status
Simulation time 411164092 ps
CPU time 1.35 seconds
Started Aug 18 04:44:42 PM PDT 24
Finished Aug 18 04:44:43 PM PDT 24
Peak memory 199344 kb
Host smart-b999e2af-b08a-4f7a-832c-70a3cb344ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607684373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.607684373
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2412162956
Short name T1269
Test name
Test status
Simulation time 85759651 ps
CPU time 0.79 seconds
Started Aug 18 04:44:32 PM PDT 24
Finished Aug 18 04:44:33 PM PDT 24
Peak memory 198728 kb
Host smart-59bfcec3-d446-4368-9bc6-8929273b89c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412162956 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2412162956
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1065501286
Short name T61
Test name
Test status
Simulation time 41958932 ps
CPU time 0.56 seconds
Started Aug 18 04:44:27 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 195504 kb
Host smart-8aa80b73-2f5c-4c22-a1c6-857533fa8f18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065501286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1065501286
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2663712964
Short name T1297
Test name
Test status
Simulation time 49598743 ps
CPU time 0.57 seconds
Started Aug 18 04:44:49 PM PDT 24
Finished Aug 18 04:44:50 PM PDT 24
Peak memory 194568 kb
Host smart-2cd795be-b5f0-4be7-8efd-0a89055ec4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663712964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2663712964
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.518870839
Short name T1291
Test name
Test status
Simulation time 48526836 ps
CPU time 0.75 seconds
Started Aug 18 04:44:27 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 197072 kb
Host smart-f15f5414-edd1-4410-8967-87bc1d1a8e99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518870839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.518870839
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3989597081
Short name T1216
Test name
Test status
Simulation time 408323073 ps
CPU time 1.85 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 200232 kb
Host smart-cc7a9d84-2c7a-4a49-9e92-096c066764b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989597081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3989597081
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.248087786
Short name T1308
Test name
Test status
Simulation time 573666193 ps
CPU time 1.35 seconds
Started Aug 18 04:44:36 PM PDT 24
Finished Aug 18 04:44:38 PM PDT 24
Peak memory 199636 kb
Host smart-f491b202-7e21-42d1-af30-f64a1770c18f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248087786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.248087786
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2560220096
Short name T1213
Test name
Test status
Simulation time 59542997 ps
CPU time 0.84 seconds
Started Aug 18 04:44:40 PM PDT 24
Finished Aug 18 04:44:41 PM PDT 24
Peak memory 199916 kb
Host smart-44b32859-bffa-481c-b0b4-eb1148ff4bae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560220096 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2560220096
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2796947330
Short name T1238
Test name
Test status
Simulation time 16938712 ps
CPU time 0.59 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:26 PM PDT 24
Peak memory 195444 kb
Host smart-e4e6b64f-c2e6-422f-a006-b1e1fde35520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796947330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2796947330
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1837971256
Short name T1200
Test name
Test status
Simulation time 41840971 ps
CPU time 0.62 seconds
Started Aug 18 04:44:32 PM PDT 24
Finished Aug 18 04:44:33 PM PDT 24
Peak memory 194460 kb
Host smart-d315dec7-35c5-442d-b9b4-74b6923281ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837971256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1837971256
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2346045801
Short name T54
Test name
Test status
Simulation time 59806329 ps
CPU time 0.76 seconds
Started Aug 18 04:44:29 PM PDT 24
Finished Aug 18 04:44:30 PM PDT 24
Peak memory 196676 kb
Host smart-da20e307-95a1-4fc5-b660-ef3311dfd139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346045801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2346045801
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1228791794
Short name T1229
Test name
Test status
Simulation time 184003265 ps
CPU time 1.2 seconds
Started Aug 18 04:44:27 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 200228 kb
Host smart-068d2c61-6911-4f1a-a3a9-19343d586472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228791794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1228791794
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1097884039
Short name T1294
Test name
Test status
Simulation time 53241547 ps
CPU time 1.08 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 199108 kb
Host smart-265d488e-4f5e-4213-8769-9746fd173fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097884039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1097884039
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3231091066
Short name T1266
Test name
Test status
Simulation time 66522782 ps
CPU time 0.69 seconds
Started Aug 18 04:44:50 PM PDT 24
Finished Aug 18 04:44:50 PM PDT 24
Peak memory 197700 kb
Host smart-4d33831e-23af-46ee-8701-ad51d498caeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231091066 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3231091066
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.977324024
Short name T1220
Test name
Test status
Simulation time 45685844 ps
CPU time 0.6 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:26 PM PDT 24
Peak memory 195556 kb
Host smart-a5e99e2b-6404-43b6-96be-6df29bf85869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977324024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.977324024
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1084043069
Short name T1315
Test name
Test status
Simulation time 16197841 ps
CPU time 0.56 seconds
Started Aug 18 04:44:36 PM PDT 24
Finished Aug 18 04:44:36 PM PDT 24
Peak memory 194468 kb
Host smart-12941a45-6977-497e-bf3e-5f138971a5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084043069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1084043069
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1791225582
Short name T1244
Test name
Test status
Simulation time 18971894 ps
CPU time 0.66 seconds
Started Aug 18 04:44:32 PM PDT 24
Finished Aug 18 04:44:33 PM PDT 24
Peak memory 195676 kb
Host smart-723ff633-2597-4ac6-8fc2-fdd78f28cf7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791225582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1791225582
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2337970567
Short name T1301
Test name
Test status
Simulation time 123500125 ps
CPU time 2.14 seconds
Started Aug 18 04:44:34 PM PDT 24
Finished Aug 18 04:44:37 PM PDT 24
Peak memory 200144 kb
Host smart-15cbbb04-ba07-4464-9032-ab55e59501b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337970567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2337970567
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3226736863
Short name T74
Test name
Test status
Simulation time 77840427 ps
CPU time 1.21 seconds
Started Aug 18 04:44:32 PM PDT 24
Finished Aug 18 04:44:34 PM PDT 24
Peak memory 199232 kb
Host smart-b9106d3a-9962-4c56-bcf1-413ca2b024f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226736863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3226736863
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.210155120
Short name T1257
Test name
Test status
Simulation time 56189689 ps
CPU time 0.85 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 199860 kb
Host smart-3d58a969-b3e1-4af1-aa8d-94f472902e09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210155120 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.210155120
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3796578520
Short name T1264
Test name
Test status
Simulation time 12618368 ps
CPU time 0.57 seconds
Started Aug 18 04:44:41 PM PDT 24
Finished Aug 18 04:44:42 PM PDT 24
Peak memory 195416 kb
Host smart-400d8407-a7ca-4488-a3d6-fd74688c6b62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796578520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3796578520
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1367286191
Short name T1272
Test name
Test status
Simulation time 28483790 ps
CPU time 0.56 seconds
Started Aug 18 04:44:49 PM PDT 24
Finished Aug 18 04:44:49 PM PDT 24
Peak memory 194468 kb
Host smart-35c55563-ef49-4cae-88eb-59e67440451c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367286191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1367286191
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3143575178
Short name T57
Test name
Test status
Simulation time 13617208 ps
CPU time 0.64 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:46 PM PDT 24
Peak memory 196804 kb
Host smart-4447671f-6a4c-4189-8cff-feb6d53e18df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143575178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3143575178
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3075215886
Short name T1281
Test name
Test status
Simulation time 64460188 ps
CPU time 1.59 seconds
Started Aug 18 04:44:41 PM PDT 24
Finished Aug 18 04:44:43 PM PDT 24
Peak memory 200216 kb
Host smart-0f9f3592-1979-4bb7-956b-3a96508d1f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075215886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3075215886
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2416132066
Short name T1311
Test name
Test status
Simulation time 342420984 ps
CPU time 1.34 seconds
Started Aug 18 04:44:32 PM PDT 24
Finished Aug 18 04:44:34 PM PDT 24
Peak memory 199308 kb
Host smart-eb470ef5-fe35-4842-8d1f-2bb6f075be33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416132066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2416132066
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1254509570
Short name T1275
Test name
Test status
Simulation time 89386692 ps
CPU time 0.79 seconds
Started Aug 18 04:44:38 PM PDT 24
Finished Aug 18 04:44:39 PM PDT 24
Peak memory 199956 kb
Host smart-9ef5c600-fa6a-480e-b0a3-c5a267b76e33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254509570 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1254509570
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1363314909
Short name T1268
Test name
Test status
Simulation time 112641393 ps
CPU time 0.59 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 195652 kb
Host smart-8e1fe58e-abd8-4392-8b7a-38efae15bfff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363314909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1363314909
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3027877319
Short name T1197
Test name
Test status
Simulation time 89053830 ps
CPU time 0.55 seconds
Started Aug 18 04:44:49 PM PDT 24
Finished Aug 18 04:44:50 PM PDT 24
Peak memory 194584 kb
Host smart-dcb82fdc-29c7-44f7-b880-bb87933c22e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027877319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3027877319
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1097987356
Short name T1304
Test name
Test status
Simulation time 16329134 ps
CPU time 0.76 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 197924 kb
Host smart-555d2748-f34f-44c2-9371-e7daccb95a6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097987356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1097987356
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3352479168
Short name T1306
Test name
Test status
Simulation time 100250449 ps
CPU time 2.17 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 200124 kb
Host smart-b5952303-8795-419d-8112-c28381d3d0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352479168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3352479168
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.868280627
Short name T69
Test name
Test status
Simulation time 306575022 ps
CPU time 1.27 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:55 PM PDT 24
Peak memory 199424 kb
Host smart-72cc3e15-d929-47ba-9fad-e7412f50aba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868280627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.868280627
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3011109424
Short name T1190
Test name
Test status
Simulation time 58661872 ps
CPU time 0.75 seconds
Started Aug 18 04:44:30 PM PDT 24
Finished Aug 18 04:44:31 PM PDT 24
Peak memory 196408 kb
Host smart-81c33ae1-e7c5-447c-a1d5-852f9c02c27b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011109424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3011109424
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2879766625
Short name T1226
Test name
Test status
Simulation time 177689525 ps
CPU time 2.36 seconds
Started Aug 18 04:44:31 PM PDT 24
Finished Aug 18 04:44:33 PM PDT 24
Peak memory 197768 kb
Host smart-4da17d0c-62b1-441a-a0d9-89c0512d15d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879766625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2879766625
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4072545473
Short name T49
Test name
Test status
Simulation time 46868310 ps
CPU time 0.59 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:46 PM PDT 24
Peak memory 195372 kb
Host smart-d526c610-7536-45d0-a01d-1c056a0ab5f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072545473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4072545473
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2963566818
Short name T1185
Test name
Test status
Simulation time 25934882 ps
CPU time 0.63 seconds
Started Aug 18 04:44:30 PM PDT 24
Finished Aug 18 04:44:31 PM PDT 24
Peak memory 197724 kb
Host smart-d2a3925d-a1ee-498d-8c5f-96f3a8b8ffbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963566818 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2963566818
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2942291064
Short name T47
Test name
Test status
Simulation time 43997394 ps
CPU time 0.57 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 195452 kb
Host smart-af3946e7-cd85-4498-8d64-01ae64e59723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942291064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2942291064
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.614310507
Short name T1312
Test name
Test status
Simulation time 16492126 ps
CPU time 0.6 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 194592 kb
Host smart-53db53aa-7786-415b-9cc8-782697700773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614310507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.614310507
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.674619132
Short name T58
Test name
Test status
Simulation time 160788461 ps
CPU time 0.64 seconds
Started Aug 18 04:44:24 PM PDT 24
Finished Aug 18 04:44:25 PM PDT 24
Peak memory 196928 kb
Host smart-8888f411-591f-46d5-8b20-fed9199a3bee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674619132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.674619132
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2475186730
Short name T1204
Test name
Test status
Simulation time 202178353 ps
CPU time 1.95 seconds
Started Aug 18 04:44:18 PM PDT 24
Finished Aug 18 04:44:20 PM PDT 24
Peak memory 200168 kb
Host smart-cb460d54-e8e8-41ee-8751-6e5320be0fbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475186730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2475186730
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.802550722
Short name T75
Test name
Test status
Simulation time 148931146 ps
CPU time 1.31 seconds
Started Aug 18 04:44:19 PM PDT 24
Finished Aug 18 04:44:21 PM PDT 24
Peak memory 199496 kb
Host smart-b101e92d-767e-45b9-bbfa-dec0b8309f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802550722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.802550722
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2073413731
Short name T1279
Test name
Test status
Simulation time 11561065 ps
CPU time 0.55 seconds
Started Aug 18 04:44:44 PM PDT 24
Finished Aug 18 04:44:45 PM PDT 24
Peak memory 194472 kb
Host smart-4b0d83fa-db6a-4156-b2c0-815061a44977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073413731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2073413731
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2258542642
Short name T1217
Test name
Test status
Simulation time 12299841 ps
CPU time 0.57 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 194420 kb
Host smart-787d370d-277d-42c5-b9f4-07d390d1f34d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258542642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2258542642
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.3236831290
Short name T1250
Test name
Test status
Simulation time 106644061 ps
CPU time 0.6 seconds
Started Aug 18 04:44:36 PM PDT 24
Finished Aug 18 04:44:37 PM PDT 24
Peak memory 194504 kb
Host smart-a6d83b75-7341-4170-8ee0-ccd22813414f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236831290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3236831290
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.989228519
Short name T1192
Test name
Test status
Simulation time 14322452 ps
CPU time 0.6 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 194484 kb
Host smart-5c35a3ee-6301-4faa-a85e-eac69d34d2c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989228519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.989228519
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.680858451
Short name T1310
Test name
Test status
Simulation time 51169542 ps
CPU time 0.62 seconds
Started Aug 18 04:44:37 PM PDT 24
Finished Aug 18 04:44:38 PM PDT 24
Peak memory 194420 kb
Host smart-7a41f9a7-52ea-4e02-b173-144c22dd7ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680858451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.680858451
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.318467389
Short name T1292
Test name
Test status
Simulation time 47004111 ps
CPU time 0.58 seconds
Started Aug 18 04:44:54 PM PDT 24
Finished Aug 18 04:44:55 PM PDT 24
Peak memory 194480 kb
Host smart-8f32e76b-edc0-4099-b760-eedcbd1d6ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318467389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.318467389
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3080405808
Short name T1285
Test name
Test status
Simulation time 24580540 ps
CPU time 0.58 seconds
Started Aug 18 04:44:47 PM PDT 24
Finished Aug 18 04:44:48 PM PDT 24
Peak memory 194556 kb
Host smart-7a04fa33-f930-4a45-8f14-84d441012213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080405808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3080405808
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2401985360
Short name T1284
Test name
Test status
Simulation time 28486320 ps
CPU time 0.6 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 194472 kb
Host smart-e6d39dd7-6c78-452d-b4a4-3cc6c103a06d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401985360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2401985360
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3937985313
Short name T1208
Test name
Test status
Simulation time 77669823 ps
CPU time 0.58 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 194436 kb
Host smart-64db12b7-9ea8-4d40-b6a7-bbccda3a7542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937985313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3937985313
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.4026796073
Short name T1286
Test name
Test status
Simulation time 87287281 ps
CPU time 0.62 seconds
Started Aug 18 04:44:43 PM PDT 24
Finished Aug 18 04:44:44 PM PDT 24
Peak memory 194476 kb
Host smart-4a99b9da-1f73-4b7c-89d2-603e4edeac5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026796073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.4026796073
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1544850200
Short name T1251
Test name
Test status
Simulation time 37351151 ps
CPU time 0.76 seconds
Started Aug 18 04:44:34 PM PDT 24
Finished Aug 18 04:44:34 PM PDT 24
Peak memory 196728 kb
Host smart-3724aeab-7971-4cdd-96f3-96634e7f7b37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544850200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1544850200
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3193463103
Short name T1248
Test name
Test status
Simulation time 636988556 ps
CPU time 2.3 seconds
Started Aug 18 04:44:29 PM PDT 24
Finished Aug 18 04:44:32 PM PDT 24
Peak memory 197676 kb
Host smart-55fbf76c-cc29-4a3e-bd73-17237e5623f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193463103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3193463103
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1456616084
Short name T1270
Test name
Test status
Simulation time 16625721 ps
CPU time 0.6 seconds
Started Aug 18 04:44:23 PM PDT 24
Finished Aug 18 04:44:24 PM PDT 24
Peak memory 195528 kb
Host smart-7e96f476-7b21-4ad6-8f3f-92638163b263
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456616084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1456616084
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.435903805
Short name T1283
Test name
Test status
Simulation time 37047265 ps
CPU time 0.94 seconds
Started Aug 18 04:44:37 PM PDT 24
Finished Aug 18 04:44:38 PM PDT 24
Peak memory 199924 kb
Host smart-54c547f8-051c-4c63-95eb-7e8aef8d54eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435903805 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.435903805
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3470234588
Short name T1245
Test name
Test status
Simulation time 51884433 ps
CPU time 0.62 seconds
Started Aug 18 04:44:35 PM PDT 24
Finished Aug 18 04:44:36 PM PDT 24
Peak memory 195512 kb
Host smart-9df36556-946d-4dd6-a75c-0014e044347a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470234588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3470234588
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3149927847
Short name T1191
Test name
Test status
Simulation time 19215337 ps
CPU time 0.56 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 194572 kb
Host smart-dfffaee0-7f09-4533-9a40-b974888fa251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149927847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3149927847
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3258750918
Short name T55
Test name
Test status
Simulation time 33358362 ps
CPU time 0.64 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:26 PM PDT 24
Peak memory 195760 kb
Host smart-d7dc8201-f807-42f6-b1e6-ea0c31cfae7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258750918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3258750918
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.489767299
Short name T1212
Test name
Test status
Simulation time 205596214 ps
CPU time 1.05 seconds
Started Aug 18 04:44:30 PM PDT 24
Finished Aug 18 04:44:31 PM PDT 24
Peak memory 199988 kb
Host smart-0444ab83-70f4-498c-81a5-b9ff76911300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489767299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.489767299
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3780986454
Short name T234
Test name
Test status
Simulation time 94283902 ps
CPU time 1.31 seconds
Started Aug 18 04:44:23 PM PDT 24
Finished Aug 18 04:44:24 PM PDT 24
Peak memory 199452 kb
Host smart-e8354cd5-7852-4fa9-882c-dc9f5578bad2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780986454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3780986454
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2522216291
Short name T1261
Test name
Test status
Simulation time 146450716 ps
CPU time 0.54 seconds
Started Aug 18 04:44:46 PM PDT 24
Finished Aug 18 04:44:47 PM PDT 24
Peak memory 194532 kb
Host smart-57213356-b6a1-400c-8d97-85de0fd3a6e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522216291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2522216291
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.4257551828
Short name T1222
Test name
Test status
Simulation time 192859369 ps
CPU time 0.55 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 194492 kb
Host smart-e8560cf1-88ee-4c31-8d55-31cff33bc81e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257551828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4257551828
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2548250811
Short name T1239
Test name
Test status
Simulation time 14479410 ps
CPU time 0.56 seconds
Started Aug 18 04:44:33 PM PDT 24
Finished Aug 18 04:44:33 PM PDT 24
Peak memory 194456 kb
Host smart-a21aa36f-79c3-4596-9232-7198cd360000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548250811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2548250811
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2255997678
Short name T1199
Test name
Test status
Simulation time 12255448 ps
CPU time 0.56 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 194420 kb
Host smart-2a0adc01-ec18-4904-b895-943bbd133622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255997678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2255997678
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3528854655
Short name T1262
Test name
Test status
Simulation time 112266501 ps
CPU time 0.59 seconds
Started Aug 18 04:44:36 PM PDT 24
Finished Aug 18 04:44:37 PM PDT 24
Peak memory 194488 kb
Host smart-67dbfe3a-14e6-4c30-9e8f-0d2f28d44c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528854655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3528854655
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4244357012
Short name T1298
Test name
Test status
Simulation time 55286846 ps
CPU time 0.59 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 194464 kb
Host smart-93cf7954-a78f-42a0-9e29-b7219a1d38c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244357012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4244357012
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.283353327
Short name T1196
Test name
Test status
Simulation time 13962885 ps
CPU time 0.57 seconds
Started Aug 18 04:44:32 PM PDT 24
Finished Aug 18 04:44:32 PM PDT 24
Peak memory 194568 kb
Host smart-eff7199c-1ee6-4fad-b922-154865d2f27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283353327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.283353327
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4159004885
Short name T1319
Test name
Test status
Simulation time 16607810 ps
CPU time 0.55 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 194472 kb
Host smart-df4261ef-a554-4cf1-8540-4a555f7faf7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159004885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4159004885
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.281342295
Short name T1267
Test name
Test status
Simulation time 29538825 ps
CPU time 0.56 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:45 PM PDT 24
Peak memory 194500 kb
Host smart-cd1720ae-325c-48bc-ac39-447e09fbdd6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281342295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.281342295
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2066239170
Short name T1205
Test name
Test status
Simulation time 16525014 ps
CPU time 0.57 seconds
Started Aug 18 04:44:44 PM PDT 24
Finished Aug 18 04:44:45 PM PDT 24
Peak memory 194472 kb
Host smart-e84afb22-a74b-41b1-96d1-fa000acf4872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066239170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2066239170
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.438902227
Short name T46
Test name
Test status
Simulation time 93729245 ps
CPU time 0.83 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 196412 kb
Host smart-b31be799-fff5-4bb7-88d8-73d678b8a22c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438902227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.438902227
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2300037843
Short name T1209
Test name
Test status
Simulation time 37683079 ps
CPU time 1.43 seconds
Started Aug 18 04:44:27 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 198248 kb
Host smart-6cecb97d-3661-41cc-8767-bf2dca490dfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300037843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2300037843
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4198796663
Short name T1318
Test name
Test status
Simulation time 38780887 ps
CPU time 0.58 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 195368 kb
Host smart-345d3839-b57f-4cf2-8c0b-ca675e95c5bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198796663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.4198796663
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1352762408
Short name T1287
Test name
Test status
Simulation time 203511998 ps
CPU time 0.86 seconds
Started Aug 18 04:44:30 PM PDT 24
Finished Aug 18 04:44:31 PM PDT 24
Peak memory 199840 kb
Host smart-f6143147-b53d-4fd2-816e-272985208b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352762408 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1352762408
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2549897561
Short name T50
Test name
Test status
Simulation time 18691884 ps
CPU time 0.64 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 195796 kb
Host smart-be467bdc-ea18-427c-a32f-579a243056c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549897561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2549897561
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3824996657
Short name T1295
Test name
Test status
Simulation time 13587558 ps
CPU time 0.57 seconds
Started Aug 18 04:44:31 PM PDT 24
Finished Aug 18 04:44:32 PM PDT 24
Peak memory 194496 kb
Host smart-3cffcced-c590-4c7e-9120-9693a37a4215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824996657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3824996657
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1473912718
Short name T1278
Test name
Test status
Simulation time 119956622 ps
CPU time 0.66 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:26 PM PDT 24
Peak memory 195728 kb
Host smart-cf32f6a3-d246-4e6d-8301-897357b314c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473912718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1473912718
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3096522060
Short name T1210
Test name
Test status
Simulation time 82792115 ps
CPU time 1.89 seconds
Started Aug 18 04:44:19 PM PDT 24
Finished Aug 18 04:44:21 PM PDT 24
Peak memory 199812 kb
Host smart-1289f8fa-834a-4545-98a9-e2e3dc40c686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096522060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3096522060
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2262911222
Short name T1260
Test name
Test status
Simulation time 179757255 ps
CPU time 0.95 seconds
Started Aug 18 04:44:43 PM PDT 24
Finished Aug 18 04:44:44 PM PDT 24
Peak memory 198988 kb
Host smart-42337843-4294-4bd2-a49b-72b1b42d4d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262911222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2262911222
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2948663524
Short name T1194
Test name
Test status
Simulation time 24643855 ps
CPU time 0.59 seconds
Started Aug 18 04:44:54 PM PDT 24
Finished Aug 18 04:44:55 PM PDT 24
Peak memory 194552 kb
Host smart-b68bfa97-91e5-4df6-92b2-1271e6740501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948663524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2948663524
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.471179186
Short name T1203
Test name
Test status
Simulation time 118996901 ps
CPU time 0.56 seconds
Started Aug 18 04:44:47 PM PDT 24
Finished Aug 18 04:44:48 PM PDT 24
Peak memory 194560 kb
Host smart-8611ac60-c5ec-43ea-8aab-cb73e0a77aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471179186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.471179186
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2641048588
Short name T1271
Test name
Test status
Simulation time 16876308 ps
CPU time 0.58 seconds
Started Aug 18 04:44:34 PM PDT 24
Finished Aug 18 04:44:35 PM PDT 24
Peak memory 194500 kb
Host smart-fe63161a-dbaf-4b42-9d40-b6c71960485b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641048588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2641048588
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4017012708
Short name T1265
Test name
Test status
Simulation time 83088537 ps
CPU time 0.56 seconds
Started Aug 18 04:44:38 PM PDT 24
Finished Aug 18 04:44:39 PM PDT 24
Peak memory 194452 kb
Host smart-7cde8af1-f91e-45ec-9851-f2657265c47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017012708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4017012708
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3538618422
Short name T1186
Test name
Test status
Simulation time 63633504 ps
CPU time 0.56 seconds
Started Aug 18 04:44:50 PM PDT 24
Finished Aug 18 04:44:51 PM PDT 24
Peak memory 194468 kb
Host smart-03ad894b-2ede-4d4e-8f1e-599cde665968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538618422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3538618422
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.321772624
Short name T1231
Test name
Test status
Simulation time 71674587 ps
CPU time 0.57 seconds
Started Aug 18 04:44:49 PM PDT 24
Finished Aug 18 04:44:49 PM PDT 24
Peak memory 194480 kb
Host smart-ab9395c9-297b-47f6-a44e-762e69b6dd54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321772624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.321772624
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3196986376
Short name T1201
Test name
Test status
Simulation time 12243612 ps
CPU time 0.53 seconds
Started Aug 18 04:44:37 PM PDT 24
Finished Aug 18 04:44:38 PM PDT 24
Peak memory 194484 kb
Host smart-7cf12592-5d75-48f1-bc2b-0178d967c3e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196986376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3196986376
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.168931324
Short name T1227
Test name
Test status
Simulation time 59422323 ps
CPU time 0.58 seconds
Started Aug 18 04:44:39 PM PDT 24
Finished Aug 18 04:44:39 PM PDT 24
Peak memory 194460 kb
Host smart-b1eb1897-245c-4ce5-9490-7f4ed8de7179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168931324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.168931324
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.860418411
Short name T1233
Test name
Test status
Simulation time 24957455 ps
CPU time 0.55 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:46 PM PDT 24
Peak memory 194476 kb
Host smart-8957a756-eecc-4cfb-b585-a266a77a0458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860418411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.860418411
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1835057271
Short name T1259
Test name
Test status
Simulation time 13669200 ps
CPU time 0.54 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:46 PM PDT 24
Peak memory 194532 kb
Host smart-cf0a88bd-c9d0-4d21-926c-3e4a5b481861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835057271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1835057271
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3545809784
Short name T1293
Test name
Test status
Simulation time 28231656 ps
CPU time 0.84 seconds
Started Aug 18 04:44:31 PM PDT 24
Finished Aug 18 04:44:32 PM PDT 24
Peak memory 200172 kb
Host smart-d3b0d4ac-b36b-458e-8e78-ce2d7ecef6b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545809784 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3545809784
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.4274518833
Short name T45
Test name
Test status
Simulation time 39403073 ps
CPU time 0.57 seconds
Started Aug 18 04:44:31 PM PDT 24
Finished Aug 18 04:44:32 PM PDT 24
Peak memory 195512 kb
Host smart-872bc963-0af6-43fe-bf4a-20d58bf717c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274518833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.4274518833
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3148236218
Short name T1296
Test name
Test status
Simulation time 45579770 ps
CPU time 0.58 seconds
Started Aug 18 04:44:37 PM PDT 24
Finished Aug 18 04:44:37 PM PDT 24
Peak memory 194496 kb
Host smart-eeab6035-4e7c-4c8c-a25d-7b9e4c36e1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148236218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3148236218
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3477130353
Short name T1300
Test name
Test status
Simulation time 68620751 ps
CPU time 0.79 seconds
Started Aug 18 04:44:25 PM PDT 24
Finished Aug 18 04:44:26 PM PDT 24
Peak memory 197020 kb
Host smart-7765c5ee-1229-48e7-aefa-851ce0a59ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477130353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3477130353
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1244903436
Short name T1215
Test name
Test status
Simulation time 115821333 ps
CPU time 2.35 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:48 PM PDT 24
Peak memory 200024 kb
Host smart-b7dad1e6-e442-4729-9e9d-44f977ab0d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244903436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1244903436
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2550056682
Short name T73
Test name
Test status
Simulation time 82372612 ps
CPU time 0.92 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 198900 kb
Host smart-777d518d-87b0-4cb7-a7e6-291ef45b63dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550056682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2550056682
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.266291613
Short name T1303
Test name
Test status
Simulation time 101413974 ps
CPU time 1.16 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 200116 kb
Host smart-e9a4ac68-df9c-495a-a3ba-19ee2a198a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266291613 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.266291613
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.849892178
Short name T51
Test name
Test status
Simulation time 18224549 ps
CPU time 0.6 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 195480 kb
Host smart-c1d23c5d-8932-48da-bc27-9fc272e602c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849892178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.849892178
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4162015460
Short name T1211
Test name
Test status
Simulation time 12587053 ps
CPU time 0.58 seconds
Started Aug 18 04:44:31 PM PDT 24
Finished Aug 18 04:44:31 PM PDT 24
Peak memory 194784 kb
Host smart-a07890a4-d69a-4216-a9cb-1435805ea0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162015460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4162015460
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2290748999
Short name T59
Test name
Test status
Simulation time 30621903 ps
CPU time 0.73 seconds
Started Aug 18 04:44:32 PM PDT 24
Finished Aug 18 04:44:33 PM PDT 24
Peak memory 197752 kb
Host smart-a4602363-0cfb-4e6a-8620-baeb27e3103e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290748999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2290748999
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2081313957
Short name T1256
Test name
Test status
Simulation time 29440752 ps
CPU time 1.26 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 200224 kb
Host smart-5bd7fd2a-ba46-4037-a3c7-3894fc7a1fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081313957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2081313957
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.916440072
Short name T1225
Test name
Test status
Simulation time 46405082 ps
CPU time 0.92 seconds
Started Aug 18 04:44:27 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 199000 kb
Host smart-63130d35-78f7-4b00-8e26-f3fb0818d839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916440072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.916440072
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2191811611
Short name T1316
Test name
Test status
Simulation time 61012736 ps
CPU time 0.65 seconds
Started Aug 18 04:44:50 PM PDT 24
Finished Aug 18 04:44:51 PM PDT 24
Peak memory 197660 kb
Host smart-9602f4f0-ece5-4927-92cc-49037bc96129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191811611 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2191811611
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2752306807
Short name T1314
Test name
Test status
Simulation time 24098470 ps
CPU time 0.59 seconds
Started Aug 18 04:44:23 PM PDT 24
Finished Aug 18 04:44:24 PM PDT 24
Peak memory 195536 kb
Host smart-c178557f-b5b1-45b4-bbe5-22ba01bf1869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752306807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2752306807
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3641991398
Short name T1189
Test name
Test status
Simulation time 14097883 ps
CPU time 0.56 seconds
Started Aug 18 04:44:44 PM PDT 24
Finished Aug 18 04:44:45 PM PDT 24
Peak memory 194560 kb
Host smart-aa32709f-cb27-48d9-a1cf-57fba49b3039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641991398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3641991398
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.280122823
Short name T1299
Test name
Test status
Simulation time 64906965 ps
CPU time 0.68 seconds
Started Aug 18 04:44:47 PM PDT 24
Finished Aug 18 04:44:48 PM PDT 24
Peak memory 196024 kb
Host smart-bbcfa4d4-7eba-4593-8121-87cd54763c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280122823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.280122823
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1018175359
Short name T1188
Test name
Test status
Simulation time 66101177 ps
CPU time 1.76 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:30 PM PDT 24
Peak memory 200140 kb
Host smart-9991da21-1509-435c-8392-bcb08a22ef27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018175359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1018175359
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.464392266
Short name T1313
Test name
Test status
Simulation time 49709879 ps
CPU time 0.96 seconds
Started Aug 18 04:44:27 PM PDT 24
Finished Aug 18 04:44:28 PM PDT 24
Peak memory 198940 kb
Host smart-a86c7626-2a6f-48ec-91a2-46afea5895c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464392266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.464392266
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2703167251
Short name T1240
Test name
Test status
Simulation time 113993822 ps
CPU time 0.89 seconds
Started Aug 18 04:44:23 PM PDT 24
Finished Aug 18 04:44:24 PM PDT 24
Peak memory 199892 kb
Host smart-50d1bbcc-4669-4fae-8dea-ab26b51d0afd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703167251 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2703167251
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2093746441
Short name T1207
Test name
Test status
Simulation time 13476783 ps
CPU time 0.6 seconds
Started Aug 18 04:44:43 PM PDT 24
Finished Aug 18 04:44:44 PM PDT 24
Peak memory 195388 kb
Host smart-4a02202b-d33f-4c76-8d9a-c7c455fcf9d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093746441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2093746441
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2357972782
Short name T1243
Test name
Test status
Simulation time 13769574 ps
CPU time 0.54 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:29 PM PDT 24
Peak memory 194484 kb
Host smart-934081d1-a4ee-4d8c-ad2e-d1c244d97fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357972782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2357972782
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1975376803
Short name T1307
Test name
Test status
Simulation time 41106946 ps
CPU time 0.65 seconds
Started Aug 18 04:44:30 PM PDT 24
Finished Aug 18 04:44:30 PM PDT 24
Peak memory 197084 kb
Host smart-36ad12c9-a378-483d-a1ca-21c9bc3e0adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975376803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1975376803
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3349214984
Short name T1273
Test name
Test status
Simulation time 134718365 ps
CPU time 2.39 seconds
Started Aug 18 04:44:48 PM PDT 24
Finished Aug 18 04:44:50 PM PDT 24
Peak memory 200100 kb
Host smart-84d77c4c-0061-4b7a-9e1f-26d6f24868aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349214984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3349214984
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3484926496
Short name T1263
Test name
Test status
Simulation time 216295285 ps
CPU time 0.98 seconds
Started Aug 18 04:44:30 PM PDT 24
Finished Aug 18 04:44:31 PM PDT 24
Peak memory 199284 kb
Host smart-77fd4bdf-71e1-483e-8ff3-4bfcd3ab0718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484926496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3484926496
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.341372119
Short name T1280
Test name
Test status
Simulation time 337793188 ps
CPU time 0.79 seconds
Started Aug 18 04:44:26 PM PDT 24
Finished Aug 18 04:44:27 PM PDT 24
Peak memory 199680 kb
Host smart-6692e946-61f3-4685-8d91-7c470c4ef58a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341372119 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.341372119
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2348399095
Short name T48
Test name
Test status
Simulation time 54182843 ps
CPU time 0.56 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:46 PM PDT 24
Peak memory 195512 kb
Host smart-b9d7dd91-0355-4fa5-85b6-50b83ac80093
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348399095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2348399095
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1562371459
Short name T1247
Test name
Test status
Simulation time 148180505 ps
CPU time 0.56 seconds
Started Aug 18 04:44:34 PM PDT 24
Finished Aug 18 04:44:35 PM PDT 24
Peak memory 194428 kb
Host smart-f7a59692-e357-4ff3-aba4-21e767252d45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562371459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1562371459
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4010550585
Short name T1232
Test name
Test status
Simulation time 22793875 ps
CPU time 0.66 seconds
Started Aug 18 04:44:31 PM PDT 24
Finished Aug 18 04:44:31 PM PDT 24
Peak memory 196304 kb
Host smart-9aefa25c-5d92-4ec4-ab81-658b53e48130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010550585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4010550585
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2207857855
Short name T1224
Test name
Test status
Simulation time 117590921 ps
CPU time 1.58 seconds
Started Aug 18 04:44:36 PM PDT 24
Finished Aug 18 04:44:38 PM PDT 24
Peak memory 200248 kb
Host smart-1133fb06-3b9b-4680-92d6-27e32a333773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207857855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2207857855
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3409209259
Short name T70
Test name
Test status
Simulation time 160743801 ps
CPU time 1.3 seconds
Started Aug 18 04:44:28 PM PDT 24
Finished Aug 18 04:44:35 PM PDT 24
Peak memory 199312 kb
Host smart-99a0b65d-7d34-4ed5-b7ef-90e2ffa4d837
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409209259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3409209259
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3123547114
Short name T587
Test name
Test status
Simulation time 156880943342 ps
CPU time 63.89 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:58:25 PM PDT 24
Peak memory 200928 kb
Host smart-e6428b44-aca2-42b1-98bc-cb43d8ffa8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123547114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3123547114
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1692352944
Short name T150
Test name
Test status
Simulation time 27846639348 ps
CPU time 53.17 seconds
Started Aug 18 05:57:23 PM PDT 24
Finished Aug 18 05:58:16 PM PDT 24
Peak memory 200820 kb
Host smart-8c08ab7e-368b-4e0b-b854-1752b58cc75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692352944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1692352944
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1157433997
Short name T123
Test name
Test status
Simulation time 43799461210 ps
CPU time 59.66 seconds
Started Aug 18 05:57:20 PM PDT 24
Finished Aug 18 05:58:20 PM PDT 24
Peak memory 200844 kb
Host smart-0e052930-e437-402b-9b6a-3679076070b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157433997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1157433997
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1666405865
Short name T1155
Test name
Test status
Simulation time 142425268769 ps
CPU time 51.46 seconds
Started Aug 18 05:57:22 PM PDT 24
Finished Aug 18 05:58:13 PM PDT 24
Peak memory 200840 kb
Host smart-840ffb8f-95b6-4f8f-b66e-7e8e6dff9dad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666405865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1666405865
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2874785019
Short name T371
Test name
Test status
Simulation time 254959382287 ps
CPU time 181.2 seconds
Started Aug 18 05:57:33 PM PDT 24
Finished Aug 18 06:00:35 PM PDT 24
Peak memory 200808 kb
Host smart-1a2bded5-adc2-4f88-88fa-26dd6d65d706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2874785019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2874785019
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3834557609
Short name T1109
Test name
Test status
Simulation time 3524905394 ps
CPU time 2.83 seconds
Started Aug 18 05:57:30 PM PDT 24
Finished Aug 18 05:57:33 PM PDT 24
Peak memory 199372 kb
Host smart-57ab9791-b54a-4b03-910d-c07b97b66471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834557609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3834557609
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3868770023
Short name T659
Test name
Test status
Simulation time 136504920705 ps
CPU time 53.01 seconds
Started Aug 18 05:57:24 PM PDT 24
Finished Aug 18 05:58:17 PM PDT 24
Peak memory 198668 kb
Host smart-aaac2617-ddc3-401d-a280-f4fd0017f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868770023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3868770023
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3975897333
Short name T806
Test name
Test status
Simulation time 16405847371 ps
CPU time 175.08 seconds
Started Aug 18 05:57:30 PM PDT 24
Finished Aug 18 06:00:25 PM PDT 24
Peak memory 200824 kb
Host smart-2558aca4-b663-464b-8dab-fad1bef34d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975897333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3975897333
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1422176511
Short name T904
Test name
Test status
Simulation time 5980920161 ps
CPU time 10.22 seconds
Started Aug 18 05:57:25 PM PDT 24
Finished Aug 18 05:57:35 PM PDT 24
Peak memory 198868 kb
Host smart-a6f13288-c28c-48b0-9853-9adb5ff6d193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422176511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1422176511
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3682053163
Short name T1001
Test name
Test status
Simulation time 20324519054 ps
CPU time 17.79 seconds
Started Aug 18 05:57:26 PM PDT 24
Finished Aug 18 05:57:44 PM PDT 24
Peak memory 200916 kb
Host smart-12c9fb9a-f052-4ad3-a79e-a9bcc51d2bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682053163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3682053163
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1470711565
Short name T492
Test name
Test status
Simulation time 884463139 ps
CPU time 0.96 seconds
Started Aug 18 05:57:23 PM PDT 24
Finished Aug 18 05:57:24 PM PDT 24
Peak memory 196580 kb
Host smart-5df8931b-1f04-4742-b96b-dc9cc5c367d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470711565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1470711565
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2956731401
Short name T28
Test name
Test status
Simulation time 159000248 ps
CPU time 0.8 seconds
Started Aug 18 05:57:31 PM PDT 24
Finished Aug 18 05:57:31 PM PDT 24
Peak memory 219060 kb
Host smart-b124149b-04b8-4676-9ea7-e6c994bb9ac8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956731401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2956731401
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.3458477079
Short name T245
Test name
Test status
Simulation time 590019727 ps
CPU time 1.68 seconds
Started Aug 18 05:57:27 PM PDT 24
Finished Aug 18 05:57:29 PM PDT 24
Peak memory 199972 kb
Host smart-d9218071-c3f4-42c2-8722-64de0dca8c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458477079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3458477079
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3323143611
Short name T1122
Test name
Test status
Simulation time 63281629882 ps
CPU time 175.82 seconds
Started Aug 18 05:57:29 PM PDT 24
Finished Aug 18 06:00:25 PM PDT 24
Peak memory 201004 kb
Host smart-9c91507c-4ae2-4658-9cd7-c59a94ccefaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323143611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3323143611
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.479000689
Short name T1079
Test name
Test status
Simulation time 7761397794 ps
CPU time 43.27 seconds
Started Aug 18 05:57:30 PM PDT 24
Finished Aug 18 05:58:13 PM PDT 24
Peak memory 217536 kb
Host smart-df8c85a4-e137-4947-8eb7-7522e473d50d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479000689 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.479000689
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3851202286
Short name T255
Test name
Test status
Simulation time 1430873591 ps
CPU time 3.26 seconds
Started Aug 18 05:57:30 PM PDT 24
Finished Aug 18 05:57:33 PM PDT 24
Peak memory 199644 kb
Host smart-111673c6-ffa8-4c0e-aa70-4251b65eaea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851202286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3851202286
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2805015095
Short name T955
Test name
Test status
Simulation time 52069060200 ps
CPU time 65.15 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:58:27 PM PDT 24
Peak memory 200916 kb
Host smart-c00835e3-9e23-4d25-9d8a-332016c6ab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805015095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2805015095
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1984587028
Short name T1054
Test name
Test status
Simulation time 20336105 ps
CPU time 0.56 seconds
Started Aug 18 05:57:39 PM PDT 24
Finished Aug 18 05:57:40 PM PDT 24
Peak memory 196188 kb
Host smart-6a363e52-8045-4b41-bc8e-6ab44da6694e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984587028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1984587028
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2684889530
Short name T624
Test name
Test status
Simulation time 14405609441 ps
CPU time 27.21 seconds
Started Aug 18 05:57:31 PM PDT 24
Finished Aug 18 05:57:58 PM PDT 24
Peak memory 200928 kb
Host smart-441ab7f7-e83b-45f0-8e77-4b42a36a04a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684889530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2684889530
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2910089929
Short name T585
Test name
Test status
Simulation time 104273456760 ps
CPU time 29.34 seconds
Started Aug 18 05:57:30 PM PDT 24
Finished Aug 18 05:57:59 PM PDT 24
Peak memory 200804 kb
Host smart-428fcb44-2a3f-4812-8dc4-603bd761aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910089929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2910089929
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1591233880
Short name T453
Test name
Test status
Simulation time 22466161202 ps
CPU time 19.96 seconds
Started Aug 18 05:57:33 PM PDT 24
Finished Aug 18 05:57:53 PM PDT 24
Peak memory 198684 kb
Host smart-911c99a6-5d5d-415f-b955-7b1c5c458bd1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591233880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1591233880
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2591459798
Short name T352
Test name
Test status
Simulation time 53125835284 ps
CPU time 46.91 seconds
Started Aug 18 05:57:30 PM PDT 24
Finished Aug 18 05:58:17 PM PDT 24
Peak memory 200824 kb
Host smart-eb64964b-a591-416b-a0fb-3e03687aedd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591459798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2591459798
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1712091644
Short name T978
Test name
Test status
Simulation time 10539164546 ps
CPU time 19.14 seconds
Started Aug 18 05:57:31 PM PDT 24
Finished Aug 18 05:57:51 PM PDT 24
Peak memory 199276 kb
Host smart-0a63f2f9-9b66-4c20-b7b7-ef63faed226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712091644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1712091644
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1539577276
Short name T1127
Test name
Test status
Simulation time 168987068285 ps
CPU time 372.51 seconds
Started Aug 18 05:57:33 PM PDT 24
Finished Aug 18 06:03:45 PM PDT 24
Peak memory 201016 kb
Host smart-a63094b2-43ef-42be-8c0f-f6e60902dccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539577276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1539577276
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3830540114
Short name T494
Test name
Test status
Simulation time 14669366605 ps
CPU time 416.1 seconds
Started Aug 18 05:57:28 PM PDT 24
Finished Aug 18 06:04:24 PM PDT 24
Peak memory 200872 kb
Host smart-9df475aa-7fee-4933-9328-940839f25cec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830540114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3830540114
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3886481233
Short name T398
Test name
Test status
Simulation time 4545272735 ps
CPU time 22.02 seconds
Started Aug 18 05:57:33 PM PDT 24
Finished Aug 18 05:57:55 PM PDT 24
Peak memory 200176 kb
Host smart-db76169c-cc9a-4b29-a3c4-bfd8b9c7251c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886481233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3886481233
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2374409958
Short name T958
Test name
Test status
Simulation time 82941322460 ps
CPU time 71.48 seconds
Started Aug 18 05:57:30 PM PDT 24
Finished Aug 18 05:58:42 PM PDT 24
Peak memory 200872 kb
Host smart-b2a59002-de39-4daa-b681-89409ec84748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374409958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2374409958
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3876187791
Short name T734
Test name
Test status
Simulation time 33237705834 ps
CPU time 26.83 seconds
Started Aug 18 05:57:28 PM PDT 24
Finished Aug 18 05:57:55 PM PDT 24
Peak memory 196828 kb
Host smart-2ca4cc12-463c-4a9f-b332-e075565fc9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876187791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3876187791
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.183423533
Short name T77
Test name
Test status
Simulation time 223601997 ps
CPU time 0.86 seconds
Started Aug 18 05:57:31 PM PDT 24
Finished Aug 18 05:57:32 PM PDT 24
Peak memory 219100 kb
Host smart-ccc2978d-9627-4b85-a622-95dea5f31be0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183423533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.183423533
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2724108812
Short name T355
Test name
Test status
Simulation time 500506108 ps
CPU time 1.55 seconds
Started Aug 18 05:57:33 PM PDT 24
Finished Aug 18 05:57:35 PM PDT 24
Peak memory 199140 kb
Host smart-55a725f1-6720-403f-a44f-6208cdf48f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724108812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2724108812
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3752629819
Short name T1080
Test name
Test status
Simulation time 224980039387 ps
CPU time 1230.83 seconds
Started Aug 18 05:57:28 PM PDT 24
Finished Aug 18 06:17:59 PM PDT 24
Peak memory 200872 kb
Host smart-b5c99a42-8c84-45ed-bcb3-0d59aa988891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752629819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3752629819
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.659950422
Short name T893
Test name
Test status
Simulation time 16585972049 ps
CPU time 51.03 seconds
Started Aug 18 05:57:33 PM PDT 24
Finished Aug 18 05:58:24 PM PDT 24
Peak memory 217448 kb
Host smart-8a5f50c0-0de1-46a2-9be1-a79bc168cc7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659950422 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.659950422
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.472917047
Short name T581
Test name
Test status
Simulation time 6445681829 ps
CPU time 21.06 seconds
Started Aug 18 05:57:33 PM PDT 24
Finished Aug 18 05:57:54 PM PDT 24
Peak memory 200188 kb
Host smart-fda64b7f-6b05-4c79-a95c-082d7e4b5141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472917047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.472917047
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.274860466
Short name T982
Test name
Test status
Simulation time 15960857389 ps
CPU time 6.49 seconds
Started Aug 18 05:57:31 PM PDT 24
Finished Aug 18 05:57:38 PM PDT 24
Peak memory 200828 kb
Host smart-9f09d293-4bed-4d1c-9089-93118175800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274860466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.274860466
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2987868802
Short name T25
Test name
Test status
Simulation time 21898832 ps
CPU time 0.54 seconds
Started Aug 18 05:58:09 PM PDT 24
Finished Aug 18 05:58:09 PM PDT 24
Peak memory 196240 kb
Host smart-65be17ed-ecf2-459d-839e-3076490c0f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987868802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2987868802
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1697632314
Short name T116
Test name
Test status
Simulation time 76553885060 ps
CPU time 50.44 seconds
Started Aug 18 05:58:03 PM PDT 24
Finished Aug 18 05:58:54 PM PDT 24
Peak memory 200860 kb
Host smart-e5bf7c87-fd47-4b9e-b54a-a66028c0045a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697632314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1697632314
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.699627076
Short name T266
Test name
Test status
Simulation time 102591244573 ps
CPU time 44.9 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:58:45 PM PDT 24
Peak memory 200824 kb
Host smart-1d0b6b16-650b-42ee-83d9-4dfec941f094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699627076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.699627076
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1358971036
Short name T793
Test name
Test status
Simulation time 22646030630 ps
CPU time 37.07 seconds
Started Aug 18 05:58:19 PM PDT 24
Finished Aug 18 05:58:56 PM PDT 24
Peak memory 200924 kb
Host smart-7909fac1-7499-495a-81bf-d1e40b082406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358971036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1358971036
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1045029231
Short name T373
Test name
Test status
Simulation time 89439130083 ps
CPU time 199.1 seconds
Started Aug 18 05:58:20 PM PDT 24
Finished Aug 18 06:01:39 PM PDT 24
Peak memory 200932 kb
Host smart-748ae8a5-8eec-4dff-82a3-40384a68e0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1045029231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1045029231
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1278466669
Short name T19
Test name
Test status
Simulation time 5271825897 ps
CPU time 2.94 seconds
Started Aug 18 05:58:17 PM PDT 24
Finished Aug 18 05:58:20 PM PDT 24
Peak memory 200752 kb
Host smart-f9f23b9c-739a-4e8b-a577-d3abdcd2f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278466669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1278466669
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2515000103
Short name T725
Test name
Test status
Simulation time 27642794647 ps
CPU time 41.33 seconds
Started Aug 18 05:58:20 PM PDT 24
Finished Aug 18 05:59:02 PM PDT 24
Peak memory 200352 kb
Host smart-05de0dfa-d509-42f5-8a2a-3cb2c43e41fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515000103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2515000103
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1993689080
Short name T240
Test name
Test status
Simulation time 8274841931 ps
CPU time 381.96 seconds
Started Aug 18 05:58:19 PM PDT 24
Finished Aug 18 06:04:41 PM PDT 24
Peak memory 200948 kb
Host smart-dcb48504-91c1-4efc-b331-6e01f0629ede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993689080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1993689080
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3510348937
Short name T1056
Test name
Test status
Simulation time 2985629733 ps
CPU time 5.67 seconds
Started Aug 18 05:58:19 PM PDT 24
Finished Aug 18 05:58:24 PM PDT 24
Peak memory 199344 kb
Host smart-9093d64f-08c6-4eb4-86e8-0d3d82e1bf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510348937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3510348937
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2768847774
Short name T326
Test name
Test status
Simulation time 20157462866 ps
CPU time 29.48 seconds
Started Aug 18 05:58:21 PM PDT 24
Finished Aug 18 05:58:50 PM PDT 24
Peak memory 200688 kb
Host smart-94cd66bc-fc26-40c1-b5ff-c3da97d54e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768847774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2768847774
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1985187010
Short name T756
Test name
Test status
Simulation time 3500911883 ps
CPU time 3.34 seconds
Started Aug 18 05:58:09 PM PDT 24
Finished Aug 18 05:58:13 PM PDT 24
Peak memory 197428 kb
Host smart-2f350cc5-ec9a-45a5-8638-aadac79c19c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985187010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1985187010
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2035223896
Short name T952
Test name
Test status
Simulation time 449421051 ps
CPU time 2.14 seconds
Started Aug 18 05:58:02 PM PDT 24
Finished Aug 18 05:58:05 PM PDT 24
Peak memory 199716 kb
Host smart-45060f71-cee5-4dd8-95ad-b74c90d98033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035223896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2035223896
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2489029320
Short name T757
Test name
Test status
Simulation time 194703576483 ps
CPU time 1429.68 seconds
Started Aug 18 05:58:09 PM PDT 24
Finished Aug 18 06:21:58 PM PDT 24
Peak memory 200932 kb
Host smart-04f1512c-71f5-430e-9dbb-93312c86f103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489029320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2489029320
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2390312242
Short name T1007
Test name
Test status
Simulation time 5736062267 ps
CPU time 13.83 seconds
Started Aug 18 05:58:20 PM PDT 24
Finished Aug 18 05:58:34 PM PDT 24
Peak memory 200952 kb
Host smart-e9e1459f-ee9d-4517-a9fc-1ff5bc402f33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390312242 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2390312242
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3147940505
Short name T513
Test name
Test status
Simulation time 1289967538 ps
CPU time 3.5 seconds
Started Aug 18 05:58:21 PM PDT 24
Finished Aug 18 05:58:24 PM PDT 24
Peak memory 199284 kb
Host smart-ef86f550-b1b0-4881-9669-7e2d85171295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147940505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3147940505
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1172099407
Short name T497
Test name
Test status
Simulation time 583410451375 ps
CPU time 73.5 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:59:15 PM PDT 24
Peak memory 200936 kb
Host smart-c709f53a-e0ad-4cc9-ad91-8d1f0428a2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172099407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1172099407
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.228980491
Short name T911
Test name
Test status
Simulation time 71434196890 ps
CPU time 53.12 seconds
Started Aug 18 06:02:16 PM PDT 24
Finished Aug 18 06:03:10 PM PDT 24
Peak memory 200884 kb
Host smart-ae316a13-7ee9-468e-b1d0-8472889bbe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228980491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.228980491
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2369978834
Short name T328
Test name
Test status
Simulation time 142495324014 ps
CPU time 25.87 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:43 PM PDT 24
Peak memory 200880 kb
Host smart-483bed44-05cf-4a86-a83c-3458761c1bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369978834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2369978834
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2781417398
Short name T399
Test name
Test status
Simulation time 15611013564 ps
CPU time 22.67 seconds
Started Aug 18 06:02:18 PM PDT 24
Finished Aug 18 06:02:41 PM PDT 24
Peak memory 200856 kb
Host smart-727b198b-2887-488b-aefc-08bf0abc9f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781417398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2781417398
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.677783084
Short name T1102
Test name
Test status
Simulation time 51216000873 ps
CPU time 22.99 seconds
Started Aug 18 06:02:21 PM PDT 24
Finished Aug 18 06:02:44 PM PDT 24
Peak memory 200928 kb
Host smart-d2b21476-deca-4479-8d37-962f71af462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677783084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.677783084
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.606271612
Short name T675
Test name
Test status
Simulation time 60284818377 ps
CPU time 142.52 seconds
Started Aug 18 06:02:16 PM PDT 24
Finished Aug 18 06:04:39 PM PDT 24
Peak memory 200868 kb
Host smart-fd31728e-9c9e-4152-9aff-40b5dcaef6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606271612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.606271612
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.955945341
Short name T229
Test name
Test status
Simulation time 28831457894 ps
CPU time 46.43 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:03:04 PM PDT 24
Peak memory 200940 kb
Host smart-8aaf7dfa-1280-43d0-bdf9-986f94eeba4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955945341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.955945341
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3768609670
Short name T844
Test name
Test status
Simulation time 109867420220 ps
CPU time 43.3 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:03:00 PM PDT 24
Peak memory 200924 kb
Host smart-ad0c6e54-34e6-426c-8fb7-9df2976b474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768609670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3768609670
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.4089975266
Short name T233
Test name
Test status
Simulation time 88034189727 ps
CPU time 36.8 seconds
Started Aug 18 06:02:18 PM PDT 24
Finished Aug 18 06:02:54 PM PDT 24
Peak memory 200924 kb
Host smart-c746af3c-7a0c-4fe8-959d-dd9ea93e1df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089975266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.4089975266
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3987069942
Short name T208
Test name
Test status
Simulation time 112254073749 ps
CPU time 161.28 seconds
Started Aug 18 06:02:18 PM PDT 24
Finished Aug 18 06:05:00 PM PDT 24
Peak memory 200816 kb
Host smart-ed9ce981-8261-4cf2-9b38-cafe8846e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987069942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3987069942
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4200802306
Short name T614
Test name
Test status
Simulation time 14046222 ps
CPU time 0.59 seconds
Started Aug 18 05:58:24 PM PDT 24
Finished Aug 18 05:58:25 PM PDT 24
Peak memory 196112 kb
Host smart-d1269771-be70-451b-a9b7-e61e011bf49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200802306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4200802306
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1253003402
Short name T804
Test name
Test status
Simulation time 168017484146 ps
CPU time 67.1 seconds
Started Aug 18 05:58:08 PM PDT 24
Finished Aug 18 05:59:16 PM PDT 24
Peak memory 200928 kb
Host smart-0eda153e-f8d8-4ffc-ba58-d4c73ca9dabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253003402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1253003402
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.627366786
Short name T1143
Test name
Test status
Simulation time 134990107949 ps
CPU time 144.24 seconds
Started Aug 18 05:58:08 PM PDT 24
Finished Aug 18 06:00:33 PM PDT 24
Peak memory 200896 kb
Host smart-9dba3a12-1305-4601-b212-6df8c0251e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627366786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.627366786
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1345191521
Short name T814
Test name
Test status
Simulation time 46274615201 ps
CPU time 20.87 seconds
Started Aug 18 05:58:27 PM PDT 24
Finished Aug 18 05:58:48 PM PDT 24
Peak memory 200944 kb
Host smart-eadf810f-ea34-4843-a791-21a4105bf619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345191521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1345191521
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.4069297440
Short name T236
Test name
Test status
Simulation time 526488907704 ps
CPU time 964.64 seconds
Started Aug 18 05:58:19 PM PDT 24
Finished Aug 18 06:14:24 PM PDT 24
Peak memory 200828 kb
Host smart-790db200-36e8-4797-86c8-82ec6c124697
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069297440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.4069297440
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.355056570
Short name T830
Test name
Test status
Simulation time 278145631304 ps
CPU time 317.16 seconds
Started Aug 18 05:58:26 PM PDT 24
Finished Aug 18 06:03:44 PM PDT 24
Peak memory 200936 kb
Host smart-808a260c-c80e-4959-b6ea-2eb48d284cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355056570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.355056570
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2444494084
Short name T865
Test name
Test status
Simulation time 1082933908 ps
CPU time 1.08 seconds
Started Aug 18 05:58:26 PM PDT 24
Finished Aug 18 05:58:27 PM PDT 24
Peak memory 196212 kb
Host smart-e73718b9-1435-4995-8792-b29ddb3759fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444494084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2444494084
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2746516280
Short name T333
Test name
Test status
Simulation time 147709385500 ps
CPU time 57.85 seconds
Started Aug 18 05:58:19 PM PDT 24
Finished Aug 18 05:59:17 PM PDT 24
Peak memory 201004 kb
Host smart-14ebb95b-6fdd-4eb6-9d75-794aedcfd3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746516280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2746516280
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2280607208
Short name T480
Test name
Test status
Simulation time 7443181022 ps
CPU time 365.76 seconds
Started Aug 18 05:58:26 PM PDT 24
Finished Aug 18 06:04:32 PM PDT 24
Peak memory 200756 kb
Host smart-b270afec-5c22-4e7f-9813-bcbdc495406f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280607208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2280607208
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3622426453
Short name T851
Test name
Test status
Simulation time 6357754996 ps
CPU time 26.75 seconds
Started Aug 18 05:58:24 PM PDT 24
Finished Aug 18 05:58:51 PM PDT 24
Peak memory 200092 kb
Host smart-7b26d58e-05e4-4528-a498-26d6a49c6ea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622426453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3622426453
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.385498383
Short name T334
Test name
Test status
Simulation time 14341099208 ps
CPU time 16.11 seconds
Started Aug 18 05:58:24 PM PDT 24
Finished Aug 18 05:58:40 PM PDT 24
Peak memory 200620 kb
Host smart-4d9d1219-fe60-4628-a918-2b42321f0c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385498383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.385498383
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1978284153
Short name T1032
Test name
Test status
Simulation time 47085195349 ps
CPU time 12.02 seconds
Started Aug 18 05:58:20 PM PDT 24
Finished Aug 18 05:58:33 PM PDT 24
Peak memory 197036 kb
Host smart-16dfb6de-ad91-4a71-9376-fe55fa1619c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978284153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1978284153
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.4284976460
Short name T620
Test name
Test status
Simulation time 554712999 ps
CPU time 2.16 seconds
Started Aug 18 05:58:08 PM PDT 24
Finished Aug 18 05:58:11 PM PDT 24
Peak memory 200784 kb
Host smart-cd749864-4830-44fa-be07-736c6735efa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284976460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4284976460
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3593765519
Short name T896
Test name
Test status
Simulation time 569961302911 ps
CPU time 905.45 seconds
Started Aug 18 05:58:18 PM PDT 24
Finished Aug 18 06:13:24 PM PDT 24
Peak memory 200856 kb
Host smart-86c777d3-b6cc-4270-9829-f5a6db589f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593765519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3593765519
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.4143148279
Short name T1115
Test name
Test status
Simulation time 4706622228 ps
CPU time 55.68 seconds
Started Aug 18 05:58:18 PM PDT 24
Finished Aug 18 05:59:14 PM PDT 24
Peak memory 216912 kb
Host smart-8872a62f-2925-4958-8842-c628222c7301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143148279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.4143148279
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.227369111
Short name T295
Test name
Test status
Simulation time 892592694 ps
CPU time 2.62 seconds
Started Aug 18 05:58:18 PM PDT 24
Finished Aug 18 05:58:20 PM PDT 24
Peak memory 199280 kb
Host smart-ba2f71af-0459-4334-9283-48ecd14c226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227369111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.227369111
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1683381835
Short name T409
Test name
Test status
Simulation time 64336527614 ps
CPU time 151.56 seconds
Started Aug 18 05:58:09 PM PDT 24
Finished Aug 18 06:00:41 PM PDT 24
Peak memory 200928 kb
Host smart-d12550aa-1aa6-4839-8820-9f2658fd79df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683381835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1683381835
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2780805241
Short name T1012
Test name
Test status
Simulation time 10024869203 ps
CPU time 13.14 seconds
Started Aug 18 06:02:20 PM PDT 24
Finished Aug 18 06:02:33 PM PDT 24
Peak memory 200856 kb
Host smart-5eda3982-26b1-4947-958d-843ccbff9a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780805241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2780805241
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3598794786
Short name T812
Test name
Test status
Simulation time 6131341420 ps
CPU time 9.99 seconds
Started Aug 18 06:02:19 PM PDT 24
Finished Aug 18 06:02:30 PM PDT 24
Peak memory 200556 kb
Host smart-70ff7f7d-9556-4911-8123-65e68691b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598794786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3598794786
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4340963
Short name T779
Test name
Test status
Simulation time 61236284651 ps
CPU time 43.49 seconds
Started Aug 18 06:02:18 PM PDT 24
Finished Aug 18 06:03:01 PM PDT 24
Peak memory 200924 kb
Host smart-794f715f-3963-4db2-a9ec-f497d15e4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4340963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4340963
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1991349181
Short name T1174
Test name
Test status
Simulation time 17184451213 ps
CPU time 20.96 seconds
Started Aug 18 06:02:18 PM PDT 24
Finished Aug 18 06:02:39 PM PDT 24
Peak memory 200792 kb
Host smart-491e8a42-3e83-456a-b5c2-b5d6d86247c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991349181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1991349181
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.610301550
Short name T903
Test name
Test status
Simulation time 24539520152 ps
CPU time 42.14 seconds
Started Aug 18 06:02:20 PM PDT 24
Finished Aug 18 06:03:02 PM PDT 24
Peak memory 200900 kb
Host smart-c45685c3-eb09-42e2-b9e1-635e4b22f117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610301550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.610301550
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1603027875
Short name T1026
Test name
Test status
Simulation time 8151394943 ps
CPU time 14.31 seconds
Started Aug 18 06:02:21 PM PDT 24
Finished Aug 18 06:02:35 PM PDT 24
Peak memory 200936 kb
Host smart-a954f3aa-6504-42fa-97fe-6dedbe1da747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603027875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1603027875
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1779096458
Short name T760
Test name
Test status
Simulation time 161416101443 ps
CPU time 44.12 seconds
Started Aug 18 06:02:20 PM PDT 24
Finished Aug 18 06:03:05 PM PDT 24
Peak memory 200620 kb
Host smart-8ab5392a-589b-4f08-87b3-f26429f67f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779096458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1779096458
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.334607264
Short name T396
Test name
Test status
Simulation time 41029041 ps
CPU time 0.65 seconds
Started Aug 18 05:58:23 PM PDT 24
Finished Aug 18 05:58:24 PM PDT 24
Peak memory 196520 kb
Host smart-4e64b112-3e84-47da-90f5-8d91f1d1b3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334607264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.334607264
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1731285068
Short name T563
Test name
Test status
Simulation time 46174144836 ps
CPU time 69.29 seconds
Started Aug 18 05:58:19 PM PDT 24
Finished Aug 18 05:59:28 PM PDT 24
Peak memory 200900 kb
Host smart-02afeb4b-62b1-417c-9c9e-f0a4a18b27a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731285068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1731285068
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2418623441
Short name T64
Test name
Test status
Simulation time 26449501768 ps
CPU time 45.6 seconds
Started Aug 18 05:58:26 PM PDT 24
Finished Aug 18 05:59:12 PM PDT 24
Peak memory 200952 kb
Host smart-79ef53d1-a37f-4cf6-936a-4841e587f086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418623441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2418623441
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1280949484
Short name T778
Test name
Test status
Simulation time 79759807730 ps
CPU time 230.39 seconds
Started Aug 18 05:58:23 PM PDT 24
Finished Aug 18 06:02:14 PM PDT 24
Peak memory 200876 kb
Host smart-b5e73d64-a8dd-4ae8-9378-c3663431b2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280949484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1280949484
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2361760303
Short name T565
Test name
Test status
Simulation time 19891043541 ps
CPU time 10.95 seconds
Started Aug 18 05:58:26 PM PDT 24
Finished Aug 18 05:58:37 PM PDT 24
Peak memory 200860 kb
Host smart-2bc2d424-90d7-42e9-a841-78544f18c61a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361760303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2361760303
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3559962478
Short name T657
Test name
Test status
Simulation time 75734090847 ps
CPU time 241.79 seconds
Started Aug 18 05:58:24 PM PDT 24
Finished Aug 18 06:02:26 PM PDT 24
Peak memory 200752 kb
Host smart-8382f399-1fb2-4ec1-b38a-3de4e8656915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559962478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3559962478
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1404365735
Short name T404
Test name
Test status
Simulation time 2022206126 ps
CPU time 2.09 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 05:58:33 PM PDT 24
Peak memory 198284 kb
Host smart-bef0f020-2cca-4fa3-a1c1-33e51fed6220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404365735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1404365735
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3764792337
Short name T490
Test name
Test status
Simulation time 16847151317 ps
CPU time 12.45 seconds
Started Aug 18 05:58:25 PM PDT 24
Finished Aug 18 05:58:38 PM PDT 24
Peak memory 200852 kb
Host smart-214efac1-9009-4c2a-9ebf-ca45750002ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764792337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3764792337
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2910742840
Short name T38
Test name
Test status
Simulation time 7113409482 ps
CPU time 168.78 seconds
Started Aug 18 05:58:39 PM PDT 24
Finished Aug 18 06:01:28 PM PDT 24
Peak memory 200788 kb
Host smart-a90cb938-cc1b-4d16-854a-0870335bec8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910742840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2910742840
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1019749652
Short name T1164
Test name
Test status
Simulation time 3520146879 ps
CPU time 29.66 seconds
Started Aug 18 05:58:39 PM PDT 24
Finished Aug 18 05:59:09 PM PDT 24
Peak memory 200004 kb
Host smart-c7dc026d-ce31-41db-9872-e74c0e7ff399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019749652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1019749652
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1794693443
Short name T559
Test name
Test status
Simulation time 17541136005 ps
CPU time 24.02 seconds
Started Aug 18 05:58:40 PM PDT 24
Finished Aug 18 05:59:04 PM PDT 24
Peak memory 200764 kb
Host smart-d194ab11-a633-41df-8da2-248a94795f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794693443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1794693443
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.66290159
Short name T379
Test name
Test status
Simulation time 1977518385 ps
CPU time 3.58 seconds
Started Aug 18 05:58:24 PM PDT 24
Finished Aug 18 05:58:27 PM PDT 24
Peak memory 196360 kb
Host smart-073f70d7-8c0b-4529-b0d3-d300d561d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66290159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.66290159
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.145443153
Short name T981
Test name
Test status
Simulation time 674061896 ps
CPU time 2.09 seconds
Started Aug 18 05:58:20 PM PDT 24
Finished Aug 18 05:58:22 PM PDT 24
Peak memory 200412 kb
Host smart-870f1573-22db-42f2-9d27-0303d19f35f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145443153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.145443153
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1519522912
Short name T1151
Test name
Test status
Simulation time 21858329943 ps
CPU time 98.52 seconds
Started Aug 18 05:58:41 PM PDT 24
Finished Aug 18 06:00:19 PM PDT 24
Peak memory 216728 kb
Host smart-1fe5ce6e-0594-487b-846b-935fd18012b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519522912 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1519522912
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3437321814
Short name T823
Test name
Test status
Simulation time 2483159908 ps
CPU time 2.36 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 05:58:34 PM PDT 24
Peak memory 200944 kb
Host smart-a3ba5f95-5d5f-4828-9967-812519013dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437321814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3437321814
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4031785048
Short name T645
Test name
Test status
Simulation time 7663759646 ps
CPU time 13.19 seconds
Started Aug 18 05:58:19 PM PDT 24
Finished Aug 18 05:58:32 PM PDT 24
Peak memory 200924 kb
Host smart-fd5148e9-701c-4477-b3ac-39c69d45952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031785048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4031785048
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2455036509
Short name T12
Test name
Test status
Simulation time 127603706523 ps
CPU time 53.54 seconds
Started Aug 18 06:02:21 PM PDT 24
Finished Aug 18 06:03:14 PM PDT 24
Peak memory 200920 kb
Host smart-3fac3045-2405-4a6a-8024-1b6b98498fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455036509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2455036509
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.4046256562
Short name T172
Test name
Test status
Simulation time 141630248237 ps
CPU time 56.52 seconds
Started Aug 18 06:02:19 PM PDT 24
Finished Aug 18 06:03:16 PM PDT 24
Peak memory 200924 kb
Host smart-3520d433-5ae1-4d83-8abf-bc2b8ce4aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046256562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.4046256562
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.135586749
Short name T219
Test name
Test status
Simulation time 28156171669 ps
CPU time 23.67 seconds
Started Aug 18 06:02:19 PM PDT 24
Finished Aug 18 06:02:42 PM PDT 24
Peak memory 200828 kb
Host smart-35fea3f0-181d-4631-ac2c-760585f36fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135586749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.135586749
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3688155098
Short name T908
Test name
Test status
Simulation time 65606211696 ps
CPU time 14.13 seconds
Started Aug 18 06:02:18 PM PDT 24
Finished Aug 18 06:02:32 PM PDT 24
Peak memory 200940 kb
Host smart-72792384-5a22-442a-954a-5517a5551298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688155098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3688155098
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1518766909
Short name T856
Test name
Test status
Simulation time 20153099391 ps
CPU time 31.71 seconds
Started Aug 18 06:02:28 PM PDT 24
Finished Aug 18 06:03:00 PM PDT 24
Peak memory 200716 kb
Host smart-f63143f6-692d-4149-a479-0a6a589e9190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518766909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1518766909
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3558991918
Short name T178
Test name
Test status
Simulation time 72244691868 ps
CPU time 199.41 seconds
Started Aug 18 06:02:27 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 200848 kb
Host smart-3e59cba4-6ac9-4e7b-850e-9dbb26ea6a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558991918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3558991918
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1509994210
Short name T458
Test name
Test status
Simulation time 14338606027 ps
CPU time 22.92 seconds
Started Aug 18 06:02:28 PM PDT 24
Finished Aug 18 06:02:51 PM PDT 24
Peak memory 200936 kb
Host smart-fe8b7a52-d281-4c46-9eb7-de2063da95ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509994210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1509994210
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.661965911
Short name T7
Test name
Test status
Simulation time 139473452727 ps
CPU time 248.95 seconds
Started Aug 18 06:02:27 PM PDT 24
Finished Aug 18 06:06:36 PM PDT 24
Peak memory 200872 kb
Host smart-16af65e4-4b10-4d5c-b64e-b80af161bcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661965911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.661965911
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2083801004
Short name T1037
Test name
Test status
Simulation time 35802645 ps
CPU time 0.57 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 05:58:33 PM PDT 24
Peak memory 196536 kb
Host smart-29a433d9-1e1c-4326-b97c-2835e0ab68af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083801004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2083801004
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1685970112
Short name T859
Test name
Test status
Simulation time 45376680923 ps
CPU time 59.1 seconds
Started Aug 18 05:58:41 PM PDT 24
Finished Aug 18 05:59:40 PM PDT 24
Peak memory 200152 kb
Host smart-8441d65f-e8f6-452e-b5b3-c74523df7edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685970112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1685970112
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.4070654568
Short name T564
Test name
Test status
Simulation time 75665541770 ps
CPU time 148.25 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 06:00:59 PM PDT 24
Peak memory 200892 kb
Host smart-cae4eee1-a82d-443d-bce3-6942cd8e83f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070654568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.4070654568
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2921865484
Short name T332
Test name
Test status
Simulation time 9431564293 ps
CPU time 16.91 seconds
Started Aug 18 05:58:41 PM PDT 24
Finished Aug 18 05:58:58 PM PDT 24
Peak memory 200084 kb
Host smart-576e5fe9-d874-437d-9759-ec2bf9087971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921865484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2921865484
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2169668051
Short name T1050
Test name
Test status
Simulation time 15913553498 ps
CPU time 21.67 seconds
Started Aug 18 05:58:40 PM PDT 24
Finished Aug 18 05:59:01 PM PDT 24
Peak memory 198148 kb
Host smart-d67124ed-a351-4959-829e-9120fbc69d09
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169668051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2169668051
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1170716180
Short name T423
Test name
Test status
Simulation time 56519109406 ps
CPU time 244.84 seconds
Started Aug 18 05:58:35 PM PDT 24
Finished Aug 18 06:02:40 PM PDT 24
Peak memory 200816 kb
Host smart-de14cf02-73e3-4699-93b4-dd077d845f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170716180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1170716180
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3473564880
Short name T704
Test name
Test status
Simulation time 7932594578 ps
CPU time 7.91 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 05:58:41 PM PDT 24
Peak memory 200816 kb
Host smart-e9b546ce-8d95-4586-a2a5-f262916f2953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473564880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3473564880
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1014969171
Short name T828
Test name
Test status
Simulation time 114899690324 ps
CPU time 257.89 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 06:02:50 PM PDT 24
Peak memory 209248 kb
Host smart-54fcf9a6-7cf0-4c14-858d-a9f954cb42a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014969171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1014969171
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2713837606
Short name T873
Test name
Test status
Simulation time 15691447278 ps
CPU time 194.49 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 06:01:46 PM PDT 24
Peak memory 200932 kb
Host smart-ecd019a7-b218-46b9-8ff0-19df65b68dec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713837606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2713837606
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1605021388
Short name T1120
Test name
Test status
Simulation time 3783744412 ps
CPU time 7.17 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 05:58:38 PM PDT 24
Peak memory 199048 kb
Host smart-98ca68ad-76ee-410c-b291-98ef7e394f6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605021388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1605021388
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1562082395
Short name T482
Test name
Test status
Simulation time 4307017655 ps
CPU time 2.27 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 05:58:34 PM PDT 24
Peak memory 196940 kb
Host smart-b55883ff-6b2d-4714-bcd6-1d9fa1dda8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562082395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1562082395
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3185379565
Short name T895
Test name
Test status
Simulation time 5954042016 ps
CPU time 17.76 seconds
Started Aug 18 05:58:24 PM PDT 24
Finished Aug 18 05:58:42 PM PDT 24
Peak memory 200848 kb
Host smart-aa780402-6bed-4ead-a724-b4d8fccd4632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185379565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3185379565
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.682362128
Short name T969
Test name
Test status
Simulation time 389619231222 ps
CPU time 881.11 seconds
Started Aug 18 05:58:34 PM PDT 24
Finished Aug 18 06:13:15 PM PDT 24
Peak memory 200944 kb
Host smart-6356533e-86c5-443c-974a-cfa97b95c9af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682362128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.682362128
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.392875576
Short name T447
Test name
Test status
Simulation time 622056229 ps
CPU time 1.17 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 05:58:35 PM PDT 24
Peak memory 199396 kb
Host smart-0f14f306-5913-4807-bc27-f07d6332fc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392875576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.392875576
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.242158726
Short name T1028
Test name
Test status
Simulation time 63396205554 ps
CPU time 53.08 seconds
Started Aug 18 05:58:40 PM PDT 24
Finished Aug 18 05:59:33 PM PDT 24
Peak memory 200816 kb
Host smart-7d3003fc-67d4-4653-8e48-d0ca81dce1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242158726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.242158726
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2048069688
Short name T1002
Test name
Test status
Simulation time 37156809894 ps
CPU time 55.48 seconds
Started Aug 18 06:02:27 PM PDT 24
Finished Aug 18 06:03:22 PM PDT 24
Peak memory 200660 kb
Host smart-d0e275b0-2ed3-423b-96b0-4e119b89ca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048069688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2048069688
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1614808213
Short name T329
Test name
Test status
Simulation time 87998559604 ps
CPU time 69.08 seconds
Started Aug 18 06:02:26 PM PDT 24
Finished Aug 18 06:03:35 PM PDT 24
Peak memory 200884 kb
Host smart-7065c82f-183c-442d-b4bf-30cdf05c92dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614808213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1614808213
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2702373473
Short name T381
Test name
Test status
Simulation time 16144544217 ps
CPU time 30.77 seconds
Started Aug 18 06:02:27 PM PDT 24
Finished Aug 18 06:02:58 PM PDT 24
Peak memory 200820 kb
Host smart-f982c1fd-da77-465c-9744-a4735e15f840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702373473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2702373473
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.542717864
Short name T114
Test name
Test status
Simulation time 75047167031 ps
CPU time 109.84 seconds
Started Aug 18 06:02:30 PM PDT 24
Finished Aug 18 06:04:20 PM PDT 24
Peak memory 200876 kb
Host smart-989a1a2e-7b94-44be-a9bf-1f220b368b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542717864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.542717864
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3634043016
Short name T560
Test name
Test status
Simulation time 20213380141 ps
CPU time 29.53 seconds
Started Aug 18 06:02:27 PM PDT 24
Finished Aug 18 06:02:56 PM PDT 24
Peak memory 200908 kb
Host smart-7e2a8590-9820-4154-83d1-9a7df72030da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634043016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3634043016
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3274668297
Short name T878
Test name
Test status
Simulation time 148070083878 ps
CPU time 98.3 seconds
Started Aug 18 06:02:31 PM PDT 24
Finished Aug 18 06:04:09 PM PDT 24
Peak memory 200916 kb
Host smart-d2ffb673-38cb-4cd8-af2f-5770e08f9d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274668297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3274668297
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.832943355
Short name T210
Test name
Test status
Simulation time 31917442875 ps
CPU time 70.44 seconds
Started Aug 18 06:02:27 PM PDT 24
Finished Aug 18 06:03:37 PM PDT 24
Peak memory 200908 kb
Host smart-bc6cb380-e0ac-4514-85e6-946b4f46c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832943355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.832943355
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2232091458
Short name T698
Test name
Test status
Simulation time 29283870 ps
CPU time 0.57 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 05:58:32 PM PDT 24
Peak memory 196228 kb
Host smart-87e6af99-b2ab-4fca-870e-6705e261dc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232091458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2232091458
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1411406800
Short name T973
Test name
Test status
Simulation time 21074746632 ps
CPU time 17.77 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 05:58:51 PM PDT 24
Peak memory 200872 kb
Host smart-d7cace89-1123-4dbf-8343-0a4589b72c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411406800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1411406800
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_intr.2922271500
Short name T1046
Test name
Test status
Simulation time 20396341685 ps
CPU time 10.93 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 05:58:42 PM PDT 24
Peak memory 200948 kb
Host smart-6d382b77-7f83-41f1-b3d8-4a386e776f67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922271500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2922271500
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3232484447
Short name T1099
Test name
Test status
Simulation time 58124613061 ps
CPU time 476.66 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 06:06:28 PM PDT 24
Peak memory 200940 kb
Host smart-6b46d2b8-f268-46cc-aac0-81a08be386e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232484447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3232484447
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1410846682
Short name T389
Test name
Test status
Simulation time 5882436304 ps
CPU time 6.26 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 05:58:38 PM PDT 24
Peak memory 200048 kb
Host smart-243c7a15-68fc-4cfc-a4d1-a76db70eeed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410846682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1410846682
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1778539986
Short name T688
Test name
Test status
Simulation time 51477974950 ps
CPU time 87.95 seconds
Started Aug 18 05:58:30 PM PDT 24
Finished Aug 18 05:59:58 PM PDT 24
Peak memory 201124 kb
Host smart-0edfd4de-5d97-4112-b630-8e17d4b14da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778539986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1778539986
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.398001711
Short name T912
Test name
Test status
Simulation time 10500189736 ps
CPU time 155.21 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 06:01:08 PM PDT 24
Peak memory 200928 kb
Host smart-cc902c32-a568-4cd7-bb46-bd99c4c8893a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398001711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.398001711
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.4030415947
Short name T679
Test name
Test status
Simulation time 7275281132 ps
CPU time 14.48 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 05:58:48 PM PDT 24
Peak memory 198724 kb
Host smart-e83e9bbb-cc7b-4b9b-807a-cdca566b1ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030415947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4030415947
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3404740294
Short name T644
Test name
Test status
Simulation time 69534603151 ps
CPU time 23.15 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 05:58:55 PM PDT 24
Peak memory 200908 kb
Host smart-8dfdc10f-dd68-4477-9065-e9c3eac3d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404740294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3404740294
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1009296611
Short name T909
Test name
Test status
Simulation time 2776081906 ps
CPU time 1.54 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 05:58:35 PM PDT 24
Peak memory 196920 kb
Host smart-1ebf1c0a-f4fa-4503-8744-93420576259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009296611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1009296611
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.783430857
Short name T511
Test name
Test status
Simulation time 719235895 ps
CPU time 2.21 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 05:58:33 PM PDT 24
Peak memory 200740 kb
Host smart-7e0b581e-8eef-4ac2-888f-f4118f85aefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783430857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.783430857
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2453404521
Short name T1144
Test name
Test status
Simulation time 273496807017 ps
CPU time 333.2 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 06:04:06 PM PDT 24
Peak memory 200928 kb
Host smart-97b6f9ba-ce2a-4e74-b919-520a6c0241cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453404521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2453404521
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3759051981
Short name T433
Test name
Test status
Simulation time 1976725712 ps
CPU time 8.65 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 05:58:41 PM PDT 24
Peak memory 200924 kb
Host smart-ac402c5b-89bf-419d-add5-af333d6ecb88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759051981 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3759051981
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2513325656
Short name T384
Test name
Test status
Simulation time 1129160703 ps
CPU time 2.42 seconds
Started Aug 18 05:58:31 PM PDT 24
Finished Aug 18 05:58:34 PM PDT 24
Peak memory 199404 kb
Host smart-8bcf49ba-32ed-4259-abaf-93a415a24d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513325656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2513325656
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3288239578
Short name T923
Test name
Test status
Simulation time 30305879911 ps
CPU time 13.36 seconds
Started Aug 18 05:58:34 PM PDT 24
Finished Aug 18 05:58:47 PM PDT 24
Peak memory 200872 kb
Host smart-d65aac07-9bf1-43c0-bc70-078782f26aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288239578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3288239578
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3662366873
Short name T192
Test name
Test status
Simulation time 23599705752 ps
CPU time 41.23 seconds
Started Aug 18 06:02:25 PM PDT 24
Finished Aug 18 06:03:07 PM PDT 24
Peak memory 200944 kb
Host smart-7ad6aadb-0fa3-424b-950f-a1be0777be0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662366873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3662366873
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.156982250
Short name T204
Test name
Test status
Simulation time 134122959789 ps
CPU time 111.7 seconds
Started Aug 18 06:02:26 PM PDT 24
Finished Aug 18 06:04:18 PM PDT 24
Peak memory 200848 kb
Host smart-4f12cdba-6fdb-4bdb-a838-977ae1e26d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156982250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.156982250
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1553252480
Short name T188
Test name
Test status
Simulation time 69732500080 ps
CPU time 100.74 seconds
Started Aug 18 06:02:30 PM PDT 24
Finished Aug 18 06:04:11 PM PDT 24
Peak memory 201108 kb
Host smart-b74bf275-218b-4477-867d-b1e5d44491e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553252480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1553252480
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3158414363
Short name T661
Test name
Test status
Simulation time 146991806405 ps
CPU time 61.01 seconds
Started Aug 18 06:02:28 PM PDT 24
Finished Aug 18 06:03:29 PM PDT 24
Peak memory 200444 kb
Host smart-0b157ed8-1d37-40f1-8ef6-855dfe693127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158414363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3158414363
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2840353464
Short name T206
Test name
Test status
Simulation time 13945946127 ps
CPU time 44.55 seconds
Started Aug 18 06:02:27 PM PDT 24
Finished Aug 18 06:03:12 PM PDT 24
Peak memory 200848 kb
Host smart-8cebe4d3-d5b7-4bc5-8c5b-e3a6ef11b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840353464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2840353464
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3171355969
Short name T180
Test name
Test status
Simulation time 45386859974 ps
CPU time 96.92 seconds
Started Aug 18 06:02:26 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 200840 kb
Host smart-10c5dd05-3eed-4eec-95dd-e48683dac936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171355969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3171355969
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3195033212
Short name T318
Test name
Test status
Simulation time 103590022210 ps
CPU time 78.49 seconds
Started Aug 18 06:02:26 PM PDT 24
Finished Aug 18 06:03:44 PM PDT 24
Peak memory 200904 kb
Host smart-2e22f523-48ba-418c-8ade-4b94de11fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195033212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3195033212
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3731179107
Short name T487
Test name
Test status
Simulation time 104102071825 ps
CPU time 158.99 seconds
Started Aug 18 06:02:34 PM PDT 24
Finished Aug 18 06:05:14 PM PDT 24
Peak memory 200704 kb
Host smart-d85e68bf-8219-4260-b326-71daea4636f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731179107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3731179107
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.585779661
Short name T547
Test name
Test status
Simulation time 11183117 ps
CPU time 0.53 seconds
Started Aug 18 05:58:44 PM PDT 24
Finished Aug 18 05:58:45 PM PDT 24
Peak memory 195672 kb
Host smart-bdec6835-8cd7-4d1d-812e-626bb3b5d276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585779661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.585779661
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2400423630
Short name T797
Test name
Test status
Simulation time 106995042887 ps
CPU time 31.11 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 05:59:05 PM PDT 24
Peak memory 200920 kb
Host smart-7a469238-4e72-4342-9957-2eb95227f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400423630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2400423630
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3593962702
Short name T1176
Test name
Test status
Simulation time 173833012612 ps
CPU time 105.55 seconds
Started Aug 18 05:58:32 PM PDT 24
Finished Aug 18 06:00:18 PM PDT 24
Peak memory 200836 kb
Host smart-01f11cd3-95b2-478a-a1cd-04ab7aa62db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593962702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3593962702
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.59909076
Short name T166
Test name
Test status
Simulation time 21092652651 ps
CPU time 21.59 seconds
Started Aug 18 05:58:33 PM PDT 24
Finished Aug 18 05:58:54 PM PDT 24
Peak memory 200932 kb
Host smart-5d7c22fb-4d56-42fc-bb30-1a0c8228ad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59909076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.59909076
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1197547440
Short name T889
Test name
Test status
Simulation time 15351483031 ps
CPU time 27.08 seconds
Started Aug 18 05:58:42 PM PDT 24
Finished Aug 18 05:59:10 PM PDT 24
Peak memory 200932 kb
Host smart-c82430fb-a1e3-4f73-8ec2-629a6ae4c93f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197547440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1197547440
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1990291902
Short name T533
Test name
Test status
Simulation time 130363076299 ps
CPU time 321.91 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 06:04:06 PM PDT 24
Peak memory 200936 kb
Host smart-b44e4d29-38a9-4b84-b293-3a77da13219d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990291902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1990291902
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2551770891
Short name T831
Test name
Test status
Simulation time 3094042698 ps
CPU time 2.2 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 05:58:45 PM PDT 24
Peak memory 197780 kb
Host smart-033e44db-9b5a-43a5-83da-0b2e0619e86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551770891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2551770891
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1315973058
Short name T312
Test name
Test status
Simulation time 96627875752 ps
CPU time 21.22 seconds
Started Aug 18 05:58:44 PM PDT 24
Finished Aug 18 05:59:05 PM PDT 24
Peak memory 201076 kb
Host smart-86d20517-da38-4e7b-9bca-a25763d65d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315973058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1315973058
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.549445968
Short name T608
Test name
Test status
Simulation time 18191240168 ps
CPU time 1090.54 seconds
Started Aug 18 05:58:44 PM PDT 24
Finished Aug 18 06:16:55 PM PDT 24
Peak memory 200916 kb
Host smart-e482b5ab-b7ff-4d35-b6ef-c0e33a2eb9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549445968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.549445968
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.458066623
Short name T630
Test name
Test status
Simulation time 5499356801 ps
CPU time 12.76 seconds
Started Aug 18 05:58:45 PM PDT 24
Finished Aug 18 05:58:58 PM PDT 24
Peak memory 199032 kb
Host smart-61380198-fc25-4846-88d8-8b4717f49c85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458066623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.458066623
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3768638288
Short name T868
Test name
Test status
Simulation time 77912345909 ps
CPU time 25.69 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 05:59:08 PM PDT 24
Peak memory 199432 kb
Host smart-3be486f5-3c56-4b57-aa47-6b775891b2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768638288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3768638288
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.644989416
Short name T516
Test name
Test status
Simulation time 34943826745 ps
CPU time 24.41 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 05:59:07 PM PDT 24
Peak memory 197048 kb
Host smart-6cd3d756-4754-4240-bb48-7dde91a13df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644989416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.644989416
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1307646172
Short name T243
Test name
Test status
Simulation time 670180566 ps
CPU time 2.55 seconds
Started Aug 18 05:58:36 PM PDT 24
Finished Aug 18 05:58:39 PM PDT 24
Peak memory 199216 kb
Host smart-175e595c-6ef6-4950-a407-5a62232859b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307646172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1307646172
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.683357817
Short name T897
Test name
Test status
Simulation time 14510419153 ps
CPU time 35.76 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 05:59:19 PM PDT 24
Peak memory 217528 kb
Host smart-ac662b8c-6cc6-49dc-b0f3-8f6e8a3ea10d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683357817 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.683357817
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2158810279
Short name T286
Test name
Test status
Simulation time 6611657306 ps
CPU time 8.23 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 05:58:51 PM PDT 24
Peak memory 199916 kb
Host smart-cbc27225-2c48-4b70-89ae-6c7abf34e7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158810279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2158810279
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2976612041
Short name T891
Test name
Test status
Simulation time 17945666998 ps
CPU time 28.49 seconds
Started Aug 18 05:58:41 PM PDT 24
Finished Aug 18 05:59:09 PM PDT 24
Peak memory 200704 kb
Host smart-0036fe14-02dd-4cd6-ba20-71ede237bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976612041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2976612041
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3933429541
Short name T1015
Test name
Test status
Simulation time 24214786689 ps
CPU time 16.8 seconds
Started Aug 18 06:02:33 PM PDT 24
Finished Aug 18 06:02:50 PM PDT 24
Peak memory 200928 kb
Host smart-6fb80ceb-3fa1-41eb-a254-6a69ddca709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933429541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3933429541
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3829325007
Short name T1138
Test name
Test status
Simulation time 170907323262 ps
CPU time 86.99 seconds
Started Aug 18 06:02:36 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 200924 kb
Host smart-12803793-cae4-45de-8a33-6ec5dff4bae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829325007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3829325007
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.250005172
Short name T514
Test name
Test status
Simulation time 13562392951 ps
CPU time 5.96 seconds
Started Aug 18 06:02:36 PM PDT 24
Finished Aug 18 06:02:42 PM PDT 24
Peak memory 200768 kb
Host smart-cf532003-f06d-4e56-8863-129b958ef41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250005172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.250005172
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3625039259
Short name T848
Test name
Test status
Simulation time 89008050365 ps
CPU time 26.82 seconds
Started Aug 18 06:02:34 PM PDT 24
Finished Aug 18 06:03:01 PM PDT 24
Peak memory 200932 kb
Host smart-19defc8a-b1d3-4e0c-8100-ff3f827a33a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625039259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3625039259
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2915421033
Short name T101
Test name
Test status
Simulation time 37542699178 ps
CPU time 13.36 seconds
Started Aug 18 06:02:37 PM PDT 24
Finished Aug 18 06:02:50 PM PDT 24
Peak memory 200876 kb
Host smart-1f95ef83-8978-4c95-a450-cb797b76f0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915421033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2915421033
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3815670371
Short name T420
Test name
Test status
Simulation time 19043282874 ps
CPU time 41.04 seconds
Started Aug 18 06:02:36 PM PDT 24
Finished Aug 18 06:03:17 PM PDT 24
Peak memory 200936 kb
Host smart-93a4b355-6476-485d-bfe4-6a97c8fa88c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815670371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3815670371
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2549137089
Short name T787
Test name
Test status
Simulation time 45436834650 ps
CPU time 17.8 seconds
Started Aug 18 06:02:36 PM PDT 24
Finished Aug 18 06:02:54 PM PDT 24
Peak memory 200648 kb
Host smart-7b80599a-4646-421b-9fba-cf162bd640b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549137089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2549137089
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1567464032
Short name T205
Test name
Test status
Simulation time 180972727380 ps
CPU time 39.98 seconds
Started Aug 18 06:02:32 PM PDT 24
Finished Aug 18 06:03:13 PM PDT 24
Peak memory 200892 kb
Host smart-abf10ede-d61e-4f17-856e-ce9b95585571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567464032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1567464032
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3528296749
Short name T983
Test name
Test status
Simulation time 20049339 ps
CPU time 0.57 seconds
Started Aug 18 05:58:53 PM PDT 24
Finished Aug 18 05:58:53 PM PDT 24
Peak memory 196248 kb
Host smart-938db1de-53a2-4cc5-85b8-5aaf84c2bbf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528296749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3528296749
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1781553374
Short name T293
Test name
Test status
Simulation time 107529091424 ps
CPU time 69.25 seconds
Started Aug 18 05:58:46 PM PDT 24
Finished Aug 18 05:59:55 PM PDT 24
Peak memory 200916 kb
Host smart-d0a1930f-4f76-4094-8385-5376a33c3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781553374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1781553374
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2531420929
Short name T588
Test name
Test status
Simulation time 98217370710 ps
CPU time 69.28 seconds
Started Aug 18 05:58:45 PM PDT 24
Finished Aug 18 05:59:54 PM PDT 24
Peak memory 200884 kb
Host smart-5e658e64-9143-42b4-a95b-27ae9ab18f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531420929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2531420929
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3878115052
Short name T1033
Test name
Test status
Simulation time 44527482343 ps
CPU time 15.15 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 05:58:58 PM PDT 24
Peak memory 200924 kb
Host smart-98741e66-68eb-40db-bb2b-1f5837d1fb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878115052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3878115052
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.788787518
Short name T641
Test name
Test status
Simulation time 29849776439 ps
CPU time 8.03 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 05:58:52 PM PDT 24
Peak memory 196992 kb
Host smart-5ff3aa64-f0c9-4c81-8dff-2d85ba27bc94
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788787518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.788787518
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3043758562
Short name T486
Test name
Test status
Simulation time 70545396689 ps
CPU time 142.7 seconds
Started Aug 18 05:58:55 PM PDT 24
Finished Aug 18 06:01:18 PM PDT 24
Peak memory 200944 kb
Host smart-e44f76a8-7b37-42b4-9638-f624abcd94fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043758562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3043758562
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2449991699
Short name T647
Test name
Test status
Simulation time 9058406692 ps
CPU time 14.23 seconds
Started Aug 18 05:58:59 PM PDT 24
Finished Aug 18 05:59:13 PM PDT 24
Peak memory 198440 kb
Host smart-f507c0e0-6254-4ca6-a3f2-f20d0e2c77e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449991699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2449991699
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4243553532
Short name T436
Test name
Test status
Simulation time 61679208073 ps
CPU time 88.41 seconds
Started Aug 18 05:58:44 PM PDT 24
Finished Aug 18 06:00:13 PM PDT 24
Peak memory 201048 kb
Host smart-56d0032e-065b-4aae-b2d4-65e173f52fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243553532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4243553532
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.4181875073
Short name T987
Test name
Test status
Simulation time 10003276594 ps
CPU time 290.09 seconds
Started Aug 18 05:58:54 PM PDT 24
Finished Aug 18 06:03:44 PM PDT 24
Peak memory 200860 kb
Host smart-8cd962e2-8869-4a5e-879c-e59f40d3ca3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181875073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4181875073
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.102535280
Short name T345
Test name
Test status
Simulation time 3487804768 ps
CPU time 10.59 seconds
Started Aug 18 05:58:45 PM PDT 24
Finished Aug 18 05:58:56 PM PDT 24
Peak memory 199528 kb
Host smart-6b1bfde8-98bb-4dae-ad83-5f444001e446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102535280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.102535280
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.918315334
Short name T916
Test name
Test status
Simulation time 132254528849 ps
CPU time 25.05 seconds
Started Aug 18 05:58:53 PM PDT 24
Finished Aug 18 05:59:18 PM PDT 24
Peak memory 200588 kb
Host smart-5650c0f7-564d-4065-90bb-29c5f4524763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918315334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.918315334
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.541070714
Short name T925
Test name
Test status
Simulation time 489864550 ps
CPU time 1.34 seconds
Started Aug 18 05:58:43 PM PDT 24
Finished Aug 18 05:58:44 PM PDT 24
Peak memory 196408 kb
Host smart-cd43b548-a3bf-40f6-a8a1-0d3762e1ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541070714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.541070714
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2566851893
Short name T656
Test name
Test status
Simulation time 927909600 ps
CPU time 3.32 seconds
Started Aug 18 05:58:42 PM PDT 24
Finished Aug 18 05:58:46 PM PDT 24
Peak memory 200228 kb
Host smart-1c0804ca-64da-498f-958f-9c80faef7508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566851893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2566851893
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3559382925
Short name T495
Test name
Test status
Simulation time 346192517182 ps
CPU time 325.59 seconds
Started Aug 18 05:59:00 PM PDT 24
Finished Aug 18 06:04:26 PM PDT 24
Peak memory 200700 kb
Host smart-fd412b94-37bc-4c8a-9a5e-819b661e33b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559382925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3559382925
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1404984069
Short name T97
Test name
Test status
Simulation time 9571018519 ps
CPU time 67.61 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 06:00:00 PM PDT 24
Peak memory 217400 kb
Host smart-e9924133-9034-4a34-9b48-fd4c210a6c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404984069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1404984069
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.979505760
Short name T434
Test name
Test status
Simulation time 6548045128 ps
CPU time 22.9 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 05:59:15 PM PDT 24
Peak memory 200640 kb
Host smart-754f8fad-928c-4b89-81bd-20537ea1d99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979505760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.979505760
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3538004047
Short name T714
Test name
Test status
Simulation time 108930994802 ps
CPU time 203.47 seconds
Started Aug 18 05:58:45 PM PDT 24
Finished Aug 18 06:02:08 PM PDT 24
Peak memory 200908 kb
Host smart-cf6828be-0dae-4a0f-b6ce-955a198125e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538004047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3538004047
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.467914
Short name T162
Test name
Test status
Simulation time 224413696395 ps
CPU time 78.09 seconds
Started Aug 18 06:02:35 PM PDT 24
Finished Aug 18 06:03:53 PM PDT 24
Peak memory 200760 kb
Host smart-b9d1566e-8d9c-4962-8515-b5a37536a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.467914
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.150373722
Short name T160
Test name
Test status
Simulation time 146221851586 ps
CPU time 114.6 seconds
Started Aug 18 06:02:36 PM PDT 24
Finished Aug 18 06:04:31 PM PDT 24
Peak memory 200924 kb
Host smart-f0981115-f2e0-4f84-a2ab-7b1ea20abb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150373722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.150373722
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3121445007
Short name T681
Test name
Test status
Simulation time 27183109283 ps
CPU time 22.58 seconds
Started Aug 18 06:02:35 PM PDT 24
Finished Aug 18 06:02:58 PM PDT 24
Peak memory 200772 kb
Host smart-131bca66-4933-4e7d-8e96-e7ee4203a05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121445007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3121445007
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2151281795
Short name T937
Test name
Test status
Simulation time 11055306085 ps
CPU time 20.08 seconds
Started Aug 18 06:02:37 PM PDT 24
Finished Aug 18 06:02:57 PM PDT 24
Peak memory 200916 kb
Host smart-d135c55f-4eb0-4cbd-8914-eeecf2e01173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151281795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2151281795
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3503053279
Short name T945
Test name
Test status
Simulation time 45830868305 ps
CPU time 29.92 seconds
Started Aug 18 06:02:37 PM PDT 24
Finished Aug 18 06:03:07 PM PDT 24
Peak memory 200924 kb
Host smart-37692757-864f-464e-81ad-79c4663b6929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503053279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3503053279
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2102641085
Short name T596
Test name
Test status
Simulation time 26234283079 ps
CPU time 35.71 seconds
Started Aug 18 06:02:38 PM PDT 24
Finished Aug 18 06:03:14 PM PDT 24
Peak memory 200916 kb
Host smart-38c96e3b-8289-441f-b2ec-da984d206ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102641085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2102641085
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3850012845
Short name T716
Test name
Test status
Simulation time 184492399518 ps
CPU time 262.1 seconds
Started Aug 18 06:02:34 PM PDT 24
Finished Aug 18 06:06:57 PM PDT 24
Peak memory 200828 kb
Host smart-2a1fd594-6d8c-4746-a1ec-85174ff09cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850012845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3850012845
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1683722674
Short name T625
Test name
Test status
Simulation time 22480865277 ps
CPU time 32.58 seconds
Started Aug 18 06:02:35 PM PDT 24
Finished Aug 18 06:03:08 PM PDT 24
Peak memory 200764 kb
Host smart-74e2d5e2-90bc-4a40-9e74-296ea09d882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683722674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1683722674
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2480494931
Short name T174
Test name
Test status
Simulation time 122210218566 ps
CPU time 188.11 seconds
Started Aug 18 06:02:34 PM PDT 24
Finished Aug 18 06:05:43 PM PDT 24
Peak memory 200844 kb
Host smart-a7337532-acd9-46bd-8539-52c817e2ea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480494931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2480494931
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2314261342
Short name T1062
Test name
Test status
Simulation time 71447015 ps
CPU time 0.55 seconds
Started Aug 18 05:58:54 PM PDT 24
Finished Aug 18 05:58:55 PM PDT 24
Peak memory 196428 kb
Host smart-f9faccb9-e03e-4bfe-8f75-b4991a0aaa12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314261342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2314261342
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1775302374
Short name T569
Test name
Test status
Simulation time 43816217791 ps
CPU time 31.51 seconds
Started Aug 18 05:58:54 PM PDT 24
Finished Aug 18 05:59:26 PM PDT 24
Peak memory 200840 kb
Host smart-09e0d1b3-e11e-4c56-9ad6-056e9ecb1626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775302374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1775302374
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.519275787
Short name T416
Test name
Test status
Simulation time 39983514311 ps
CPU time 14.49 seconds
Started Aug 18 05:58:53 PM PDT 24
Finished Aug 18 05:59:08 PM PDT 24
Peak memory 200840 kb
Host smart-a7cb1523-7a8f-4bd8-acdd-be742896c4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519275787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.519275787
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.4175491073
Short name T217
Test name
Test status
Simulation time 52239049508 ps
CPU time 64.41 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 05:59:57 PM PDT 24
Peak memory 200876 kb
Host smart-92784150-d886-499c-b770-0fe701594e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175491073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.4175491073
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2223050587
Short name T913
Test name
Test status
Simulation time 270434743261 ps
CPU time 192.25 seconds
Started Aug 18 05:59:00 PM PDT 24
Finished Aug 18 06:02:12 PM PDT 24
Peak memory 198496 kb
Host smart-8e09a5f5-c007-4107-905d-1049e73e4568
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223050587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2223050587
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1764681887
Short name T1134
Test name
Test status
Simulation time 80450854241 ps
CPU time 298.26 seconds
Started Aug 18 05:59:00 PM PDT 24
Finished Aug 18 06:03:58 PM PDT 24
Peak memory 200712 kb
Host smart-0ed51000-9180-44ad-849c-b29f71314319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1764681887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1764681887
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1643451137
Short name T527
Test name
Test status
Simulation time 4867263875 ps
CPU time 11.14 seconds
Started Aug 18 05:58:54 PM PDT 24
Finished Aug 18 05:59:05 PM PDT 24
Peak memory 199940 kb
Host smart-f9d3cd1c-54c0-4096-8767-d29b7f1f73fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643451137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1643451137
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2407429540
Short name T276
Test name
Test status
Simulation time 144685427117 ps
CPU time 290.16 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 06:03:42 PM PDT 24
Peak memory 201192 kb
Host smart-196fd31b-ffb2-4219-88ec-2617d816d129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407429540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2407429540
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2851030230
Short name T860
Test name
Test status
Simulation time 15464645939 ps
CPU time 766.4 seconds
Started Aug 18 05:58:59 PM PDT 24
Finished Aug 18 06:11:46 PM PDT 24
Peak memory 200704 kb
Host smart-87c63203-f4a2-4a67-bd1d-9099f2c8f3bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851030230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2851030230
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3561483042
Short name T990
Test name
Test status
Simulation time 3369502015 ps
CPU time 12.73 seconds
Started Aug 18 05:59:00 PM PDT 24
Finished Aug 18 05:59:13 PM PDT 24
Peak memory 199132 kb
Host smart-1f0de20f-95a2-4070-8346-8c0ff4e69de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561483042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3561483042
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2366134058
Short name T957
Test name
Test status
Simulation time 15185594641 ps
CPU time 39.09 seconds
Started Aug 18 05:58:54 PM PDT 24
Finished Aug 18 05:59:34 PM PDT 24
Peak memory 200828 kb
Host smart-3823dde7-0952-4096-b5d0-a2f1214044d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366134058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2366134058
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.934688829
Short name T924
Test name
Test status
Simulation time 3989025962 ps
CPU time 3.41 seconds
Started Aug 18 05:58:51 PM PDT 24
Finished Aug 18 05:58:55 PM PDT 24
Peak memory 197392 kb
Host smart-7560ecf1-59d3-4565-aaab-7dd487fd6f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934688829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.934688829
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.4066424085
Short name T538
Test name
Test status
Simulation time 735663378 ps
CPU time 2.68 seconds
Started Aug 18 05:58:56 PM PDT 24
Finished Aug 18 05:58:59 PM PDT 24
Peak memory 200580 kb
Host smart-be8e54b8-bb99-4388-841b-06c90f38c9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066424085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4066424085
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1607780116
Short name T553
Test name
Test status
Simulation time 168730269342 ps
CPU time 153.89 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 06:01:26 PM PDT 24
Peak memory 209348 kb
Host smart-728af6b1-c7ee-4dc6-aba6-3cf6248a7bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607780116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1607780116
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1254854847
Short name T822
Test name
Test status
Simulation time 1382192774 ps
CPU time 18.44 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 05:59:11 PM PDT 24
Peak memory 201036 kb
Host smart-6cf72ea4-9831-42eb-a6d7-d07c269b20f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254854847 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1254854847
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3447964834
Short name T617
Test name
Test status
Simulation time 1201803786 ps
CPU time 3.8 seconds
Started Aug 18 05:58:53 PM PDT 24
Finished Aug 18 05:58:57 PM PDT 24
Peak memory 199280 kb
Host smart-170a59fc-75db-4640-810f-c24b24a990cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447964834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3447964834
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1464577159
Short name T597
Test name
Test status
Simulation time 100574900380 ps
CPU time 57.33 seconds
Started Aug 18 05:58:53 PM PDT 24
Finished Aug 18 05:59:50 PM PDT 24
Peak memory 200924 kb
Host smart-61f07bfc-a02a-495a-90d3-04bd9bba14b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464577159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1464577159
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.162810136
Short name T79
Test name
Test status
Simulation time 23106225517 ps
CPU time 12.7 seconds
Started Aug 18 06:02:32 PM PDT 24
Finished Aug 18 06:02:45 PM PDT 24
Peak memory 200936 kb
Host smart-6af9cfc4-bf3a-4544-a45c-64d2d03f05d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162810136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.162810136
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.4285960719
Short name T922
Test name
Test status
Simulation time 12122946106 ps
CPU time 19.49 seconds
Started Aug 18 06:02:38 PM PDT 24
Finished Aug 18 06:02:57 PM PDT 24
Peak memory 200912 kb
Host smart-b7cd8a2f-6cce-4135-98ef-32f427075ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285960719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.4285960719
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3206421426
Short name T103
Test name
Test status
Simulation time 158060726052 ps
CPU time 13.58 seconds
Started Aug 18 06:02:36 PM PDT 24
Finished Aug 18 06:02:50 PM PDT 24
Peak memory 200632 kb
Host smart-f08ad510-4e28-49c0-acb2-c2fcba39f533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206421426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3206421426
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3620469470
Short name T1091
Test name
Test status
Simulation time 46854790109 ps
CPU time 21.35 seconds
Started Aug 18 06:02:34 PM PDT 24
Finished Aug 18 06:02:56 PM PDT 24
Peak memory 200940 kb
Host smart-4e3497cb-11ab-48bf-becb-5b702a359095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620469470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3620469470
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2320436364
Short name T735
Test name
Test status
Simulation time 101654319793 ps
CPU time 159.12 seconds
Started Aug 18 06:02:44 PM PDT 24
Finished Aug 18 06:05:23 PM PDT 24
Peak memory 200828 kb
Host smart-2a154826-c138-4acb-b3c4-ac68142fe250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320436364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2320436364
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.875550171
Short name T576
Test name
Test status
Simulation time 79326107912 ps
CPU time 16.15 seconds
Started Aug 18 06:02:42 PM PDT 24
Finished Aug 18 06:02:58 PM PDT 24
Peak memory 200700 kb
Host smart-9b7ebd2a-d1a3-40fb-a2fb-9de3687e9158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875550171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.875550171
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.407242652
Short name T1022
Test name
Test status
Simulation time 112217053532 ps
CPU time 184.73 seconds
Started Aug 18 06:02:42 PM PDT 24
Finished Aug 18 06:05:47 PM PDT 24
Peak memory 200948 kb
Host smart-9e0441b4-fda4-4583-801b-b58f9e9d1610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407242652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.407242652
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.169168145
Short name T890
Test name
Test status
Simulation time 17034040653 ps
CPU time 26.83 seconds
Started Aug 18 06:02:45 PM PDT 24
Finished Aug 18 06:03:12 PM PDT 24
Peak memory 200928 kb
Host smart-9ed19592-a4d3-43e6-a524-00a30154fadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169168145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.169168145
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.755148037
Short name T475
Test name
Test status
Simulation time 38309651 ps
CPU time 0.57 seconds
Started Aug 18 05:58:58 PM PDT 24
Finished Aug 18 05:58:59 PM PDT 24
Peak memory 196224 kb
Host smart-e7233fd5-082b-4c8e-87e5-a1fb5076e85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755148037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.755148037
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1145390262
Short name T317
Test name
Test status
Simulation time 23227941286 ps
CPU time 40.33 seconds
Started Aug 18 05:58:55 PM PDT 24
Finished Aug 18 05:59:35 PM PDT 24
Peak memory 201108 kb
Host smart-c5013cb5-b511-43d9-8f53-ff0a2019227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145390262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1145390262
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1702761892
Short name T693
Test name
Test status
Simulation time 136408008140 ps
CPU time 164.01 seconds
Started Aug 18 05:58:54 PM PDT 24
Finished Aug 18 06:01:38 PM PDT 24
Peak memory 200864 kb
Host smart-a9e4c14f-7202-4e61-8f8d-06621ec676ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702761892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1702761892
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1021718728
Short name T164
Test name
Test status
Simulation time 92726851802 ps
CPU time 50.67 seconds
Started Aug 18 05:58:53 PM PDT 24
Finished Aug 18 05:59:44 PM PDT 24
Peak memory 200856 kb
Host smart-82feedee-0838-400f-bd98-cc8d1d00fc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021718728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1021718728
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2166784642
Short name T310
Test name
Test status
Simulation time 20207136103 ps
CPU time 9.85 seconds
Started Aug 18 05:58:54 PM PDT 24
Finished Aug 18 05:59:04 PM PDT 24
Peak memory 200928 kb
Host smart-4cfeb977-ead9-4459-af39-6ddb8c601edf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166784642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2166784642
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3110063286
Short name T488
Test name
Test status
Simulation time 94138850754 ps
CPU time 405.37 seconds
Started Aug 18 05:59:02 PM PDT 24
Finished Aug 18 06:05:48 PM PDT 24
Peak memory 200924 kb
Host smart-35d65e24-e53f-48a9-978d-b1475162474e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110063286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3110063286
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.223722749
Short name T796
Test name
Test status
Simulation time 2082762258 ps
CPU time 2.26 seconds
Started Aug 18 05:58:59 PM PDT 24
Finished Aug 18 05:59:02 PM PDT 24
Peak memory 199652 kb
Host smart-d723fc8e-b6d8-4349-966c-157562b0e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223722749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.223722749
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1311512709
Short name T562
Test name
Test status
Simulation time 99998764492 ps
CPU time 156.99 seconds
Started Aug 18 05:58:56 PM PDT 24
Finished Aug 18 06:01:33 PM PDT 24
Peak memory 208900 kb
Host smart-de5c7005-c113-4ff2-85d4-7cb71b057a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311512709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1311512709
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1640176266
Short name T722
Test name
Test status
Simulation time 19031036007 ps
CPU time 272.08 seconds
Started Aug 18 05:59:01 PM PDT 24
Finished Aug 18 06:03:33 PM PDT 24
Peak memory 200924 kb
Host smart-b340c9a3-462d-4b9b-9d7b-ac7c6fdbe912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640176266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1640176266
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2962266608
Short name T1145
Test name
Test status
Simulation time 1823255578 ps
CPU time 1.92 seconds
Started Aug 18 05:58:53 PM PDT 24
Finished Aug 18 05:58:55 PM PDT 24
Peak memory 198868 kb
Host smart-335c302b-3d2e-48d3-aa86-e42f5ae472ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962266608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2962266608
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2525493067
Short name T671
Test name
Test status
Simulation time 21267554414 ps
CPU time 7.67 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 05:59:00 PM PDT 24
Peak memory 200912 kb
Host smart-e8690dd3-bb6a-4fd0-b8a9-bf9262f5495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525493067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2525493067
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.946706790
Short name T994
Test name
Test status
Simulation time 37272801351 ps
CPU time 53.76 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 05:59:46 PM PDT 24
Peak memory 196952 kb
Host smart-428afa5d-53a6-47e1-badb-1dba9a6843ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946706790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.946706790
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2578911398
Short name T705
Test name
Test status
Simulation time 303783817 ps
CPU time 1.14 seconds
Started Aug 18 05:58:55 PM PDT 24
Finished Aug 18 05:58:57 PM PDT 24
Peak memory 199352 kb
Host smart-be42d3a3-7276-41be-aae9-0cd2b0dd488f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578911398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2578911398
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1920423133
Short name T811
Test name
Test status
Simulation time 96750016816 ps
CPU time 248.32 seconds
Started Aug 18 05:59:04 PM PDT 24
Finished Aug 18 06:03:12 PM PDT 24
Peak memory 200848 kb
Host smart-1fd9b355-56ad-41ee-a8b1-2d15a0812e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920423133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1920423133
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3280155654
Short name T750
Test name
Test status
Simulation time 1049153012 ps
CPU time 19.31 seconds
Started Aug 18 05:59:02 PM PDT 24
Finished Aug 18 05:59:22 PM PDT 24
Peak memory 209628 kb
Host smart-03366b04-150b-427c-a09a-f932936d3ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280155654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3280155654
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2922428352
Short name T965
Test name
Test status
Simulation time 424356524 ps
CPU time 1.74 seconds
Started Aug 18 05:58:52 PM PDT 24
Finished Aug 18 05:58:54 PM PDT 24
Peak memory 199344 kb
Host smart-babfe23c-6951-45cf-a720-c2f09510b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922428352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2922428352
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.32813539
Short name T774
Test name
Test status
Simulation time 45075897627 ps
CPU time 23.99 seconds
Started Aug 18 05:59:00 PM PDT 24
Finished Aug 18 05:59:24 PM PDT 24
Peak memory 200696 kb
Host smart-4cbd7104-54b6-4404-923c-b4bf9215fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32813539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.32813539
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3593066886
Short name T984
Test name
Test status
Simulation time 9357596731 ps
CPU time 34.06 seconds
Started Aug 18 06:02:43 PM PDT 24
Finished Aug 18 06:03:17 PM PDT 24
Peak memory 200932 kb
Host smart-39112a68-955c-489a-90cf-494629e3186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593066886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3593066886
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3790551973
Short name T136
Test name
Test status
Simulation time 70652017729 ps
CPU time 26.47 seconds
Started Aug 18 06:02:42 PM PDT 24
Finished Aug 18 06:03:08 PM PDT 24
Peak memory 200912 kb
Host smart-55528b86-2d9f-4dce-b374-ca1eda54ea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790551973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3790551973
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1136670194
Short name T110
Test name
Test status
Simulation time 31772324033 ps
CPU time 22.53 seconds
Started Aug 18 06:02:42 PM PDT 24
Finished Aug 18 06:03:05 PM PDT 24
Peak memory 200880 kb
Host smart-19918091-70bc-4382-bf1f-9c83bacd679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136670194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1136670194
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.4096668
Short name T299
Test name
Test status
Simulation time 29804854842 ps
CPU time 77.14 seconds
Started Aug 18 06:02:44 PM PDT 24
Finished Aug 18 06:04:01 PM PDT 24
Peak memory 200872 kb
Host smart-92f0c556-d26c-4057-87d9-d407507c3820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.4096668
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1860404924
Short name T191
Test name
Test status
Simulation time 17190744693 ps
CPU time 26.29 seconds
Started Aug 18 06:02:42 PM PDT 24
Finished Aug 18 06:03:08 PM PDT 24
Peak memory 200652 kb
Host smart-be428849-98c1-4dc0-b903-0d6ae5cfd16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860404924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1860404924
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.553118676
Short name T455
Test name
Test status
Simulation time 294626689075 ps
CPU time 116.83 seconds
Started Aug 18 06:02:43 PM PDT 24
Finished Aug 18 06:04:39 PM PDT 24
Peak memory 200720 kb
Host smart-91ddfc50-0f26-475a-ab8b-5f37c66acb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553118676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.553118676
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1561196451
Short name T528
Test name
Test status
Simulation time 32558716631 ps
CPU time 27.27 seconds
Started Aug 18 06:02:43 PM PDT 24
Finished Aug 18 06:03:10 PM PDT 24
Peak memory 200916 kb
Host smart-05049a57-28fc-4999-9548-c2c51572242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561196451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1561196451
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2989826897
Short name T718
Test name
Test status
Simulation time 57301921236 ps
CPU time 29.51 seconds
Started Aug 18 06:02:41 PM PDT 24
Finished Aug 18 06:03:10 PM PDT 24
Peak memory 200868 kb
Host smart-f9a20ee4-7759-43a2-8e06-6469964aadb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989826897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2989826897
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3495509979
Short name T252
Test name
Test status
Simulation time 134657904450 ps
CPU time 67.37 seconds
Started Aug 18 06:02:42 PM PDT 24
Finished Aug 18 06:03:49 PM PDT 24
Peak memory 200940 kb
Host smart-1c85c929-6439-4e81-80f3-f0a84151c9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495509979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3495509979
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.870089688
Short name T127
Test name
Test status
Simulation time 110451461873 ps
CPU time 87.93 seconds
Started Aug 18 06:02:42 PM PDT 24
Finished Aug 18 06:04:10 PM PDT 24
Peak memory 200932 kb
Host smart-e3d60e97-6efa-436a-8643-a2bce0a8c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870089688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.870089688
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2904507636
Short name T1161
Test name
Test status
Simulation time 48889205 ps
CPU time 0.56 seconds
Started Aug 18 05:59:04 PM PDT 24
Finished Aug 18 05:59:04 PM PDT 24
Peak memory 195504 kb
Host smart-671188db-abb5-4dc0-abcc-0c1a3e6b2416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904507636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2904507636
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.789854414
Short name T131
Test name
Test status
Simulation time 29205901705 ps
CPU time 24.44 seconds
Started Aug 18 05:59:00 PM PDT 24
Finished Aug 18 05:59:25 PM PDT 24
Peak memory 200756 kb
Host smart-927120c2-9798-47bd-b80f-0ac7a6d83f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789854414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.789854414
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.4282682851
Short name T839
Test name
Test status
Simulation time 52333684148 ps
CPU time 61.17 seconds
Started Aug 18 05:59:03 PM PDT 24
Finished Aug 18 06:00:04 PM PDT 24
Peak memory 200368 kb
Host smart-7d8b5cd4-fc9f-403d-9ad7-d8fe5bf7315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282682851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4282682851
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3022247621
Short name T921
Test name
Test status
Simulation time 149248470826 ps
CPU time 169.28 seconds
Started Aug 18 05:58:59 PM PDT 24
Finished Aug 18 06:01:48 PM PDT 24
Peak memory 200884 kb
Host smart-efbfbe3f-8156-4547-84ef-09844309a928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022247621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3022247621
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1088014526
Short name T654
Test name
Test status
Simulation time 33868117657 ps
CPU time 11.2 seconds
Started Aug 18 05:59:03 PM PDT 24
Finished Aug 18 05:59:14 PM PDT 24
Peak memory 200568 kb
Host smart-0c6b8353-f8e8-48dd-b5e6-72d03b7af273
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088014526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1088014526
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.756667753
Short name T876
Test name
Test status
Simulation time 129202908226 ps
CPU time 529.31 seconds
Started Aug 18 05:59:00 PM PDT 24
Finished Aug 18 06:07:50 PM PDT 24
Peak memory 200856 kb
Host smart-02240788-7578-46dc-9095-d01a2a06f4b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=756667753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.756667753
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1870043874
Short name T1182
Test name
Test status
Simulation time 12219268850 ps
CPU time 4.1 seconds
Started Aug 18 05:59:01 PM PDT 24
Finished Aug 18 05:59:05 PM PDT 24
Peak memory 200820 kb
Host smart-b3e0a96b-a59a-4610-b26c-c865d52852e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870043874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1870043874
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.1150043716
Short name T768
Test name
Test status
Simulation time 16923969936 ps
CPU time 131.05 seconds
Started Aug 18 05:58:59 PM PDT 24
Finished Aug 18 06:01:10 PM PDT 24
Peak memory 200944 kb
Host smart-046800d6-0ad5-4ea3-9275-d5b2b860348e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150043716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1150043716
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2184583347
Short name T899
Test name
Test status
Simulation time 1582791135 ps
CPU time 3.12 seconds
Started Aug 18 05:59:02 PM PDT 24
Finished Aug 18 05:59:05 PM PDT 24
Peak memory 199076 kb
Host smart-d83873ee-579e-4384-8e63-e6f0b02294c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184583347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2184583347
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3055055107
Short name T809
Test name
Test status
Simulation time 66499322434 ps
CPU time 51.67 seconds
Started Aug 18 05:59:01 PM PDT 24
Finished Aug 18 05:59:52 PM PDT 24
Peak memory 200932 kb
Host smart-fa413921-7c13-4ea0-9402-1c575a61150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055055107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3055055107
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.802746363
Short name T504
Test name
Test status
Simulation time 2780422053 ps
CPU time 5.21 seconds
Started Aug 18 05:59:01 PM PDT 24
Finished Aug 18 05:59:07 PM PDT 24
Peak memory 197416 kb
Host smart-2b63cad2-cc5b-4d11-8f57-5212e1965ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802746363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.802746363
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3246923924
Short name T971
Test name
Test status
Simulation time 275413500 ps
CPU time 1.24 seconds
Started Aug 18 05:59:02 PM PDT 24
Finished Aug 18 05:59:04 PM PDT 24
Peak memory 199640 kb
Host smart-b72379de-4013-46c3-9115-a41ac54e46ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246923924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3246923924
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1899909297
Short name T944
Test name
Test status
Simulation time 22627980180 ps
CPU time 63.82 seconds
Started Aug 18 05:59:01 PM PDT 24
Finished Aug 18 06:00:05 PM PDT 24
Peak memory 217576 kb
Host smart-a62b69c8-0065-43f5-9de5-32be9562e832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899909297 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1899909297
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.927348026
Short name T1095
Test name
Test status
Simulation time 9325982756 ps
CPU time 12.44 seconds
Started Aug 18 05:59:02 PM PDT 24
Finished Aug 18 05:59:14 PM PDT 24
Peak memory 200872 kb
Host smart-322c43d4-5342-40ab-8c68-6a7d60f1618f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927348026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.927348026
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.482386383
Short name T292
Test name
Test status
Simulation time 19345275552 ps
CPU time 30.25 seconds
Started Aug 18 05:59:01 PM PDT 24
Finished Aug 18 05:59:32 PM PDT 24
Peak memory 200872 kb
Host smart-d53810d1-7cb3-4a29-98c5-90c102154d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482386383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.482386383
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.275906169
Short name T615
Test name
Test status
Simulation time 116583436436 ps
CPU time 153.92 seconds
Started Aug 18 06:02:50 PM PDT 24
Finished Aug 18 06:05:24 PM PDT 24
Peak memory 200936 kb
Host smart-c3a7f99e-b4f0-4875-9885-a22b4d04d96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275906169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.275906169
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1084381370
Short name T780
Test name
Test status
Simulation time 46326924778 ps
CPU time 20.93 seconds
Started Aug 18 06:02:51 PM PDT 24
Finished Aug 18 06:03:12 PM PDT 24
Peak memory 200784 kb
Host smart-6bf988e6-d571-4ffc-b00e-a1e532933e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084381370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1084381370
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2690230373
Short name T216
Test name
Test status
Simulation time 165843442393 ps
CPU time 71.09 seconds
Started Aug 18 06:02:49 PM PDT 24
Finished Aug 18 06:04:00 PM PDT 24
Peak memory 200908 kb
Host smart-ec230b84-310b-4ef8-89cc-9a6e9607b26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690230373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2690230373
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2548360179
Short name T1065
Test name
Test status
Simulation time 40673668469 ps
CPU time 30.07 seconds
Started Aug 18 06:02:50 PM PDT 24
Finished Aug 18 06:03:20 PM PDT 24
Peak memory 200724 kb
Host smart-65c95d8b-234d-446d-a576-17a5519b09fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548360179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2548360179
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.145431062
Short name T1067
Test name
Test status
Simulation time 171326355894 ps
CPU time 29.16 seconds
Started Aug 18 06:02:54 PM PDT 24
Finished Aug 18 06:03:23 PM PDT 24
Peak memory 200940 kb
Host smart-7f67c4c7-33af-4717-89f0-c4b4f6228aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145431062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.145431062
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3392553485
Short name T946
Test name
Test status
Simulation time 176873502644 ps
CPU time 82.13 seconds
Started Aug 18 06:02:50 PM PDT 24
Finished Aug 18 06:04:12 PM PDT 24
Peak memory 200704 kb
Host smart-bb38e296-3e47-431b-a881-71465af35aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392553485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3392553485
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2668316438
Short name T177
Test name
Test status
Simulation time 104057268904 ps
CPU time 42.34 seconds
Started Aug 18 06:02:54 PM PDT 24
Finished Aug 18 06:03:36 PM PDT 24
Peak memory 200924 kb
Host smart-fc1dbe8b-e147-430f-8435-4a657f19c5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668316438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2668316438
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3516225954
Short name T1098
Test name
Test status
Simulation time 132373640765 ps
CPU time 210.88 seconds
Started Aug 18 06:02:49 PM PDT 24
Finished Aug 18 06:06:20 PM PDT 24
Peak memory 200928 kb
Host smart-d00aa374-773a-428f-8b72-25dd648899d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516225954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3516225954
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3683146574
Short name T874
Test name
Test status
Simulation time 184152723262 ps
CPU time 218.54 seconds
Started Aug 18 06:02:50 PM PDT 24
Finished Aug 18 06:06:29 PM PDT 24
Peak memory 200924 kb
Host smart-6d74d2e5-9199-4c57-8594-335fe5c0dc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683146574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3683146574
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1749275066
Short name T753
Test name
Test status
Simulation time 20394906572 ps
CPU time 40.39 seconds
Started Aug 18 06:02:49 PM PDT 24
Finished Aug 18 06:03:30 PM PDT 24
Peak memory 200932 kb
Host smart-307231c2-b5c9-4e20-b545-0dbfc0f4f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749275066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1749275066
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2912971346
Short name T692
Test name
Test status
Simulation time 57390774 ps
CPU time 0.56 seconds
Started Aug 18 05:57:39 PM PDT 24
Finished Aug 18 05:57:39 PM PDT 24
Peak memory 196244 kb
Host smart-ac88aef7-26d9-4704-8d19-9ecb8bc83fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912971346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2912971346
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3842573562
Short name T556
Test name
Test status
Simulation time 71975271886 ps
CPU time 21.68 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:57:58 PM PDT 24
Peak memory 200876 kb
Host smart-c486ea2c-1910-442f-abe1-4c24f7d7a1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842573562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3842573562
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3560780860
Short name T1160
Test name
Test status
Simulation time 22339829118 ps
CPU time 21.3 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:57:58 PM PDT 24
Peak memory 200872 kb
Host smart-047ba2e7-3148-4829-9286-597365f43e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560780860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3560780860
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.714523094
Short name T470
Test name
Test status
Simulation time 212047041777 ps
CPU time 183.34 seconds
Started Aug 18 05:57:38 PM PDT 24
Finished Aug 18 06:00:42 PM PDT 24
Peak memory 200904 kb
Host smart-96948de7-2dba-4106-a86f-ef10466c7d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714523094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.714523094
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3645959027
Short name T1084
Test name
Test status
Simulation time 24407165590 ps
CPU time 34.09 seconds
Started Aug 18 05:57:38 PM PDT 24
Finished Aug 18 05:58:12 PM PDT 24
Peak memory 198120 kb
Host smart-11fc1144-2f8b-4b44-b136-430023cdbdb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645959027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3645959027
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1299502466
Short name T637
Test name
Test status
Simulation time 153782518355 ps
CPU time 1405.85 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 06:21:03 PM PDT 24
Peak memory 200872 kb
Host smart-e78c4162-c951-4155-a698-1a912e0587f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299502466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1299502466
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2376655184
Short name T1121
Test name
Test status
Simulation time 9033360659 ps
CPU time 10.36 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:57:48 PM PDT 24
Peak memory 200824 kb
Host smart-7c192942-4352-41de-8569-b3dd20b19472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376655184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2376655184
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1379876966
Short name T472
Test name
Test status
Simulation time 15729691665 ps
CPU time 25.97 seconds
Started Aug 18 05:57:38 PM PDT 24
Finished Aug 18 05:58:05 PM PDT 24
Peak memory 199312 kb
Host smart-20089ab1-8bcb-42c8-ba64-99671a5c2f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379876966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1379876966
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1039338688
Short name T815
Test name
Test status
Simulation time 9482917377 ps
CPU time 84.98 seconds
Started Aug 18 05:57:40 PM PDT 24
Finished Aug 18 05:59:05 PM PDT 24
Peak memory 200924 kb
Host smart-375627dc-7ae0-4263-b8f3-158ba39bb2ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039338688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1039338688
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2721431226
Short name T817
Test name
Test status
Simulation time 7481184890 ps
CPU time 67.53 seconds
Started Aug 18 05:57:35 PM PDT 24
Finished Aug 18 05:58:43 PM PDT 24
Peak memory 199048 kb
Host smart-e4425709-19f2-4c84-80ce-692c18c3c35c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721431226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2721431226
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3783072458
Short name T141
Test name
Test status
Simulation time 44785774477 ps
CPU time 33.82 seconds
Started Aug 18 05:57:36 PM PDT 24
Finished Aug 18 05:58:10 PM PDT 24
Peak memory 200888 kb
Host smart-8c099b87-7208-4567-b2bf-e2f60f665fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783072458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3783072458
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3792716678
Short name T278
Test name
Test status
Simulation time 5474349225 ps
CPU time 9.26 seconds
Started Aug 18 05:57:39 PM PDT 24
Finished Aug 18 05:57:48 PM PDT 24
Peak memory 197188 kb
Host smart-939a4cc7-9254-450f-b754-498a84d0f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792716678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3792716678
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1024911739
Short name T29
Test name
Test status
Simulation time 112537447 ps
CPU time 0.82 seconds
Started Aug 18 05:57:40 PM PDT 24
Finished Aug 18 05:57:41 PM PDT 24
Peak memory 218776 kb
Host smart-b65b01d5-ee22-4225-916a-1bebdeba3d21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024911739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1024911739
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2798170570
Short name T930
Test name
Test status
Simulation time 721837973 ps
CPU time 1.59 seconds
Started Aug 18 05:57:38 PM PDT 24
Finished Aug 18 05:57:40 PM PDT 24
Peak memory 199736 kb
Host smart-e94de95a-6635-4418-ad0e-08dda4a360b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798170570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2798170570
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.54070629
Short name T770
Test name
Test status
Simulation time 9688904686 ps
CPU time 32.77 seconds
Started Aug 18 05:57:35 PM PDT 24
Finished Aug 18 05:58:08 PM PDT 24
Peak memory 209388 kb
Host smart-804a3254-495a-4c06-bd08-9ac153a9be27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54070629 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.54070629
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1881256576
Short name T732
Test name
Test status
Simulation time 1941998509 ps
CPU time 1.8 seconds
Started Aug 18 05:57:36 PM PDT 24
Finished Aug 18 05:57:38 PM PDT 24
Peak memory 199648 kb
Host smart-8994db40-5185-41d7-b665-834d77f5587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881256576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1881256576
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3134471229
Short name T772
Test name
Test status
Simulation time 166961095453 ps
CPU time 43.89 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:58:21 PM PDT 24
Peak memory 200808 kb
Host smart-1a097898-dc61-4303-ad31-d7aafb13234f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134471229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3134471229
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.688534735
Short name T1141
Test name
Test status
Simulation time 19989059 ps
CPU time 0.58 seconds
Started Aug 18 05:59:11 PM PDT 24
Finished Aug 18 05:59:12 PM PDT 24
Peak memory 196124 kb
Host smart-60d41d53-bb5d-45d6-bf14-83572b52da06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688534735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.688534735
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.525556737
Short name T1014
Test name
Test status
Simulation time 71946625172 ps
CPU time 116.01 seconds
Started Aug 18 05:59:10 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 200840 kb
Host smart-443eddc3-d66b-4086-b630-c5a92e5c793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525556737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.525556737
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3194717269
Short name T261
Test name
Test status
Simulation time 46479143370 ps
CPU time 98 seconds
Started Aug 18 05:59:10 PM PDT 24
Finished Aug 18 06:00:48 PM PDT 24
Peak memory 200924 kb
Host smart-be3b8aef-e4fc-4682-bacc-10dd12aa4047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194717269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3194717269
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.109049771
Short name T886
Test name
Test status
Simulation time 29568511091 ps
CPU time 54.12 seconds
Started Aug 18 05:59:10 PM PDT 24
Finished Aug 18 06:00:04 PM PDT 24
Peak memory 200840 kb
Host smart-067ae3a8-1f64-4a46-9b80-c48529a38512
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109049771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.109049771
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3541429107
Short name T250
Test name
Test status
Simulation time 290145564632 ps
CPU time 391.72 seconds
Started Aug 18 05:59:10 PM PDT 24
Finished Aug 18 06:05:42 PM PDT 24
Peak memory 200860 kb
Host smart-bea9efcd-280a-4c8e-8278-b7e07bb0e6c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541429107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3541429107
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1811124039
Short name T531
Test name
Test status
Simulation time 6467852320 ps
CPU time 4.02 seconds
Started Aug 18 05:59:12 PM PDT 24
Finished Aug 18 05:59:16 PM PDT 24
Peak memory 200524 kb
Host smart-d5d8683f-b4ce-42a2-a1d4-5ba5d5d35bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811124039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1811124039
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1065406359
Short name T1085
Test name
Test status
Simulation time 155785573373 ps
CPU time 33.65 seconds
Started Aug 18 05:59:10 PM PDT 24
Finished Aug 18 05:59:44 PM PDT 24
Peak memory 209168 kb
Host smart-b58c5d71-a287-4acc-b0af-38d1529a12c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065406359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1065406359
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.750951202
Short name T852
Test name
Test status
Simulation time 9318882758 ps
CPU time 78.23 seconds
Started Aug 18 05:59:12 PM PDT 24
Finished Aug 18 06:00:30 PM PDT 24
Peak memory 200864 kb
Host smart-3448e21c-77bf-4fe7-921f-f31f87fc8cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750951202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.750951202
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.4290355638
Short name T469
Test name
Test status
Simulation time 5074505819 ps
CPU time 10.71 seconds
Started Aug 18 05:59:12 PM PDT 24
Finished Aug 18 05:59:23 PM PDT 24
Peak memory 200024 kb
Host smart-14994e15-8204-49c2-a11d-21a5663556ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290355638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.4290355638
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2853625866
Short name T426
Test name
Test status
Simulation time 42882205476 ps
CPU time 72.99 seconds
Started Aug 18 05:59:12 PM PDT 24
Finished Aug 18 06:00:25 PM PDT 24
Peak memory 200872 kb
Host smart-8d14e0aa-59ce-4da8-8cf2-e6a180bf1906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853625866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2853625866
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.570101146
Short name T500
Test name
Test status
Simulation time 5462935183 ps
CPU time 8.38 seconds
Started Aug 18 05:59:13 PM PDT 24
Finished Aug 18 05:59:22 PM PDT 24
Peak memory 197032 kb
Host smart-c75ac16b-9c7b-4cec-a297-b806a72f590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570101146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.570101146
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.726016320
Short name T80
Test name
Test status
Simulation time 463086415 ps
CPU time 2.2 seconds
Started Aug 18 05:59:11 PM PDT 24
Finished Aug 18 05:59:13 PM PDT 24
Peak memory 199808 kb
Host smart-8029e84f-8bd5-44c3-9da8-f66d0c6d64c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726016320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.726016320
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2743218598
Short name T1061
Test name
Test status
Simulation time 377643669784 ps
CPU time 424.49 seconds
Started Aug 18 05:59:11 PM PDT 24
Finished Aug 18 06:06:16 PM PDT 24
Peak memory 200928 kb
Host smart-dda69547-1715-4b70-a21a-a625739ce4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743218598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2743218598
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3641597529
Short name T370
Test name
Test status
Simulation time 7874252144 ps
CPU time 7.2 seconds
Started Aug 18 05:59:11 PM PDT 24
Finished Aug 18 05:59:18 PM PDT 24
Peak memory 200848 kb
Host smart-6fc06d2a-adf1-43d5-9a2a-5ef593381c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641597529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3641597529
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2495881369
Short name T380
Test name
Test status
Simulation time 20504308174 ps
CPU time 35.82 seconds
Started Aug 18 05:59:10 PM PDT 24
Finished Aug 18 05:59:46 PM PDT 24
Peak memory 200920 kb
Host smart-3f3ba760-3a5f-47ae-bc30-d347c456654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495881369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2495881369
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.899821103
Short name T1041
Test name
Test status
Simulation time 66442901522 ps
CPU time 26.6 seconds
Started Aug 18 06:02:51 PM PDT 24
Finished Aug 18 06:03:18 PM PDT 24
Peak memory 200940 kb
Host smart-5ae5a6e7-5162-455a-b1e9-480b74c57af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899821103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.899821103
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3294037881
Short name T1093
Test name
Test status
Simulation time 42379402963 ps
CPU time 56.96 seconds
Started Aug 18 06:02:49 PM PDT 24
Finished Aug 18 06:03:46 PM PDT 24
Peak memory 200808 kb
Host smart-73cd5bf2-b82a-4558-aa09-2f50fb719409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294037881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3294037881
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1725244290
Short name T222
Test name
Test status
Simulation time 98136808657 ps
CPU time 94.43 seconds
Started Aug 18 06:02:49 PM PDT 24
Finished Aug 18 06:04:23 PM PDT 24
Peak memory 200904 kb
Host smart-3a815ff5-74b4-422b-af67-2942beefad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725244290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1725244290
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1007155200
Short name T1003
Test name
Test status
Simulation time 123930029233 ps
CPU time 209.11 seconds
Started Aug 18 06:02:48 PM PDT 24
Finished Aug 18 06:06:17 PM PDT 24
Peak memory 200908 kb
Host smart-2a86c4ae-130f-4145-93b8-80dcbaba00c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007155200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1007155200
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4048200705
Short name T132
Test name
Test status
Simulation time 39844630801 ps
CPU time 15.36 seconds
Started Aug 18 06:02:49 PM PDT 24
Finished Aug 18 06:03:05 PM PDT 24
Peak memory 200808 kb
Host smart-b2607556-c3c0-43d3-b447-f979481d539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048200705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4048200705
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3320443280
Short name T751
Test name
Test status
Simulation time 29550700399 ps
CPU time 43.44 seconds
Started Aug 18 06:02:49 PM PDT 24
Finished Aug 18 06:03:33 PM PDT 24
Peak memory 200948 kb
Host smart-d641e8be-346e-4c91-81a6-0949ab5582de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320443280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3320443280
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3872035652
Short name T184
Test name
Test status
Simulation time 140175945559 ps
CPU time 212.4 seconds
Started Aug 18 06:02:49 PM PDT 24
Finished Aug 18 06:06:22 PM PDT 24
Peak memory 200836 kb
Host smart-0c640d03-fe67-466c-8453-69c530a5c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872035652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3872035652
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3503350139
Short name T212
Test name
Test status
Simulation time 73012757485 ps
CPU time 56.75 seconds
Started Aug 18 06:02:51 PM PDT 24
Finished Aug 18 06:03:47 PM PDT 24
Peak memory 200892 kb
Host smart-f2ae8800-0273-4e1d-8242-82388af1d0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503350139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3503350139
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3968544356
Short name T918
Test name
Test status
Simulation time 32470801537 ps
CPU time 48.05 seconds
Started Aug 18 06:02:50 PM PDT 24
Finished Aug 18 06:03:38 PM PDT 24
Peak memory 200924 kb
Host smart-d38cfb06-02ae-4a69-bab7-8343dff62af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968544356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3968544356
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2941600586
Short name T962
Test name
Test status
Simulation time 46681951013 ps
CPU time 38.52 seconds
Started Aug 18 06:02:53 PM PDT 24
Finished Aug 18 06:03:32 PM PDT 24
Peak memory 200920 kb
Host smart-ad75ab10-2b2b-45d1-bf3f-900b777f4719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941600586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2941600586
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3768733616
Short name T362
Test name
Test status
Simulation time 15179538 ps
CPU time 0.57 seconds
Started Aug 18 05:59:17 PM PDT 24
Finished Aug 18 05:59:18 PM PDT 24
Peak memory 196236 kb
Host smart-492089ce-f724-4375-a571-700d9e10fc76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768733616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3768733616
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2291909681
Short name T417
Test name
Test status
Simulation time 159453289935 ps
CPU time 409.76 seconds
Started Aug 18 05:59:12 PM PDT 24
Finished Aug 18 06:06:02 PM PDT 24
Peak memory 200932 kb
Host smart-452a6859-7f9b-498c-8134-79a3cdaff8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291909681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2291909681
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.324264727
Short name T505
Test name
Test status
Simulation time 129776018338 ps
CPU time 199.12 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 06:02:37 PM PDT 24
Peak memory 200912 kb
Host smart-c0009c95-549b-4fff-ab7c-5e59ec0b16a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324264727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.324264727
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2631149912
Short name T1173
Test name
Test status
Simulation time 124634059290 ps
CPU time 179.95 seconds
Started Aug 18 05:59:15 PM PDT 24
Finished Aug 18 06:02:15 PM PDT 24
Peak memory 200856 kb
Host smart-70528aec-e165-4c37-acf6-18b5ab170ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631149912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2631149912
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2873859089
Short name T1136
Test name
Test status
Simulation time 4315084790 ps
CPU time 14.06 seconds
Started Aug 18 05:59:17 PM PDT 24
Finished Aug 18 05:59:31 PM PDT 24
Peak memory 200804 kb
Host smart-c8e5cfa0-fac8-4565-85ef-c7cedb883ec8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873859089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2873859089
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2199351400
Short name T920
Test name
Test status
Simulation time 387251761703 ps
CPU time 142.19 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 06:01:40 PM PDT 24
Peak memory 200924 kb
Host smart-522810ee-41e8-4871-9d5d-21405253ef97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199351400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2199351400
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.730911491
Short name T1128
Test name
Test status
Simulation time 8202151034 ps
CPU time 8.33 seconds
Started Aug 18 05:59:16 PM PDT 24
Finished Aug 18 05:59:25 PM PDT 24
Peak memory 200900 kb
Host smart-6341f111-1a5a-4b4b-9c1f-7aa55831fd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730911491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.730911491
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3091915614
Short name T35
Test name
Test status
Simulation time 55651414301 ps
CPU time 42.92 seconds
Started Aug 18 05:59:16 PM PDT 24
Finished Aug 18 05:59:59 PM PDT 24
Peak memory 201060 kb
Host smart-a995b48c-8bbb-48aa-9d07-53bc37df0dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091915614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3091915614
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2655282763
Short name T840
Test name
Test status
Simulation time 11408392691 ps
CPU time 152.69 seconds
Started Aug 18 05:59:17 PM PDT 24
Finished Aug 18 06:01:50 PM PDT 24
Peak memory 200924 kb
Host smart-539ec7b0-9659-4899-943c-ae9c339eb468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655282763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2655282763
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3550201284
Short name T383
Test name
Test status
Simulation time 3490861855 ps
CPU time 6.81 seconds
Started Aug 18 05:59:19 PM PDT 24
Finished Aug 18 05:59:26 PM PDT 24
Peak memory 199452 kb
Host smart-a82d1e03-c2fd-4aa6-b92d-f048f39cdee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550201284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3550201284
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1049187401
Short name T1089
Test name
Test status
Simulation time 79431932128 ps
CPU time 18.15 seconds
Started Aug 18 05:59:19 PM PDT 24
Finished Aug 18 05:59:37 PM PDT 24
Peak memory 200860 kb
Host smart-593a5062-fcbc-4dca-a62f-faa6f7f33fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049187401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1049187401
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.58151124
Short name T818
Test name
Test status
Simulation time 2675974124 ps
CPU time 2.53 seconds
Started Aug 18 05:59:16 PM PDT 24
Finished Aug 18 05:59:19 PM PDT 24
Peak memory 197320 kb
Host smart-531838c2-506d-4301-8fd8-a732a598fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58151124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.58151124
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2883474766
Short name T699
Test name
Test status
Simulation time 987970505 ps
CPU time 3.14 seconds
Started Aug 18 05:59:10 PM PDT 24
Finished Aug 18 05:59:13 PM PDT 24
Peak memory 199828 kb
Host smart-17ca8701-aab9-4be0-b5a1-bb8c6bba7dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883474766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2883474766
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2548777797
Short name T89
Test name
Test status
Simulation time 125221096339 ps
CPU time 102.62 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 06:01:01 PM PDT 24
Peak memory 200836 kb
Host smart-04a7a0e2-39e5-431b-a684-8e0042a848e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548777797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2548777797
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.856903426
Short name T1118
Test name
Test status
Simulation time 33395596988 ps
CPU time 19.85 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 05:59:38 PM PDT 24
Peak memory 210256 kb
Host smart-fb664d0a-354e-49ef-b26a-b23c0fe33716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856903426 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.856903426
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.310546844
Short name T566
Test name
Test status
Simulation time 6144809601 ps
CPU time 14.43 seconds
Started Aug 18 05:59:17 PM PDT 24
Finished Aug 18 05:59:32 PM PDT 24
Peak memory 200768 kb
Host smart-344ef88b-0218-4046-bf32-41a16e38ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310546844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.310546844
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1555475420
Short name T249
Test name
Test status
Simulation time 56542019270 ps
CPU time 82.42 seconds
Started Aug 18 05:59:10 PM PDT 24
Finished Aug 18 06:00:32 PM PDT 24
Peak memory 200908 kb
Host smart-f98be6e6-2218-40bd-a6ef-c59c4b63d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555475420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1555475420
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3737031148
Short name T1031
Test name
Test status
Simulation time 180922556869 ps
CPU time 75.09 seconds
Started Aug 18 06:02:48 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 200868 kb
Host smart-2fcd064c-0c50-4a20-b2bc-4979a15684a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737031148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3737031148
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.4250557709
Short name T8
Test name
Test status
Simulation time 25659188122 ps
CPU time 10.37 seconds
Started Aug 18 06:02:50 PM PDT 24
Finished Aug 18 06:03:00 PM PDT 24
Peak memory 200756 kb
Host smart-a3fc84d0-c6b3-4c56-b98c-ca88f8c1610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250557709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4250557709
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.252288749
Short name T942
Test name
Test status
Simulation time 47440598293 ps
CPU time 14.57 seconds
Started Aug 18 06:02:50 PM PDT 24
Finished Aug 18 06:03:04 PM PDT 24
Peak memory 200876 kb
Host smart-d29bb06e-c631-4197-b53f-c834de43cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252288749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.252288749
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2669910803
Short name T165
Test name
Test status
Simulation time 175601657318 ps
CPU time 81.87 seconds
Started Aug 18 06:02:48 PM PDT 24
Finished Aug 18 06:04:10 PM PDT 24
Peak memory 200916 kb
Host smart-842453ca-4987-484d-b41f-29b647f7004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669910803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2669910803
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.433643714
Short name T771
Test name
Test status
Simulation time 68464529720 ps
CPU time 110.05 seconds
Started Aug 18 06:02:54 PM PDT 24
Finished Aug 18 06:04:44 PM PDT 24
Peak memory 200936 kb
Host smart-6b3a0f21-8fde-4d7e-a8d4-4029863139eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433643714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.433643714
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1603072373
Short name T829
Test name
Test status
Simulation time 30469884173 ps
CPU time 48.65 seconds
Started Aug 18 06:02:47 PM PDT 24
Finished Aug 18 06:03:36 PM PDT 24
Peak memory 200916 kb
Host smart-9978b0a2-3df0-4a87-806f-e9789ab6f6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603072373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1603072373
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3925536353
Short name T544
Test name
Test status
Simulation time 140027769205 ps
CPU time 57.34 seconds
Started Aug 18 06:02:51 PM PDT 24
Finished Aug 18 06:03:48 PM PDT 24
Peak memory 200664 kb
Host smart-b37ed411-d9db-4903-bf65-cd020545bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925536353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3925536353
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.1839030724
Short name T124
Test name
Test status
Simulation time 60243342354 ps
CPU time 21.17 seconds
Started Aug 18 06:03:00 PM PDT 24
Finished Aug 18 06:03:22 PM PDT 24
Peak memory 200668 kb
Host smart-3ef52c1e-a61d-42b0-820f-0a83a158a449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839030724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1839030724
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2343612745
Short name T854
Test name
Test status
Simulation time 19108252299 ps
CPU time 35.76 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:03:35 PM PDT 24
Peak memory 200896 kb
Host smart-7d8649ce-28a3-481d-96b0-ea3acef42e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343612745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2343612745
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3403291795
Short name T879
Test name
Test status
Simulation time 37241999 ps
CPU time 0.55 seconds
Started Aug 18 05:59:25 PM PDT 24
Finished Aug 18 05:59:25 PM PDT 24
Peak memory 196240 kb
Host smart-311d74ac-5001-4249-8cc1-dddb74f85006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403291795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3403291795
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2270232218
Short name T702
Test name
Test status
Simulation time 87566939993 ps
CPU time 125.97 seconds
Started Aug 18 05:59:16 PM PDT 24
Finished Aug 18 06:01:22 PM PDT 24
Peak memory 200932 kb
Host smart-62078495-703f-4bf6-96df-ec287ea4cfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270232218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2270232218
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1802348712
Short name T441
Test name
Test status
Simulation time 17984765012 ps
CPU time 19.29 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 05:59:38 PM PDT 24
Peak memory 200932 kb
Host smart-0fda8928-8fb4-4df7-a570-640cbfacd103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802348712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1802348712
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1544888894
Short name T186
Test name
Test status
Simulation time 26969594972 ps
CPU time 43.3 seconds
Started Aug 18 05:59:17 PM PDT 24
Finished Aug 18 06:00:00 PM PDT 24
Peak memory 200868 kb
Host smart-bd15375f-fea8-485d-b84b-3c86fd3af4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544888894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1544888894
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3554882888
Short name T402
Test name
Test status
Simulation time 257897661635 ps
CPU time 91.07 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 06:00:49 PM PDT 24
Peak memory 200888 kb
Host smart-e533cf4e-54e2-4997-8078-37d8acf5249c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554882888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3554882888
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4170723627
Short name T368
Test name
Test status
Simulation time 209096817331 ps
CPU time 403.36 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 06:06:01 PM PDT 24
Peak memory 200928 kb
Host smart-3205c76c-3569-47ed-92a1-42121f9a842d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170723627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4170723627
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2753766663
Short name T660
Test name
Test status
Simulation time 2442741399 ps
CPU time 1.97 seconds
Started Aug 18 05:59:16 PM PDT 24
Finished Aug 18 05:59:18 PM PDT 24
Peak memory 199668 kb
Host smart-df700a29-38da-425c-92e1-1e4979700c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753766663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2753766663
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.4040727863
Short name T1107
Test name
Test status
Simulation time 145883035375 ps
CPU time 65.32 seconds
Started Aug 18 05:59:19 PM PDT 24
Finished Aug 18 06:00:25 PM PDT 24
Peak memory 201244 kb
Host smart-fc87b15b-56cc-41d9-a55e-c73c974a2923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040727863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.4040727863
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.621454129
Short name T575
Test name
Test status
Simulation time 15146273259 ps
CPU time 443.85 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 06:06:42 PM PDT 24
Peak memory 201104 kb
Host smart-ff36d526-d11d-4367-b9a4-c945ed0bfbdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621454129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.621454129
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.905850564
Short name T700
Test name
Test status
Simulation time 1716123551 ps
CPU time 2 seconds
Started Aug 18 05:59:16 PM PDT 24
Finished Aug 18 05:59:18 PM PDT 24
Peak memory 199188 kb
Host smart-f237bfa1-6a55-43b4-819d-0a6eb41b1548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905850564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.905850564
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.6023523
Short name T155
Test name
Test status
Simulation time 36323903032 ps
CPU time 17.23 seconds
Started Aug 18 05:59:19 PM PDT 24
Finished Aug 18 05:59:36 PM PDT 24
Peak memory 200624 kb
Host smart-962b78e3-e596-4c74-b706-abcdb96b0e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6023523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.6023523
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.272716479
Short name T410
Test name
Test status
Simulation time 2942978109 ps
CPU time 3.24 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 05:59:21 PM PDT 24
Peak memory 197416 kb
Host smart-36d05e10-5ede-4aa2-abac-feeca65c678c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272716479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.272716479
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1760669720
Short name T803
Test name
Test status
Simulation time 955946290 ps
CPU time 1.86 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 05:59:20 PM PDT 24
Peak memory 199196 kb
Host smart-5b5943ee-74e6-4487-8220-aa6582189e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760669720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1760669720
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.835770480
Short name T991
Test name
Test status
Simulation time 392442498464 ps
CPU time 145.44 seconds
Started Aug 18 05:59:24 PM PDT 24
Finished Aug 18 06:01:50 PM PDT 24
Peak memory 200768 kb
Host smart-39f26a0a-dda8-498e-bb66-5c5ea2e468bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835770480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.835770480
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3755879428
Short name T34
Test name
Test status
Simulation time 8792513623 ps
CPU time 28.33 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 06:00:00 PM PDT 24
Peak memory 217132 kb
Host smart-2f9ee34b-e1e2-4f9f-83c2-78d5a6b600e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755879428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3755879428
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3304827504
Short name T391
Test name
Test status
Simulation time 7667619588 ps
CPU time 15.62 seconds
Started Aug 18 05:59:17 PM PDT 24
Finished Aug 18 05:59:33 PM PDT 24
Peak memory 200704 kb
Host smart-642d350a-57d5-4254-bcd2-e0bdc124b537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304827504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3304827504
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3035190819
Short name T739
Test name
Test status
Simulation time 13626072404 ps
CPU time 24.56 seconds
Started Aug 18 05:59:18 PM PDT 24
Finished Aug 18 05:59:43 PM PDT 24
Peak memory 200796 kb
Host smart-630e5023-58e2-4b95-a6d6-88520049bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035190819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3035190819
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.8028092
Short name T1097
Test name
Test status
Simulation time 202521061340 ps
CPU time 31.18 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:03:30 PM PDT 24
Peak memory 200892 kb
Host smart-ac9c47fa-aee2-4cb5-b315-3049f97dc8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8028092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.8028092
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3884643612
Short name T603
Test name
Test status
Simulation time 181589661130 ps
CPU time 77.63 seconds
Started Aug 18 06:03:02 PM PDT 24
Finished Aug 18 06:04:20 PM PDT 24
Peak memory 200928 kb
Host smart-c7ea2a30-7994-42c6-bd26-b10426c6f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884643612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3884643612
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.690322160
Short name T989
Test name
Test status
Simulation time 113729996567 ps
CPU time 78.09 seconds
Started Aug 18 06:02:58 PM PDT 24
Finished Aug 18 06:04:17 PM PDT 24
Peak memory 200828 kb
Host smart-297fc39f-270c-49c4-868f-2c74a64fd725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690322160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.690322160
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1412613553
Short name T203
Test name
Test status
Simulation time 120616955464 ps
CPU time 98.51 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:04:37 PM PDT 24
Peak memory 200912 kb
Host smart-a6c1181d-e5ac-4f73-9906-292879203955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412613553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1412613553
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.667746012
Short name T491
Test name
Test status
Simulation time 19736402025 ps
CPU time 21.93 seconds
Started Aug 18 06:03:03 PM PDT 24
Finished Aug 18 06:03:25 PM PDT 24
Peak memory 200848 kb
Host smart-379edc59-f4aa-4517-b216-7eda59f91b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667746012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.667746012
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2914505152
Short name T446
Test name
Test status
Simulation time 47232427731 ps
CPU time 6.54 seconds
Started Aug 18 06:03:00 PM PDT 24
Finished Aug 18 06:03:07 PM PDT 24
Peak memory 200824 kb
Host smart-f808b2dd-b02a-48c3-a3a5-68caf7208177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914505152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2914505152
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3722155930
Short name T872
Test name
Test status
Simulation time 20408802883 ps
CPU time 32.73 seconds
Started Aug 18 06:03:00 PM PDT 24
Finished Aug 18 06:03:33 PM PDT 24
Peak memory 200860 kb
Host smart-2bc48e7a-c71a-4f96-85d9-3edba6d70ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722155930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3722155930
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3003347150
Short name T198
Test name
Test status
Simulation time 19313864437 ps
CPU time 42.14 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:03:41 PM PDT 24
Peak memory 200752 kb
Host smart-dd8e05f8-111d-4ea3-9d65-1a26dad9d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003347150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3003347150
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3051107312
Short name T650
Test name
Test status
Simulation time 70639843304 ps
CPU time 35.53 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:03:35 PM PDT 24
Peak memory 200936 kb
Host smart-3a45b9c4-402c-4d97-98d1-0a83122aaae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051107312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3051107312
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3752515708
Short name T1168
Test name
Test status
Simulation time 17424004 ps
CPU time 0.54 seconds
Started Aug 18 05:59:23 PM PDT 24
Finished Aug 18 05:59:23 PM PDT 24
Peak memory 196520 kb
Host smart-efa159c4-b05e-4382-a21e-af11cefcbd20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752515708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3752515708
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3495304125
Short name T857
Test name
Test status
Simulation time 45530467151 ps
CPU time 32.96 seconds
Started Aug 18 05:59:24 PM PDT 24
Finished Aug 18 05:59:57 PM PDT 24
Peak memory 200828 kb
Host smart-00fd5861-9cc5-45b7-8227-283aa84fd15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495304125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3495304125
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2510768262
Short name T273
Test name
Test status
Simulation time 73448276766 ps
CPU time 72.3 seconds
Started Aug 18 05:59:26 PM PDT 24
Finished Aug 18 06:00:39 PM PDT 24
Peak memory 200888 kb
Host smart-019b6d67-6006-415d-84d8-ba5c81598f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510768262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2510768262
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3456063376
Short name T880
Test name
Test status
Simulation time 62212623194 ps
CPU time 9.86 seconds
Started Aug 18 05:59:24 PM PDT 24
Finished Aug 18 05:59:34 PM PDT 24
Peak memory 200880 kb
Host smart-31078d27-e592-47fb-9d59-c5df43eb80d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456063376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3456063376
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2064354711
Short name T1074
Test name
Test status
Simulation time 26087340214 ps
CPU time 14.47 seconds
Started Aug 18 05:59:26 PM PDT 24
Finished Aug 18 05:59:41 PM PDT 24
Peak memory 200856 kb
Host smart-b2230f6e-385d-4aa3-ac6e-5cc635f50a9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064354711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2064354711
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2009028939
Short name T311
Test name
Test status
Simulation time 334166840389 ps
CPU time 177.48 seconds
Started Aug 18 05:59:29 PM PDT 24
Finished Aug 18 06:02:27 PM PDT 24
Peak memory 200876 kb
Host smart-67b0bf64-a7aa-4077-a694-17e8a979feb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009028939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2009028939
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1167206546
Short name T1171
Test name
Test status
Simulation time 982806842 ps
CPU time 2.3 seconds
Started Aug 18 05:59:25 PM PDT 24
Finished Aug 18 05:59:27 PM PDT 24
Peak memory 198428 kb
Host smart-fcca83ff-2090-441e-a74d-9f638558ba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167206546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1167206546
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.4227837389
Short name T548
Test name
Test status
Simulation time 49772694150 ps
CPU time 74.51 seconds
Started Aug 18 05:59:23 PM PDT 24
Finished Aug 18 06:00:38 PM PDT 24
Peak memory 199892 kb
Host smart-9d0a0c3e-8889-445e-90ca-0b8442fdf4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227837389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.4227837389
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1936568122
Short name T484
Test name
Test status
Simulation time 28531651385 ps
CPU time 774.2 seconds
Started Aug 18 05:59:25 PM PDT 24
Finished Aug 18 06:12:19 PM PDT 24
Peak memory 200872 kb
Host smart-d057a0d7-b153-491e-8f90-be45f1502659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936568122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1936568122
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1452799652
Short name T766
Test name
Test status
Simulation time 6726168016 ps
CPU time 32.06 seconds
Started Aug 18 05:59:25 PM PDT 24
Finished Aug 18 05:59:57 PM PDT 24
Peak memory 200180 kb
Host smart-24547e75-91bd-4242-bc55-de62816725e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452799652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1452799652
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.405067209
Short name T1096
Test name
Test status
Simulation time 119989619728 ps
CPU time 195.79 seconds
Started Aug 18 05:59:25 PM PDT 24
Finished Aug 18 06:02:41 PM PDT 24
Peak memory 200884 kb
Host smart-98eb1d74-d1f1-417b-b7ef-9f6b7afc71d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405067209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.405067209
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1553474306
Short name T980
Test name
Test status
Simulation time 4848943661 ps
CPU time 2.63 seconds
Started Aug 18 05:59:26 PM PDT 24
Finished Aug 18 05:59:29 PM PDT 24
Peak memory 197024 kb
Host smart-c66e403e-9ac1-4967-82fe-ea9d08ec59af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553474306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1553474306
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2697420459
Short name T949
Test name
Test status
Simulation time 462216954 ps
CPU time 1.41 seconds
Started Aug 18 05:59:24 PM PDT 24
Finished Aug 18 05:59:25 PM PDT 24
Peak memory 199556 kb
Host smart-d8ea6371-d348-495f-8bda-3a1b63bb74b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697420459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2697420459
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.471880260
Short name T1104
Test name
Test status
Simulation time 351619394164 ps
CPU time 528.57 seconds
Started Aug 18 05:59:28 PM PDT 24
Finished Aug 18 06:08:17 PM PDT 24
Peak memory 200936 kb
Host smart-bf08d574-09d7-4f46-8e09-dfd5204c9aee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471880260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.471880260
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3773156467
Short name T988
Test name
Test status
Simulation time 31945152656 ps
CPU time 78.48 seconds
Started Aug 18 05:59:28 PM PDT 24
Finished Aug 18 06:00:46 PM PDT 24
Peak memory 217556 kb
Host smart-f27cfd81-c50b-46bd-a494-1510ee7f51f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773156467 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3773156467
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.185735991
Short name T1169
Test name
Test status
Simulation time 6736514946 ps
CPU time 29.35 seconds
Started Aug 18 05:59:23 PM PDT 24
Finished Aug 18 05:59:52 PM PDT 24
Peak memory 200848 kb
Host smart-e3583250-7cd8-4750-b1c6-e547376b70ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185735991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.185735991
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2569124214
Short name T330
Test name
Test status
Simulation time 37379180971 ps
CPU time 69.05 seconds
Started Aug 18 05:59:24 PM PDT 24
Finished Aug 18 06:00:33 PM PDT 24
Peak memory 200848 kb
Host smart-fcebdcb1-84e0-4942-b6a3-ac783f901a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569124214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2569124214
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2033459290
Short name T40
Test name
Test status
Simulation time 24606566753 ps
CPU time 39.55 seconds
Started Aug 18 06:03:01 PM PDT 24
Finished Aug 18 06:03:40 PM PDT 24
Peak memory 200920 kb
Host smart-bfcb6d07-5718-496d-b13f-5bd2d995bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033459290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2033459290
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3092423773
Short name T881
Test name
Test status
Simulation time 86227700343 ps
CPU time 14.98 seconds
Started Aug 18 06:03:00 PM PDT 24
Finished Aug 18 06:03:15 PM PDT 24
Peak memory 200828 kb
Host smart-99b6b2a8-038b-4e1a-89c2-c27b5246e242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092423773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3092423773
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2324137475
Short name T907
Test name
Test status
Simulation time 111810995461 ps
CPU time 76.57 seconds
Started Aug 18 06:03:00 PM PDT 24
Finished Aug 18 06:04:17 PM PDT 24
Peak memory 200836 kb
Host smart-4d2b3ff5-2c5a-49d5-89a9-756925b0adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324137475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2324137475
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.524497457
Short name T1052
Test name
Test status
Simulation time 16672827003 ps
CPU time 25.85 seconds
Started Aug 18 06:02:57 PM PDT 24
Finished Aug 18 06:03:23 PM PDT 24
Peak memory 200856 kb
Host smart-59c3f493-8781-4709-bae9-4cb4d8290faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524497457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.524497457
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1571043968
Short name T476
Test name
Test status
Simulation time 11097163314 ps
CPU time 28.14 seconds
Started Aug 18 06:03:00 PM PDT 24
Finished Aug 18 06:03:28 PM PDT 24
Peak memory 200924 kb
Host smart-6fbf4763-b9da-4453-bc1f-ccd8be1986fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571043968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1571043968
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1064949092
Short name T850
Test name
Test status
Simulation time 144510948847 ps
CPU time 642.93 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 200896 kb
Host smart-d8161b3d-6eb9-4ba3-9148-f691abf619af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064949092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1064949092
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1914237089
Short name T526
Test name
Test status
Simulation time 30361450019 ps
CPU time 48.57 seconds
Started Aug 18 06:03:00 PM PDT 24
Finished Aug 18 06:03:49 PM PDT 24
Peak memory 200940 kb
Host smart-e1d8a4a3-edae-443c-ab8e-8bd0255fbcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914237089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1914237089
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2181492419
Short name T635
Test name
Test status
Simulation time 10637635827 ps
CPU time 4.56 seconds
Started Aug 18 06:02:58 PM PDT 24
Finished Aug 18 06:03:02 PM PDT 24
Peak memory 200572 kb
Host smart-abd19722-4323-4b62-8d80-bcd27eea12a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181492419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2181492419
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1911010118
Short name T905
Test name
Test status
Simulation time 23221491940 ps
CPU time 10.09 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:03:10 PM PDT 24
Peak memory 200504 kb
Host smart-919e33fd-4639-4d03-b2bc-c801d2262736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911010118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1911010118
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3103979520
Short name T1167
Test name
Test status
Simulation time 22310260 ps
CPU time 0.55 seconds
Started Aug 18 05:59:35 PM PDT 24
Finished Aug 18 05:59:36 PM PDT 24
Peak memory 196532 kb
Host smart-913e9129-b0c1-4b47-9b2e-5fb930e9fb88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103979520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3103979520
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.628586230
Short name T1076
Test name
Test status
Simulation time 240828772900 ps
CPU time 482.94 seconds
Started Aug 18 05:59:25 PM PDT 24
Finished Aug 18 06:07:28 PM PDT 24
Peak memory 200816 kb
Host smart-e86f1df2-a1ad-4fdb-9917-329c56b434a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628586230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.628586230
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2147679534
Short name T765
Test name
Test status
Simulation time 118780945763 ps
CPU time 252.89 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 06:03:45 PM PDT 24
Peak memory 200860 kb
Host smart-e8659306-4686-4cce-a5b9-c9b03ef1ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147679534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2147679534
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2380237927
Short name T1025
Test name
Test status
Simulation time 102546624982 ps
CPU time 111.61 seconds
Started Aug 18 05:59:33 PM PDT 24
Finished Aug 18 06:01:24 PM PDT 24
Peak memory 200812 kb
Host smart-bc6e0a3b-4024-42e3-9614-dfd7c0145ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380237927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2380237927
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.849427288
Short name T888
Test name
Test status
Simulation time 56305005593 ps
CPU time 14.33 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 05:59:48 PM PDT 24
Peak memory 200728 kb
Host smart-d6ff93e0-fe2a-4d0e-9024-10209f9936ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849427288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.849427288
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4254964789
Short name T1101
Test name
Test status
Simulation time 59902887591 ps
CPU time 599.83 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 06:09:32 PM PDT 24
Peak memory 200924 kb
Host smart-78630a36-cb3c-4100-9eeb-b79531e51e93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254964789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4254964789
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3717671535
Short name T431
Test name
Test status
Simulation time 5281295766 ps
CPU time 9.79 seconds
Started Aug 18 05:59:35 PM PDT 24
Finished Aug 18 05:59:44 PM PDT 24
Peak memory 200832 kb
Host smart-4fa0da58-1143-483c-994b-b2f4d4882b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717671535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3717671535
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3327734289
Short name T932
Test name
Test status
Simulation time 68589326290 ps
CPU time 121.01 seconds
Started Aug 18 05:59:33 PM PDT 24
Finished Aug 18 06:01:34 PM PDT 24
Peak memory 209132 kb
Host smart-9aafbee3-4d20-47af-9cf6-8e41ed6b38d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327734289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3327734289
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1911425002
Short name T507
Test name
Test status
Simulation time 21927940826 ps
CPU time 1146.78 seconds
Started Aug 18 05:59:33 PM PDT 24
Finished Aug 18 06:18:40 PM PDT 24
Peak memory 200932 kb
Host smart-cf05b9b3-cbd2-4af3-b653-4f04989ec766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911425002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1911425002
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1905600440
Short name T344
Test name
Test status
Simulation time 5260520444 ps
CPU time 10.46 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 05:59:42 PM PDT 24
Peak memory 200180 kb
Host smart-21fca3c4-12c8-43e8-b7a9-a4f054d9ed36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905600440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1905600440
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3495617365
Short name T67
Test name
Test status
Simulation time 31795823519 ps
CPU time 46.97 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 06:00:22 PM PDT 24
Peak memory 200848 kb
Host smart-284992d0-93d6-4c07-bc9f-b5c494d92a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495617365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3495617365
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3155635337
Short name T353
Test name
Test status
Simulation time 4122040438 ps
CPU time 6.92 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 05:59:41 PM PDT 24
Peak memory 197400 kb
Host smart-250a9434-f969-46e8-8876-5d12b4b4f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155635337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3155635337
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1287826994
Short name T752
Test name
Test status
Simulation time 908533597 ps
CPU time 2.34 seconds
Started Aug 18 05:59:26 PM PDT 24
Finished Aug 18 05:59:29 PM PDT 24
Peak memory 199884 kb
Host smart-3d0e2cb5-ed6c-47ea-a3bc-8e0d7dc52c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287826994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1287826994
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3320908670
Short name T960
Test name
Test status
Simulation time 4376801970 ps
CPU time 28.1 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 06:00:02 PM PDT 24
Peak memory 209124 kb
Host smart-de6ee8ea-e2cd-4d16-ab88-2a2b8cecb8f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320908670 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3320908670
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1530786773
Short name T408
Test name
Test status
Simulation time 6829569263 ps
CPU time 13.8 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 05:59:48 PM PDT 24
Peak memory 200748 kb
Host smart-eeab93b1-2666-4624-9262-4efb2918301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530786773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1530786773
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2814688137
Short name T42
Test name
Test status
Simulation time 215785493773 ps
CPU time 46.59 seconds
Started Aug 18 05:59:22 PM PDT 24
Finished Aug 18 06:00:09 PM PDT 24
Peak memory 200880 kb
Host smart-6dba1b05-2d67-4c76-b3c4-60d49cb56b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814688137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2814688137
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3178780700
Short name T502
Test name
Test status
Simulation time 44137046524 ps
CPU time 82.07 seconds
Started Aug 18 06:02:59 PM PDT 24
Finished Aug 18 06:04:21 PM PDT 24
Peak memory 200832 kb
Host smart-756e1b0f-8be0-4454-a6ad-3711ce2bbfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178780700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3178780700
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.4060521418
Short name T663
Test name
Test status
Simulation time 103747304342 ps
CPU time 59.45 seconds
Started Aug 18 06:03:02 PM PDT 24
Finished Aug 18 06:04:01 PM PDT 24
Peak memory 200912 kb
Host smart-1d0ea866-0e29-49d1-99cf-a74620981e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060521418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4060521418
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.726810582
Short name T1021
Test name
Test status
Simulation time 71345180849 ps
CPU time 62.47 seconds
Started Aug 18 06:03:12 PM PDT 24
Finished Aug 18 06:04:14 PM PDT 24
Peak memory 200948 kb
Host smart-037b8f9d-65ca-44ad-aecd-0db9e0d30475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726810582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.726810582
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1607530303
Short name T711
Test name
Test status
Simulation time 8113054765 ps
CPU time 14.83 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:03:26 PM PDT 24
Peak memory 200940 kb
Host smart-293a8b8c-d670-49e8-9017-1bc0f68ee628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607530303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1607530303
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3811820979
Short name T726
Test name
Test status
Simulation time 57607032298 ps
CPU time 178.31 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:06:09 PM PDT 24
Peak memory 200848 kb
Host smart-3ae88c02-e72a-4592-8e8b-0c8890e8983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811820979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3811820979
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2364813785
Short name T1034
Test name
Test status
Simulation time 93907038118 ps
CPU time 66.15 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:04:18 PM PDT 24
Peak memory 200880 kb
Host smart-f9ff78b2-a31b-45a1-a558-39ccc51abe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364813785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2364813785
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.792097776
Short name T1181
Test name
Test status
Simulation time 19167865207 ps
CPU time 35.58 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:03:47 PM PDT 24
Peak memory 200936 kb
Host smart-dace4fc9-2acc-4658-84e5-33e855200359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792097776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.792097776
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2499209706
Short name T182
Test name
Test status
Simulation time 8304343096 ps
CPU time 13.54 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:03:25 PM PDT 24
Peak memory 200912 kb
Host smart-58663fed-f418-4499-b2b4-f54e5da11ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499209706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2499209706
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4015224769
Short name T781
Test name
Test status
Simulation time 26700119 ps
CPU time 0.56 seconds
Started Aug 18 05:59:31 PM PDT 24
Finished Aug 18 05:59:32 PM PDT 24
Peak memory 196244 kb
Host smart-bcc513b5-6a8b-41b9-b86b-29024df6f8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015224769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4015224769
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3538499759
Short name T517
Test name
Test status
Simulation time 84238863137 ps
CPU time 170.63 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 06:02:22 PM PDT 24
Peak memory 200912 kb
Host smart-ddd3b674-a1c1-47e9-b38b-3bfb2417276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538499759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3538499759
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2034651742
Short name T294
Test name
Test status
Simulation time 160241377059 ps
CPU time 92.66 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 06:01:05 PM PDT 24
Peak memory 200800 kb
Host smart-1dff75e6-6da4-4181-828a-d5748ede49eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034651742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2034651742
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.2627074731
Short name T1154
Test name
Test status
Simulation time 97516805324 ps
CPU time 86.57 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 06:01:00 PM PDT 24
Peak memory 200872 kb
Host smart-697f4c04-6df6-48df-acd6-577e751d804e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627074731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2627074731
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.547474123
Short name T1175
Test name
Test status
Simulation time 211599946564 ps
CPU time 158.63 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 06:02:10 PM PDT 24
Peak memory 200896 kb
Host smart-623703aa-5b94-4e2b-a8da-33baecba17c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547474123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.547474123
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.4202543628
Short name T710
Test name
Test status
Simulation time 4071254740 ps
CPU time 5.76 seconds
Started Aug 18 05:59:40 PM PDT 24
Finished Aug 18 05:59:46 PM PDT 24
Peak memory 199744 kb
Host smart-4ec08805-028b-4773-b1b0-fa469d239e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202543628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.4202543628
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.810980378
Short name T929
Test name
Test status
Simulation time 81832777380 ps
CPU time 36.29 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 06:00:11 PM PDT 24
Peak memory 200136 kb
Host smart-e02d75fc-09ca-4f1e-b0f0-112ae850bc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810980378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.810980378
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1212689509
Short name T759
Test name
Test status
Simulation time 8609858000 ps
CPU time 451.18 seconds
Started Aug 18 05:59:33 PM PDT 24
Finished Aug 18 06:07:04 PM PDT 24
Peak memory 200836 kb
Host smart-bf19d795-ded9-4947-845f-e1cbf0ed5a6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212689509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1212689509
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.18232085
Short name T622
Test name
Test status
Simulation time 4247300128 ps
CPU time 31.48 seconds
Started Aug 18 05:59:33 PM PDT 24
Finished Aug 18 06:00:04 PM PDT 24
Peak memory 199576 kb
Host smart-f0822242-5cca-4efb-8191-f88bb918d6b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18232085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.18232085
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2554344447
Short name T122
Test name
Test status
Simulation time 37235220953 ps
CPU time 64.84 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 06:00:39 PM PDT 24
Peak memory 200864 kb
Host smart-232aae81-8d8d-4a53-b60e-891570b0511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554344447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2554344447
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2019679992
Short name T619
Test name
Test status
Simulation time 5656804275 ps
CPU time 9.03 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 05:59:48 PM PDT 24
Peak memory 197072 kb
Host smart-36092131-bb83-40fa-b8f2-15171e970fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019679992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2019679992
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3449714021
Short name T685
Test name
Test status
Simulation time 5747881096 ps
CPU time 18.27 seconds
Started Aug 18 05:59:32 PM PDT 24
Finished Aug 18 05:59:50 PM PDT 24
Peak memory 200228 kb
Host smart-68e9fe54-ca1a-4fa9-ba6f-00c2bfd2d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449714021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3449714021
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.964054778
Short name T997
Test name
Test status
Simulation time 843285140995 ps
CPU time 175.44 seconds
Started Aug 18 05:59:36 PM PDT 24
Finished Aug 18 06:02:31 PM PDT 24
Peak memory 209352 kb
Host smart-836cadcb-ff16-4721-8f96-ec2c6dd1e9db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964054778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.964054778
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.176042116
Short name T906
Test name
Test status
Simulation time 5485213252 ps
CPU time 39.42 seconds
Started Aug 18 05:59:33 PM PDT 24
Finished Aug 18 06:00:13 PM PDT 24
Peak memory 209444 kb
Host smart-999e39d0-557b-4c84-8f0f-7112fe96dfae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176042116 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.176042116
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1085797047
Short name T761
Test name
Test status
Simulation time 6865669439 ps
CPU time 24.52 seconds
Started Aug 18 05:59:34 PM PDT 24
Finished Aug 18 05:59:58 PM PDT 24
Peak memory 200688 kb
Host smart-bd34f8f0-46d2-4da8-85e3-a00d926a2d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085797047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1085797047
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.662446916
Short name T1114
Test name
Test status
Simulation time 89429276260 ps
CPU time 37.4 seconds
Started Aug 18 05:59:35 PM PDT 24
Finished Aug 18 06:00:13 PM PDT 24
Peak memory 200916 kb
Host smart-30495859-e0fc-4050-bc90-4b2a58325649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662446916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.662446916
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1028380920
Short name T11
Test name
Test status
Simulation time 58314459922 ps
CPU time 24.57 seconds
Started Aug 18 06:03:13 PM PDT 24
Finished Aug 18 06:03:38 PM PDT 24
Peak memory 200848 kb
Host smart-8f4281dd-7648-406a-89fb-391423fe89f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028380920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1028380920
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3655891081
Short name T557
Test name
Test status
Simulation time 15267781176 ps
CPU time 13.25 seconds
Started Aug 18 06:03:13 PM PDT 24
Finished Aug 18 06:03:26 PM PDT 24
Peak memory 199440 kb
Host smart-4dfe93ed-7d13-48db-bdc5-09c928e3cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655891081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3655891081
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1360693021
Short name T201
Test name
Test status
Simulation time 62802080737 ps
CPU time 101.01 seconds
Started Aug 18 06:03:08 PM PDT 24
Finished Aug 18 06:04:49 PM PDT 24
Peak memory 200844 kb
Host smart-f2de00d9-eaf6-4a09-a638-b05fa4cd5423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360693021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1360693021
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3235301993
Short name T1055
Test name
Test status
Simulation time 43173961438 ps
CPU time 32.99 seconds
Started Aug 18 06:03:09 PM PDT 24
Finished Aug 18 06:03:42 PM PDT 24
Peak memory 200908 kb
Host smart-19566fcc-e94c-4d92-a564-2d92d906f6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235301993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3235301993
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3105228065
Short name T187
Test name
Test status
Simulation time 115276888861 ps
CPU time 94.5 seconds
Started Aug 18 06:03:13 PM PDT 24
Finished Aug 18 06:04:47 PM PDT 24
Peak memory 200820 kb
Host smart-1d298d46-e3eb-4214-a241-4503e6d6e552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105228065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3105228065
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3423267980
Short name T151
Test name
Test status
Simulation time 17929165565 ps
CPU time 29.08 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:03:39 PM PDT 24
Peak memory 200908 kb
Host smart-847840a9-fdeb-47b0-a420-0652e5f32535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423267980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3423267980
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1754471581
Short name T120
Test name
Test status
Simulation time 100578132614 ps
CPU time 60.91 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:04:11 PM PDT 24
Peak memory 200908 kb
Host smart-542c2787-1744-4bd0-b28a-5943cec2f7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754471581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1754471581
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3429624827
Short name T65
Test name
Test status
Simulation time 10591247772 ps
CPU time 19.2 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:03:30 PM PDT 24
Peak memory 200832 kb
Host smart-d4755926-822e-4aad-9bfd-9265cf020769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429624827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3429624827
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3667207693
Short name T99
Test name
Test status
Simulation time 31956360192 ps
CPU time 27.42 seconds
Started Aug 18 06:03:09 PM PDT 24
Finished Aug 18 06:03:36 PM PDT 24
Peak memory 200852 kb
Host smart-b1ceb3ca-a5a1-4305-831c-2b00c67b6c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667207693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3667207693
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2994295533
Short name T602
Test name
Test status
Simulation time 73093669986 ps
CPU time 257.66 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:07:28 PM PDT 24
Peak memory 200868 kb
Host smart-f21d4f67-f87a-4d98-8a6b-f937dc0c4b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994295533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2994295533
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2691190642
Short name T869
Test name
Test status
Simulation time 14676832 ps
CPU time 0.58 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 05:59:39 PM PDT 24
Peak memory 196228 kb
Host smart-65e75ab5-5072-411e-b5b5-c518cc71961e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691190642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2691190642
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3655646499
Short name T419
Test name
Test status
Simulation time 62157789528 ps
CPU time 91.37 seconds
Started Aug 18 05:59:40 PM PDT 24
Finished Aug 18 06:01:11 PM PDT 24
Peak memory 200872 kb
Host smart-796af1b6-8291-4596-8b53-671b93cf9ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655646499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3655646499
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4090511308
Short name T152
Test name
Test status
Simulation time 26567864971 ps
CPU time 14.48 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 05:59:54 PM PDT 24
Peak memory 200536 kb
Host smart-4108e923-0c92-4dc8-b12c-d8ee04f4ea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090511308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4090511308
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1454426321
Short name T539
Test name
Test status
Simulation time 26776808153 ps
CPU time 49.33 seconds
Started Aug 18 05:59:41 PM PDT 24
Finished Aug 18 06:00:30 PM PDT 24
Peak memory 200916 kb
Host smart-d139b6da-6d3d-4d86-8f83-e3b4ff0527db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454426321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1454426321
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.800164035
Short name T1027
Test name
Test status
Simulation time 264047291432 ps
CPU time 102.74 seconds
Started Aug 18 05:59:43 PM PDT 24
Finished Aug 18 06:01:26 PM PDT 24
Peak memory 200708 kb
Host smart-90564f57-bbd9-4122-a16f-038558e0c5a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800164035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.800164035
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3541954278
Short name T807
Test name
Test status
Simulation time 110263052923 ps
CPU time 777.69 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 06:12:37 PM PDT 24
Peak memory 200828 kb
Host smart-41fd95f1-e0b7-40a1-be13-b19450fa7528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541954278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3541954278
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2516009530
Short name T369
Test name
Test status
Simulation time 8028969186 ps
CPU time 9.53 seconds
Started Aug 18 05:59:44 PM PDT 24
Finished Aug 18 05:59:54 PM PDT 24
Peak memory 200772 kb
Host smart-7dbce479-01c0-4384-9284-8d2cbde5d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516009530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2516009530
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3966387985
Short name T258
Test name
Test status
Simulation time 101485159828 ps
CPU time 56.15 seconds
Started Aug 18 05:59:42 PM PDT 24
Finished Aug 18 06:00:38 PM PDT 24
Peak memory 201116 kb
Host smart-bb32062e-5368-4f1b-9966-47109b2cd810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966387985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3966387985
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2233259920
Short name T998
Test name
Test status
Simulation time 7365874746 ps
CPU time 167.71 seconds
Started Aug 18 05:59:43 PM PDT 24
Finished Aug 18 06:02:31 PM PDT 24
Peak memory 200928 kb
Host smart-a81840b7-04d0-4055-9e43-c8f77cd68394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233259920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2233259920
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2382027137
Short name T570
Test name
Test status
Simulation time 5139559505 ps
CPU time 22.15 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 06:00:01 PM PDT 24
Peak memory 200412 kb
Host smart-39e2fce6-19e5-44d2-a1b4-14dd907ef662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382027137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2382027137
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2947953548
Short name T687
Test name
Test status
Simulation time 25994739928 ps
CPU time 42.62 seconds
Started Aug 18 05:59:43 PM PDT 24
Finished Aug 18 06:00:26 PM PDT 24
Peak memory 200944 kb
Host smart-980d9783-35f8-4e15-9be7-db6a3b8a8146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947953548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2947953548
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1642769922
Short name T917
Test name
Test status
Simulation time 37805319599 ps
CPU time 47.95 seconds
Started Aug 18 05:59:45 PM PDT 24
Finished Aug 18 06:00:33 PM PDT 24
Peak memory 196848 kb
Host smart-c40de638-ee26-46d9-a96a-822011a823ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642769922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1642769922
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.546325241
Short name T782
Test name
Test status
Simulation time 5377822107 ps
CPU time 5.64 seconds
Started Aug 18 05:59:40 PM PDT 24
Finished Aug 18 05:59:46 PM PDT 24
Peak memory 200224 kb
Host smart-5594c173-42ba-4d36-8213-624b3a654be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546325241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.546325241
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1639237416
Short name T84
Test name
Test status
Simulation time 3521803400 ps
CPU time 42.85 seconds
Started Aug 18 05:59:41 PM PDT 24
Finished Aug 18 06:00:23 PM PDT 24
Peak memory 217308 kb
Host smart-60c09adb-4a69-44df-81e4-db24a925f6c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639237416 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1639237416
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1112997306
Short name T1111
Test name
Test status
Simulation time 6256083871 ps
CPU time 30.79 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 06:00:10 PM PDT 24
Peak memory 200928 kb
Host smart-7da5d0ea-68c3-41e4-8577-be7579cfcd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112997306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1112997306
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.548090288
Short name T98
Test name
Test status
Simulation time 36915846075 ps
CPU time 15.57 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 05:59:55 PM PDT 24
Peak memory 200860 kb
Host smart-b4dcff0a-be44-43f1-9970-9d07d5228ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548090288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.548090288
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2109095803
Short name T1077
Test name
Test status
Simulation time 113070093674 ps
CPU time 186.87 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:06:17 PM PDT 24
Peak memory 200836 kb
Host smart-fe4de8ea-9a22-47bd-bb68-78a620557c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109095803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2109095803
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2187747180
Short name T670
Test name
Test status
Simulation time 88093065371 ps
CPU time 40.67 seconds
Started Aug 18 06:03:12 PM PDT 24
Finished Aug 18 06:03:53 PM PDT 24
Peak memory 200944 kb
Host smart-32168858-83a4-4b1a-922a-9469d1cea775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187747180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2187747180
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2972411386
Short name T140
Test name
Test status
Simulation time 80997152996 ps
CPU time 33.17 seconds
Started Aug 18 06:03:12 PM PDT 24
Finished Aug 18 06:03:46 PM PDT 24
Peak memory 200912 kb
Host smart-892325ac-00fd-48d4-a8b9-f71ba0321b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972411386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2972411386
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2820440872
Short name T244
Test name
Test status
Simulation time 166328025319 ps
CPU time 145.99 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:05:36 PM PDT 24
Peak memory 200932 kb
Host smart-61a69e0c-78e3-4c13-9fa2-a2546231947a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820440872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2820440872
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1123292258
Short name T194
Test name
Test status
Simulation time 135928533206 ps
CPU time 188.61 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:06:19 PM PDT 24
Peak memory 200928 kb
Host smart-7d429d70-c531-4f3a-8daf-336f0ab79286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123292258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1123292258
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3215004533
Short name T223
Test name
Test status
Simulation time 58896165037 ps
CPU time 21.12 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:03:33 PM PDT 24
Peak memory 200916 kb
Host smart-705affac-c685-4b0e-903c-db919d187805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215004533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3215004533
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2615882375
Short name T118
Test name
Test status
Simulation time 58987511549 ps
CPU time 97.76 seconds
Started Aug 18 06:03:12 PM PDT 24
Finished Aug 18 06:04:50 PM PDT 24
Peak memory 200824 kb
Host smart-f43e13ec-5323-4e9f-9a12-e424d478e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615882375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2615882375
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2725991191
Short name T853
Test name
Test status
Simulation time 7205567541 ps
CPU time 9.85 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:03:20 PM PDT 24
Peak memory 200944 kb
Host smart-0ef3524c-fb22-4ce0-9d7c-4a42a4d202bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725991191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2725991191
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3991927084
Short name T649
Test name
Test status
Simulation time 11819084907 ps
CPU time 24.21 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:03:35 PM PDT 24
Peak memory 200856 kb
Host smart-64737e4d-1187-4848-9b74-0015110adbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991927084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3991927084
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3683564334
Short name T337
Test name
Test status
Simulation time 34933760 ps
CPU time 0.58 seconds
Started Aug 18 05:59:48 PM PDT 24
Finished Aug 18 05:59:49 PM PDT 24
Peak memory 196244 kb
Host smart-cf0b6b3e-5616-4561-919d-9ae823ade7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683564334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3683564334
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.225384805
Short name T894
Test name
Test status
Simulation time 33665287686 ps
CPU time 38.18 seconds
Started Aug 18 05:59:43 PM PDT 24
Finished Aug 18 06:00:22 PM PDT 24
Peak memory 200860 kb
Host smart-7f8b1070-e0df-4745-bbf1-bf13b5d0e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225384805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.225384805
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2825848925
Short name T142
Test name
Test status
Simulation time 47200700139 ps
CPU time 81.18 seconds
Started Aug 18 05:59:42 PM PDT 24
Finished Aug 18 06:01:03 PM PDT 24
Peak memory 200896 kb
Host smart-d447941f-efa8-43ec-9d63-22cf6e2bec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825848925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2825848925
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1162571050
Short name T365
Test name
Test status
Simulation time 84965514886 ps
CPU time 34.87 seconds
Started Aug 18 05:59:40 PM PDT 24
Finished Aug 18 06:00:15 PM PDT 24
Peak memory 199492 kb
Host smart-16d5baac-55ab-4ce2-9703-d4b4bc7f1ffd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162571050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1162571050
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_loopback.3518180254
Short name T632
Test name
Test status
Simulation time 2363840502 ps
CPU time 0.89 seconds
Started Aug 18 05:59:48 PM PDT 24
Finished Aug 18 05:59:49 PM PDT 24
Peak memory 197080 kb
Host smart-d4b6f9ac-c032-476e-abec-6b1e745504aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518180254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3518180254
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3457176353
Short name T824
Test name
Test status
Simulation time 29414598880 ps
CPU time 48.28 seconds
Started Aug 18 05:59:40 PM PDT 24
Finished Aug 18 06:00:28 PM PDT 24
Peak memory 200740 kb
Host smart-aae63e05-462b-459c-a92a-1fc25e98f82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457176353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3457176353
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2929637427
Short name T485
Test name
Test status
Simulation time 31433919993 ps
CPU time 867.74 seconds
Started Aug 18 05:59:47 PM PDT 24
Finished Aug 18 06:14:15 PM PDT 24
Peak memory 200916 kb
Host smart-6740aae7-febd-4903-b1a5-e0451655eafb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929637427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2929637427
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.988825021
Short name T616
Test name
Test status
Simulation time 5485433471 ps
CPU time 45.75 seconds
Started Aug 18 05:59:44 PM PDT 24
Finished Aug 18 06:00:29 PM PDT 24
Peak memory 200056 kb
Host smart-c9785412-8983-4bd2-87ae-58fad59e8bca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988825021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.988825021
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3000123483
Short name T648
Test name
Test status
Simulation time 30877413995 ps
CPU time 25.48 seconds
Started Aug 18 05:59:44 PM PDT 24
Finished Aug 18 06:00:10 PM PDT 24
Peak memory 200860 kb
Host smart-70751336-18c6-45f7-bfe8-022a201eb6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000123483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3000123483
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.981574807
Short name T1000
Test name
Test status
Simulation time 4714873203 ps
CPU time 4.15 seconds
Started Aug 18 05:59:40 PM PDT 24
Finished Aug 18 05:59:45 PM PDT 24
Peak memory 197312 kb
Host smart-1fa8542c-a9b1-4ab0-88a8-0dc779b25981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981574807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.981574807
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3461153735
Short name T1013
Test name
Test status
Simulation time 481483710 ps
CPU time 1.71 seconds
Started Aug 18 05:59:39 PM PDT 24
Finished Aug 18 05:59:41 PM PDT 24
Peak memory 199320 kb
Host smart-02b6f9f4-77da-4c10-8bf7-6b1a5af3f025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461153735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3461153735
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.383562653
Short name T360
Test name
Test status
Simulation time 1221615254 ps
CPU time 1.25 seconds
Started Aug 18 05:59:40 PM PDT 24
Finished Aug 18 05:59:42 PM PDT 24
Peak memory 198860 kb
Host smart-863ec13e-f3ff-42b0-b864-a43891064d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383562653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.383562653
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.673851367
Short name T357
Test name
Test status
Simulation time 7677535117 ps
CPU time 12.28 seconds
Started Aug 18 05:59:42 PM PDT 24
Finished Aug 18 05:59:55 PM PDT 24
Peak memory 200588 kb
Host smart-f1b47559-cbc0-451b-a75b-182eeb80888f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673851367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.673851367
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.733564880
Short name T694
Test name
Test status
Simulation time 149391385979 ps
CPU time 115.35 seconds
Started Aug 18 06:03:09 PM PDT 24
Finished Aug 18 06:05:05 PM PDT 24
Peak memory 200916 kb
Host smart-baf4512c-317e-4d6f-8256-c76333a51513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733564880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.733564880
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2821311395
Short name T1069
Test name
Test status
Simulation time 34101316694 ps
CPU time 18.86 seconds
Started Aug 18 06:03:11 PM PDT 24
Finished Aug 18 06:03:30 PM PDT 24
Peak memory 200936 kb
Host smart-16b7c069-5f28-4465-987f-ecdfb7d798ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821311395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2821311395
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1174904773
Short name T737
Test name
Test status
Simulation time 102652744075 ps
CPU time 47.68 seconds
Started Aug 18 06:03:09 PM PDT 24
Finished Aug 18 06:03:57 PM PDT 24
Peak memory 200704 kb
Host smart-cbc34970-6763-4777-a4b7-cd3b3fa8ea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174904773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1174904773
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3045389614
Short name T501
Test name
Test status
Simulation time 110566123682 ps
CPU time 373.5 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:09:23 PM PDT 24
Peak memory 200912 kb
Host smart-08806ba9-0fc7-464f-be40-8e6c25647081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045389614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3045389614
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1780340802
Short name T805
Test name
Test status
Simulation time 39455480948 ps
CPU time 21.59 seconds
Started Aug 18 06:03:13 PM PDT 24
Finished Aug 18 06:03:34 PM PDT 24
Peak memory 200820 kb
Host smart-d524385f-86cf-4e2a-a696-902e88e55455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780340802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1780340802
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.902894141
Short name T148
Test name
Test status
Simulation time 69234324326 ps
CPU time 42.74 seconds
Started Aug 18 06:03:08 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 200928 kb
Host smart-5096fce7-2fb2-4dea-bf41-80558db69396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902894141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.902894141
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.597238187
Short name T540
Test name
Test status
Simulation time 53896838924 ps
CPU time 105.33 seconds
Started Aug 18 06:03:12 PM PDT 24
Finished Aug 18 06:04:58 PM PDT 24
Peak memory 200912 kb
Host smart-1831f481-7b33-44f7-a0dc-b2e7d99987cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597238187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.597238187
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2129232439
Short name T729
Test name
Test status
Simulation time 9199630873 ps
CPU time 15.37 seconds
Started Aug 18 06:03:12 PM PDT 24
Finished Aug 18 06:03:28 PM PDT 24
Peak memory 200800 kb
Host smart-45375203-0ea0-4c5a-ae62-146ae4881f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129232439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2129232439
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2076348425
Short name T1086
Test name
Test status
Simulation time 79162602759 ps
CPU time 42.37 seconds
Started Aug 18 06:03:13 PM PDT 24
Finished Aug 18 06:03:55 PM PDT 24
Peak memory 200904 kb
Host smart-6713cf40-d995-451a-be10-9150a83fd09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076348425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2076348425
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.523575490
Short name T26
Test name
Test status
Simulation time 13723779 ps
CPU time 0.55 seconds
Started Aug 18 05:59:49 PM PDT 24
Finished Aug 18 05:59:50 PM PDT 24
Peak memory 196184 kb
Host smart-192fb6fc-6529-40d9-80a1-52842c7ec8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523575490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.523575490
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3534259126
Short name T1083
Test name
Test status
Simulation time 229009756968 ps
CPU time 135.78 seconds
Started Aug 18 05:59:50 PM PDT 24
Finished Aug 18 06:02:06 PM PDT 24
Peak memory 200864 kb
Host smart-68473034-70e8-4899-be36-402f5d8af215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534259126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3534259126
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1099675774
Short name T137
Test name
Test status
Simulation time 43206374586 ps
CPU time 21.95 seconds
Started Aug 18 05:59:49 PM PDT 24
Finished Aug 18 06:00:11 PM PDT 24
Peak memory 200912 kb
Host smart-9eb3b548-6710-4cb4-a334-ef08555e8c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099675774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1099675774
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4006239618
Short name T301
Test name
Test status
Simulation time 83251792387 ps
CPU time 32.36 seconds
Started Aug 18 05:59:51 PM PDT 24
Finished Aug 18 06:00:23 PM PDT 24
Peak memory 200908 kb
Host smart-24b992fb-9243-49d6-a657-6813462e6313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006239618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4006239618
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1237317781
Short name T736
Test name
Test status
Simulation time 6139518551 ps
CPU time 24.13 seconds
Started Aug 18 05:59:48 PM PDT 24
Finished Aug 18 06:00:13 PM PDT 24
Peak memory 200772 kb
Host smart-e790a17b-2c5c-42a9-ba44-cfefea14c534
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237317781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1237317781
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3160257840
Short name T452
Test name
Test status
Simulation time 199734785123 ps
CPU time 1271.49 seconds
Started Aug 18 05:59:48 PM PDT 24
Finished Aug 18 06:21:00 PM PDT 24
Peak memory 200936 kb
Host smart-251b6d04-1510-454b-87a4-23fbe1258317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160257840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3160257840
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2032070259
Short name T17
Test name
Test status
Simulation time 4132745190 ps
CPU time 8.08 seconds
Started Aug 18 05:59:48 PM PDT 24
Finished Aug 18 05:59:56 PM PDT 24
Peak memory 198624 kb
Host smart-1ed34b84-4f8c-42fe-93cb-f54747b4f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032070259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2032070259
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2962266557
Short name T1030
Test name
Test status
Simulation time 105059002379 ps
CPU time 229.45 seconds
Started Aug 18 05:59:51 PM PDT 24
Finished Aug 18 06:03:40 PM PDT 24
Peak memory 200900 kb
Host smart-1cdef298-cdb1-43f6-a3f2-e49e106f6f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962266557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2962266557
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.650606531
Short name T951
Test name
Test status
Simulation time 21034457726 ps
CPU time 626.4 seconds
Started Aug 18 05:59:52 PM PDT 24
Finished Aug 18 06:10:19 PM PDT 24
Peak memory 200912 kb
Host smart-99a8e6ed-ed5a-4afa-8608-b31479324755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650606531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.650606531
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1734230298
Short name T959
Test name
Test status
Simulation time 3993480894 ps
CPU time 7.48 seconds
Started Aug 18 05:59:50 PM PDT 24
Finished Aug 18 05:59:58 PM PDT 24
Peak memory 199332 kb
Host smart-db231d8d-30d0-4bd0-beb3-89abef43c58c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734230298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1734230298
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.982240149
Short name T884
Test name
Test status
Simulation time 137446293832 ps
CPU time 64 seconds
Started Aug 18 05:59:49 PM PDT 24
Finished Aug 18 06:00:53 PM PDT 24
Peak memory 200948 kb
Host smart-4313997e-c7ae-43f7-a0e6-1790a1a2aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982240149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.982240149
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2515836801
Short name T545
Test name
Test status
Simulation time 3214564323 ps
CPU time 4.86 seconds
Started Aug 18 05:59:49 PM PDT 24
Finished Aug 18 05:59:54 PM PDT 24
Peak memory 197404 kb
Host smart-a4c5831a-3097-4ec6-8d2c-5333ab998640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515836801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2515836801
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1571433418
Short name T462
Test name
Test status
Simulation time 5984338083 ps
CPU time 7.76 seconds
Started Aug 18 05:59:50 PM PDT 24
Finished Aug 18 05:59:58 PM PDT 24
Peak memory 200912 kb
Host smart-05985a99-c4ac-44ed-9345-c19cf752d5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571433418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1571433418
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.324935107
Short name T715
Test name
Test status
Simulation time 8768846768 ps
CPU time 40.67 seconds
Started Aug 18 05:59:49 PM PDT 24
Finished Aug 18 06:00:30 PM PDT 24
Peak memory 216464 kb
Host smart-cb240a39-b19d-4e2c-9b73-572311d54f6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324935107 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.324935107
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1345175628
Short name T776
Test name
Test status
Simulation time 758492827 ps
CPU time 2.97 seconds
Started Aug 18 05:59:47 PM PDT 24
Finished Aug 18 05:59:50 PM PDT 24
Peak memory 199760 kb
Host smart-e101d2b8-da45-434f-904d-d049bb921fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345175628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1345175628
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3964755733
Short name T437
Test name
Test status
Simulation time 48398077042 ps
CPU time 81.57 seconds
Started Aug 18 05:59:48 PM PDT 24
Finished Aug 18 06:01:10 PM PDT 24
Peak memory 200832 kb
Host smart-8b17436b-1356-4bec-a630-9c5283a22b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964755733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3964755733
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.642409564
Short name T721
Test name
Test status
Simulation time 59289803316 ps
CPU time 46.47 seconds
Started Aug 18 06:03:10 PM PDT 24
Finished Aug 18 06:03:57 PM PDT 24
Peak memory 200936 kb
Host smart-b87a4cc4-8166-4609-b1cd-464530184c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642409564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.642409564
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1224077766
Short name T157
Test name
Test status
Simulation time 98389126629 ps
CPU time 87.53 seconds
Started Aug 18 06:03:09 PM PDT 24
Finished Aug 18 06:04:37 PM PDT 24
Peak memory 200940 kb
Host smart-7fb0cfdd-2c23-4fd4-b8b5-d94365c4737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224077766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1224077766
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3692564612
Short name T202
Test name
Test status
Simulation time 37622668493 ps
CPU time 16.07 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:03:34 PM PDT 24
Peak memory 200856 kb
Host smart-45f29599-b024-449b-acc2-2d18e15e22c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692564612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3692564612
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3464159805
Short name T709
Test name
Test status
Simulation time 24517062805 ps
CPU time 32.95 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:03:51 PM PDT 24
Peak memory 200932 kb
Host smart-3d64a5d0-eb34-4ddf-a007-cf43d6626b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464159805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3464159805
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2488755577
Short name T221
Test name
Test status
Simulation time 77321059703 ps
CPU time 116.97 seconds
Started Aug 18 06:03:19 PM PDT 24
Finished Aug 18 06:05:16 PM PDT 24
Peak memory 200872 kb
Host smart-033bd03a-b0b1-42b2-9239-4cc1cea207d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488755577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2488755577
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3249580562
Short name T1024
Test name
Test status
Simulation time 95348816827 ps
CPU time 217.05 seconds
Started Aug 18 06:03:22 PM PDT 24
Finished Aug 18 06:06:59 PM PDT 24
Peak memory 200864 kb
Host smart-df54a611-0387-4983-a5b6-c87ff0e1c8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249580562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3249580562
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2670394062
Short name T731
Test name
Test status
Simulation time 63291474550 ps
CPU time 86.67 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:04:45 PM PDT 24
Peak memory 200864 kb
Host smart-df8fb4b0-54ca-4b2c-84c0-7aae1e39e572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670394062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2670394062
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2886898365
Short name T593
Test name
Test status
Simulation time 14692973 ps
CPU time 0.56 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 05:59:56 PM PDT 24
Peak memory 196212 kb
Host smart-05314488-649f-401a-a3ec-8bfcab22a303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886898365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2886898365
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3946387112
Short name T288
Test name
Test status
Simulation time 216869120488 ps
CPU time 689.42 seconds
Started Aug 18 05:59:50 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 200928 kb
Host smart-b0025a4a-c141-4361-a375-2164478f5753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946387112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3946387112
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3098453273
Short name T936
Test name
Test status
Simulation time 164773449900 ps
CPU time 68.33 seconds
Started Aug 18 05:59:55 PM PDT 24
Finished Aug 18 06:01:04 PM PDT 24
Peak memory 200844 kb
Host smart-a4abae9d-6e54-4b5e-91ed-e30c71417a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098453273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3098453273
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1239011482
Short name T451
Test name
Test status
Simulation time 35652093176 ps
CPU time 66.8 seconds
Started Aug 18 05:59:54 PM PDT 24
Finished Aug 18 06:01:01 PM PDT 24
Peak memory 200832 kb
Host smart-29db7506-4a65-4176-8149-2a0ba0f688b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239011482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1239011482
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1483430666
Short name T798
Test name
Test status
Simulation time 6061561460 ps
CPU time 1.75 seconds
Started Aug 18 05:59:58 PM PDT 24
Finished Aug 18 06:00:00 PM PDT 24
Peak memory 198724 kb
Host smart-64d91d53-529d-4ecb-aaf4-f888c18d512a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483430666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1483430666
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3470406798
Short name T1103
Test name
Test status
Simulation time 153840626024 ps
CPU time 950.98 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:15:47 PM PDT 24
Peak memory 200932 kb
Host smart-ac6c63b0-d308-41c4-8be5-7c73f6315b5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470406798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3470406798
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3340149424
Short name T655
Test name
Test status
Simulation time 2429675708 ps
CPU time 3.34 seconds
Started Aug 18 05:59:54 PM PDT 24
Finished Aug 18 05:59:58 PM PDT 24
Peak memory 200184 kb
Host smart-247b6818-3172-4b68-b2a4-1cd1c32d1e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340149424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3340149424
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.4043215894
Short name T438
Test name
Test status
Simulation time 85294335833 ps
CPU time 125.85 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:02:02 PM PDT 24
Peak memory 201284 kb
Host smart-da578054-35c9-4305-b2a7-87facdf06c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043215894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4043215894
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1680972704
Short name T415
Test name
Test status
Simulation time 11504300844 ps
CPU time 222.82 seconds
Started Aug 18 06:00:01 PM PDT 24
Finished Aug 18 06:03:48 PM PDT 24
Peak memory 200860 kb
Host smart-8e918df7-4749-40c3-93b4-31603421a9b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1680972704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1680972704
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.899398392
Short name T723
Test name
Test status
Simulation time 5774789815 ps
CPU time 13.25 seconds
Started Aug 18 06:00:02 PM PDT 24
Finished Aug 18 06:00:18 PM PDT 24
Peak memory 200280 kb
Host smart-f038e9f4-3254-4de6-af2e-160c39b145d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899398392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.899398392
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1734861690
Short name T554
Test name
Test status
Simulation time 29538112902 ps
CPU time 24 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:00:20 PM PDT 24
Peak memory 200724 kb
Host smart-c3d9f5b6-03eb-429b-827a-b67d9c012c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734861690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1734861690
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2001699445
Short name T680
Test name
Test status
Simulation time 42202865714 ps
CPU time 68.18 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:01:05 PM PDT 24
Peak memory 197728 kb
Host smart-2c78c27a-02d9-421a-adde-268ad18d0bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001699445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2001699445
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.903966354
Short name T543
Test name
Test status
Simulation time 894724863 ps
CPU time 2.77 seconds
Started Aug 18 05:59:50 PM PDT 24
Finished Aug 18 05:59:53 PM PDT 24
Peak memory 200792 kb
Host smart-6b2ab6fb-c307-4feb-b4ad-3ac7bb183486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903966354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.903966354
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2714647408
Short name T1048
Test name
Test status
Simulation time 230881068482 ps
CPU time 916.9 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:15:13 PM PDT 24
Peak memory 209296 kb
Host smart-3a54ff89-665e-4f70-92ff-d8538b86ec66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714647408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2714647408
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.455495670
Short name T1005
Test name
Test status
Simulation time 5937180800 ps
CPU time 52.71 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:00:49 PM PDT 24
Peak memory 210420 kb
Host smart-bff1b621-487a-49dd-a25d-a731a8218b9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455495670 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.455495670
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1072276645
Short name T914
Test name
Test status
Simulation time 6564741385 ps
CPU time 28.33 seconds
Started Aug 18 05:59:58 PM PDT 24
Finished Aug 18 06:00:27 PM PDT 24
Peak memory 200460 kb
Host smart-f2067dc2-2749-4afe-bcf5-45ea0a042709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072276645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1072276645
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3547543050
Short name T296
Test name
Test status
Simulation time 26002489001 ps
CPU time 20.97 seconds
Started Aug 18 05:59:48 PM PDT 24
Finished Aug 18 06:00:09 PM PDT 24
Peak memory 200916 kb
Host smart-15751324-7f74-4988-bfb9-003945ca7c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547543050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3547543050
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1902163960
Short name T185
Test name
Test status
Simulation time 27920314716 ps
CPU time 40.12 seconds
Started Aug 18 06:03:20 PM PDT 24
Finished Aug 18 06:04:01 PM PDT 24
Peak memory 200752 kb
Host smart-208e0e55-a3fd-4187-88c1-8a7d821a1823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902163960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1902163960
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1275186341
Short name T1057
Test name
Test status
Simulation time 55849644925 ps
CPU time 230.75 seconds
Started Aug 18 06:03:17 PM PDT 24
Finished Aug 18 06:07:08 PM PDT 24
Peak memory 200924 kb
Host smart-0ac260a7-087d-4c30-a0c6-aa0058b4c252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275186341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1275186341
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.670556250
Short name T195
Test name
Test status
Simulation time 116785496001 ps
CPU time 92.49 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:04:50 PM PDT 24
Peak memory 200860 kb
Host smart-f5a37485-b5f6-48d5-8660-ab121f20bd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670556250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.670556250
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1114751858
Short name T939
Test name
Test status
Simulation time 140549762618 ps
CPU time 360.97 seconds
Started Aug 18 06:03:21 PM PDT 24
Finished Aug 18 06:09:22 PM PDT 24
Peak memory 200896 kb
Host smart-30ceeb71-e0e8-4b02-add6-d1864950e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114751858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1114751858
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2314031516
Short name T197
Test name
Test status
Simulation time 95146914152 ps
CPU time 44.86 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 200928 kb
Host smart-7cdc4ee3-8002-4145-85f4-f2907c36f171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314031516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2314031516
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.639175056
Short name T1149
Test name
Test status
Simulation time 113998777414 ps
CPU time 44.34 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:04:02 PM PDT 24
Peak memory 200884 kb
Host smart-5f2af3d7-e0b1-4bef-affa-0a33e88f983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639175056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.639175056
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2086545848
Short name T214
Test name
Test status
Simulation time 81487930786 ps
CPU time 65.32 seconds
Started Aug 18 06:03:18 PM PDT 24
Finished Aug 18 06:04:24 PM PDT 24
Peak memory 200916 kb
Host smart-2dda3dd7-0a5d-4d11-8778-90b26ca46bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086545848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2086545848
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2311229928
Short name T105
Test name
Test status
Simulation time 37844942020 ps
CPU time 34.04 seconds
Started Aug 18 06:03:19 PM PDT 24
Finished Aug 18 06:03:53 PM PDT 24
Peak memory 200940 kb
Host smart-a194b2e0-139f-498f-8794-518b20c0235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311229928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2311229928
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2111279841
Short name T468
Test name
Test status
Simulation time 61853463 ps
CPU time 0.56 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:57:38 PM PDT 24
Peak memory 196244 kb
Host smart-3abe94a2-51ac-4b34-ac5f-19a40a3ebfbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111279841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2111279841
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3314899044
Short name T237
Test name
Test status
Simulation time 139882468004 ps
CPU time 81.05 seconds
Started Aug 18 05:57:36 PM PDT 24
Finished Aug 18 05:58:57 PM PDT 24
Peak memory 200852 kb
Host smart-02316ae7-44f1-4a71-bc71-432821a4b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314899044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3314899044
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1229997661
Short name T1106
Test name
Test status
Simulation time 30894040256 ps
CPU time 28.8 seconds
Started Aug 18 05:57:39 PM PDT 24
Finished Aug 18 05:58:08 PM PDT 24
Peak memory 200856 kb
Host smart-79129d9a-84d2-44dc-8168-cd4aa95b59f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229997661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1229997661
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3771513460
Short name T724
Test name
Test status
Simulation time 15835871095 ps
CPU time 26.54 seconds
Started Aug 18 05:57:39 PM PDT 24
Finished Aug 18 05:58:06 PM PDT 24
Peak memory 200900 kb
Host smart-0583a8de-12cb-40b0-84e0-3f856b2b374d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771513460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3771513460
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3272522683
Short name T836
Test name
Test status
Simulation time 27338720614 ps
CPU time 5.44 seconds
Started Aug 18 05:57:38 PM PDT 24
Finished Aug 18 05:57:43 PM PDT 24
Peak memory 200904 kb
Host smart-477e0b9e-791c-4f80-a065-7bedfd46c21f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272522683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3272522683
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.244217527
Short name T425
Test name
Test status
Simulation time 96941314796 ps
CPU time 777.65 seconds
Started Aug 18 05:57:40 PM PDT 24
Finished Aug 18 06:10:38 PM PDT 24
Peak memory 200912 kb
Host smart-fd3160c7-597b-431f-821b-d29b1556ebdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=244217527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.244217527
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2471806892
Short name T323
Test name
Test status
Simulation time 5784069998 ps
CPU time 3.57 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:57:41 PM PDT 24
Peak memory 200344 kb
Host smart-b5235571-2841-496c-a2ed-663902559685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471806892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2471806892
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3687889817
Short name T395
Test name
Test status
Simulation time 76727859931 ps
CPU time 166.06 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 06:00:23 PM PDT 24
Peak memory 200700 kb
Host smart-34bac047-1202-4dbb-8ed2-5e29dab67a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687889817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3687889817
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1264934999
Short name T238
Test name
Test status
Simulation time 11972782973 ps
CPU time 111.97 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:59:29 PM PDT 24
Peak memory 200940 kb
Host smart-a3ceb721-a6ec-4f37-8460-e13a2c0495a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264934999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1264934999
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1274039653
Short name T341
Test name
Test status
Simulation time 6007924188 ps
CPU time 3.12 seconds
Started Aug 18 05:57:40 PM PDT 24
Finished Aug 18 05:57:43 PM PDT 24
Peak memory 199460 kb
Host smart-d88f2343-83bb-4ccc-8a67-5165d6e0b865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274039653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1274039653
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.376245728
Short name T926
Test name
Test status
Simulation time 124348805229 ps
CPU time 210.63 seconds
Started Aug 18 05:57:40 PM PDT 24
Finished Aug 18 06:01:11 PM PDT 24
Peak memory 201112 kb
Host smart-9e63154b-74f8-4934-b896-a8f7071c4d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376245728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.376245728
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3155533740
Short name T795
Test name
Test status
Simulation time 19453938490 ps
CPU time 28.39 seconds
Started Aug 18 05:57:36 PM PDT 24
Finished Aug 18 05:58:05 PM PDT 24
Peak memory 197048 kb
Host smart-691e4b77-2708-4fd9-8ee3-d99a705683e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155533740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3155533740
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.2553037415
Short name T919
Test name
Test status
Simulation time 530876346 ps
CPU time 1.28 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:57:39 PM PDT 24
Peak memory 199940 kb
Host smart-8188330f-982e-4a11-8820-01fda620c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553037415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2553037415
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2962329296
Short name T561
Test name
Test status
Simulation time 237111825049 ps
CPU time 168.15 seconds
Started Aug 18 05:57:36 PM PDT 24
Finished Aug 18 06:00:25 PM PDT 24
Peak memory 200828 kb
Host smart-297ffb5d-cd53-49d1-9fac-80196b3ed172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962329296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2962329296
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.938043656
Short name T640
Test name
Test status
Simulation time 1464711230 ps
CPU time 8.73 seconds
Started Aug 18 05:57:40 PM PDT 24
Finished Aug 18 05:57:49 PM PDT 24
Peak memory 209292 kb
Host smart-09e8159e-8675-45d2-8fa4-8fab9e0bcd9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938043656 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.938043656
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2387817009
Short name T338
Test name
Test status
Simulation time 1294000740 ps
CPU time 3.14 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:57:41 PM PDT 24
Peak memory 199824 kb
Host smart-cb8f6eeb-91f0-4193-8537-7949f93fe89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387817009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2387817009
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.133126845
Short name T534
Test name
Test status
Simulation time 37518879860 ps
CPU time 22.64 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:58:00 PM PDT 24
Peak memory 200916 kb
Host smart-211f84d7-a77e-49f3-9d87-1a61d8d0559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133126845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.133126845
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1292585502
Short name T343
Test name
Test status
Simulation time 20235562 ps
CPU time 0.55 seconds
Started Aug 18 06:00:05 PM PDT 24
Finished Aug 18 06:00:06 PM PDT 24
Peak memory 196244 kb
Host smart-0bb1f74f-d9e3-499f-a8b0-822d632c6631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292585502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1292585502
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1241772213
Short name T550
Test name
Test status
Simulation time 40137230327 ps
CPU time 53.1 seconds
Started Aug 18 05:59:55 PM PDT 24
Finished Aug 18 06:00:48 PM PDT 24
Peak memory 200856 kb
Host smart-a61c9b33-f9fc-45bf-8446-7ecbae6e862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241772213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1241772213
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1027221344
Short name T1060
Test name
Test status
Simulation time 72559140704 ps
CPU time 29.67 seconds
Started Aug 18 05:59:57 PM PDT 24
Finished Aug 18 06:00:27 PM PDT 24
Peak memory 200876 kb
Host smart-e9ede16b-17d6-47a8-9482-54fb63b4d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027221344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1027221344
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.1253365121
Short name T316
Test name
Test status
Simulation time 90924872022 ps
CPU time 135.43 seconds
Started Aug 18 05:59:57 PM PDT 24
Finished Aug 18 06:02:13 PM PDT 24
Peak memory 200720 kb
Host smart-87e159a7-7adf-4421-96d5-cb7e576662a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253365121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1253365121
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.255623558
Short name T870
Test name
Test status
Simulation time 48464506915 ps
CPU time 282.56 seconds
Started Aug 18 06:00:03 PM PDT 24
Finished Aug 18 06:04:48 PM PDT 24
Peak memory 200720 kb
Host smart-f1127cde-013a-4188-987d-7899008f21f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255623558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.255623558
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2642098304
Short name T773
Test name
Test status
Simulation time 5866672099 ps
CPU time 4.32 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:00:00 PM PDT 24
Peak memory 199316 kb
Host smart-cf7cb289-ae07-40ab-b62d-2270d64b69b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642098304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2642098304
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1067591732
Short name T259
Test name
Test status
Simulation time 73970836836 ps
CPU time 143.58 seconds
Started Aug 18 05:59:57 PM PDT 24
Finished Aug 18 06:02:21 PM PDT 24
Peak memory 201144 kb
Host smart-19057540-7f2a-4e4d-9952-4cfcf8c9ac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067591732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1067591732
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1001106956
Short name T835
Test name
Test status
Simulation time 17779534166 ps
CPU time 400.21 seconds
Started Aug 18 05:59:55 PM PDT 24
Finished Aug 18 06:06:36 PM PDT 24
Peak memory 200912 kb
Host smart-56b7f52e-1396-475e-afed-b86b972420bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001106956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1001106956
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3871565178
Short name T669
Test name
Test status
Simulation time 1437866599 ps
CPU time 1.23 seconds
Started Aug 18 05:59:57 PM PDT 24
Finished Aug 18 05:59:58 PM PDT 24
Peak memory 198964 kb
Host smart-63d1eeb0-1b86-43ec-9e50-93bbccff3bfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871565178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3871565178
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3193875143
Short name T743
Test name
Test status
Simulation time 5872194333 ps
CPU time 8.87 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 06:00:05 PM PDT 24
Peak memory 200044 kb
Host smart-ff5b42f2-e4ca-45d0-bf75-bb4b718427ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193875143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3193875143
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.721205098
Short name T1035
Test name
Test status
Simulation time 1387563568 ps
CPU time 2.9 seconds
Started Aug 18 05:59:56 PM PDT 24
Finished Aug 18 05:59:59 PM PDT 24
Peak memory 196328 kb
Host smart-23415cf9-5d4c-40c6-ac90-6b5fa25e5f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721205098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.721205098
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1960637846
Short name T280
Test name
Test status
Simulation time 6067933853 ps
CPU time 8.77 seconds
Started Aug 18 05:59:57 PM PDT 24
Finished Aug 18 06:00:06 PM PDT 24
Peak memory 200840 kb
Host smart-d1d30d4a-a309-49e6-863b-afcd31346e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960637846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1960637846
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.334356874
Short name T443
Test name
Test status
Simulation time 227649116381 ps
CPU time 1043.8 seconds
Started Aug 18 06:00:06 PM PDT 24
Finished Aug 18 06:17:30 PM PDT 24
Peak memory 209356 kb
Host smart-aa58936e-ce7e-4271-bc84-153feed08f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334356874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.334356874
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.4281884181
Short name T745
Test name
Test status
Simulation time 6645643188 ps
CPU time 16.42 seconds
Started Aug 18 06:00:05 PM PDT 24
Finished Aug 18 06:00:22 PM PDT 24
Peak memory 217276 kb
Host smart-6a2644bd-cf2d-4f2f-85e2-80b0b8fd6923
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281884181 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.4281884181
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3200520766
Short name T287
Test name
Test status
Simulation time 600767262 ps
CPU time 2.25 seconds
Started Aug 18 05:59:57 PM PDT 24
Finished Aug 18 05:59:59 PM PDT 24
Peak memory 200880 kb
Host smart-8f365a9c-76f6-4d8c-b218-144c65c7652d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200520766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3200520766
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3072630532
Short name T307
Test name
Test status
Simulation time 18732557839 ps
CPU time 7.64 seconds
Started Aug 18 05:59:55 PM PDT 24
Finished Aug 18 06:00:03 PM PDT 24
Peak memory 200616 kb
Host smart-4dba4a74-7b12-43ac-84bb-906357834634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072630532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3072630532
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2246344233
Short name T1018
Test name
Test status
Simulation time 21721518 ps
CPU time 0.55 seconds
Started Aug 18 06:00:07 PM PDT 24
Finished Aug 18 06:00:07 PM PDT 24
Peak memory 196228 kb
Host smart-e3fdaf96-ec62-447a-9e30-04f64ea67b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246344233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2246344233
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3215286574
Short name T584
Test name
Test status
Simulation time 359528621591 ps
CPU time 33.64 seconds
Started Aug 18 06:00:06 PM PDT 24
Finished Aug 18 06:00:40 PM PDT 24
Peak memory 200900 kb
Host smart-4f2d5ac1-94dc-4b62-b7ac-bce9948dc8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215286574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3215286574
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1371147757
Short name T128
Test name
Test status
Simulation time 88643884904 ps
CPU time 38.91 seconds
Started Aug 18 06:00:03 PM PDT 24
Finished Aug 18 06:00:44 PM PDT 24
Peak memory 200824 kb
Host smart-792c6321-1238-4229-b5ba-7e2ca9a05d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371147757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1371147757
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.220233375
Short name T775
Test name
Test status
Simulation time 20885760414 ps
CPU time 30.76 seconds
Started Aug 18 06:00:04 PM PDT 24
Finished Aug 18 06:00:36 PM PDT 24
Peak memory 200944 kb
Host smart-be3dfa38-101d-4d2c-a552-c36de19d018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220233375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.220233375
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3591177829
Short name T977
Test name
Test status
Simulation time 172110417635 ps
CPU time 25.21 seconds
Started Aug 18 06:00:04 PM PDT 24
Finished Aug 18 06:00:30 PM PDT 24
Peak memory 197152 kb
Host smart-ee161579-cfa7-44bf-8b95-0460b30c1913
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591177829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3591177829
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3099294723
Short name T467
Test name
Test status
Simulation time 141535099475 ps
CPU time 578.05 seconds
Started Aug 18 06:00:03 PM PDT 24
Finished Aug 18 06:09:43 PM PDT 24
Peak memory 200944 kb
Host smart-765ab259-7cbe-4a6c-bb4b-cd6a07882a93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099294723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3099294723
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.472932382
Short name T340
Test name
Test status
Simulation time 1298991622 ps
CPU time 1.49 seconds
Started Aug 18 06:00:03 PM PDT 24
Finished Aug 18 06:00:07 PM PDT 24
Peak memory 198700 kb
Host smart-9627333d-9356-46e8-b63d-9df7baba2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472932382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.472932382
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.255939736
Short name T686
Test name
Test status
Simulation time 112944265811 ps
CPU time 181.55 seconds
Started Aug 18 06:00:04 PM PDT 24
Finished Aug 18 06:03:07 PM PDT 24
Peak memory 201228 kb
Host smart-0448b7d9-c14f-4e75-9272-e2449671d725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255939736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.255939736
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2068913767
Short name T405
Test name
Test status
Simulation time 17880269680 ps
CPU time 231.07 seconds
Started Aug 18 06:00:04 PM PDT 24
Finished Aug 18 06:03:56 PM PDT 24
Peak memory 200904 kb
Host smart-196b879e-2db5-4f00-b17d-425e1bd4e958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068913767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2068913767
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2375666680
Short name T742
Test name
Test status
Simulation time 4413354145 ps
CPU time 7.84 seconds
Started Aug 18 06:00:05 PM PDT 24
Finished Aug 18 06:00:13 PM PDT 24
Peak memory 200876 kb
Host smart-78bde9ee-62ac-4898-802b-de7baf980e63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375666680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2375666680
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2317393888
Short name T730
Test name
Test status
Simulation time 13987144034 ps
CPU time 23.01 seconds
Started Aug 18 06:00:04 PM PDT 24
Finished Aug 18 06:00:28 PM PDT 24
Peak memory 200136 kb
Host smart-5a4b04b5-6348-401f-b827-13440b0dbd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317393888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2317393888
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1035608401
Short name T790
Test name
Test status
Simulation time 2941409968 ps
CPU time 4.77 seconds
Started Aug 18 06:00:03 PM PDT 24
Finished Aug 18 06:00:10 PM PDT 24
Peak memory 197484 kb
Host smart-4b0df127-d9ea-47ef-8562-d2d28bbf36fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035608401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1035608401
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3587768037
Short name T948
Test name
Test status
Simulation time 5813987908 ps
CPU time 17.4 seconds
Started Aug 18 06:00:04 PM PDT 24
Finished Aug 18 06:00:23 PM PDT 24
Peak memory 200872 kb
Host smart-5c58b2c0-4a2a-4c4a-834a-39db6e589e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587768037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3587768037
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2237102129
Short name T1066
Test name
Test status
Simulation time 164318000511 ps
CPU time 301.68 seconds
Started Aug 18 06:00:04 PM PDT 24
Finished Aug 18 06:05:07 PM PDT 24
Peak memory 200952 kb
Host smart-15069e69-b6f0-404c-892b-dfb625c76981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237102129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2237102129
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3989749313
Short name T1108
Test name
Test status
Simulation time 5362008060 ps
CPU time 81.07 seconds
Started Aug 18 06:00:06 PM PDT 24
Finished Aug 18 06:01:27 PM PDT 24
Peak memory 217364 kb
Host smart-8d446f84-9025-48b8-92b3-44c095eb9a7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989749313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3989749313
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1198076186
Short name T275
Test name
Test status
Simulation time 648469425 ps
CPU time 2.4 seconds
Started Aug 18 06:00:03 PM PDT 24
Finished Aug 18 06:00:08 PM PDT 24
Peak memory 200464 kb
Host smart-57985d6a-da8c-45c5-ba46-6f9f3add30b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198076186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1198076186
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.427622315
Short name T1117
Test name
Test status
Simulation time 34822351846 ps
CPU time 11.61 seconds
Started Aug 18 06:00:05 PM PDT 24
Finished Aug 18 06:00:17 PM PDT 24
Peak memory 200840 kb
Host smart-89247ca5-8b40-4d4b-8e8f-29e0dd2d0b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427622315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.427622315
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2923681974
Short name T999
Test name
Test status
Simulation time 18923070 ps
CPU time 0.55 seconds
Started Aug 18 06:00:13 PM PDT 24
Finished Aug 18 06:00:14 PM PDT 24
Peak memory 196140 kb
Host smart-b0d314f2-4033-42af-bf72-92d4b7156f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923681974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2923681974
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3196452614
Short name T662
Test name
Test status
Simulation time 66659671469 ps
CPU time 29.24 seconds
Started Aug 18 06:00:08 PM PDT 24
Finished Aug 18 06:00:37 PM PDT 24
Peak memory 200828 kb
Host smart-b7812986-db40-4a11-867a-0a31c911a541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196452614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3196452614
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1929453974
Short name T270
Test name
Test status
Simulation time 127349359113 ps
CPU time 250.51 seconds
Started Aug 18 06:00:04 PM PDT 24
Finished Aug 18 06:04:16 PM PDT 24
Peak memory 200872 kb
Host smart-d5223613-598c-4d72-bc26-91645439ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929453974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1929453974
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.689238441
Short name T701
Test name
Test status
Simulation time 13811550690 ps
CPU time 25.9 seconds
Started Aug 18 06:00:12 PM PDT 24
Finished Aug 18 06:00:38 PM PDT 24
Peak memory 200936 kb
Host smart-aa773b34-f98a-4267-a91b-63b3242595a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689238441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.689238441
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2857604800
Short name T400
Test name
Test status
Simulation time 18568657669 ps
CPU time 11.11 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:00:25 PM PDT 24
Peak memory 198248 kb
Host smart-f4dc4c48-a784-47d4-96ca-be9b7955a364
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857604800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2857604800
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2321071793
Short name T612
Test name
Test status
Simulation time 111489279686 ps
CPU time 817.64 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 200868 kb
Host smart-45c0be11-a1cf-4c71-a250-480d322073d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321071793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2321071793
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3518822435
Short name T1017
Test name
Test status
Simulation time 2600831056 ps
CPU time 2.92 seconds
Started Aug 18 06:00:13 PM PDT 24
Finished Aug 18 06:00:16 PM PDT 24
Peak memory 197128 kb
Host smart-940c4025-994e-4fc1-a6c9-43705e370884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518822435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3518822435
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3818094320
Short name T985
Test name
Test status
Simulation time 36723537147 ps
CPU time 67.03 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:01:21 PM PDT 24
Peak memory 201032 kb
Host smart-10ef5bde-753c-4837-b9e4-1b4876f1a1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818094320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3818094320
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3226319693
Short name T582
Test name
Test status
Simulation time 25232224207 ps
CPU time 123.46 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:02:18 PM PDT 24
Peak memory 200888 kb
Host smart-768f9f40-2e11-4326-9dd7-959c8e24b19d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3226319693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3226319693
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.4123488972
Short name T820
Test name
Test status
Simulation time 2963262392 ps
CPU time 11.44 seconds
Started Aug 18 06:00:18 PM PDT 24
Finished Aug 18 06:00:30 PM PDT 24
Peak memory 199060 kb
Host smart-22edefe3-79ff-4f2f-a191-790732dd3669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123488972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4123488972
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3991354544
Short name T631
Test name
Test status
Simulation time 52965635112 ps
CPU time 82.28 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:01:36 PM PDT 24
Peak memory 200832 kb
Host smart-f467498f-1865-42b9-ae1d-668bd0cba62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991354544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3991354544
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2792131924
Short name T636
Test name
Test status
Simulation time 5441450357 ps
CPU time 2.72 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:00:17 PM PDT 24
Peak memory 197416 kb
Host smart-ea1b6761-bf48-4541-a62a-a27321f37acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792131924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2792131924
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1945731537
Short name T411
Test name
Test status
Simulation time 739437569 ps
CPU time 2.93 seconds
Started Aug 18 06:00:03 PM PDT 24
Finished Aug 18 06:00:08 PM PDT 24
Peak memory 199208 kb
Host smart-f3f867a4-b94c-450d-b0c2-c64dc5508cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945731537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1945731537
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3595889630
Short name T816
Test name
Test status
Simulation time 116950745689 ps
CPU time 309.57 seconds
Started Aug 18 06:00:13 PM PDT 24
Finished Aug 18 06:05:22 PM PDT 24
Peak memory 200956 kb
Host smart-afd6346a-5086-459b-80bd-0757e2b54c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595889630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3595889630
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.4029945651
Short name T626
Test name
Test status
Simulation time 4194560787 ps
CPU time 57.9 seconds
Started Aug 18 06:00:16 PM PDT 24
Finished Aug 18 06:01:14 PM PDT 24
Peak memory 210536 kb
Host smart-d4f6d5df-377e-4958-a7c4-3dca1bf8660c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029945651 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.4029945651
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1544774623
Short name T672
Test name
Test status
Simulation time 1154405794 ps
CPU time 2.09 seconds
Started Aug 18 06:00:15 PM PDT 24
Finished Aug 18 06:00:17 PM PDT 24
Peak memory 199816 kb
Host smart-6d865775-c7b2-4062-9fcf-003b1edf39e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544774623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1544774623
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3110451459
Short name T719
Test name
Test status
Simulation time 23942339593 ps
CPU time 22.26 seconds
Started Aug 18 06:00:07 PM PDT 24
Finished Aug 18 06:00:30 PM PDT 24
Peak memory 200844 kb
Host smart-65f1fb37-2bad-462e-8ef6-eccd7f768f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110451459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3110451459
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.352893067
Short name T609
Test name
Test status
Simulation time 14152783 ps
CPU time 0.54 seconds
Started Aug 18 06:00:23 PM PDT 24
Finished Aug 18 06:00:24 PM PDT 24
Peak memory 196128 kb
Host smart-0dd14370-2771-4502-bfca-7f7be3a5c2dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352893067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.352893067
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.378655829
Short name T478
Test name
Test status
Simulation time 126127335640 ps
CPU time 81.25 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:01:35 PM PDT 24
Peak memory 200804 kb
Host smart-ea19f917-1e1b-4925-8c46-17787eb8fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378655829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.378655829
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.621000899
Short name T567
Test name
Test status
Simulation time 118518806866 ps
CPU time 180.73 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:03:15 PM PDT 24
Peak memory 200776 kb
Host smart-5d3749c5-cf64-4595-9bd3-0b4c46a7c917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621000899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.621000899
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3648312614
Short name T90
Test name
Test status
Simulation time 57166257798 ps
CPU time 29.74 seconds
Started Aug 18 06:00:18 PM PDT 24
Finished Aug 18 06:00:48 PM PDT 24
Peak memory 200932 kb
Host smart-eb13e858-84a3-4c58-a343-5486a32338b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648312614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3648312614
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.695759651
Short name T1059
Test name
Test status
Simulation time 81041480189 ps
CPU time 22.36 seconds
Started Aug 18 06:00:13 PM PDT 24
Finished Aug 18 06:00:35 PM PDT 24
Peak memory 200860 kb
Host smart-bf1006c1-2b20-4b8d-b18c-8d692bfb2f24
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695759651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.695759651
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1610590539
Short name T358
Test name
Test status
Simulation time 134236066314 ps
CPU time 386.45 seconds
Started Aug 18 06:00:20 PM PDT 24
Finished Aug 18 06:06:47 PM PDT 24
Peak memory 200864 kb
Host smart-65bc7315-f704-4f64-b47f-e8f53a495bb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610590539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1610590539
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3468587357
Short name T412
Test name
Test status
Simulation time 3600347390 ps
CPU time 8.23 seconds
Started Aug 18 06:00:20 PM PDT 24
Finished Aug 18 06:00:28 PM PDT 24
Peak memory 199952 kb
Host smart-e366fdd0-2a00-4831-9979-0c7b9df1622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468587357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3468587357
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2092196773
Short name T1051
Test name
Test status
Simulation time 75673134572 ps
CPU time 37.68 seconds
Started Aug 18 06:00:29 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 201068 kb
Host smart-52ea011e-b321-4115-abba-de17c390d41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092196773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2092196773
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2706939279
Short name T506
Test name
Test status
Simulation time 15426948338 ps
CPU time 702.24 seconds
Started Aug 18 06:00:25 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 200832 kb
Host smart-e7883ba8-d7ed-47dd-8704-8e50508150ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706939279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2706939279
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2442554429
Short name T799
Test name
Test status
Simulation time 6059023203 ps
CPU time 13.61 seconds
Started Aug 18 06:00:14 PM PDT 24
Finished Aug 18 06:00:28 PM PDT 24
Peak memory 199080 kb
Host smart-18a1a34b-ae01-473c-a127-cfbea95794a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442554429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2442554429
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1918962979
Short name T499
Test name
Test status
Simulation time 38987303369 ps
CPU time 16.44 seconds
Started Aug 18 06:00:22 PM PDT 24
Finished Aug 18 06:00:39 PM PDT 24
Peak memory 200912 kb
Host smart-e8eecf82-be57-419d-984c-66b811132433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918962979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1918962979
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1277844314
Short name T324
Test name
Test status
Simulation time 28557563201 ps
CPU time 24.29 seconds
Started Aug 18 06:00:20 PM PDT 24
Finished Aug 18 06:00:44 PM PDT 24
Peak memory 197036 kb
Host smart-814d9f4c-b9f0-4a56-83a9-9549d0531dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277844314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1277844314
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1370666896
Short name T428
Test name
Test status
Simulation time 498749930 ps
CPU time 1.61 seconds
Started Aug 18 06:00:18 PM PDT 24
Finished Aug 18 06:00:20 PM PDT 24
Peak memory 200340 kb
Host smart-e8012b82-0322-4f02-9fa6-6a846077f957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370666896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1370666896
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2382826728
Short name T1068
Test name
Test status
Simulation time 182163957271 ps
CPU time 956.3 seconds
Started Aug 18 06:00:21 PM PDT 24
Finished Aug 18 06:16:18 PM PDT 24
Peak memory 210724 kb
Host smart-2df9ec29-708d-46b9-97d7-1603ca7e76f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382826728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2382826728
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2082198256
Short name T1042
Test name
Test status
Simulation time 9117718051 ps
CPU time 36.61 seconds
Started Aug 18 06:00:19 PM PDT 24
Finished Aug 18 06:00:56 PM PDT 24
Peak memory 217552 kb
Host smart-b1f4c15d-db8e-47d1-b35c-95249d0b7344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082198256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2082198256
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3380489017
Short name T351
Test name
Test status
Simulation time 6147112897 ps
CPU time 26.83 seconds
Started Aug 18 06:00:22 PM PDT 24
Finished Aug 18 06:00:49 PM PDT 24
Peak memory 200628 kb
Host smart-01b6b847-2822-487a-9213-70be76088417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380489017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3380489017
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1278349503
Short name T785
Test name
Test status
Simulation time 176391113618 ps
CPU time 39.96 seconds
Started Aug 18 06:00:12 PM PDT 24
Finished Aug 18 06:00:52 PM PDT 24
Peak memory 200932 kb
Host smart-a7845444-2103-473a-8698-785a4a6dfec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278349503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1278349503
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1701098210
Short name T992
Test name
Test status
Simulation time 15320686 ps
CPU time 0.58 seconds
Started Aug 18 06:00:33 PM PDT 24
Finished Aug 18 06:00:33 PM PDT 24
Peak memory 196244 kb
Host smart-4bd91e8c-44b6-4d09-a62a-10029f80dc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701098210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1701098210
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.4081964802
Short name T251
Test name
Test status
Simulation time 70483370304 ps
CPU time 63.75 seconds
Started Aug 18 06:00:22 PM PDT 24
Finished Aug 18 06:01:26 PM PDT 24
Peak memory 200840 kb
Host smart-2d688b7e-1a36-4fa0-b283-27c62ee6ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081964802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4081964802
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3577218998
Short name T748
Test name
Test status
Simulation time 53423076660 ps
CPU time 11.78 seconds
Started Aug 18 06:00:20 PM PDT 24
Finished Aug 18 06:00:32 PM PDT 24
Peak memory 200852 kb
Host smart-bf2e180f-4a22-4707-9f77-58cea380c357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577218998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3577218998
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2716411061
Short name T684
Test name
Test status
Simulation time 52896667306 ps
CPU time 27.67 seconds
Started Aug 18 06:00:21 PM PDT 24
Finished Aug 18 06:00:49 PM PDT 24
Peak memory 200944 kb
Host smart-4c469216-7d66-439c-834e-c5875caf6852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716411061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2716411061
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1070168924
Short name T94
Test name
Test status
Simulation time 15491707615 ps
CPU time 22.49 seconds
Started Aug 18 06:00:21 PM PDT 24
Finished Aug 18 06:00:43 PM PDT 24
Peak memory 197960 kb
Host smart-a7a13041-0600-459f-aea8-0b2f6b986e03
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070168924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1070168924
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.4125125495
Short name T537
Test name
Test status
Simulation time 62902379122 ps
CPU time 481.58 seconds
Started Aug 18 06:00:34 PM PDT 24
Finished Aug 18 06:08:36 PM PDT 24
Peak memory 200920 kb
Host smart-f708b4b9-24c2-4b9c-ab00-564f04dd58fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125125495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.4125125495
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2965085731
Short name T364
Test name
Test status
Simulation time 4507266534 ps
CPU time 11.65 seconds
Started Aug 18 06:00:34 PM PDT 24
Finished Aug 18 06:00:45 PM PDT 24
Peak memory 200868 kb
Host smart-e6a6d5a8-a35d-4aa5-9356-bdaf71965311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965085731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2965085731
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2437740831
Short name T1129
Test name
Test status
Simulation time 69876494801 ps
CPU time 133.9 seconds
Started Aug 18 06:00:21 PM PDT 24
Finished Aug 18 06:02:35 PM PDT 24
Peak memory 200744 kb
Host smart-54191057-c970-4e86-9cb9-c7fa3154ebac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437740831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2437740831
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1726797057
Short name T442
Test name
Test status
Simulation time 12586790982 ps
CPU time 550.92 seconds
Started Aug 18 06:00:34 PM PDT 24
Finished Aug 18 06:09:45 PM PDT 24
Peak memory 201104 kb
Host smart-e98cc0bf-35d5-4f4f-a212-ae60d09ca5f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726797057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1726797057
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.3384599631
Short name T762
Test name
Test status
Simulation time 1497110519 ps
CPU time 2.18 seconds
Started Aug 18 06:00:22 PM PDT 24
Finished Aug 18 06:00:24 PM PDT 24
Peak memory 199152 kb
Host smart-d1b9c0a9-5039-456d-802e-e261729f0cc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384599631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3384599631
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4052944160
Short name T633
Test name
Test status
Simulation time 28784435796 ps
CPU time 27.22 seconds
Started Aug 18 06:00:21 PM PDT 24
Finished Aug 18 06:00:48 PM PDT 24
Peak memory 200888 kb
Host smart-90201d25-a440-4e3c-beb8-ccf45371d30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052944160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4052944160
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1404373630
Short name T866
Test name
Test status
Simulation time 2762929184 ps
CPU time 2.04 seconds
Started Aug 18 06:00:21 PM PDT 24
Finished Aug 18 06:00:23 PM PDT 24
Peak memory 197444 kb
Host smart-cfe0136d-6121-4671-9804-25406eb610b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404373630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1404373630
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2913116235
Short name T864
Test name
Test status
Simulation time 5879810659 ps
CPU time 14.81 seconds
Started Aug 18 06:00:21 PM PDT 24
Finished Aug 18 06:00:36 PM PDT 24
Peak memory 200888 kb
Host smart-797301d3-30a4-4038-a5dc-0735e55117ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913116235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2913116235
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3643853892
Short name T1043
Test name
Test status
Simulation time 80573921223 ps
CPU time 24.61 seconds
Started Aug 18 06:00:30 PM PDT 24
Finished Aug 18 06:00:55 PM PDT 24
Peak memory 200904 kb
Host smart-26732fb3-4c5e-42d4-adb9-24e0127f388b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643853892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3643853892
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.4093920359
Short name T674
Test name
Test status
Simulation time 2243106032 ps
CPU time 25.06 seconds
Started Aug 18 06:00:33 PM PDT 24
Finished Aug 18 06:00:58 PM PDT 24
Peak memory 217300 kb
Host smart-3ae8b90d-c9a0-436a-bac2-e3367cab8bbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093920359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.4093920359
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2590754882
Short name T1135
Test name
Test status
Simulation time 896676272 ps
CPU time 1.4 seconds
Started Aug 18 06:00:21 PM PDT 24
Finished Aug 18 06:00:23 PM PDT 24
Peak memory 199592 kb
Host smart-d44f8e70-07ce-4151-bdea-93b30a3c9226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590754882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2590754882
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3148922916
Short name T592
Test name
Test status
Simulation time 9322556866 ps
CPU time 19.42 seconds
Started Aug 18 06:00:20 PM PDT 24
Finished Aug 18 06:00:40 PM PDT 24
Peak memory 200880 kb
Host smart-cfb6b808-5354-4313-ad81-d3b9e015da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148922916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3148922916
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2373338828
Short name T577
Test name
Test status
Simulation time 32101885 ps
CPU time 0.54 seconds
Started Aug 18 06:00:38 PM PDT 24
Finished Aug 18 06:00:39 PM PDT 24
Peak memory 196228 kb
Host smart-3bd86422-ddbf-4228-92b6-75037cef933b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373338828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2373338828
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2149503450
Short name T639
Test name
Test status
Simulation time 118518517205 ps
CPU time 44.67 seconds
Started Aug 18 06:00:32 PM PDT 24
Finished Aug 18 06:01:17 PM PDT 24
Peak memory 200912 kb
Host smart-b630150d-67ea-4b60-905d-1d8439dad71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149503450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2149503450
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.76404458
Short name T568
Test name
Test status
Simulation time 52863096948 ps
CPU time 26.01 seconds
Started Aug 18 06:00:32 PM PDT 24
Finished Aug 18 06:00:58 PM PDT 24
Peak memory 200856 kb
Host smart-f7fddc87-80bc-4b80-a281-48d00582184e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76404458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.76404458
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2467698729
Short name T1170
Test name
Test status
Simulation time 19477913143 ps
CPU time 28.31 seconds
Started Aug 18 06:00:31 PM PDT 24
Finished Aug 18 06:01:00 PM PDT 24
Peak memory 200672 kb
Host smart-78e99ffa-2019-4899-8ff6-e64d8d2b2720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467698729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2467698729
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1464101559
Short name T706
Test name
Test status
Simulation time 167844123314 ps
CPU time 269.2 seconds
Started Aug 18 06:00:31 PM PDT 24
Finished Aug 18 06:05:00 PM PDT 24
Peak memory 200628 kb
Host smart-6b25ba2f-a664-451c-b149-9f6f04c5a8f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464101559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1464101559
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3165907812
Short name T651
Test name
Test status
Simulation time 136704897407 ps
CPU time 212.01 seconds
Started Aug 18 06:00:33 PM PDT 24
Finished Aug 18 06:04:05 PM PDT 24
Peak memory 200908 kb
Host smart-79026c9b-d94a-4274-af49-22967160082b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165907812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3165907812
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3532758336
Short name T628
Test name
Test status
Simulation time 7495177095 ps
CPU time 12.62 seconds
Started Aug 18 06:00:31 PM PDT 24
Finished Aug 18 06:00:44 PM PDT 24
Peak memory 200596 kb
Host smart-fe64dd3e-f8de-46c1-8652-4376759a8ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532758336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3532758336
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.494309146
Short name T611
Test name
Test status
Simulation time 63980511118 ps
CPU time 78.13 seconds
Started Aug 18 06:00:37 PM PDT 24
Finished Aug 18 06:01:55 PM PDT 24
Peak memory 201056 kb
Host smart-6ac379b3-e552-405b-9d4c-44f033070405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494309146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.494309146
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3444526254
Short name T1140
Test name
Test status
Simulation time 13338058064 ps
CPU time 267.07 seconds
Started Aug 18 06:00:31 PM PDT 24
Finished Aug 18 06:04:59 PM PDT 24
Peak memory 200880 kb
Host smart-6070efdc-a00a-4e2a-8233-bd779dead415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444526254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3444526254
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.814494247
Short name T466
Test name
Test status
Simulation time 3273295411 ps
CPU time 19.32 seconds
Started Aug 18 06:00:31 PM PDT 24
Finished Aug 18 06:00:50 PM PDT 24
Peak memory 199120 kb
Host smart-9cf55bf3-1e1b-4f8e-86cc-dbadc3bd06e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814494247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.814494247
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.705831088
Short name T1172
Test name
Test status
Simulation time 34727638332 ps
CPU time 36.07 seconds
Started Aug 18 06:00:30 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 200948 kb
Host smart-a6325b50-4929-4e82-abfa-d0fa5718d5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705831088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.705831088
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3827083355
Short name T382
Test name
Test status
Simulation time 2921430369 ps
CPU time 5.55 seconds
Started Aug 18 06:00:32 PM PDT 24
Finished Aug 18 06:00:37 PM PDT 24
Peak memory 196800 kb
Host smart-2a417b58-d1ff-423d-a62c-4a6b9e9a8397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827083355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3827083355
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3223309116
Short name T477
Test name
Test status
Simulation time 11052670409 ps
CPU time 50.89 seconds
Started Aug 18 06:00:31 PM PDT 24
Finished Aug 18 06:01:22 PM PDT 24
Peak memory 200872 kb
Host smart-13aed556-6b0b-45ca-8412-bcf81d08c3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223309116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3223309116
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3686783899
Short name T634
Test name
Test status
Simulation time 51424037605 ps
CPU time 991.73 seconds
Started Aug 18 06:00:31 PM PDT 24
Finished Aug 18 06:17:03 PM PDT 24
Peak memory 200948 kb
Host smart-8a6d0d34-8fe3-42d0-9211-f53a32485e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686783899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3686783899
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1756148082
Short name T1073
Test name
Test status
Simulation time 39711947871 ps
CPU time 80.36 seconds
Started Aug 18 06:00:34 PM PDT 24
Finished Aug 18 06:01:55 PM PDT 24
Peak memory 214108 kb
Host smart-a7200b82-8601-44dd-ac20-59c192b0ef60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756148082 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1756148082
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1911751296
Short name T265
Test name
Test status
Simulation time 588807428 ps
CPU time 2.26 seconds
Started Aug 18 06:00:32 PM PDT 24
Finished Aug 18 06:00:34 PM PDT 24
Peak memory 199720 kb
Host smart-863472cb-9271-4e52-8428-90c0b93d7c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911751296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1911751296
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2841763808
Short name T695
Test name
Test status
Simulation time 105960175694 ps
CPU time 39.36 seconds
Started Aug 18 06:00:31 PM PDT 24
Finished Aug 18 06:01:10 PM PDT 24
Peak memory 200860 kb
Host smart-51bd61d8-1b75-464f-b311-d428c592f232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841763808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2841763808
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.584019683
Short name T376
Test name
Test status
Simulation time 18064599 ps
CPU time 0.56 seconds
Started Aug 18 06:00:36 PM PDT 24
Finished Aug 18 06:00:37 PM PDT 24
Peak memory 195856 kb
Host smart-d3dd095d-62a5-41b9-9f74-c75af5a009f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584019683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.584019683
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2902971174
Short name T102
Test name
Test status
Simulation time 32964340351 ps
CPU time 26.69 seconds
Started Aug 18 06:00:44 PM PDT 24
Finished Aug 18 06:01:11 PM PDT 24
Peak memory 200928 kb
Host smart-932df779-9e84-4c2a-aa68-9d04dd541931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902971174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2902971174
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1636865076
Short name T810
Test name
Test status
Simulation time 76390826817 ps
CPU time 26.11 seconds
Started Aug 18 06:00:37 PM PDT 24
Finished Aug 18 06:01:03 PM PDT 24
Peak memory 200948 kb
Host smart-10cb804d-6a3e-4570-ae00-9dfdf11171a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636865076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1636865076
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1083301059
Short name T549
Test name
Test status
Simulation time 147676845524 ps
CPU time 58.5 seconds
Started Aug 18 06:00:42 PM PDT 24
Finished Aug 18 06:01:41 PM PDT 24
Peak memory 200904 kb
Host smart-85bd87ff-103c-4c16-ab1a-51a486bca9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083301059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1083301059
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2786465221
Short name T943
Test name
Test status
Simulation time 119901283287 ps
CPU time 46.73 seconds
Started Aug 18 06:00:37 PM PDT 24
Finished Aug 18 06:01:23 PM PDT 24
Peak memory 198016 kb
Host smart-47298519-b447-4b67-952e-52b2bab3291d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786465221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2786465221
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1711362337
Short name T667
Test name
Test status
Simulation time 106374429021 ps
CPU time 212.44 seconds
Started Aug 18 06:00:44 PM PDT 24
Finished Aug 18 06:04:17 PM PDT 24
Peak memory 200920 kb
Host smart-0510cf42-c680-4b51-9940-7ce784ec040b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711362337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1711362337
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3275954993
Short name T574
Test name
Test status
Simulation time 1252348972 ps
CPU time 2.22 seconds
Started Aug 18 06:00:37 PM PDT 24
Finished Aug 18 06:00:39 PM PDT 24
Peak memory 198832 kb
Host smart-e130bf3f-11f1-4df4-b7b1-788e82aade55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275954993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3275954993
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1181131663
Short name T274
Test name
Test status
Simulation time 139775745071 ps
CPU time 78.99 seconds
Started Aug 18 06:00:35 PM PDT 24
Finished Aug 18 06:01:54 PM PDT 24
Peak memory 199796 kb
Host smart-67f2465a-03e8-44a2-9819-376ec6016693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181131663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1181131663
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.185472854
Short name T1112
Test name
Test status
Simulation time 3558371746 ps
CPU time 47.54 seconds
Started Aug 18 06:00:37 PM PDT 24
Finished Aug 18 06:01:25 PM PDT 24
Peak memory 200868 kb
Host smart-5f1eeeee-4b1b-4a5a-a0aa-ad693579c469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185472854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.185472854
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2871886231
Short name T354
Test name
Test status
Simulation time 5576178168 ps
CPU time 45.1 seconds
Started Aug 18 06:00:38 PM PDT 24
Finished Aug 18 06:01:23 PM PDT 24
Peak memory 200196 kb
Host smart-8b2c306e-4adb-4812-8673-c2996a0bd6ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871886231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2871886231
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3594803532
Short name T551
Test name
Test status
Simulation time 45485490704 ps
CPU time 46.94 seconds
Started Aug 18 06:00:36 PM PDT 24
Finished Aug 18 06:01:23 PM PDT 24
Peak memory 200816 kb
Host smart-353b6bb4-41cb-430c-a13d-1e089a37a49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594803532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3594803532
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.269496638
Short name T512
Test name
Test status
Simulation time 44233564853 ps
CPU time 24.62 seconds
Started Aug 18 06:00:38 PM PDT 24
Finished Aug 18 06:01:03 PM PDT 24
Peak memory 197744 kb
Host smart-e3cffae3-86c1-4f50-8748-d751cd6e937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269496638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.269496638
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4244749857
Short name T464
Test name
Test status
Simulation time 294675773 ps
CPU time 1.49 seconds
Started Aug 18 06:00:37 PM PDT 24
Finished Aug 18 06:00:39 PM PDT 24
Peak memory 199144 kb
Host smart-bafce7f2-fd2e-45df-b452-b38e9bc4104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244749857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4244749857
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1819359380
Short name T1125
Test name
Test status
Simulation time 72344534014 ps
CPU time 1678.86 seconds
Started Aug 18 06:00:36 PM PDT 24
Finished Aug 18 06:28:35 PM PDT 24
Peak memory 200800 kb
Host smart-1780a8a6-a877-41a8-99d5-0fcec62e2db2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819359380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1819359380
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1815516073
Short name T85
Test name
Test status
Simulation time 9581468745 ps
CPU time 29.52 seconds
Started Aug 18 06:00:36 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 210392 kb
Host smart-6a5fa861-243b-45bb-80f8-e528dcd3add3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815516073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1815516073
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3254917320
Short name T474
Test name
Test status
Simulation time 7284860579 ps
CPU time 17.17 seconds
Started Aug 18 06:00:37 PM PDT 24
Finished Aug 18 06:00:55 PM PDT 24
Peak memory 200468 kb
Host smart-05228c8f-9a88-4bc6-8d34-7a2d01343742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254917320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3254917320
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3905136341
Short name T1110
Test name
Test status
Simulation time 72589808543 ps
CPU time 38.99 seconds
Started Aug 18 06:00:38 PM PDT 24
Finished Aug 18 06:01:17 PM PDT 24
Peak memory 200764 kb
Host smart-e6f805b2-5bea-4ffa-b547-0556bf69c95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905136341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3905136341
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.286117424
Short name T1132
Test name
Test status
Simulation time 11792779 ps
CPU time 0.55 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:00:48 PM PDT 24
Peak memory 196232 kb
Host smart-cb8860a8-0a34-463e-bd92-a0bdfe8d76b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286117424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.286117424
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2998409377
Short name T1116
Test name
Test status
Simulation time 92260170949 ps
CPU time 30.92 seconds
Started Aug 18 06:00:38 PM PDT 24
Finished Aug 18 06:01:09 PM PDT 24
Peak memory 200872 kb
Host smart-f94e7880-f570-4e9b-9a3e-8712110295b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998409377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2998409377
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2872625203
Short name T993
Test name
Test status
Simulation time 29176819619 ps
CPU time 46.73 seconds
Started Aug 18 06:00:38 PM PDT 24
Finished Aug 18 06:01:25 PM PDT 24
Peak memory 200848 kb
Host smart-4c32e04d-1437-4e4d-89a9-65baabea2fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872625203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2872625203
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4066367863
Short name T483
Test name
Test status
Simulation time 183887171757 ps
CPU time 215.59 seconds
Started Aug 18 06:00:36 PM PDT 24
Finished Aug 18 06:04:12 PM PDT 24
Peak memory 200912 kb
Host smart-9837b335-2cf9-418b-b85f-f180abc1424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066367863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4066367863
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1521755499
Short name T1094
Test name
Test status
Simulation time 17778309635 ps
CPU time 7.47 seconds
Started Aug 18 06:00:48 PM PDT 24
Finished Aug 18 06:00:55 PM PDT 24
Peak memory 199212 kb
Host smart-4e145c5c-627c-4a18-8121-23e2b02df5d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521755499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1521755499
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2497359431
Short name T841
Test name
Test status
Simulation time 108098290739 ps
CPU time 315.19 seconds
Started Aug 18 06:00:45 PM PDT 24
Finished Aug 18 06:06:00 PM PDT 24
Peak memory 200892 kb
Host smart-a28d5848-4b77-4094-8029-84273c059e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497359431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2497359431
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1725485033
Short name T668
Test name
Test status
Simulation time 1862622918 ps
CPU time 4.05 seconds
Started Aug 18 06:00:46 PM PDT 24
Finished Aug 18 06:00:50 PM PDT 24
Peak memory 199136 kb
Host smart-2710228d-e455-4040-be44-7405021a2409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725485033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1725485033
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3975358785
Short name T720
Test name
Test status
Simulation time 439912901670 ps
CPU time 94.05 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:02:21 PM PDT 24
Peak memory 201192 kb
Host smart-6ffd7a34-e281-4d11-8cdc-608b534f86a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975358785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3975358785
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4239677408
Short name T733
Test name
Test status
Simulation time 9136598040 ps
CPU time 139.36 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:03:06 PM PDT 24
Peak memory 200924 kb
Host smart-b0410de6-4f7a-4a65-9455-63bdee6bfbab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239677408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4239677408
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2880425402
Short name T342
Test name
Test status
Simulation time 6532739570 ps
CPU time 26.11 seconds
Started Aug 18 06:00:46 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 199796 kb
Host smart-752049de-1be5-4f52-8a6e-38d86e323ac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880425402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2880425402
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3323893182
Short name T298
Test name
Test status
Simulation time 9200266686 ps
CPU time 13.3 seconds
Started Aug 18 06:00:46 PM PDT 24
Finished Aug 18 06:01:00 PM PDT 24
Peak memory 200724 kb
Host smart-ed3a4d92-648d-445a-85f1-ffe58772e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323893182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3323893182
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1339820333
Short name T995
Test name
Test status
Simulation time 49774244948 ps
CPU time 11.03 seconds
Started Aug 18 06:00:44 PM PDT 24
Finished Aug 18 06:00:55 PM PDT 24
Peak memory 196788 kb
Host smart-722999bb-8fbd-4b8a-96e1-8dcf286b763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339820333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1339820333
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3982071704
Short name T589
Test name
Test status
Simulation time 11056483096 ps
CPU time 18.59 seconds
Started Aug 18 06:00:37 PM PDT 24
Finished Aug 18 06:00:55 PM PDT 24
Peak memory 200900 kb
Host smart-a2c280f1-457f-457e-b4a7-2d8dc67bc923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982071704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3982071704
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2299945439
Short name T643
Test name
Test status
Simulation time 67883649511 ps
CPU time 62.99 seconds
Started Aug 18 06:00:46 PM PDT 24
Finished Aug 18 06:01:49 PM PDT 24
Peak memory 200848 kb
Host smart-23e2975a-38b7-4b53-9dfc-f4e2adea2774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299945439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2299945439
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.481650139
Short name T322
Test name
Test status
Simulation time 6917238875 ps
CPU time 9.47 seconds
Started Aug 18 06:00:46 PM PDT 24
Finished Aug 18 06:00:56 PM PDT 24
Peak memory 200860 kb
Host smart-48ede542-926d-4616-a84e-9dcb9e06f548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481650139 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.481650139
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1581165937
Short name T1023
Test name
Test status
Simulation time 9253167710 ps
CPU time 8.27 seconds
Started Aug 18 06:00:45 PM PDT 24
Finished Aug 18 06:00:53 PM PDT 24
Peak memory 200944 kb
Host smart-9537edce-7351-45f2-bdb1-1f8c43a46dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581165937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1581165937
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.450830031
Short name T289
Test name
Test status
Simulation time 55080698680 ps
CPU time 102.25 seconds
Started Aug 18 06:00:44 PM PDT 24
Finished Aug 18 06:02:27 PM PDT 24
Peak memory 200924 kb
Host smart-f396736e-7e2a-4b0b-8e7b-dd89a3d2d5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450830031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.450830031
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3819833012
Short name T1142
Test name
Test status
Simulation time 34329379 ps
CPU time 0.56 seconds
Started Aug 18 06:00:57 PM PDT 24
Finished Aug 18 06:00:58 PM PDT 24
Peak memory 195684 kb
Host smart-5c3383d2-713f-4f42-96f4-763e9386d909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819833012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3819833012
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2693092175
Short name T618
Test name
Test status
Simulation time 26214123044 ps
CPU time 23.49 seconds
Started Aug 18 06:00:44 PM PDT 24
Finished Aug 18 06:01:07 PM PDT 24
Peak memory 200632 kb
Host smart-11d0871b-0f3b-4ae5-88f3-6ebc42bbd113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693092175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2693092175
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.236041002
Short name T460
Test name
Test status
Simulation time 140435923532 ps
CPU time 56.67 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:01:44 PM PDT 24
Peak memory 200756 kb
Host smart-35177de3-d52b-4835-b0e8-2e84205db25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236041002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.236041002
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1553280352
Short name T1123
Test name
Test status
Simulation time 18208233508 ps
CPU time 34.5 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:01:21 PM PDT 24
Peak memory 200880 kb
Host smart-32b142db-dca1-49c2-8b9d-3cd35d8ff956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553280352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1553280352
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3947747825
Short name T1153
Test name
Test status
Simulation time 38303634180 ps
CPU time 6.71 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:00:54 PM PDT 24
Peak memory 200944 kb
Host smart-46e23b07-b95b-4b4d-9854-d6b7f4aaa1fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947747825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3947747825
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.151204722
Short name T1038
Test name
Test status
Simulation time 179398181065 ps
CPU time 488.78 seconds
Started Aug 18 06:00:55 PM PDT 24
Finished Aug 18 06:09:04 PM PDT 24
Peak memory 200940 kb
Host smart-1bc2d2eb-b6a3-4d9a-be65-28f2e85faee5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151204722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.151204722
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.945920630
Short name T1071
Test name
Test status
Simulation time 1370141530 ps
CPU time 1.31 seconds
Started Aug 18 06:00:58 PM PDT 24
Finished Aug 18 06:01:00 PM PDT 24
Peak memory 197972 kb
Host smart-fcfbf5fa-2b3f-4b41-a8ac-cddbe50539fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945920630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.945920630
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3464815055
Short name T9
Test name
Test status
Simulation time 6084198185 ps
CPU time 9.81 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:00:57 PM PDT 24
Peak memory 196744 kb
Host smart-165c2858-3826-4461-8005-516e16135b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464815055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3464815055
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3603823077
Short name T697
Test name
Test status
Simulation time 28061718204 ps
CPU time 120.76 seconds
Started Aug 18 06:00:58 PM PDT 24
Finished Aug 18 06:02:59 PM PDT 24
Peak memory 200840 kb
Host smart-5612d2f3-3d04-4899-8ae2-9a8f3347e666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3603823077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3603823077
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3444253989
Short name T529
Test name
Test status
Simulation time 1486178732 ps
CPU time 5.59 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:00:52 PM PDT 24
Peak memory 199068 kb
Host smart-4741da0b-a729-4b3c-9340-8c5060eebf58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444253989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3444253989
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.925652490
Short name T308
Test name
Test status
Simulation time 12046279064 ps
CPU time 18.7 seconds
Started Aug 18 06:00:46 PM PDT 24
Finished Aug 18 06:01:05 PM PDT 24
Peak memory 200240 kb
Host smart-ba248b15-12f1-4916-917b-556707125605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925652490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.925652490
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1219326448
Short name T518
Test name
Test status
Simulation time 2753171861 ps
CPU time 5.08 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:00:52 PM PDT 24
Peak memory 196748 kb
Host smart-aaed1641-757e-4ad5-8e51-e6f60c4cd4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219326448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1219326448
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2966980723
Short name T510
Test name
Test status
Simulation time 476052920 ps
CPU time 1.47 seconds
Started Aug 18 06:00:46 PM PDT 24
Finished Aug 18 06:00:48 PM PDT 24
Peak memory 199144 kb
Host smart-2958e9d6-c701-4911-8b94-5eea733fc5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966980723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2966980723
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2974583991
Short name T1019
Test name
Test status
Simulation time 16511957909 ps
CPU time 42.92 seconds
Started Aug 18 06:00:56 PM PDT 24
Finished Aug 18 06:01:39 PM PDT 24
Peak memory 216620 kb
Host smart-20510157-f874-41ec-b523-014cf6016a5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974583991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2974583991
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2875667803
Short name T508
Test name
Test status
Simulation time 581319320 ps
CPU time 1.89 seconds
Started Aug 18 06:00:47 PM PDT 24
Finished Aug 18 06:00:49 PM PDT 24
Peak memory 199708 kb
Host smart-2e5141ec-a186-4e9e-a98b-da445acf9be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875667803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2875667803
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3170311737
Short name T435
Test name
Test status
Simulation time 18644710539 ps
CPU time 25.19 seconds
Started Aug 18 06:00:46 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 200880 kb
Host smart-f060b4fc-eb95-44c6-9c88-784896256ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170311737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3170311737
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1824945967
Short name T525
Test name
Test status
Simulation time 12284995 ps
CPU time 0.59 seconds
Started Aug 18 06:01:05 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 195896 kb
Host smart-4b984cdf-1b31-472b-8835-2e0eb6c1687d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824945967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1824945967
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.4065398364
Short name T359
Test name
Test status
Simulation time 54867489204 ps
CPU time 72.48 seconds
Started Aug 18 06:00:55 PM PDT 24
Finished Aug 18 06:02:08 PM PDT 24
Peak memory 200932 kb
Host smart-32bc553c-7b53-471d-b08a-39f0987746e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065398364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.4065398364
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1141843910
Short name T934
Test name
Test status
Simulation time 59802006973 ps
CPU time 28.33 seconds
Started Aug 18 06:00:57 PM PDT 24
Finished Aug 18 06:01:25 PM PDT 24
Peak memory 200780 kb
Host smart-397eeb33-31a7-44b4-9b5c-ae98ec1826e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141843910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1141843910
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1786120334
Short name T503
Test name
Test status
Simulation time 564188825137 ps
CPU time 69.19 seconds
Started Aug 18 06:00:57 PM PDT 24
Finished Aug 18 06:02:07 PM PDT 24
Peak memory 200660 kb
Host smart-2f5c5978-8c12-4b9b-a455-e108da319d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786120334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1786120334
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.878395120
Short name T444
Test name
Test status
Simulation time 349220259689 ps
CPU time 139.52 seconds
Started Aug 18 06:00:57 PM PDT 24
Finished Aug 18 06:03:17 PM PDT 24
Peak memory 198032 kb
Host smart-91558665-f7b6-4e97-a662-5dc5d710231c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878395120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.878395120
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.655375396
Short name T1070
Test name
Test status
Simulation time 182818681820 ps
CPU time 343.24 seconds
Started Aug 18 06:00:57 PM PDT 24
Finished Aug 18 06:06:41 PM PDT 24
Peak memory 200920 kb
Host smart-82406c0c-e9c1-4c06-b1ed-329590d1c6b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655375396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.655375396
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.294975487
Short name T986
Test name
Test status
Simulation time 2455310239 ps
CPU time 3.46 seconds
Started Aug 18 06:00:56 PM PDT 24
Finished Aug 18 06:01:00 PM PDT 24
Peak memory 199496 kb
Host smart-55a61f26-ea40-409b-ac15-7873ea49240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294975487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.294975487
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.242990171
Short name T875
Test name
Test status
Simulation time 143676369782 ps
CPU time 58.31 seconds
Started Aug 18 06:00:55 PM PDT 24
Finished Aug 18 06:01:54 PM PDT 24
Peak memory 201072 kb
Host smart-5949345f-055d-4106-ac0b-3ead86004a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242990171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.242990171
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.926879096
Short name T642
Test name
Test status
Simulation time 9324077419 ps
CPU time 58.16 seconds
Started Aug 18 06:00:54 PM PDT 24
Finished Aug 18 06:01:52 PM PDT 24
Peak memory 200928 kb
Host smart-dc1aa5a4-8bbc-41c7-a7db-4f7bab7ec908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=926879096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.926879096
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.151824349
Short name T339
Test name
Test status
Simulation time 2651417477 ps
CPU time 8.12 seconds
Started Aug 18 06:00:57 PM PDT 24
Finished Aug 18 06:01:05 PM PDT 24
Peak memory 199024 kb
Host smart-628ae6ff-26ab-4c90-9af2-448467047d64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151824349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.151824349
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1778195439
Short name T571
Test name
Test status
Simulation time 37363769985 ps
CPU time 32.87 seconds
Started Aug 18 06:00:57 PM PDT 24
Finished Aug 18 06:01:30 PM PDT 24
Peak memory 200892 kb
Host smart-0596ac82-3cbc-4145-b73d-4837047b1ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778195439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1778195439
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1618114870
Short name T285
Test name
Test status
Simulation time 5175279443 ps
CPU time 4.07 seconds
Started Aug 18 06:00:58 PM PDT 24
Finished Aug 18 06:01:02 PM PDT 24
Peak memory 197028 kb
Host smart-6401408d-0f46-41f6-bc57-dedac8f05577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618114870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1618114870
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1133275795
Short name T302
Test name
Test status
Simulation time 490491896 ps
CPU time 1.57 seconds
Started Aug 18 06:00:54 PM PDT 24
Finished Aug 18 06:00:55 PM PDT 24
Peak memory 199344 kb
Host smart-fe14e11d-ccce-460c-9737-9e84f3fa7cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133275795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1133275795
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3309718431
Short name T471
Test name
Test status
Simulation time 2993784581 ps
CPU time 43.67 seconds
Started Aug 18 06:01:08 PM PDT 24
Finished Aug 18 06:01:52 PM PDT 24
Peak memory 217252 kb
Host smart-4afb9a8a-4215-411c-a3f7-07aca97bbf95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309718431 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3309718431
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1173229024
Short name T397
Test name
Test status
Simulation time 1150669535 ps
CPU time 2.09 seconds
Started Aug 18 06:00:54 PM PDT 24
Finished Aug 18 06:00:56 PM PDT 24
Peak memory 199588 kb
Host smart-574e9d3e-411c-42f7-bad9-a9321618e023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173229024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1173229024
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1729130893
Short name T291
Test name
Test status
Simulation time 20404277489 ps
CPU time 32.09 seconds
Started Aug 18 06:00:56 PM PDT 24
Finished Aug 18 06:01:28 PM PDT 24
Peak memory 200860 kb
Host smart-22fc2f9b-7003-42cd-95c5-d2e93a0a0b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729130893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1729130893
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.675011746
Short name T348
Test name
Test status
Simulation time 12402029 ps
CPU time 0.57 seconds
Started Aug 18 05:57:43 PM PDT 24
Finished Aug 18 05:57:44 PM PDT 24
Peak memory 196484 kb
Host smart-a829c1e9-4fe1-4b61-83f4-b7968f3afc03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675011746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.675011746
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1502041706
Short name T6
Test name
Test status
Simulation time 137348546025 ps
CPU time 62.51 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:58:39 PM PDT 24
Peak memory 200828 kb
Host smart-6ed0f834-a16a-42b0-8d44-94fdce28ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502041706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1502041706
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2465115358
Short name T666
Test name
Test status
Simulation time 22460178167 ps
CPU time 27.65 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:58:12 PM PDT 24
Peak memory 200924 kb
Host smart-0b94a76e-f19b-4b6e-a71d-f9cbbb043f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465115358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2465115358
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.384636989
Short name T689
Test name
Test status
Simulation time 14042362904 ps
CPU time 13.49 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:57:58 PM PDT 24
Peak memory 200900 kb
Host smart-4135db29-df17-4008-a127-d7d722bacd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384636989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.384636989
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1843814479
Short name T532
Test name
Test status
Simulation time 331991772515 ps
CPU time 474.69 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 06:05:40 PM PDT 24
Peak memory 200732 kb
Host smart-89b3551e-e6e0-471b-862d-c7e2013c6199
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843814479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1843814479
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4291636267
Short name T63
Test name
Test status
Simulation time 73040064881 ps
CPU time 744.76 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 06:10:08 PM PDT 24
Peak memory 200940 kb
Host smart-60aea946-9f67-46bd-b73c-4b2e4e799882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291636267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4291636267
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2671067267
Short name T867
Test name
Test status
Simulation time 9740622299 ps
CPU time 13.23 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:57:58 PM PDT 24
Peak memory 200872 kb
Host smart-dfbf0067-9ef0-4d44-8fcb-a240699accc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671067267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2671067267
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2204290029
Short name T246
Test name
Test status
Simulation time 171155562464 ps
CPU time 39 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:58:23 PM PDT 24
Peak memory 209136 kb
Host smart-10606cf8-bcea-49a5-b568-d6730534f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204290029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2204290029
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2019038412
Short name T248
Test name
Test status
Simulation time 16661763046 ps
CPU time 988.11 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 200920 kb
Host smart-33e956a1-3743-481b-b6d4-a399658134e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019038412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2019038412
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.670268504
Short name T883
Test name
Test status
Simulation time 3709810819 ps
CPU time 30.66 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:58:16 PM PDT 24
Peak memory 198936 kb
Host smart-fe9316ca-c7c7-4b43-97ae-172ca9cacaad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670268504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.670268504
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2304386992
Short name T496
Test name
Test status
Simulation time 144483066424 ps
CPU time 206.06 seconds
Started Aug 18 05:57:46 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 200028 kb
Host smart-75669a67-2e60-45ce-b5c6-c45f53ff91fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304386992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2304386992
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2316897497
Short name T421
Test name
Test status
Simulation time 4061744218 ps
CPU time 2.15 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:57:47 PM PDT 24
Peak memory 197012 kb
Host smart-bbe7f608-ebdf-4768-9776-c9ac308bf7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316897497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2316897497
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2974819169
Short name T78
Test name
Test status
Simulation time 227075799 ps
CPU time 0.82 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:57:46 PM PDT 24
Peak memory 218912 kb
Host smart-a727f0ef-d7fb-45b9-9d68-1fa29118b34b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974819169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2974819169
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2317759366
Short name T450
Test name
Test status
Simulation time 5538237640 ps
CPU time 14.81 seconds
Started Aug 18 05:57:37 PM PDT 24
Finished Aug 18 05:57:52 PM PDT 24
Peak memory 200868 kb
Host smart-cad32e67-022a-49da-8e20-22cec786afcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317759366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2317759366
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3509402404
Short name T591
Test name
Test status
Simulation time 5315806691 ps
CPU time 82.86 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:59:08 PM PDT 24
Peak memory 217516 kb
Host smart-3adc3757-a42f-4991-9bae-8c81eb3ef420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509402404 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3509402404
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.207428306
Short name T313
Test name
Test status
Simulation time 7479016964 ps
CPU time 8.7 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:57:53 PM PDT 24
Peak memory 200196 kb
Host smart-17cc08af-02ce-4ad0-b8c4-9ea8021bb80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207428306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.207428306
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.4184093853
Short name T664
Test name
Test status
Simulation time 89694999577 ps
CPU time 107.52 seconds
Started Aug 18 05:57:39 PM PDT 24
Finished Aug 18 05:59:27 PM PDT 24
Peak memory 200920 kb
Host smart-442884a7-de93-4ccf-a1e9-49b41454d94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184093853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.4184093853
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.834758741
Short name T449
Test name
Test status
Simulation time 11555938 ps
CPU time 0.54 seconds
Started Aug 18 06:01:04 PM PDT 24
Finished Aug 18 06:01:04 PM PDT 24
Peak memory 196528 kb
Host smart-2db37d42-656e-45f1-9a01-245ff16617f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834758741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.834758741
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1667465485
Short name T112
Test name
Test status
Simulation time 100515564416 ps
CPU time 19.56 seconds
Started Aug 18 06:01:00 PM PDT 24
Finished Aug 18 06:01:20 PM PDT 24
Peak memory 200856 kb
Host smart-95c9dfa5-9d00-4b04-b1bd-ac1fda3d7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667465485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1667465485
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3310239311
Short name T747
Test name
Test status
Simulation time 19873721180 ps
CPU time 10.29 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 200912 kb
Host smart-d2213780-c1e3-4369-8180-b04c056c4737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310239311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3310239311
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1160478124
Short name T877
Test name
Test status
Simulation time 17165319591 ps
CPU time 11.28 seconds
Started Aug 18 06:01:04 PM PDT 24
Finished Aug 18 06:01:15 PM PDT 24
Peak memory 200936 kb
Host smart-9c410313-d5de-4be6-b1fd-6c8732c31fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160478124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1160478124
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2879249598
Short name T325
Test name
Test status
Simulation time 73971455903 ps
CPU time 141.48 seconds
Started Aug 18 06:01:08 PM PDT 24
Finished Aug 18 06:03:30 PM PDT 24
Peak memory 200788 kb
Host smart-b9dc2aac-5cc3-4581-9791-5f93279c81cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879249598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2879249598
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2206357222
Short name T375
Test name
Test status
Simulation time 113626352666 ps
CPU time 494.52 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:09:16 PM PDT 24
Peak memory 200884 kb
Host smart-978798e5-76ae-4844-9d62-8ee9b2fbaa60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206357222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2206357222
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2829093797
Short name T808
Test name
Test status
Simulation time 4176404607 ps
CPU time 11.15 seconds
Started Aug 18 06:01:01 PM PDT 24
Finished Aug 18 06:01:13 PM PDT 24
Peak memory 200840 kb
Host smart-079d6197-3bf9-433c-9fd0-6ac810f249fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829093797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2829093797
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1464919268
Short name T935
Test name
Test status
Simulation time 165783683351 ps
CPU time 75.43 seconds
Started Aug 18 06:01:03 PM PDT 24
Finished Aug 18 06:02:18 PM PDT 24
Peak memory 209288 kb
Host smart-296da063-c6d2-41c9-8664-136c01b298f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464919268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1464919268
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3269049262
Short name T283
Test name
Test status
Simulation time 12086051960 ps
CPU time 701.26 seconds
Started Aug 18 06:01:01 PM PDT 24
Finished Aug 18 06:12:43 PM PDT 24
Peak memory 200884 kb
Host smart-49b496d6-8759-41d9-92ed-7138ae0e9d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269049262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3269049262
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3295632494
Short name T66
Test name
Test status
Simulation time 2251622481 ps
CPU time 3.7 seconds
Started Aug 18 06:01:08 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 199644 kb
Host smart-fb54705f-3db7-46e5-ab0f-68ab59ef718f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295632494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3295632494
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1898781999
Short name T832
Test name
Test status
Simulation time 41084891296 ps
CPU time 16.73 seconds
Started Aug 18 06:01:08 PM PDT 24
Finished Aug 18 06:01:25 PM PDT 24
Peak memory 200828 kb
Host smart-84c56062-d252-42e6-8573-3a99b88057de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898781999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1898781999
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2353938680
Short name T629
Test name
Test status
Simulation time 40459736438 ps
CPU time 62.67 seconds
Started Aug 18 06:01:03 PM PDT 24
Finished Aug 18 06:02:05 PM PDT 24
Peak memory 197084 kb
Host smart-edad9858-c8c8-48cd-b629-b0535e6ea085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353938680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2353938680
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.191268932
Short name T515
Test name
Test status
Simulation time 481518274 ps
CPU time 1.54 seconds
Started Aug 18 06:01:03 PM PDT 24
Finished Aug 18 06:01:04 PM PDT 24
Peak memory 200572 kb
Host smart-7d180dab-6691-4687-9cc4-2eab77d7919a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191268932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.191268932
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3675878568
Short name T535
Test name
Test status
Simulation time 216000972181 ps
CPU time 83.8 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:02:26 PM PDT 24
Peak memory 200788 kb
Host smart-1c61e17e-9fa1-4f2d-bdf7-5aeef926efac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675878568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3675878568
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.205415084
Short name T21
Test name
Test status
Simulation time 2617249860 ps
CPU time 58.75 seconds
Started Aug 18 06:01:04 PM PDT 24
Finished Aug 18 06:02:03 PM PDT 24
Peak memory 217108 kb
Host smart-743b6972-4a3d-44bf-8157-4a98b95697fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205415084 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.205415084
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1940844505
Short name T968
Test name
Test status
Simulation time 1379413393 ps
CPU time 6.14 seconds
Started Aug 18 06:01:00 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 200628 kb
Host smart-e2c68d18-edb7-4af2-988f-2cde929c1d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940844505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1940844505
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.943836768
Short name T260
Test name
Test status
Simulation time 55387810392 ps
CPU time 55.13 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:01:57 PM PDT 24
Peak memory 200768 kb
Host smart-58ea41b4-8a80-4697-ab16-fccf51f92cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943836768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.943836768
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.943242157
Short name T346
Test name
Test status
Simulation time 35037157 ps
CPU time 0.57 seconds
Started Aug 18 06:01:13 PM PDT 24
Finished Aug 18 06:01:13 PM PDT 24
Peak memory 195696 kb
Host smart-cc96a275-5b3d-41a2-9780-07bc6f245d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943242157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.943242157
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.600974210
Short name T277
Test name
Test status
Simulation time 230292568140 ps
CPU time 150.92 seconds
Started Aug 18 06:01:01 PM PDT 24
Finished Aug 18 06:03:32 PM PDT 24
Peak memory 200828 kb
Host smart-dae3ca4d-a313-42a7-81d6-a4a5addf9a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600974210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.600974210
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1307091726
Short name T842
Test name
Test status
Simulation time 113633069986 ps
CPU time 157.22 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:03:39 PM PDT 24
Peak memory 200884 kb
Host smart-8ad69311-d761-4920-a702-e1d9671eed9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307091726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1307091726
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.162254858
Short name T967
Test name
Test status
Simulation time 158624416284 ps
CPU time 71.38 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:02:13 PM PDT 24
Peak memory 200820 kb
Host smart-1e9cb0a2-24f2-4123-b9bf-108993cefa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162254858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.162254858
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3505797478
Short name T430
Test name
Test status
Simulation time 53220555245 ps
CPU time 24.39 seconds
Started Aug 18 06:01:01 PM PDT 24
Finished Aug 18 06:01:25 PM PDT 24
Peak memory 200888 kb
Host smart-dcae0b4e-b1b9-48db-a937-a8418e101eb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505797478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3505797478
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.371209975
Short name T262
Test name
Test status
Simulation time 144053045545 ps
CPU time 698.94 seconds
Started Aug 18 06:01:13 PM PDT 24
Finished Aug 18 06:12:52 PM PDT 24
Peak memory 200932 kb
Host smart-9a825f0c-9d1d-44bf-8b20-7529e6d289f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371209975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.371209975
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.62400048
Short name T1010
Test name
Test status
Simulation time 1153743253 ps
CPU time 1.54 seconds
Started Aug 18 06:01:08 PM PDT 24
Finished Aug 18 06:01:10 PM PDT 24
Peak memory 196256 kb
Host smart-4f1fa90a-23e7-48b5-9109-ded72d81b7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62400048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.62400048
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.4241277822
Short name T387
Test name
Test status
Simulation time 35095023381 ps
CPU time 29.14 seconds
Started Aug 18 06:01:03 PM PDT 24
Finished Aug 18 06:01:32 PM PDT 24
Peak memory 200848 kb
Host smart-770a67ca-ee92-4f3a-ae20-0d11bbe3a7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241277822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.4241277822
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3219236922
Short name T801
Test name
Test status
Simulation time 17907078398 ps
CPU time 218.87 seconds
Started Aug 18 06:01:16 PM PDT 24
Finished Aug 18 06:04:55 PM PDT 24
Peak memory 200840 kb
Host smart-ef03382d-d883-491a-8fbf-db6da8f3f4a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219236922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3219236922
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1655142184
Short name T367
Test name
Test status
Simulation time 4003300454 ps
CPU time 7.98 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:01:10 PM PDT 24
Peak memory 200348 kb
Host smart-fa30695e-199c-4506-be9e-178a97cde20b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655142184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1655142184
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1997999514
Short name T1150
Test name
Test status
Simulation time 219020343644 ps
CPU time 52.94 seconds
Started Aug 18 06:01:03 PM PDT 24
Finished Aug 18 06:01:56 PM PDT 24
Peak memory 200836 kb
Host smart-259f8e8f-2f39-401d-b807-b8ac9bd9aedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997999514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1997999514
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1238959857
Short name T377
Test name
Test status
Simulation time 3853627312 ps
CPU time 6.33 seconds
Started Aug 18 06:01:05 PM PDT 24
Finished Aug 18 06:01:11 PM PDT 24
Peak memory 197048 kb
Host smart-afd8ede0-a211-42cb-adcb-ce11e6ed8b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238959857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1238959857
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.8179374
Short name T363
Test name
Test status
Simulation time 885778331 ps
CPU time 4.1 seconds
Started Aug 18 06:01:02 PM PDT 24
Finished Aug 18 06:01:06 PM PDT 24
Peak memory 200396 kb
Host smart-06e524a4-6353-43c7-8d4e-458e598513f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8179374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.8179374
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3002673005
Short name T493
Test name
Test status
Simulation time 555312324743 ps
CPU time 338.92 seconds
Started Aug 18 06:01:13 PM PDT 24
Finished Aug 18 06:06:53 PM PDT 24
Peak memory 200864 kb
Host smart-b5264652-f48f-4430-8e2e-635e41f3cac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002673005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3002673005
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3255870075
Short name T320
Test name
Test status
Simulation time 2858191778 ps
CPU time 27.41 seconds
Started Aug 18 06:01:11 PM PDT 24
Finished Aug 18 06:01:38 PM PDT 24
Peak memory 216684 kb
Host smart-a223fe7d-2a24-47bf-8250-7b5a08eab570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255870075 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3255870075
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1378272112
Short name T406
Test name
Test status
Simulation time 7114620091 ps
CPU time 7.02 seconds
Started Aug 18 06:01:06 PM PDT 24
Finished Aug 18 06:01:13 PM PDT 24
Peak memory 200856 kb
Host smart-6600de50-b057-4719-94ba-28801f590efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378272112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1378272112
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1019403973
Short name T1162
Test name
Test status
Simulation time 21775202712 ps
CPU time 31.8 seconds
Started Aug 18 06:01:03 PM PDT 24
Finished Aug 18 06:01:35 PM PDT 24
Peak memory 200872 kb
Host smart-152f7d6d-34e3-47e6-98dd-35be5fd68cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019403973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1019403973
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3914901021
Short name T24
Test name
Test status
Simulation time 14970937 ps
CPU time 0.55 seconds
Started Aug 18 06:01:12 PM PDT 24
Finished Aug 18 06:01:13 PM PDT 24
Peak memory 196228 kb
Host smart-2c5cd804-cff6-4fa3-883f-3a2c71dadf13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914901021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3914901021
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3301974136
Short name T855
Test name
Test status
Simulation time 319532954786 ps
CPU time 284.83 seconds
Started Aug 18 06:01:12 PM PDT 24
Finished Aug 18 06:05:57 PM PDT 24
Peak memory 200936 kb
Host smart-39c298a5-01be-4562-958f-58ba8d0bb86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301974136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3301974136
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.165732802
Short name T898
Test name
Test status
Simulation time 90551495433 ps
CPU time 24.35 seconds
Started Aug 18 06:01:09 PM PDT 24
Finished Aug 18 06:01:34 PM PDT 24
Peak memory 200856 kb
Host smart-5f00491f-87e6-4d13-855d-aa18b44269c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165732802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.165732802
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2513076092
Short name T1082
Test name
Test status
Simulation time 26576601740 ps
CPU time 41.05 seconds
Started Aug 18 06:01:11 PM PDT 24
Finished Aug 18 06:01:52 PM PDT 24
Peak memory 200924 kb
Host smart-61b5c6b2-8631-430f-8fc0-2579594e32f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513076092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2513076092
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.85834887
Short name T846
Test name
Test status
Simulation time 3743216909 ps
CPU time 2.21 seconds
Started Aug 18 06:01:12 PM PDT 24
Finished Aug 18 06:01:15 PM PDT 24
Peak memory 197392 kb
Host smart-95d16dba-696e-4498-9372-638763e5d16b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85834887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.85834887
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3731967049
Short name T456
Test name
Test status
Simulation time 69594462432 ps
CPU time 284.19 seconds
Started Aug 18 06:01:11 PM PDT 24
Finished Aug 18 06:05:55 PM PDT 24
Peak memory 200924 kb
Host smart-7bd3cee8-6c3d-4173-8bfe-4f2b8ff0efb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731967049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3731967049
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.780145809
Short name T784
Test name
Test status
Simulation time 7534149261 ps
CPU time 10.08 seconds
Started Aug 18 06:01:11 PM PDT 24
Finished Aug 18 06:01:22 PM PDT 24
Peak memory 200768 kb
Host smart-fcd3fd47-9a98-4ede-8cca-29849fdeb952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780145809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.780145809
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1567370460
Short name T975
Test name
Test status
Simulation time 61930494351 ps
CPU time 122.12 seconds
Started Aug 18 06:01:12 PM PDT 24
Finished Aug 18 06:03:14 PM PDT 24
Peak memory 200008 kb
Host smart-15ec043e-b3f5-45c7-8dac-f7c058c9d5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567370460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1567370460
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.85382162
Short name T1044
Test name
Test status
Simulation time 16457917964 ps
CPU time 909.41 seconds
Started Aug 18 06:01:13 PM PDT 24
Finished Aug 18 06:16:22 PM PDT 24
Peak memory 200428 kb
Host smart-81cf68b6-1605-44c7-a1cc-d2ac109142c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85382162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.85382162
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.236585602
Short name T522
Test name
Test status
Simulation time 6890997539 ps
CPU time 62.1 seconds
Started Aug 18 06:01:12 PM PDT 24
Finished Aug 18 06:02:14 PM PDT 24
Peak memory 199808 kb
Host smart-ca95c673-80ca-49ea-a128-b67e2c9a0102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236585602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.236585602
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3013932542
Short name T813
Test name
Test status
Simulation time 23156098835 ps
CPU time 35.22 seconds
Started Aug 18 06:01:12 PM PDT 24
Finished Aug 18 06:01:48 PM PDT 24
Peak memory 200848 kb
Host smart-5005072e-28e9-4cdb-85e8-66832b8aaa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013932542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3013932542
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3119559733
Short name T1020
Test name
Test status
Simulation time 675899851 ps
CPU time 0.92 seconds
Started Aug 18 06:01:11 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 196384 kb
Host smart-3329dc3c-3427-472c-acc4-e90094a3fc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119559733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3119559733
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3248491030
Short name T847
Test name
Test status
Simulation time 309606748 ps
CPU time 1.19 seconds
Started Aug 18 06:01:12 PM PDT 24
Finished Aug 18 06:01:13 PM PDT 24
Peak memory 199988 kb
Host smart-db1052ec-d519-4531-8538-0545a43d958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248491030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3248491030
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2770816688
Short name T170
Test name
Test status
Simulation time 21476479874 ps
CPU time 26.66 seconds
Started Aug 18 06:01:11 PM PDT 24
Finished Aug 18 06:01:37 PM PDT 24
Peak memory 200952 kb
Host smart-43314a3b-86e2-455c-9e2c-b510759cef7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770816688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2770816688
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.4116739635
Short name T1058
Test name
Test status
Simulation time 4945774417 ps
CPU time 60.44 seconds
Started Aug 18 06:01:12 PM PDT 24
Finished Aug 18 06:02:13 PM PDT 24
Peak memory 209388 kb
Host smart-598e502d-cb65-4671-a3d2-8c55821319af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116739635 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.4116739635
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1923193637
Short name T579
Test name
Test status
Simulation time 2104586028 ps
CPU time 1.92 seconds
Started Aug 18 06:01:11 PM PDT 24
Finished Aug 18 06:01:13 PM PDT 24
Peak memory 200468 kb
Host smart-770b542c-5ac6-4778-ab86-31fb89b33432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923193637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1923193637
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4284053820
Short name T974
Test name
Test status
Simulation time 89959792564 ps
CPU time 225.71 seconds
Started Aug 18 06:01:13 PM PDT 24
Finished Aug 18 06:04:59 PM PDT 24
Peak memory 200936 kb
Host smart-c5829046-0a76-4260-820a-4f4b2b3025fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284053820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4284053820
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1916353149
Short name T964
Test name
Test status
Simulation time 90432187 ps
CPU time 0.58 seconds
Started Aug 18 06:01:22 PM PDT 24
Finished Aug 18 06:01:23 PM PDT 24
Peak memory 196484 kb
Host smart-fa2e44a3-7918-4914-918e-6cd39afdb6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916353149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1916353149
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1438532197
Short name T1039
Test name
Test status
Simulation time 19623686863 ps
CPU time 15.09 seconds
Started Aug 18 06:01:19 PM PDT 24
Finished Aug 18 06:01:35 PM PDT 24
Peak memory 200652 kb
Host smart-dab9624c-c944-4245-a4ab-05289f7d9cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438532197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1438532197
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2088472587
Short name T41
Test name
Test status
Simulation time 246314164686 ps
CPU time 331.07 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:06:52 PM PDT 24
Peak memory 200896 kb
Host smart-978ddf21-5750-42b6-9a55-a152c20c07ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088472587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2088472587
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2924312941
Short name T168
Test name
Test status
Simulation time 47812819210 ps
CPU time 13.47 seconds
Started Aug 18 06:01:22 PM PDT 24
Finished Aug 18 06:01:36 PM PDT 24
Peak memory 200924 kb
Host smart-99721c41-07b6-4d55-b717-8bf3402f3c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924312941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2924312941
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2504801283
Short name T95
Test name
Test status
Simulation time 12045836684 ps
CPU time 5.87 seconds
Started Aug 18 06:01:20 PM PDT 24
Finished Aug 18 06:01:26 PM PDT 24
Peak memory 199280 kb
Host smart-7cf40379-7c1b-41ad-97e9-f79b9b6ba131
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504801283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2504801283
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3985090163
Short name T953
Test name
Test status
Simulation time 106668515812 ps
CPU time 440.29 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:08:42 PM PDT 24
Peak memory 200836 kb
Host smart-995ce094-9db8-454b-b0f6-c604ba17ef87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985090163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3985090163
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.282765226
Short name T432
Test name
Test status
Simulation time 2992148536 ps
CPU time 2.95 seconds
Started Aug 18 06:01:20 PM PDT 24
Finished Aug 18 06:01:23 PM PDT 24
Peak memory 198104 kb
Host smart-d873354b-e089-4751-9a9f-c469c25b3168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282765226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.282765226
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.817205326
Short name T241
Test name
Test status
Simulation time 99479462086 ps
CPU time 165.49 seconds
Started Aug 18 06:01:22 PM PDT 24
Finished Aug 18 06:04:08 PM PDT 24
Peak memory 199948 kb
Host smart-ee14366d-84d0-4514-a0fb-33899ae5bf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817205326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.817205326
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3446359654
Short name T335
Test name
Test status
Simulation time 8046255975 ps
CPU time 196.13 seconds
Started Aug 18 06:01:20 PM PDT 24
Finished Aug 18 06:04:37 PM PDT 24
Peak memory 200880 kb
Host smart-05dfecd9-00f9-4dd4-b829-a44c91ffbf80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3446359654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3446359654
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.4116222170
Short name T713
Test name
Test status
Simulation time 5543982524 ps
CPU time 51.09 seconds
Started Aug 18 06:01:22 PM PDT 24
Finished Aug 18 06:02:13 PM PDT 24
Peak memory 200088 kb
Host smart-040ea94d-fac1-4b22-a799-caf2c1bd766b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116222170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4116222170
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1122178990
Short name T594
Test name
Test status
Simulation time 35247946656 ps
CPU time 58.52 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:02:20 PM PDT 24
Peak memory 200820 kb
Host smart-973fa867-0745-41fc-95dd-ee1603373128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122178990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1122178990
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3361034179
Short name T707
Test name
Test status
Simulation time 4104820313 ps
CPU time 3.07 seconds
Started Aug 18 06:01:20 PM PDT 24
Finished Aug 18 06:01:23 PM PDT 24
Peak memory 197412 kb
Host smart-ca669454-64b0-4622-9d25-699b2f529390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361034179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3361034179
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2602583876
Short name T1029
Test name
Test status
Simulation time 123898550 ps
CPU time 1.02 seconds
Started Aug 18 06:01:10 PM PDT 24
Finished Aug 18 06:01:12 PM PDT 24
Peak memory 199956 kb
Host smart-e106fbff-917f-4314-9bd8-5d13ed401924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602583876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2602583876
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2865940517
Short name T683
Test name
Test status
Simulation time 4761381796 ps
CPU time 21.92 seconds
Started Aug 18 06:01:25 PM PDT 24
Finished Aug 18 06:01:47 PM PDT 24
Peak memory 216540 kb
Host smart-0e58b4fa-3e78-44c8-b4b6-37a751fe0223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865940517 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2865940517
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.755094104
Short name T479
Test name
Test status
Simulation time 7544427725 ps
CPU time 12.82 seconds
Started Aug 18 06:01:20 PM PDT 24
Finished Aug 18 06:01:33 PM PDT 24
Peak memory 200896 kb
Host smart-c13fb809-681d-46e4-bd7c-572de8375d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755094104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.755094104
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2610235291
Short name T263
Test name
Test status
Simulation time 41323908493 ps
CPU time 71.63 seconds
Started Aug 18 06:01:13 PM PDT 24
Finished Aug 18 06:02:25 PM PDT 24
Peak memory 200632 kb
Host smart-d5551fd2-76dd-4e80-85ff-ca9588c68948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610235291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2610235291
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2744634505
Short name T789
Test name
Test status
Simulation time 24830101 ps
CPU time 0.55 seconds
Started Aug 18 06:01:27 PM PDT 24
Finished Aug 18 06:01:27 PM PDT 24
Peak memory 196528 kb
Host smart-f5e3f6e7-24e4-4de6-8ed4-a4a313090929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744634505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2744634505
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3766946975
Short name T489
Test name
Test status
Simulation time 119535547148 ps
CPU time 20.94 seconds
Started Aug 18 06:01:19 PM PDT 24
Finished Aug 18 06:01:40 PM PDT 24
Peak memory 200916 kb
Host smart-157d01c0-41e8-49e4-aca9-9b8cc51571c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766946975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3766946975
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2222860603
Short name T109
Test name
Test status
Simulation time 91867445749 ps
CPU time 103.26 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:03:04 PM PDT 24
Peak memory 200928 kb
Host smart-b9f3d684-f578-4766-bf04-75672ba873e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222860603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2222860603
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3669636877
Short name T169
Test name
Test status
Simulation time 32389921013 ps
CPU time 25.44 seconds
Started Aug 18 06:01:19 PM PDT 24
Finished Aug 18 06:01:44 PM PDT 24
Peak memory 200848 kb
Host smart-fbcf7961-697f-4bf2-b92e-e084ecc1851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669636877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3669636877
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2795712653
Short name T940
Test name
Test status
Simulation time 43662351034 ps
CPU time 60.47 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:02:21 PM PDT 24
Peak memory 199076 kb
Host smart-2d8da9ae-d439-404f-88d9-e5b3db24635a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795712653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2795712653
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.516969268
Short name T1064
Test name
Test status
Simulation time 269103249245 ps
CPU time 241.12 seconds
Started Aug 18 06:01:20 PM PDT 24
Finished Aug 18 06:05:21 PM PDT 24
Peak memory 200884 kb
Host smart-a7c80007-45ec-427b-88c7-fbd6d8aecb7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516969268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.516969268
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3104072584
Short name T833
Test name
Test status
Simulation time 8496752094 ps
CPU time 4.67 seconds
Started Aug 18 06:01:32 PM PDT 24
Finished Aug 18 06:01:36 PM PDT 24
Peak memory 199920 kb
Host smart-d7a773bb-add7-48ac-9674-b64a5f7d7905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104072584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3104072584
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.4256288211
Short name T305
Test name
Test status
Simulation time 118371433864 ps
CPU time 50.65 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:02:12 PM PDT 24
Peak memory 200880 kb
Host smart-3e8c9394-0370-45d6-b476-847ef0d95824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256288211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.4256288211
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2046725758
Short name T81
Test name
Test status
Simulation time 15615752768 ps
CPU time 909.98 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:16:32 PM PDT 24
Peak memory 200924 kb
Host smart-834d523f-b934-4dd9-b47a-1e4fa788caa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046725758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2046725758
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2495727897
Short name T361
Test name
Test status
Simulation time 6032426801 ps
CPU time 24.39 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:01:45 PM PDT 24
Peak memory 199000 kb
Host smart-131f777a-45da-41be-9d1b-cd18cb033fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2495727897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2495727897
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.4198193907
Short name T156
Test name
Test status
Simulation time 148571563398 ps
CPU time 55.51 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:02:17 PM PDT 24
Peak memory 200836 kb
Host smart-4412d0d7-57b3-462b-b880-ed6cbfaaf7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198193907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4198193907
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2531840442
Short name T928
Test name
Test status
Simulation time 533524069 ps
CPU time 1.55 seconds
Started Aug 18 06:01:21 PM PDT 24
Finished Aug 18 06:01:23 PM PDT 24
Peak memory 196412 kb
Host smart-35597c5f-a7da-4e54-944c-9e29145fff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531840442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2531840442
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.4078832603
Short name T394
Test name
Test status
Simulation time 257330449 ps
CPU time 1.29 seconds
Started Aug 18 06:01:22 PM PDT 24
Finished Aug 18 06:01:24 PM PDT 24
Peak memory 199132 kb
Host smart-dd0ba9b3-e165-4f33-a057-04c0164cc77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078832603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4078832603
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2785397983
Short name T827
Test name
Test status
Simulation time 563564838627 ps
CPU time 1276.46 seconds
Started Aug 18 06:01:27 PM PDT 24
Finished Aug 18 06:22:44 PM PDT 24
Peak memory 200952 kb
Host smart-aa225b37-d8d9-48fc-97b0-a6584b71df43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785397983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2785397983
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2535200124
Short name T315
Test name
Test status
Simulation time 619533257 ps
CPU time 1.29 seconds
Started Aug 18 06:01:23 PM PDT 24
Finished Aug 18 06:01:24 PM PDT 24
Peak memory 199060 kb
Host smart-75d679e7-276f-4a32-bbe1-a3544d5c3202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535200124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2535200124
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.37416556
Short name T800
Test name
Test status
Simulation time 94530112939 ps
CPU time 50.65 seconds
Started Aug 18 06:01:22 PM PDT 24
Finished Aug 18 06:02:12 PM PDT 24
Peak memory 200932 kb
Host smart-9def7b99-94cb-4494-a5ac-f104b7f5cced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37416556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.37416556
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3793342460
Short name T388
Test name
Test status
Simulation time 28770948 ps
CPU time 0.51 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:01:29 PM PDT 24
Peak memory 195216 kb
Host smart-eaa672c5-e642-418f-baa5-b61b86eafae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793342460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3793342460
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2520673738
Short name T802
Test name
Test status
Simulation time 281502637628 ps
CPU time 113.02 seconds
Started Aug 18 06:01:26 PM PDT 24
Finished Aug 18 06:03:19 PM PDT 24
Peak memory 200824 kb
Host smart-1910a5ce-f5ce-4ab0-8cc1-904953f9c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520673738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2520673738
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3507938359
Short name T133
Test name
Test status
Simulation time 20027693044 ps
CPU time 11.43 seconds
Started Aug 18 06:01:29 PM PDT 24
Finished Aug 18 06:01:40 PM PDT 24
Peak memory 200924 kb
Host smart-5ebafee6-9bad-4c77-a938-c41a679ce12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507938359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3507938359
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_intr.2506520709
Short name T366
Test name
Test status
Simulation time 15119883350 ps
CPU time 26.25 seconds
Started Aug 18 06:01:30 PM PDT 24
Finished Aug 18 06:01:57 PM PDT 24
Peak memory 200824 kb
Host smart-29802c00-748d-47ab-9fef-56abcd03f174
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506520709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2506520709
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1492432423
Short name T390
Test name
Test status
Simulation time 106804522469 ps
CPU time 781.08 seconds
Started Aug 18 06:01:29 PM PDT 24
Finished Aug 18 06:14:30 PM PDT 24
Peak memory 200828 kb
Host smart-4f431da0-d659-44cf-9606-aae07c2bc0d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492432423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1492432423
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.248037173
Short name T910
Test name
Test status
Simulation time 7871407300 ps
CPU time 13.04 seconds
Started Aug 18 06:01:29 PM PDT 24
Finished Aug 18 06:01:42 PM PDT 24
Peak memory 200616 kb
Host smart-ecc8c90d-88c6-4ffe-877f-412adc3ba027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248037173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.248037173
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.560618378
Short name T1113
Test name
Test status
Simulation time 154086631243 ps
CPU time 279.95 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:06:08 PM PDT 24
Peak memory 209304 kb
Host smart-054ecbee-654e-4d23-a4ed-370318140585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560618378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.560618378
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1653679657
Short name T242
Test name
Test status
Simulation time 4955783154 ps
CPU time 181.32 seconds
Started Aug 18 06:01:27 PM PDT 24
Finished Aug 18 06:04:28 PM PDT 24
Peak memory 200948 kb
Host smart-c14517ef-0853-4444-a60e-afb0c551efba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653679657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1653679657
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1310847442
Short name T1158
Test name
Test status
Simulation time 2328481305 ps
CPU time 13.47 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:01:41 PM PDT 24
Peak memory 199020 kb
Host smart-7f406bde-0e44-4b78-9f9c-daa6cb9c5d8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310847442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1310847442
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.807124591
Short name T861
Test name
Test status
Simulation time 78507357460 ps
CPU time 33.27 seconds
Started Aug 18 06:01:27 PM PDT 24
Finished Aug 18 06:02:00 PM PDT 24
Peak memory 200884 kb
Host smart-b2b8cfe3-510f-46f3-b4e3-a91403af122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807124591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.807124591
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.954632054
Short name T646
Test name
Test status
Simulation time 3210802643 ps
CPU time 0.93 seconds
Started Aug 18 06:01:33 PM PDT 24
Finished Aug 18 06:01:34 PM PDT 24
Peak memory 196820 kb
Host smart-ebd8cc87-3bfd-4c1a-a91b-1ee11f9c3b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954632054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.954632054
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3186401187
Short name T826
Test name
Test status
Simulation time 5907125265 ps
CPU time 24.71 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:01:53 PM PDT 24
Peak memory 200592 kb
Host smart-73db1564-d4ec-4fab-b2eb-44b2194f856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186401187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3186401187
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.849775387
Short name T996
Test name
Test status
Simulation time 1312928008 ps
CPU time 23.49 seconds
Started Aug 18 06:01:29 PM PDT 24
Finished Aug 18 06:01:53 PM PDT 24
Peak memory 217292 kb
Host smart-9db09c39-e563-42be-87ba-39dd6b3aa3bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849775387 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.849775387
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.4186726391
Short name T901
Test name
Test status
Simulation time 7294076579 ps
CPU time 13.58 seconds
Started Aug 18 06:01:33 PM PDT 24
Finished Aug 18 06:01:47 PM PDT 24
Peak memory 200660 kb
Host smart-7051a456-fde0-49bb-a2b4-81548e89d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186726391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4186726391
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3009335651
Short name T610
Test name
Test status
Simulation time 60492653963 ps
CPU time 95.06 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:03:03 PM PDT 24
Peak memory 200936 kb
Host smart-d0fa8530-d91b-4d42-b8ea-b8802d6f3630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009335651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3009335651
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2487933108
Short name T691
Test name
Test status
Simulation time 30683277 ps
CPU time 0.55 seconds
Started Aug 18 06:01:40 PM PDT 24
Finished Aug 18 06:01:41 PM PDT 24
Peak memory 196472 kb
Host smart-08f97a86-1721-458f-a728-085107ac6444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487933108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2487933108
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1217662745
Short name T282
Test name
Test status
Simulation time 107645632655 ps
CPU time 191.35 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:04:39 PM PDT 24
Peak memory 200936 kb
Host smart-26396e32-6550-4604-ae81-6e651ac00513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217662745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1217662745
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.255088482
Short name T1177
Test name
Test status
Simulation time 14530470952 ps
CPU time 55.44 seconds
Started Aug 18 06:01:30 PM PDT 24
Finished Aug 18 06:02:26 PM PDT 24
Peak memory 200872 kb
Host smart-14a6062d-b7fe-4ab2-b320-aca0a25c7fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255088482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.255088482
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3919593727
Short name T590
Test name
Test status
Simulation time 108637826744 ps
CPU time 65.51 seconds
Started Aug 18 06:01:27 PM PDT 24
Finished Aug 18 06:02:33 PM PDT 24
Peak memory 200844 kb
Host smart-9f72fce1-c295-4e30-a848-2489c6e621cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919593727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3919593727
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3301342962
Short name T20
Test name
Test status
Simulation time 6429955117 ps
CPU time 9.11 seconds
Started Aug 18 06:01:28 PM PDT 24
Finished Aug 18 06:01:37 PM PDT 24
Peak memory 200896 kb
Host smart-2b89057a-f282-4be6-84c5-e5db193e8726
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301342962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3301342962
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_loopback.3955517415
Short name T349
Test name
Test status
Simulation time 2802839452 ps
CPU time 6.51 seconds
Started Aug 18 06:01:27 PM PDT 24
Finished Aug 18 06:01:34 PM PDT 24
Peak memory 199364 kb
Host smart-a07bbe38-b6b7-4a94-b8e6-4feeec375d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955517415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3955517415
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.570613568
Short name T938
Test name
Test status
Simulation time 10554945543 ps
CPU time 150.04 seconds
Started Aug 18 06:01:26 PM PDT 24
Finished Aug 18 06:03:56 PM PDT 24
Peak memory 200912 kb
Host smart-10a2e0a6-7b33-4fa1-9d33-6ffdc8019493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570613568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.570613568
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2731420182
Short name T418
Test name
Test status
Simulation time 1915955023 ps
CPU time 11.96 seconds
Started Aug 18 06:01:29 PM PDT 24
Finished Aug 18 06:01:41 PM PDT 24
Peak memory 199012 kb
Host smart-f8a5013e-9cae-46a6-bea0-89f68200f45d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731420182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2731420182
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2318422611
Short name T933
Test name
Test status
Simulation time 130402744623 ps
CPU time 65.58 seconds
Started Aug 18 06:01:27 PM PDT 24
Finished Aug 18 06:02:33 PM PDT 24
Peak memory 200576 kb
Host smart-a4ba43c8-99b8-4f5f-b2da-bdaaf2f2d318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318422611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2318422611
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1743082772
Short name T970
Test name
Test status
Simulation time 2523654648 ps
CPU time 4.28 seconds
Started Aug 18 06:01:30 PM PDT 24
Finished Aug 18 06:01:34 PM PDT 24
Peak memory 197412 kb
Host smart-e443c6f0-ac6b-45b9-837e-c6b1be4ee2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743082772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1743082772
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.953906332
Short name T386
Test name
Test status
Simulation time 5503837805 ps
CPU time 14.9 seconds
Started Aug 18 06:01:29 PM PDT 24
Finished Aug 18 06:01:44 PM PDT 24
Peak memory 200860 kb
Host smart-8930ce41-3fc1-496a-8f0d-4eccead9d95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953906332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.953906332
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1415297460
Short name T712
Test name
Test status
Simulation time 6224680054 ps
CPU time 31.86 seconds
Started Aug 18 06:01:36 PM PDT 24
Finished Aug 18 06:02:08 PM PDT 24
Peak memory 217564 kb
Host smart-d79c63e7-fa48-4cc3-ac4e-8f9d8e57269f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415297460 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1415297460
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2195394233
Short name T268
Test name
Test status
Simulation time 1550564017 ps
CPU time 2.96 seconds
Started Aug 18 06:01:30 PM PDT 24
Finished Aug 18 06:01:33 PM PDT 24
Peak memory 199356 kb
Host smart-f4c22b49-091c-4d54-9d3a-39033ba5bc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195394233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2195394233
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.387352883
Short name T445
Test name
Test status
Simulation time 170908750226 ps
CPU time 82.34 seconds
Started Aug 18 06:01:33 PM PDT 24
Finished Aug 18 06:02:55 PM PDT 24
Peak memory 200924 kb
Host smart-e52e7aab-30f7-4723-92ed-dd54a19aaf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387352883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.387352883
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3791880260
Short name T600
Test name
Test status
Simulation time 45191051 ps
CPU time 0.57 seconds
Started Aug 18 06:01:36 PM PDT 24
Finished Aug 18 06:01:37 PM PDT 24
Peak memory 196232 kb
Host smart-9f1fd479-35d2-4673-a800-c0c0ec8fa625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791880260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3791880260
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.270451656
Short name T931
Test name
Test status
Simulation time 264572655531 ps
CPU time 234.44 seconds
Started Aug 18 06:01:38 PM PDT 24
Finished Aug 18 06:05:33 PM PDT 24
Peak memory 200716 kb
Host smart-03f03133-74bf-4041-95f6-eb55d806da79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270451656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.270451656
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1003935501
Short name T284
Test name
Test status
Simulation time 46577764877 ps
CPU time 68.09 seconds
Started Aug 18 06:01:35 PM PDT 24
Finished Aug 18 06:02:43 PM PDT 24
Peak memory 200504 kb
Host smart-ad59976d-0e43-45d6-918b-e759ea38d947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003935501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1003935501
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_intr.93989077
Short name T1131
Test name
Test status
Simulation time 12346236409 ps
CPU time 6.32 seconds
Started Aug 18 06:01:39 PM PDT 24
Finished Aug 18 06:01:45 PM PDT 24
Peak memory 200732 kb
Host smart-d299175c-a722-4fd2-a656-96f6f58745c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93989077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.93989077
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1619532146
Short name T1008
Test name
Test status
Simulation time 52790481520 ps
CPU time 164.17 seconds
Started Aug 18 06:01:34 PM PDT 24
Finished Aug 18 06:04:19 PM PDT 24
Peak memory 200924 kb
Host smart-8f2166d2-f670-42a5-a5d6-dbd0ef1b11ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619532146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1619532146
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.551894836
Short name T1009
Test name
Test status
Simulation time 376935807 ps
CPU time 1.23 seconds
Started Aug 18 06:01:37 PM PDT 24
Finished Aug 18 06:01:38 PM PDT 24
Peak memory 196960 kb
Host smart-0f190168-2cae-4f72-9855-c44154130e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551894836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.551894836
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3972820973
Short name T306
Test name
Test status
Simulation time 47561647144 ps
CPU time 21.49 seconds
Started Aug 18 06:01:34 PM PDT 24
Finished Aug 18 06:01:56 PM PDT 24
Peak memory 201120 kb
Host smart-3ad4bfae-6334-48c9-b8c1-d25dddfc1a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972820973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3972820973
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1231624852
Short name T972
Test name
Test status
Simulation time 6549368083 ps
CPU time 27.57 seconds
Started Aug 18 06:01:37 PM PDT 24
Finished Aug 18 06:02:04 PM PDT 24
Peak memory 200804 kb
Host smart-bbd45f21-cf99-4f8c-aa86-2257ab67b557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231624852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1231624852
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2791120347
Short name T1075
Test name
Test status
Simulation time 2393814750 ps
CPU time 2.28 seconds
Started Aug 18 06:01:37 PM PDT 24
Finished Aug 18 06:01:39 PM PDT 24
Peak memory 199052 kb
Host smart-1f9c2d50-53d7-40c8-8143-a51c27ed82e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791120347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2791120347
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3427532256
Short name T915
Test name
Test status
Simulation time 42083163771 ps
CPU time 16.16 seconds
Started Aug 18 06:01:36 PM PDT 24
Finished Aug 18 06:01:52 PM PDT 24
Peak memory 199472 kb
Host smart-5812085e-2611-495b-bfb0-e0de73a5394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427532256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3427532256
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3849679946
Short name T509
Test name
Test status
Simulation time 626541768 ps
CPU time 0.85 seconds
Started Aug 18 06:01:40 PM PDT 24
Finished Aug 18 06:01:41 PM PDT 24
Peak memory 196356 kb
Host smart-219d4bcb-a139-4284-b94e-3bcd4d5d8acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849679946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3849679946
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.427630712
Short name T665
Test name
Test status
Simulation time 938936082 ps
CPU time 2.24 seconds
Started Aug 18 06:01:35 PM PDT 24
Finished Aug 18 06:01:37 PM PDT 24
Peak memory 199664 kb
Host smart-ed137fbe-2edf-4b32-bff6-0b8e605ae77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427630712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.427630712
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1203488746
Short name T1036
Test name
Test status
Simulation time 248847973484 ps
CPU time 100.05 seconds
Started Aug 18 06:01:39 PM PDT 24
Finished Aug 18 06:03:19 PM PDT 24
Peak memory 200896 kb
Host smart-438bc7db-f05e-47db-950a-817b0bfe1ab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203488746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1203488746
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3201586355
Short name T83
Test name
Test status
Simulation time 11736540526 ps
CPU time 40.64 seconds
Started Aug 18 06:01:36 PM PDT 24
Finished Aug 18 06:02:17 PM PDT 24
Peak memory 210360 kb
Host smart-fa5f8908-1f01-4d1e-84d3-b604204766a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201586355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3201586355
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1429258336
Short name T16
Test name
Test status
Simulation time 1381288833 ps
CPU time 2.29 seconds
Started Aug 18 06:01:41 PM PDT 24
Finished Aug 18 06:01:43 PM PDT 24
Peak memory 199680 kb
Host smart-a4ebf930-e221-459a-a80f-5c9ae813028a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429258336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1429258336
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.214354763
Short name T583
Test name
Test status
Simulation time 9935668344 ps
CPU time 9.4 seconds
Started Aug 18 06:01:35 PM PDT 24
Finished Aug 18 06:01:45 PM PDT 24
Peak memory 200704 kb
Host smart-86cecab4-7de3-4a40-9c3e-c354745e4ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214354763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.214354763
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3929080688
Short name T961
Test name
Test status
Simulation time 39904807 ps
CPU time 0.57 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:01:44 PM PDT 24
Peak memory 196240 kb
Host smart-e9ad029e-4097-4213-8358-9ade7b791f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929080688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3929080688
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.4006368310
Short name T690
Test name
Test status
Simulation time 181622699641 ps
CPU time 271.97 seconds
Started Aug 18 06:01:37 PM PDT 24
Finished Aug 18 06:06:09 PM PDT 24
Peak memory 200868 kb
Host smart-7a04f383-905d-4728-9df3-749dee0e5853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006368310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.4006368310
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.465091505
Short name T1148
Test name
Test status
Simulation time 66323477847 ps
CPU time 12.81 seconds
Started Aug 18 06:01:39 PM PDT 24
Finished Aug 18 06:01:52 PM PDT 24
Peak memory 200728 kb
Host smart-e8f435b6-6a50-49c4-a645-9713a45bbb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465091505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.465091505
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3104491268
Short name T225
Test name
Test status
Simulation time 88658789496 ps
CPU time 68.21 seconds
Started Aug 18 06:01:37 PM PDT 24
Finished Aug 18 06:02:45 PM PDT 24
Peak memory 200720 kb
Host smart-38fc9200-6a25-4b13-8247-9a0ad07baafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104491268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3104491268
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3546180645
Short name T4
Test name
Test status
Simulation time 8349942195 ps
CPU time 16.07 seconds
Started Aug 18 06:01:37 PM PDT 24
Finished Aug 18 06:01:53 PM PDT 24
Peak memory 200724 kb
Host smart-307101ab-ac01-4115-8f43-99e53192038b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546180645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3546180645
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1225250886
Short name T1011
Test name
Test status
Simulation time 144734347853 ps
CPU time 297.98 seconds
Started Aug 18 06:01:46 PM PDT 24
Finished Aug 18 06:06:44 PM PDT 24
Peak memory 200944 kb
Host smart-ee72e249-b229-49e6-8881-b7383d3ad590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225250886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1225250886
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3863976561
Short name T457
Test name
Test status
Simulation time 252620308 ps
CPU time 0.85 seconds
Started Aug 18 06:01:50 PM PDT 24
Finished Aug 18 06:01:51 PM PDT 24
Peak memory 196868 kb
Host smart-94055f16-00f2-48e0-bfa8-a96f664c5756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863976561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3863976561
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.4251691632
Short name T429
Test name
Test status
Simulation time 259187782605 ps
CPU time 52.78 seconds
Started Aug 18 06:01:40 PM PDT 24
Finished Aug 18 06:02:33 PM PDT 24
Peak memory 209276 kb
Host smart-9a2db662-d66d-48a4-b8c2-6fb5d91bafa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251691632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.4251691632
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.991622300
Short name T1137
Test name
Test status
Simulation time 3589284786 ps
CPU time 51.35 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:02:35 PM PDT 24
Peak memory 200940 kb
Host smart-c9300bbe-137b-4c69-96e9-37200630e674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991622300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.991622300
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3968140916
Short name T347
Test name
Test status
Simulation time 3536345845 ps
CPU time 22.97 seconds
Started Aug 18 06:01:37 PM PDT 24
Finished Aug 18 06:02:00 PM PDT 24
Peak memory 199324 kb
Host smart-e1c72ade-68e1-42ee-ab4a-917c54e51e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968140916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3968140916
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.4047098714
Short name T1133
Test name
Test status
Simulation time 60533555591 ps
CPU time 96.11 seconds
Started Aug 18 06:01:42 PM PDT 24
Finished Aug 18 06:03:18 PM PDT 24
Peak memory 200852 kb
Host smart-eeaaf10d-192f-4e49-87d6-9158c4920167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047098714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4047098714
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1766569596
Short name T272
Test name
Test status
Simulation time 68760191776 ps
CPU time 51.19 seconds
Started Aug 18 06:01:42 PM PDT 24
Finished Aug 18 06:02:33 PM PDT 24
Peak memory 196920 kb
Host smart-cacd665c-ec9d-4685-8a0c-e2b6f8c64464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766569596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1766569596
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3868641035
Short name T459
Test name
Test status
Simulation time 708265102 ps
CPU time 1.7 seconds
Started Aug 18 06:01:35 PM PDT 24
Finished Aug 18 06:01:37 PM PDT 24
Peak memory 199644 kb
Host smart-025baec7-889a-4e8b-9aeb-4b1eeae3dd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868641035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3868641035
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1544382626
Short name T837
Test name
Test status
Simulation time 5022117686 ps
CPU time 17.89 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:02:02 PM PDT 24
Peak memory 200972 kb
Host smart-15cd82b3-d318-4295-8332-f4e5fe3d7ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544382626 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1544382626
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2339329378
Short name T523
Test name
Test status
Simulation time 868487593 ps
CPU time 1.75 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:01:46 PM PDT 24
Peak memory 200576 kb
Host smart-080f58c7-04c6-434d-8997-6ba777013f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339329378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2339329378
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1584427158
Short name T741
Test name
Test status
Simulation time 19390076785 ps
CPU time 28.95 seconds
Started Aug 18 06:01:36 PM PDT 24
Finished Aug 18 06:02:05 PM PDT 24
Peak memory 200944 kb
Host smart-af57b327-2322-42c2-ba49-014d5d2e1ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584427158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1584427158
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.617072208
Short name T623
Test name
Test status
Simulation time 56854816 ps
CPU time 0.54 seconds
Started Aug 18 06:01:47 PM PDT 24
Finished Aug 18 06:01:48 PM PDT 24
Peak memory 195200 kb
Host smart-f2c7957f-d0e3-4fb9-bc32-04e596c13967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617072208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.617072208
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4034829764
Short name T1163
Test name
Test status
Simulation time 56427894982 ps
CPU time 14.17 seconds
Started Aug 18 06:01:45 PM PDT 24
Finished Aug 18 06:01:59 PM PDT 24
Peak memory 200900 kb
Host smart-e00838e2-5fc7-4a44-86f3-970f19d25f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034829764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4034829764
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3971280234
Short name T606
Test name
Test status
Simulation time 135789011496 ps
CPU time 204.12 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:05:08 PM PDT 24
Peak memory 200848 kb
Host smart-c77624ac-e043-4d0f-b07f-e7d1f99930a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971280234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3971280234
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3865702963
Short name T1063
Test name
Test status
Simulation time 60873479831 ps
CPU time 29.61 seconds
Started Aug 18 06:01:45 PM PDT 24
Finished Aug 18 06:02:15 PM PDT 24
Peak memory 200920 kb
Host smart-c6968de0-8c64-4194-bb81-46b7086f26cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865702963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3865702963
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.329653181
Short name T578
Test name
Test status
Simulation time 44773400986 ps
CPU time 66.32 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:02:50 PM PDT 24
Peak memory 200804 kb
Host smart-ebd26374-75c5-445d-b2ca-339fa406a1ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329653181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.329653181
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3707687043
Short name T658
Test name
Test status
Simulation time 72930895167 ps
CPU time 427.72 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:08:51 PM PDT 24
Peak memory 200928 kb
Host smart-65469a7e-307a-40d6-98e5-53b6395b6d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3707687043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3707687043
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1554667283
Short name T546
Test name
Test status
Simulation time 2896268270 ps
CPU time 5.06 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:01:49 PM PDT 24
Peak memory 197252 kb
Host smart-ec5baaed-abe3-4cd3-a605-456f847a87b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554667283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1554667283
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2280702752
Short name T794
Test name
Test status
Simulation time 20774405743 ps
CPU time 15.63 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:01:59 PM PDT 24
Peak memory 197792 kb
Host smart-b226172a-cff5-4886-bd26-a9ee3500fe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280702752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2280702752
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3930330392
Short name T1119
Test name
Test status
Simulation time 12086208039 ps
CPU time 613.38 seconds
Started Aug 18 06:01:47 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 200920 kb
Host smart-2e1687a4-b356-4051-87ea-1514dd70fc28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930330392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3930330392
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1126469232
Short name T350
Test name
Test status
Simulation time 2236399871 ps
CPU time 3.64 seconds
Started Aug 18 06:01:45 PM PDT 24
Finished Aug 18 06:01:49 PM PDT 24
Peak memory 198736 kb
Host smart-c2ee229f-5d92-40c0-8645-6f6abc8dfca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126469232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1126469232
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.74947765
Short name T638
Test name
Test status
Simulation time 31596158077 ps
CPU time 15.48 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:02:00 PM PDT 24
Peak memory 200816 kb
Host smart-cc0adb31-247f-4338-aae0-081c4dcf60f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74947765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.74947765
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3753051128
Short name T22
Test name
Test status
Simulation time 37764281649 ps
CPU time 56.44 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:02:39 PM PDT 24
Peak memory 196972 kb
Host smart-1fd7ddfb-6072-4240-b247-b0d3fb364733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753051128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3753051128
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1666298740
Short name T849
Test name
Test status
Simulation time 5361459241 ps
CPU time 12.99 seconds
Started Aug 18 06:01:45 PM PDT 24
Finished Aug 18 06:01:58 PM PDT 24
Peak memory 200716 kb
Host smart-5aa4bb8f-523f-4ede-8371-8511ac97cafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666298740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1666298740
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2890142828
Short name T586
Test name
Test status
Simulation time 756171437321 ps
CPU time 458.54 seconds
Started Aug 18 06:02:10 PM PDT 24
Finished Aug 18 06:09:49 PM PDT 24
Peak memory 200872 kb
Host smart-99ba0578-4523-4d58-916e-7c6ed36ab2a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890142828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2890142828
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2867369399
Short name T15
Test name
Test status
Simulation time 8943615385 ps
CPU time 74.91 seconds
Started Aug 18 06:01:42 PM PDT 24
Finished Aug 18 06:02:57 PM PDT 24
Peak memory 217500 kb
Host smart-e5d2745d-79e3-4f1c-82b3-afc619891a3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867369399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2867369399
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1761908811
Short name T461
Test name
Test status
Simulation time 805295661 ps
CPU time 2.92 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:01:47 PM PDT 24
Peak memory 199300 kb
Host smart-c8c811b2-b74a-468f-9d85-50df9ad1e496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761908811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1761908811
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.931844888
Short name T413
Test name
Test status
Simulation time 30847781443 ps
CPU time 44.79 seconds
Started Aug 18 06:01:45 PM PDT 24
Finished Aug 18 06:02:30 PM PDT 24
Peak memory 200896 kb
Host smart-d46384b3-5fb7-4631-b0a1-11c2fba0587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931844888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.931844888
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1629387552
Short name T601
Test name
Test status
Simulation time 20959137 ps
CPU time 0.56 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:57:46 PM PDT 24
Peak memory 196220 kb
Host smart-1a38d0e0-7b67-498a-a48a-63757a839af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629387552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1629387552
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1292495707
Short name T314
Test name
Test status
Simulation time 19081941322 ps
CPU time 26.01 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:58:10 PM PDT 24
Peak memory 200832 kb
Host smart-82b8bf4c-a13a-40bc-a959-a0d31437a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292495707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1292495707
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2562437841
Short name T304
Test name
Test status
Simulation time 77236484519 ps
CPU time 41.67 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:58:26 PM PDT 24
Peak memory 200872 kb
Host smart-170989eb-5c42-4f17-931b-d2b6c0d67e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562437841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2562437841
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2300413867
Short name T777
Test name
Test status
Simulation time 164252880005 ps
CPU time 79.1 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:59:04 PM PDT 24
Peak memory 200924 kb
Host smart-da3fe2df-d5bd-4888-a66f-6afcd817a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300413867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2300413867
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1147275683
Short name T673
Test name
Test status
Simulation time 66040457950 ps
CPU time 104.36 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:59:28 PM PDT 24
Peak memory 200808 kb
Host smart-e4d2c9a1-5c8f-4842-9e33-ac94a998808d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147275683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1147275683
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1021713636
Short name T682
Test name
Test status
Simulation time 347524999232 ps
CPU time 240.91 seconds
Started Aug 18 05:57:43 PM PDT 24
Finished Aug 18 06:01:44 PM PDT 24
Peak memory 200852 kb
Host smart-4e24db09-e165-4f96-8f3a-2f2945e261b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021713636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1021713636
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.310069309
Short name T1179
Test name
Test status
Simulation time 4471294226 ps
CPU time 2.98 seconds
Started Aug 18 05:57:46 PM PDT 24
Finished Aug 18 05:57:49 PM PDT 24
Peak memory 198588 kb
Host smart-8626fc2d-3c08-49f1-9097-e77985f623d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310069309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.310069309
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2429234990
Short name T976
Test name
Test status
Simulation time 152803149672 ps
CPU time 80.7 seconds
Started Aug 18 05:57:46 PM PDT 24
Finished Aug 18 05:59:06 PM PDT 24
Peak memory 201008 kb
Host smart-a9aaf717-6465-4316-b8a4-643ca5571ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429234990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2429234990
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1403551337
Short name T43
Test name
Test status
Simulation time 28710026265 ps
CPU time 397.81 seconds
Started Aug 18 05:57:48 PM PDT 24
Finished Aug 18 06:04:26 PM PDT 24
Peak memory 201108 kb
Host smart-eec143e4-d5eb-4bcd-b042-74f1692e370a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403551337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1403551337
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2822581409
Short name T558
Test name
Test status
Simulation time 2221455431 ps
CPU time 6.88 seconds
Started Aug 18 05:57:46 PM PDT 24
Finished Aug 18 05:57:53 PM PDT 24
Peak memory 198784 kb
Host smart-c991d8bf-bc6f-4240-9ca9-26668f7fd660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822581409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2822581409
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.73449919
Short name T755
Test name
Test status
Simulation time 107482229144 ps
CPU time 48.16 seconds
Started Aug 18 05:57:46 PM PDT 24
Finished Aug 18 05:58:34 PM PDT 24
Peak memory 200848 kb
Host smart-beb148d1-ec37-43b9-8155-b8fc59c92c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73449919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.73449919
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.420303071
Short name T239
Test name
Test status
Simulation time 4748262683 ps
CPU time 1.01 seconds
Started Aug 18 05:57:43 PM PDT 24
Finished Aug 18 05:57:44 PM PDT 24
Peak memory 197028 kb
Host smart-9df005d4-9f12-4fd0-b54f-49310bd243a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420303071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.420303071
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.731782388
Short name T281
Test name
Test status
Simulation time 552030683 ps
CPU time 2.23 seconds
Started Aug 18 05:57:44 PM PDT 24
Finished Aug 18 05:57:46 PM PDT 24
Peak memory 199212 kb
Host smart-6a2e88fd-4f9e-4aa0-becf-5dfb8723ff84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731782388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.731782388
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3372660539
Short name T1092
Test name
Test status
Simulation time 42849498077 ps
CPU time 24.12 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:58:09 PM PDT 24
Peak memory 200908 kb
Host smart-40386689-f77a-4afb-a035-2df6b6e63dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372660539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3372660539
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2637658614
Short name T1152
Test name
Test status
Simulation time 4045701033 ps
CPU time 68.8 seconds
Started Aug 18 05:57:46 PM PDT 24
Finished Aug 18 05:58:55 PM PDT 24
Peak memory 217488 kb
Host smart-28291e70-c5d7-4f01-a8f9-4349c2e076eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637658614 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2637658614
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.831547791
Short name T834
Test name
Test status
Simulation time 456984788 ps
CPU time 1.56 seconds
Started Aug 18 05:57:43 PM PDT 24
Finished Aug 18 05:57:44 PM PDT 24
Peak memory 200168 kb
Host smart-3ef0dd9f-1564-4493-8595-d4d95a5da3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831547791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.831547791
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3869952483
Short name T39
Test name
Test status
Simulation time 48688191083 ps
CPU time 102 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:59:27 PM PDT 24
Peak memory 200912 kb
Host smart-9a475264-ccbd-42c7-97d1-ce7a079344f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869952483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3869952483
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3041899426
Short name T303
Test name
Test status
Simulation time 59542458792 ps
CPU time 109.43 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:03:33 PM PDT 24
Peak memory 200960 kb
Host smart-3fcd2486-191a-4973-9cfc-0c175a1057c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041899426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3041899426
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.496070700
Short name T1004
Test name
Test status
Simulation time 7869922979 ps
CPU time 32.05 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:02:15 PM PDT 24
Peak memory 217368 kb
Host smart-f56669f5-422d-41a8-8680-58fe4ffe6290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496070700 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.496070700
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2823529687
Short name T717
Test name
Test status
Simulation time 107658037325 ps
CPU time 144.27 seconds
Started Aug 18 06:01:45 PM PDT 24
Finished Aug 18 06:04:09 PM PDT 24
Peak memory 200864 kb
Host smart-be7902e8-cf20-4be8-bb96-e715b66b4c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823529687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2823529687
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3019388143
Short name T1
Test name
Test status
Simulation time 8816979893 ps
CPU time 40.11 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:02:23 PM PDT 24
Peak memory 217384 kb
Host smart-41e09cb7-d9ed-4a0c-8865-4c8bb5587813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019388143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3019388143
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2834226004
Short name T254
Test name
Test status
Simulation time 67108591719 ps
CPU time 139.64 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:04:04 PM PDT 24
Peak memory 200864 kb
Host smart-3cdec4df-8b80-4598-b9e3-6e25b3d90429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834226004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2834226004
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3190386484
Short name T764
Test name
Test status
Simulation time 1267426516 ps
CPU time 14.28 seconds
Started Aug 18 06:01:44 PM PDT 24
Finished Aug 18 06:01:58 PM PDT 24
Peak memory 200920 kb
Host smart-f796cb7b-bbc8-49b0-ba1f-a78b266b66c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190386484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3190386484
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2453887528
Short name T257
Test name
Test status
Simulation time 103531897821 ps
CPU time 136.7 seconds
Started Aug 18 06:01:46 PM PDT 24
Finished Aug 18 06:04:03 PM PDT 24
Peak memory 200904 kb
Host smart-853e2f6e-f993-494e-9da5-2ee1c120c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453887528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2453887528
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1631556935
Short name T1087
Test name
Test status
Simulation time 6300958331 ps
CPU time 47.42 seconds
Started Aug 18 06:01:42 PM PDT 24
Finished Aug 18 06:02:29 PM PDT 24
Peak memory 216588 kb
Host smart-e97c32df-feb9-48f6-8b24-c0c40991c593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631556935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1631556935
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3133875150
Short name T941
Test name
Test status
Simulation time 21411814450 ps
CPU time 30.22 seconds
Started Aug 18 06:01:43 PM PDT 24
Finished Aug 18 06:02:14 PM PDT 24
Peak memory 200884 kb
Host smart-6693ccbd-10f8-4b2c-91f2-c7ba0b2b09ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133875150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3133875150
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2535579534
Short name T309
Test name
Test status
Simulation time 54750911331 ps
CPU time 69.27 seconds
Started Aug 18 06:01:55 PM PDT 24
Finished Aug 18 06:03:05 PM PDT 24
Peak memory 217360 kb
Host smart-a256d226-96b1-4521-b4a1-4468b786e7ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535579534 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2535579534
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1333241330
Short name T1047
Test name
Test status
Simulation time 14540597949 ps
CPU time 25.48 seconds
Started Aug 18 06:01:51 PM PDT 24
Finished Aug 18 06:02:17 PM PDT 24
Peak memory 200928 kb
Host smart-671a0ac5-cdfd-4c83-88bf-81471cfb1d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333241330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1333241330
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2846187019
Short name T1016
Test name
Test status
Simulation time 6514467110 ps
CPU time 20.05 seconds
Started Aug 18 06:01:54 PM PDT 24
Finished Aug 18 06:02:14 PM PDT 24
Peak memory 216860 kb
Host smart-9b81ab18-c774-4d67-a1d4-3a5f6e38ec4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846187019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2846187019
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3906209276
Short name T88
Test name
Test status
Simulation time 3546109106 ps
CPU time 33.71 seconds
Started Aug 18 06:01:57 PM PDT 24
Finished Aug 18 06:02:31 PM PDT 24
Peak memory 209452 kb
Host smart-9183e007-a51f-4217-8efd-59ed5f4cdf8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906209276 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3906209276
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1090785253
Short name T1100
Test name
Test status
Simulation time 148006175391 ps
CPU time 214.51 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:05:28 PM PDT 24
Peak memory 200948 kb
Host smart-4a073415-7040-481d-81d1-fe0865e1a436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090785253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1090785253
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1938673114
Short name T763
Test name
Test status
Simulation time 1651408199 ps
CPU time 47.23 seconds
Started Aug 18 06:01:52 PM PDT 24
Finished Aug 18 06:02:39 PM PDT 24
Peak memory 216452 kb
Host smart-5d74635b-97b1-464e-b5cd-c3fe5973e55a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938673114 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1938673114
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3907164396
Short name T677
Test name
Test status
Simulation time 18134613722 ps
CPU time 14.31 seconds
Started Aug 18 06:01:54 PM PDT 24
Finished Aug 18 06:02:09 PM PDT 24
Peak memory 200848 kb
Host smart-dbfb8375-7f19-40d0-a96b-605931444c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907164396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3907164396
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3442664319
Short name T595
Test name
Test status
Simulation time 11435691751 ps
CPU time 37.55 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:31 PM PDT 24
Peak memory 217572 kb
Host smart-2e98a1b7-124d-4673-a0ec-fc763dec2f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442664319 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3442664319
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.487339363
Short name T676
Test name
Test status
Simulation time 11623035976 ps
CPU time 21.28 seconds
Started Aug 18 06:01:55 PM PDT 24
Finished Aug 18 06:02:16 PM PDT 24
Peak memory 200940 kb
Host smart-d99c0f03-0ffa-4c34-9de0-888cf1f65c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487339363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.487339363
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.400321987
Short name T607
Test name
Test status
Simulation time 2163529912 ps
CPU time 17.22 seconds
Started Aug 18 06:01:55 PM PDT 24
Finished Aug 18 06:02:12 PM PDT 24
Peak memory 200964 kb
Host smart-b90b00ff-bcc1-4d92-8c2e-4e9ee4c990d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400321987 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.400321987
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3498204438
Short name T1088
Test name
Test status
Simulation time 12091677 ps
CPU time 0.57 seconds
Started Aug 18 05:57:57 PM PDT 24
Finished Aug 18 05:57:57 PM PDT 24
Peak memory 196500 kb
Host smart-593d0f49-af9f-4515-99b4-c5029d1ad4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498204438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3498204438
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3551643484
Short name T653
Test name
Test status
Simulation time 69986575807 ps
CPU time 78.8 seconds
Started Aug 18 05:57:47 PM PDT 24
Finished Aug 18 05:59:06 PM PDT 24
Peak memory 200864 kb
Host smart-b9e4714e-5c66-492d-a679-5c59c7804c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551643484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3551643484
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.389575164
Short name T121
Test name
Test status
Simulation time 113700695753 ps
CPU time 46.66 seconds
Started Aug 18 05:57:45 PM PDT 24
Finished Aug 18 05:58:32 PM PDT 24
Peak memory 200864 kb
Host smart-8686799c-b65e-4f34-8370-9792eca9a952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389575164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.389575164
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1529765734
Short name T792
Test name
Test status
Simulation time 14837385163 ps
CPU time 12.11 seconds
Started Aug 18 05:57:42 PM PDT 24
Finished Aug 18 05:57:55 PM PDT 24
Peak memory 200932 kb
Host smart-222a98c4-2575-41c7-8786-a4653a95a650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529765734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1529765734
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2557224274
Short name T1072
Test name
Test status
Simulation time 16931934258 ps
CPU time 3.34 seconds
Started Aug 18 05:57:54 PM PDT 24
Finished Aug 18 05:57:57 PM PDT 24
Peak memory 198684 kb
Host smart-d2147a3c-f5c4-4048-ac2a-4fcbaa830399
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557224274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2557224274
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1585975815
Short name T424
Test name
Test status
Simulation time 98107733420 ps
CPU time 604.24 seconds
Started Aug 18 05:57:51 PM PDT 24
Finished Aug 18 06:07:55 PM PDT 24
Peak memory 200892 kb
Host smart-c43f3d2c-0ac9-45d7-afa1-6112c62c4b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585975815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1585975815
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.457285196
Short name T521
Test name
Test status
Simulation time 8537743004 ps
CPU time 14.01 seconds
Started Aug 18 05:57:57 PM PDT 24
Finished Aug 18 05:58:11 PM PDT 24
Peak memory 200844 kb
Host smart-e66b3064-4a3a-4d3a-b1df-74fb0be30833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457285196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.457285196
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2486921870
Short name T858
Test name
Test status
Simulation time 23808721376 ps
CPU time 20.95 seconds
Started Aug 18 05:57:51 PM PDT 24
Finished Aug 18 05:58:12 PM PDT 24
Peak memory 199528 kb
Host smart-f68f1aef-776a-4018-8c84-18ece35db141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486921870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2486921870
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1819899335
Short name T297
Test name
Test status
Simulation time 18647014830 ps
CPU time 644.66 seconds
Started Aug 18 05:57:50 PM PDT 24
Finished Aug 18 06:08:35 PM PDT 24
Peak memory 200788 kb
Host smart-1cd10fad-2757-4266-8bba-9c3e0a779cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819899335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1819899335
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.4064149705
Short name T498
Test name
Test status
Simulation time 1991128323 ps
CPU time 9.32 seconds
Started Aug 18 05:57:46 PM PDT 24
Finished Aug 18 05:57:55 PM PDT 24
Peak memory 197976 kb
Host smart-8860b37f-cc88-4a74-bae4-a7975b2e22bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064149705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.4064149705
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1911400268
Short name T821
Test name
Test status
Simulation time 92186245010 ps
CPU time 37.27 seconds
Started Aug 18 05:57:50 PM PDT 24
Finished Aug 18 05:58:27 PM PDT 24
Peak memory 200912 kb
Host smart-0c1df3cd-d3e4-44e3-820b-a773d64c6370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911400268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1911400268
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.4025084739
Short name T1166
Test name
Test status
Simulation time 3643485741 ps
CPU time 5.64 seconds
Started Aug 18 05:57:50 PM PDT 24
Finished Aug 18 05:57:56 PM PDT 24
Peak memory 197416 kb
Host smart-cbdc5358-eef4-415b-b795-2aab652a9173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025084739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.4025084739
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.853491498
Short name T727
Test name
Test status
Simulation time 984747854 ps
CPU time 1.9 seconds
Started Aug 18 05:57:43 PM PDT 24
Finished Aug 18 05:57:45 PM PDT 24
Peak memory 200220 kb
Host smart-2b2ba286-b909-426b-bc6a-61e2873795d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853491498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.853491498
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2874680690
Short name T1139
Test name
Test status
Simulation time 2757817980 ps
CPU time 25.77 seconds
Started Aug 18 05:57:52 PM PDT 24
Finished Aug 18 05:58:18 PM PDT 24
Peak memory 209372 kb
Host smart-2c5bba0b-77ee-4417-9492-c9e90be4aa6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874680690 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2874680690
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.188402750
Short name T427
Test name
Test status
Simulation time 2625580697 ps
CPU time 3.25 seconds
Started Aug 18 05:57:52 PM PDT 24
Finished Aug 18 05:57:55 PM PDT 24
Peak memory 199908 kb
Host smart-9c1d1ca9-7051-4b30-928d-2b6ace449d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188402750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.188402750
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1628555672
Short name T372
Test name
Test status
Simulation time 21994257243 ps
CPU time 8.51 seconds
Started Aug 18 05:57:47 PM PDT 24
Finished Aug 18 05:57:56 PM PDT 24
Peak memory 200032 kb
Host smart-b574360d-9a1e-464f-87de-624d0d478754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628555672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1628555672
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.196745163
Short name T843
Test name
Test status
Simulation time 21025261558 ps
CPU time 35.58 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:29 PM PDT 24
Peak memory 200872 kb
Host smart-197746fd-9da7-4a01-8aeb-3706a5da2e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196745163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.196745163
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.902454187
Short name T1105
Test name
Test status
Simulation time 23156968584 ps
CPU time 102.86 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:03:36 PM PDT 24
Peak memory 216756 kb
Host smart-eae1a954-2da3-4988-96fb-b4d8b7fae6c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902454187 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.902454187
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3234724434
Short name T627
Test name
Test status
Simulation time 100069332795 ps
CPU time 82.43 seconds
Started Aug 18 06:01:52 PM PDT 24
Finished Aug 18 06:03:15 PM PDT 24
Peak memory 200880 kb
Host smart-65274e42-fdc5-4478-9924-32598b140a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234724434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3234724434
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2756889307
Short name T749
Test name
Test status
Simulation time 930168279 ps
CPU time 9.12 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:02 PM PDT 24
Peak memory 217272 kb
Host smart-c453f72a-5668-4ab9-9e7b-f66a84c0713e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756889307 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2756889307
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1212753817
Short name T253
Test name
Test status
Simulation time 16519941422 ps
CPU time 29.49 seconds
Started Aug 18 06:01:52 PM PDT 24
Finished Aug 18 06:02:21 PM PDT 24
Peak memory 200920 kb
Host smart-b46398b1-e63b-4538-8819-3251ab6fa7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212753817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1212753817
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3496281048
Short name T30
Test name
Test status
Simulation time 6531657472 ps
CPU time 53.67 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:47 PM PDT 24
Peak memory 216536 kb
Host smart-59a3b87b-198c-457c-a6e7-6b17f4920993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496281048 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3496281048
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1609475663
Short name T183
Test name
Test status
Simulation time 15583641758 ps
CPU time 26.13 seconds
Started Aug 18 06:01:54 PM PDT 24
Finished Aug 18 06:02:20 PM PDT 24
Peak memory 200924 kb
Host smart-972dcef1-b1bf-4a8d-afc0-f99e7217d206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609475663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1609475663
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3263569800
Short name T703
Test name
Test status
Simulation time 3677122237 ps
CPU time 30.99 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:24 PM PDT 24
Peak memory 217544 kb
Host smart-55b78df4-dffb-41ae-b429-af4758b3b58a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263569800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3263569800
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3127489863
Short name T200
Test name
Test status
Simulation time 29957130587 ps
CPU time 25.87 seconds
Started Aug 18 06:01:51 PM PDT 24
Finished Aug 18 06:02:17 PM PDT 24
Peak memory 200940 kb
Host smart-a786bcd9-9904-48ea-ba41-62fb2a746183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127489863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3127489863
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.801579996
Short name T746
Test name
Test status
Simulation time 1867799614 ps
CPU time 39.33 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:33 PM PDT 24
Peak memory 200920 kb
Host smart-e69f0569-3193-498e-b7cd-0d842246578e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801579996 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.801579996
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2648499107
Short name T678
Test name
Test status
Simulation time 52725622537 ps
CPU time 21.98 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:15 PM PDT 24
Peak memory 200860 kb
Host smart-f447474c-a9b3-4b97-863d-34d0e394763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648499107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2648499107
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1679925353
Short name T481
Test name
Test status
Simulation time 18214198836 ps
CPU time 62.96 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:56 PM PDT 24
Peak memory 209148 kb
Host smart-c34d2644-5e3a-43be-a750-3580e03f55ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679925353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1679925353
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1401701213
Short name T1178
Test name
Test status
Simulation time 165442296509 ps
CPU time 134.38 seconds
Started Aug 18 06:01:55 PM PDT 24
Finished Aug 18 06:04:09 PM PDT 24
Peak memory 200808 kb
Host smart-4df816be-e927-40bb-8731-7b520ee94cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401701213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1401701213
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2868932093
Short name T82
Test name
Test status
Simulation time 7329872556 ps
CPU time 33.45 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:27 PM PDT 24
Peak memory 217368 kb
Host smart-698d896c-9db5-4953-b599-421c7997b938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868932093 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2868932093
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.4037232424
Short name T863
Test name
Test status
Simulation time 45518698540 ps
CPU time 18.8 seconds
Started Aug 18 06:01:54 PM PDT 24
Finished Aug 18 06:02:13 PM PDT 24
Peak memory 200692 kb
Host smart-64603a1f-2893-4cd3-8178-dcd3ffbe55e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037232424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.4037232424
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1502333327
Short name T1146
Test name
Test status
Simulation time 1863224487 ps
CPU time 29.81 seconds
Started Aug 18 06:01:54 PM PDT 24
Finished Aug 18 06:02:24 PM PDT 24
Peak memory 209316 kb
Host smart-3369a0f4-5de8-40b2-b445-1e9327ac8e91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502333327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1502333327
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.508540530
Short name T125
Test name
Test status
Simulation time 58366492600 ps
CPU time 31.05 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:24 PM PDT 24
Peak memory 200824 kb
Host smart-22fa6b31-43ae-4b1f-9deb-472b18c4908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508540530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.508540530
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2905936053
Short name T403
Test name
Test status
Simulation time 2789289409 ps
CPU time 32.01 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:25 PM PDT 24
Peak memory 216564 kb
Host smart-151eee5b-4fd8-492f-bd10-281f0b9ee581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905936053 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2905936053
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4192186799
Short name T454
Test name
Test status
Simulation time 33646952201 ps
CPU time 14.08 seconds
Started Aug 18 06:01:53 PM PDT 24
Finished Aug 18 06:02:08 PM PDT 24
Peak memory 199712 kb
Host smart-4f905bcd-97b9-4b93-a189-0f8b31fee86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192186799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4192186799
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.113348707
Short name T1040
Test name
Test status
Simulation time 17178371332 ps
CPU time 80.1 seconds
Started Aug 18 06:01:52 PM PDT 24
Finished Aug 18 06:03:12 PM PDT 24
Peak memory 216536 kb
Host smart-e089ac4c-ef51-473c-b4df-f470380d9eb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113348707 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.113348707
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.24088532
Short name T524
Test name
Test status
Simulation time 27474184 ps
CPU time 0.56 seconds
Started Aug 18 05:57:51 PM PDT 24
Finished Aug 18 05:57:52 PM PDT 24
Peak memory 196472 kb
Host smart-cfcaab9a-9e7c-44bd-b031-85701a1cfd31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.24088532
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.418656603
Short name T580
Test name
Test status
Simulation time 162232559276 ps
CPU time 208.73 seconds
Started Aug 18 05:57:51 PM PDT 24
Finished Aug 18 06:01:20 PM PDT 24
Peak memory 200888 kb
Host smart-7a3e2134-f7cb-48f3-a1b3-622a4cd89b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418656603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.418656603
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2288313086
Short name T963
Test name
Test status
Simulation time 153333303658 ps
CPU time 62.74 seconds
Started Aug 18 05:57:51 PM PDT 24
Finished Aug 18 05:58:54 PM PDT 24
Peak memory 200936 kb
Host smart-c055be50-faf5-4643-ba30-f8d7351f1fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288313086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2288313086
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2743594348
Short name T1053
Test name
Test status
Simulation time 52309698107 ps
CPU time 29.9 seconds
Started Aug 18 05:57:54 PM PDT 24
Finished Aug 18 05:58:24 PM PDT 24
Peak memory 200932 kb
Host smart-5f797875-cb98-4b8a-abb0-4732b4133459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743594348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2743594348
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.990235252
Short name T950
Test name
Test status
Simulation time 35911905770 ps
CPU time 13.84 seconds
Started Aug 18 05:57:51 PM PDT 24
Finished Aug 18 05:58:05 PM PDT 24
Peak memory 199864 kb
Host smart-33618083-e94d-479e-94a2-be89e3292cc4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990235252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.990235252
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2903217511
Short name T374
Test name
Test status
Simulation time 128736690350 ps
CPU time 1105.94 seconds
Started Aug 18 05:57:52 PM PDT 24
Finished Aug 18 06:16:18 PM PDT 24
Peak memory 200912 kb
Host smart-f391bf9b-e20b-49e5-acb2-0979494363a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903217511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2903217511
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2353013269
Short name T439
Test name
Test status
Simulation time 10680356123 ps
CPU time 8.88 seconds
Started Aug 18 05:57:51 PM PDT 24
Finished Aug 18 05:58:00 PM PDT 24
Peak memory 199548 kb
Host smart-77b80912-2b13-4fea-b755-ec4bba713cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353013269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2353013269
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.569862158
Short name T392
Test name
Test status
Simulation time 134968016627 ps
CPU time 91.17 seconds
Started Aug 18 05:57:57 PM PDT 24
Finished Aug 18 05:59:28 PM PDT 24
Peak memory 200232 kb
Host smart-31c859f7-675a-49e2-beb0-dfea2ab2425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569862158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.569862158
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1271090118
Short name T621
Test name
Test status
Simulation time 15143698738 ps
CPU time 168.93 seconds
Started Aug 18 05:57:50 PM PDT 24
Finished Aug 18 06:00:39 PM PDT 24
Peak memory 200904 kb
Host smart-3012aaac-e0ea-4f10-930b-63b80d3a3aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271090118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1271090118
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1832101600
Short name T696
Test name
Test status
Simulation time 2406791548 ps
CPU time 15.29 seconds
Started Aug 18 05:57:57 PM PDT 24
Finished Aug 18 05:58:12 PM PDT 24
Peak memory 200348 kb
Host smart-d11d7f39-b2f1-4926-b679-0fc09c7ea973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832101600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1832101600
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2974293182
Short name T708
Test name
Test status
Simulation time 12254597453 ps
CPU time 19.58 seconds
Started Aug 18 05:57:57 PM PDT 24
Finished Aug 18 05:58:17 PM PDT 24
Peak memory 200792 kb
Host smart-1c35720c-ec86-42b0-9345-448cc04d1c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974293182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2974293182
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1593660704
Short name T530
Test name
Test status
Simulation time 2303596698 ps
CPU time 3.61 seconds
Started Aug 18 05:57:53 PM PDT 24
Finished Aug 18 05:57:56 PM PDT 24
Peak memory 196552 kb
Host smart-6e060e7d-91de-4066-8b6f-8b01919410c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593660704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1593660704
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3561120838
Short name T414
Test name
Test status
Simulation time 5777217967 ps
CPU time 17.54 seconds
Started Aug 18 05:57:52 PM PDT 24
Finished Aug 18 05:58:09 PM PDT 24
Peak memory 200552 kb
Host smart-d7e3a05a-7cb6-4f11-88b4-ec9432b2badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561120838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3561120838
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.445099359
Short name T604
Test name
Test status
Simulation time 11381289798 ps
CPU time 113.34 seconds
Started Aug 18 05:57:51 PM PDT 24
Finished Aug 18 05:59:44 PM PDT 24
Peak memory 210712 kb
Host smart-7caa8e90-816d-47af-8e4f-ae1b7c9baccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445099359 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.445099359
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3660755076
Short name T573
Test name
Test status
Simulation time 5313342304 ps
CPU time 1.72 seconds
Started Aug 18 05:57:53 PM PDT 24
Finished Aug 18 05:57:55 PM PDT 24
Peak memory 199544 kb
Host smart-f21f896a-852e-40e2-9189-9310b6c81127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660755076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3660755076
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3652972970
Short name T652
Test name
Test status
Simulation time 16387978329 ps
CPU time 23.94 seconds
Started Aug 18 05:57:54 PM PDT 24
Finished Aug 18 05:58:18 PM PDT 24
Peak memory 201040 kb
Host smart-729f032b-4dd5-4936-a6b1-dbbdb89d2b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652972970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3652972970
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3592269352
Short name T327
Test name
Test status
Simulation time 171140360995 ps
CPU time 67.7 seconds
Started Aug 18 06:02:04 PM PDT 24
Finished Aug 18 06:03:11 PM PDT 24
Peak memory 200888 kb
Host smart-626d2c5b-0aee-49bb-a1fe-7c0719bd8d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592269352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3592269352
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2895876819
Short name T1130
Test name
Test status
Simulation time 2648032579 ps
CPU time 60.25 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:03:03 PM PDT 24
Peak memory 217260 kb
Host smart-b0ae3e6c-a369-4a12-a14f-e848a504a429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895876819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2895876819
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3250724382
Short name T378
Test name
Test status
Simulation time 2946776260 ps
CPU time 16.98 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:02:19 PM PDT 24
Peak memory 200948 kb
Host smart-f2e41ea0-5d16-4bfd-a81b-fb79db95a4ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250724382 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3250724382
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.19359627
Short name T738
Test name
Test status
Simulation time 30912600337 ps
CPU time 47.06 seconds
Started Aug 18 06:02:00 PM PDT 24
Finished Aug 18 06:02:47 PM PDT 24
Peak memory 200928 kb
Host smart-8e7b8a10-b167-4f79-b49e-eb425e78ea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19359627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.19359627
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.364659832
Short name T31
Test name
Test status
Simulation time 9381665591 ps
CPU time 72.81 seconds
Started Aug 18 06:02:01 PM PDT 24
Finished Aug 18 06:03:14 PM PDT 24
Peak memory 217392 kb
Host smart-7c71a159-3806-4f40-9359-e06747e6394b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364659832 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.364659832
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.340291527
Short name T825
Test name
Test status
Simulation time 65718322856 ps
CPU time 25.89 seconds
Started Aug 18 06:02:00 PM PDT 24
Finished Aug 18 06:02:26 PM PDT 24
Peak memory 200932 kb
Host smart-e16ed096-2695-4a24-a876-0b15866d25d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340291527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.340291527
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1130121175
Short name T33
Test name
Test status
Simulation time 2756904514 ps
CPU time 37.79 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:02:40 PM PDT 24
Peak memory 209368 kb
Host smart-f5de4016-a236-4435-b16c-bf9c7bc4ed30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130121175 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1130121175
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.738244575
Short name T1126
Test name
Test status
Simulation time 177551909730 ps
CPU time 76.82 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:03:20 PM PDT 24
Peak memory 200884 kb
Host smart-67e26cac-8c6c-4f3b-b226-7f181ff90fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738244575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.738244575
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1377966576
Short name T728
Test name
Test status
Simulation time 6166235959 ps
CPU time 34 seconds
Started Aug 18 06:02:00 PM PDT 24
Finished Aug 18 06:02:34 PM PDT 24
Peak memory 216948 kb
Host smart-07f9a0b7-15c6-4107-b2e0-37300e2103a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377966576 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1377966576
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2233883965
Short name T966
Test name
Test status
Simulation time 29270794349 ps
CPU time 49.1 seconds
Started Aug 18 06:02:04 PM PDT 24
Finished Aug 18 06:02:53 PM PDT 24
Peak memory 200844 kb
Host smart-49d9d18a-3211-4f3d-8a4e-747d9977306e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233883965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2233883965
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1938481016
Short name T882
Test name
Test status
Simulation time 6243771865 ps
CPU time 87.74 seconds
Started Aug 18 06:02:01 PM PDT 24
Finished Aug 18 06:03:29 PM PDT 24
Peak memory 216836 kb
Host smart-2e10e57c-81f0-4a99-b426-8b018ac9aada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938481016 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1938481016
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3203999938
Short name T819
Test name
Test status
Simulation time 52499643196 ps
CPU time 21.52 seconds
Started Aug 18 06:02:01 PM PDT 24
Finished Aug 18 06:02:22 PM PDT 24
Peak memory 200940 kb
Host smart-210786f2-8519-4d8b-a00d-5f63494ea57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203999938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3203999938
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2483490796
Short name T163
Test name
Test status
Simulation time 24971574994 ps
CPU time 40.62 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:02:42 PM PDT 24
Peak memory 200920 kb
Host smart-548a7a0f-d18b-4230-b0cb-9a0e207e5c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483490796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2483490796
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.4095562596
Short name T744
Test name
Test status
Simulation time 5755541865 ps
CPU time 20.47 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:02:23 PM PDT 24
Peak memory 209184 kb
Host smart-928ab74d-1a3a-4068-84c7-2d730cd4dcdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095562596 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.4095562596
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1987618010
Short name T167
Test name
Test status
Simulation time 20895311000 ps
CPU time 29.91 seconds
Started Aug 18 06:02:01 PM PDT 24
Finished Aug 18 06:02:31 PM PDT 24
Peak memory 200868 kb
Host smart-5b49de55-ea98-45aa-a258-914489e3eccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987618010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1987618010
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1957734585
Short name T758
Test name
Test status
Simulation time 20649945333 ps
CPU time 59.21 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:03:03 PM PDT 24
Peak memory 216696 kb
Host smart-99946755-f8fd-44cf-9c23-84a7da9e694e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957734585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1957734585
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2438138981
Short name T1180
Test name
Test status
Simulation time 21667963211 ps
CPU time 34.95 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:02:37 PM PDT 24
Peak memory 200936 kb
Host smart-ac9ac569-4337-4deb-9ca4-6846f7052bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438138981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2438138981
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3721820538
Short name T86
Test name
Test status
Simulation time 1669633312 ps
CPU time 14.51 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:02:18 PM PDT 24
Peak memory 200928 kb
Host smart-3ba81f1f-4f72-4aba-9697-c08ff5bb7fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721820538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3721820538
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3076299299
Short name T1124
Test name
Test status
Simulation time 71199379 ps
CPU time 0.56 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:58:02 PM PDT 24
Peak memory 196232 kb
Host smart-18d1eb96-90ca-4826-9881-f163e44da105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076299299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3076299299
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1636996736
Short name T1165
Test name
Test status
Simulation time 53909424059 ps
CPU time 39.62 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:58:41 PM PDT 24
Peak memory 200932 kb
Host smart-13397fec-4d07-43bb-b427-1795c3cba9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636996736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1636996736
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1418519757
Short name T130
Test name
Test status
Simulation time 53706990955 ps
CPU time 70.32 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:59:11 PM PDT 24
Peak memory 200688 kb
Host smart-e7a5f9f4-1fc9-486e-a969-f54f795f63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418519757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1418519757
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.26313439
Short name T979
Test name
Test status
Simulation time 183537009902 ps
CPU time 110.78 seconds
Started Aug 18 05:58:02 PM PDT 24
Finished Aug 18 05:59:53 PM PDT 24
Peak memory 200860 kb
Host smart-3700280f-c1aa-4296-97cf-24ca4be6dd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26313439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.26313439
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1876279257
Short name T845
Test name
Test status
Simulation time 51705181621 ps
CPU time 17.92 seconds
Started Aug 18 05:58:04 PM PDT 24
Finished Aug 18 05:58:22 PM PDT 24
Peak memory 198736 kb
Host smart-4dc7f112-0dd2-4624-acdf-b4f896711abc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876279257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1876279257
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.764320590
Short name T1184
Test name
Test status
Simulation time 134005389772 ps
CPU time 736.19 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 06:10:18 PM PDT 24
Peak memory 200908 kb
Host smart-f6afb0e8-2c6a-429f-a7c9-eed4041ca284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764320590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.764320590
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3317197221
Short name T900
Test name
Test status
Simulation time 702862631 ps
CPU time 1.12 seconds
Started Aug 18 05:58:06 PM PDT 24
Finished Aug 18 05:58:07 PM PDT 24
Peak memory 198984 kb
Host smart-62f6b5b6-c156-40dc-aa3a-c6fab4c9a519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317197221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3317197221
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1903074984
Short name T256
Test name
Test status
Simulation time 47816226650 ps
CPU time 79.28 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:59:19 PM PDT 24
Peak memory 200244 kb
Host smart-908d216b-bf76-4c8d-b0eb-ce2cc38a3646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903074984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1903074984
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3769518443
Short name T463
Test name
Test status
Simulation time 25476683016 ps
CPU time 196.57 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 06:01:17 PM PDT 24
Peak memory 200872 kb
Host smart-068465e1-6218-4cb5-a909-1a6333a31020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769518443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3769518443
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2838036845
Short name T956
Test name
Test status
Simulation time 5814796192 ps
CPU time 46.63 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:58:47 PM PDT 24
Peak memory 199976 kb
Host smart-4336e42a-cfd7-4b16-a7c2-0c9b4b018332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838036845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2838036845
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.140277333
Short name T786
Test name
Test status
Simulation time 79857653875 ps
CPU time 29.81 seconds
Started Aug 18 05:58:06 PM PDT 24
Finished Aug 18 05:58:36 PM PDT 24
Peak memory 201048 kb
Host smart-ff0b66ce-202a-469d-9ab9-f373ff66f8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140277333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.140277333
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2028132537
Short name T407
Test name
Test status
Simulation time 36294611174 ps
CPU time 52.11 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:58:53 PM PDT 24
Peak memory 196756 kb
Host smart-e2016ae0-b342-44f5-a415-8f49556a3071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028132537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2028132537
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1965153861
Short name T422
Test name
Test status
Simulation time 902285174 ps
CPU time 2.04 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:58:02 PM PDT 24
Peak memory 199224 kb
Host smart-b8b63460-53b7-4ba3-b34e-d2d202a55806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965153861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1965153861
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3193219729
Short name T473
Test name
Test status
Simulation time 20815515761 ps
CPU time 136.65 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 06:00:17 PM PDT 24
Peak memory 200880 kb
Host smart-f7c1b97e-5426-4dc1-b324-6ec93e5aa276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193219729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3193219729
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1728420196
Short name T87
Test name
Test status
Simulation time 2881506709 ps
CPU time 28.55 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:58:28 PM PDT 24
Peak memory 216636 kb
Host smart-27cf4d11-0508-45f1-8b24-42016cf6ad91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728420196 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1728420196
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2700703646
Short name T791
Test name
Test status
Simulation time 11876495369 ps
CPU time 21.51 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:58:22 PM PDT 24
Peak memory 200860 kb
Host smart-493a8de4-eef9-4623-818d-ecd670221f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700703646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2700703646
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.4193269712
Short name T598
Test name
Test status
Simulation time 180166714490 ps
CPU time 284.15 seconds
Started Aug 18 05:58:02 PM PDT 24
Finished Aug 18 06:02:46 PM PDT 24
Peak memory 200876 kb
Host smart-92c998f5-dd85-421c-93bf-21043c1e3f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193269712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.4193269712
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.515452541
Short name T954
Test name
Test status
Simulation time 194569127905 ps
CPU time 578.36 seconds
Started Aug 18 06:02:00 PM PDT 24
Finished Aug 18 06:11:39 PM PDT 24
Peak memory 200884 kb
Host smart-8d403f91-6921-470f-972f-bceb760af51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515452541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.515452541
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2980203494
Short name T599
Test name
Test status
Simulation time 31658563663 ps
CPU time 47.69 seconds
Started Aug 18 06:02:01 PM PDT 24
Finished Aug 18 06:02:48 PM PDT 24
Peak memory 217468 kb
Host smart-fd327580-0aea-4d5f-a0cc-3fb24122e6b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980203494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2980203494
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3908721183
Short name T552
Test name
Test status
Simulation time 38163787386 ps
CPU time 17.16 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:02:20 PM PDT 24
Peak memory 200924 kb
Host smart-d4649691-19e6-49ef-949a-1b56c89b38d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908721183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3908721183
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.801064376
Short name T902
Test name
Test status
Simulation time 2486110765 ps
CPU time 10.51 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:02:13 PM PDT 24
Peak memory 209152 kb
Host smart-5ad1c28c-a6af-42e1-94ea-2931e153c45c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801064376 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.801064376
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3638959411
Short name T542
Test name
Test status
Simulation time 220756392775 ps
CPU time 287.44 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:06:51 PM PDT 24
Peak memory 200896 kb
Host smart-65f78985-d84c-4b9b-b6b1-94c13bb9b0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638959411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3638959411
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.565622289
Short name T740
Test name
Test status
Simulation time 5563230027 ps
CPU time 54.26 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:02:56 PM PDT 24
Peak memory 216608 kb
Host smart-68e61226-387c-431c-83e3-0600e1f01016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565622289 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.565622289
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.271994118
Short name T838
Test name
Test status
Simulation time 306671019775 ps
CPU time 47.47 seconds
Started Aug 18 06:02:04 PM PDT 24
Finished Aug 18 06:02:51 PM PDT 24
Peak memory 200868 kb
Host smart-847706a7-9a7e-4f0c-880b-b215d9704315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271994118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.271994118
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1260246636
Short name T536
Test name
Test status
Simulation time 3985046029 ps
CPU time 30.01 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:02:33 PM PDT 24
Peak memory 216720 kb
Host smart-5842d094-8329-44ec-b641-ba27d94fb793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260246636 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1260246636
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.541523712
Short name T892
Test name
Test status
Simulation time 33785794568 ps
CPU time 32.39 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:02:36 PM PDT 24
Peak memory 200912 kb
Host smart-12166499-99aa-4cae-9fc1-8ef66187b875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541523712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.541523712
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.25909890
Short name T1156
Test name
Test status
Simulation time 7234833562 ps
CPU time 42.27 seconds
Started Aug 18 06:02:03 PM PDT 24
Finished Aug 18 06:02:45 PM PDT 24
Peak memory 209176 kb
Host smart-29e3ff4a-3210-44a5-90aa-314c9cce91f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25909890 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.25909890
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.432282840
Short name T887
Test name
Test status
Simulation time 22171062992 ps
CPU time 42.14 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:02:44 PM PDT 24
Peak memory 200856 kb
Host smart-fb742e2f-f8a4-46eb-8c68-0457138146fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432282840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.432282840
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.14976866
Short name T1183
Test name
Test status
Simulation time 4845693819 ps
CPU time 41.18 seconds
Started Aug 18 06:02:02 PM PDT 24
Finished Aug 18 06:02:43 PM PDT 24
Peak memory 217368 kb
Host smart-db18d42f-8cb2-4f58-82d8-4dcb55c4b48c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14976866 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.14976866
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1095009388
Short name T1157
Test name
Test status
Simulation time 56921680864 ps
CPU time 69.52 seconds
Started Aug 18 06:02:13 PM PDT 24
Finished Aug 18 06:03:23 PM PDT 24
Peak memory 200856 kb
Host smart-ef210a62-d2a9-48e8-91d6-93ee1a88abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095009388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1095009388
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3815851281
Short name T520
Test name
Test status
Simulation time 2077435620 ps
CPU time 55.29 seconds
Started Aug 18 06:02:09 PM PDT 24
Finished Aug 18 06:03:04 PM PDT 24
Peak memory 217180 kb
Host smart-df1d780e-fabb-4071-a5f9-98336e7f3c70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815851281 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3815851281
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2984642508
Short name T145
Test name
Test status
Simulation time 42992346658 ps
CPU time 15.95 seconds
Started Aug 18 06:02:08 PM PDT 24
Finished Aug 18 06:02:24 PM PDT 24
Peak memory 200868 kb
Host smart-594447ce-4e58-479d-8ce6-962b4ee60f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984642508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2984642508
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1313659111
Short name T783
Test name
Test status
Simulation time 3454239298 ps
CPU time 68.1 seconds
Started Aug 18 06:02:08 PM PDT 24
Finished Aug 18 06:03:16 PM PDT 24
Peak memory 216744 kb
Host smart-2fb94015-082c-4014-957f-a92bc3a34e5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313659111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1313659111
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2082622371
Short name T1090
Test name
Test status
Simulation time 14829129684 ps
CPU time 12.27 seconds
Started Aug 18 06:02:11 PM PDT 24
Finished Aug 18 06:02:23 PM PDT 24
Peak memory 200808 kb
Host smart-9f8653c1-ab92-414d-bfeb-ae9aeff0d0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082622371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2082622371
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.836165237
Short name T788
Test name
Test status
Simulation time 3822543246 ps
CPU time 49.33 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:03:07 PM PDT 24
Peak memory 209328 kb
Host smart-83739794-4b89-49ed-aee3-3287c670e305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836165237 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.836165237
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2841190021
Short name T465
Test name
Test status
Simulation time 27583475153 ps
CPU time 17.92 seconds
Started Aug 18 06:02:13 PM PDT 24
Finished Aug 18 06:02:31 PM PDT 24
Peak memory 199908 kb
Host smart-459a80f9-6940-4cf0-8fdf-f367b0a5dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841190021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2841190021
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2468556075
Short name T319
Test name
Test status
Simulation time 4930876531 ps
CPU time 55.36 seconds
Started Aug 18 06:02:08 PM PDT 24
Finished Aug 18 06:03:04 PM PDT 24
Peak memory 209196 kb
Host smart-7817eb18-fe4e-4d9a-b17b-022c86d6696a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468556075 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2468556075
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2572590381
Short name T555
Test name
Test status
Simulation time 114043686 ps
CPU time 0.55 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:58:01 PM PDT 24
Peak memory 196240 kb
Host smart-b8d1cbac-0072-4271-8072-7f13c11ff8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572590381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2572590381
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.468830739
Short name T927
Test name
Test status
Simulation time 24754505931 ps
CPU time 40.87 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:58:41 PM PDT 24
Peak memory 200900 kb
Host smart-125be228-4166-4d84-8237-fe371004e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468830739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.468830739
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2067158888
Short name T269
Test name
Test status
Simulation time 177736898759 ps
CPU time 83.66 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:59:24 PM PDT 24
Peak memory 200888 kb
Host smart-bce4f0ae-9e0a-4721-95b0-72d36d418689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067158888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2067158888
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2505172077
Short name T519
Test name
Test status
Simulation time 15265795637 ps
CPU time 22.14 seconds
Started Aug 18 05:58:02 PM PDT 24
Finished Aug 18 05:58:24 PM PDT 24
Peak memory 200564 kb
Host smart-b5551c15-f47f-44df-8f5b-7ff5a8d2a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505172077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2505172077
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2059260532
Short name T605
Test name
Test status
Simulation time 52804065985 ps
CPU time 48.33 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 05:58:50 PM PDT 24
Peak memory 200928 kb
Host smart-fbd97313-c52d-4748-b88e-55a7863b522d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059260532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2059260532
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3706292297
Short name T393
Test name
Test status
Simulation time 314425385176 ps
CPU time 139.49 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 06:00:21 PM PDT 24
Peak memory 200828 kb
Host smart-174a50e7-4d1a-4e02-9fe1-97c0cbdc5418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706292297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3706292297
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1101194231
Short name T356
Test name
Test status
Simulation time 9275597688 ps
CPU time 16.6 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:58:17 PM PDT 24
Peak memory 200904 kb
Host smart-fd437fae-4562-4953-8de7-ff12c535c513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101194231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1101194231
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3852953835
Short name T271
Test name
Test status
Simulation time 45998491510 ps
CPU time 74.07 seconds
Started Aug 18 05:58:05 PM PDT 24
Finished Aug 18 05:59:20 PM PDT 24
Peak memory 201028 kb
Host smart-d4c0b48f-63dc-4de1-99bb-bc5fba1fc541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852953835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3852953835
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3912905972
Short name T572
Test name
Test status
Simulation time 15031312115 ps
CPU time 795.77 seconds
Started Aug 18 05:58:01 PM PDT 24
Finished Aug 18 06:11:17 PM PDT 24
Peak memory 200844 kb
Host smart-4706c12d-7d0e-4e16-b20e-76efd9907342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912905972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3912905972
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.923050618
Short name T385
Test name
Test status
Simulation time 7335414399 ps
CPU time 34.76 seconds
Started Aug 18 05:58:02 PM PDT 24
Finished Aug 18 05:58:37 PM PDT 24
Peak memory 199972 kb
Host smart-9373b98e-2084-4df5-89c7-34f2ffbb95b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923050618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.923050618
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3461776628
Short name T1049
Test name
Test status
Simulation time 102320464524 ps
CPU time 167.62 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 06:00:48 PM PDT 24
Peak memory 200920 kb
Host smart-24eb1e1a-e84d-495d-9f82-a457b35e23bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461776628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3461776628
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.243154624
Short name T448
Test name
Test status
Simulation time 2851857917 ps
CPU time 1.85 seconds
Started Aug 18 05:58:12 PM PDT 24
Finished Aug 18 05:58:14 PM PDT 24
Peak memory 197452 kb
Host smart-c9325e59-73a0-4e16-a246-4046e3f14a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243154624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.243154624
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.955586107
Short name T862
Test name
Test status
Simulation time 5829145392 ps
CPU time 14.71 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:58:15 PM PDT 24
Peak memory 200672 kb
Host smart-90b67d26-aa2e-4b6b-9903-9cfa123fc376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955586107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.955586107
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1826151405
Short name T1006
Test name
Test status
Simulation time 3537695170 ps
CPU time 48.99 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:58:50 PM PDT 24
Peak memory 209192 kb
Host smart-35f4bbf5-39db-463e-8934-2b466fb4e738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826151405 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1826151405
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2592813576
Short name T1045
Test name
Test status
Simulation time 2384756116 ps
CPU time 2.65 seconds
Started Aug 18 05:58:04 PM PDT 24
Finished Aug 18 05:58:07 PM PDT 24
Peak memory 199852 kb
Host smart-261262ad-e189-4894-ab14-fa112c37dfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592813576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2592813576
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1684587889
Short name T1078
Test name
Test status
Simulation time 99702697267 ps
CPU time 30.62 seconds
Started Aug 18 05:58:00 PM PDT 24
Finished Aug 18 05:58:30 PM PDT 24
Peak memory 200908 kb
Host smart-ab58ee1d-0ccb-4004-ad55-59d1b7608cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684587889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1684587889
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3679743686
Short name T1081
Test name
Test status
Simulation time 48663970153 ps
CPU time 20.63 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:38 PM PDT 24
Peak memory 200908 kb
Host smart-1648912c-74dd-4ed5-a69e-cbce9f93812f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679743686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3679743686
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.758963013
Short name T885
Test name
Test status
Simulation time 1591756081 ps
CPU time 12.11 seconds
Started Aug 18 06:02:13 PM PDT 24
Finished Aug 18 06:02:25 PM PDT 24
Peak memory 200916 kb
Host smart-5824f3e5-0fea-4c0e-8f67-aaec426fe3c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758963013 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.758963013
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3318918866
Short name T176
Test name
Test status
Simulation time 46743606363 ps
CPU time 68.8 seconds
Started Aug 18 06:02:09 PM PDT 24
Finished Aug 18 06:03:18 PM PDT 24
Peak memory 200916 kb
Host smart-1ef6ec48-d091-413f-a533-6557fb661369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318918866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3318918866
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2386602594
Short name T153
Test name
Test status
Simulation time 9183191044 ps
CPU time 30.87 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:48 PM PDT 24
Peak memory 209064 kb
Host smart-82212802-b894-43ba-81e1-f17412e2355a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386602594 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2386602594
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3894339056
Short name T211
Test name
Test status
Simulation time 64767239548 ps
CPU time 10.09 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:28 PM PDT 24
Peak memory 200852 kb
Host smart-b1281d40-df20-4d96-8ab4-b340b8aaa4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894339056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3894339056
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3935902404
Short name T401
Test name
Test status
Simulation time 4384704073 ps
CPU time 52.16 seconds
Started Aug 18 06:02:08 PM PDT 24
Finished Aug 18 06:03:01 PM PDT 24
Peak memory 209504 kb
Host smart-fb13daf9-0103-47ce-aa05-e5ba8aac869c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935902404 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3935902404
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.230265147
Short name T767
Test name
Test status
Simulation time 14143095623 ps
CPU time 22.55 seconds
Started Aug 18 06:02:11 PM PDT 24
Finished Aug 18 06:02:33 PM PDT 24
Peak memory 217512 kb
Host smart-858acb81-17c5-4c52-9d84-990ab049346f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230265147 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.230265147
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2190691130
Short name T947
Test name
Test status
Simulation time 148014626911 ps
CPU time 59.25 seconds
Started Aug 18 06:02:10 PM PDT 24
Finished Aug 18 06:03:09 PM PDT 24
Peak memory 200764 kb
Host smart-002a973e-dbcb-4aaa-b0bc-2507a2c11044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190691130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2190691130
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3063614615
Short name T32
Test name
Test status
Simulation time 19334249507 ps
CPU time 63.95 seconds
Started Aug 18 06:02:10 PM PDT 24
Finished Aug 18 06:03:14 PM PDT 24
Peak memory 217564 kb
Host smart-a773a96d-8513-4ec7-b0ce-176ad464e55d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063614615 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3063614615
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1371191719
Short name T613
Test name
Test status
Simulation time 93817323814 ps
CPU time 116.41 seconds
Started Aug 18 06:02:09 PM PDT 24
Finished Aug 18 06:04:06 PM PDT 24
Peak memory 200848 kb
Host smart-600f131c-4b4b-439e-acbb-e79027a028a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371191719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1371191719
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.4041121417
Short name T181
Test name
Test status
Simulation time 58453208067 ps
CPU time 43.72 seconds
Started Aug 18 06:02:11 PM PDT 24
Finished Aug 18 06:02:54 PM PDT 24
Peak memory 200924 kb
Host smart-778fa933-ed2a-4556-894d-d71b5fd0fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041121417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.4041121417
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3891021920
Short name T754
Test name
Test status
Simulation time 1192876680 ps
CPU time 11.98 seconds
Started Aug 18 06:02:09 PM PDT 24
Finished Aug 18 06:02:21 PM PDT 24
Peak memory 200940 kb
Host smart-67b2c444-c948-4407-8bc1-2e68450759b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891021920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3891021920
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3986140168
Short name T1147
Test name
Test status
Simulation time 52351687442 ps
CPU time 70.99 seconds
Started Aug 18 06:02:19 PM PDT 24
Finished Aug 18 06:03:30 PM PDT 24
Peak memory 200896 kb
Host smart-98c3b885-c737-4c99-9008-66f5de6d3d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986140168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3986140168
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1868414069
Short name T769
Test name
Test status
Simulation time 14599318072 ps
CPU time 46.92 seconds
Started Aug 18 06:02:19 PM PDT 24
Finished Aug 18 06:03:06 PM PDT 24
Peak memory 209048 kb
Host smart-5566a945-34fd-414c-8174-b00215d3ba5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868414069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1868414069
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.266503549
Short name T218
Test name
Test status
Simulation time 220553291854 ps
CPU time 20.33 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:37 PM PDT 24
Peak memory 200764 kb
Host smart-4cfc38b0-6f46-4f08-b2a3-9cff60ef15de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266503549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.266503549
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.583552108
Short name T871
Test name
Test status
Simulation time 3780470104 ps
CPU time 35.12 seconds
Started Aug 18 06:02:21 PM PDT 24
Finished Aug 18 06:02:56 PM PDT 24
Peak memory 209204 kb
Host smart-3fa5d8a7-e82f-4d0a-a2bb-942d801f4a29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583552108 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.583552108
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.177054818
Short name T331
Test name
Test status
Simulation time 5664817571 ps
CPU time 9.16 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:26 PM PDT 24
Peak memory 200844 kb
Host smart-b4763cc0-5cc0-4f8c-9755-92d38bf5720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177054818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.177054818
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3415828113
Short name T1159
Test name
Test status
Simulation time 1852007447 ps
CPU time 8.58 seconds
Started Aug 18 06:02:17 PM PDT 24
Finished Aug 18 06:02:26 PM PDT 24
Peak memory 200936 kb
Host smart-f7c17911-4c39-494d-8665-565840c9c366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415828113 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3415828113
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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