Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	76861	1			T1	1043		T3	1278		T4	2
all_values[1]	76861	1			T1	1043		T3	1278		T4	2
all_values[2]	76861	1			T1	1043		T3	1278		T4	2
all_values[3]	76861	1			T1	1043		T3	1278		T4	2
all_values[4]	76861	1			T1	1043		T3	1278		T4	2
all_values[5]	76861	1			T1	1043		T3	1278		T4	2
all_values[6]	76861	1			T1	1043		T3	1278		T4	2
all_values[7]	76861	1			T1	1043		T3	1278		T4	2
all_values[8]	76861	1			T1	1043		T3	1278		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351161

1

T1

5581

T3

5248

T4

18

auto[1]

340588

1

T1

3806

T3

6254

T5

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623137

1

T1

8150

T3

11467

T4

13

auto[1]

68612

1

T1

1237

T3

35

T4

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	21061	1			T1	54		T3	1240		T6	10
all_values[0]	auto[0]	auto[1]	18585	1			T1	231		T3	12		T4	2
all_values[0]	auto[1]	auto[0]	22014	1			T1	306		T3	20		T6	7
all_values[0]	auto[1]	auto[1]	15201	1			T1	452		T3	6		T5	4
all_values[1]	auto[0]	auto[0]	38374	1			T1	519		T3	1278		T4	2
all_values[1]	auto[0]	auto[1]	1234	1			T1	8		T6	2		T9	8
all_values[1]	auto[1]	auto[0]	35879	1			T1	516		T5	2		T6	9
all_values[1]	auto[1]	auto[1]	1374	1			T6	1		T12	1		T16	19
all_values[2]	auto[0]	auto[0]	35289	1			T1	569		T3	145		T4	1
all_values[2]	auto[0]	auto[1]	2199	1			T1	16		T3	2		T4	1
all_values[2]	auto[1]	auto[0]	37234	1			T1	447		T3	1129		T5	1
all_values[2]	auto[1]	auto[1]	2139	1			T1	11		T3	2		T5	1
all_values[3]	auto[0]	auto[0]	39717	1			T1	769		T3	163		T4	2
all_values[3]	auto[0]	auto[1]	238	1			T1	6		T6	3		T12	1
all_values[3]	auto[1]	auto[0]	36666	1			T1	268		T3	1115		T5	4
all_values[3]	auto[1]	auto[1]	240	1			T9	1		T12	2		T13	2
all_values[4]	auto[0]	auto[0]	40641	1			T1	629		T3	479		T4	2
all_values[4]	auto[0]	auto[1]	382	1			T1	4		T12	6		T98	2
all_values[4]	auto[1]	auto[0]	35478	1			T1	408		T3	799		T6	62
all_values[4]	auto[1]	auto[1]	360	1			T1	2		T6	2		T9	1
all_values[5]	auto[0]	auto[0]	38088	1			T1	331		T3	317		T4	2
all_values[5]	auto[0]	auto[1]	136	1			T6	6		T12	1		T32	4
all_values[5]	auto[1]	auto[0]	38511	1			T1	707		T3	961		T5	4
all_values[5]	auto[1]	auto[1]	126	1			T1	5		T6	2		T12	5
all_values[6]	auto[0]	auto[0]	39948	1			T1	894		T3	1132		T4	2
all_values[6]	auto[0]	auto[1]	152	1			T1	4		T6	3		T12	1
all_values[6]	auto[1]	auto[0]	36603	1			T1	143		T3	146		T5	2
all_values[6]	auto[1]	auto[1]	158	1			T1	2		T6	5		T12	3
all_values[7]	auto[0]	auto[0]	38469	1			T1	815		T3	317		T4	2
all_values[7]	auto[0]	auto[1]	214	1			T1	3		T6	4		T12	2
all_values[7]	auto[1]	auto[0]	37871	1			T1	222		T3	961		T5	2
all_values[7]	auto[1]	auto[1]	307	1			T1	3		T6	1		T12	2
all_values[8]	auto[0]	auto[0]	22774	1			T1	500		T3	161		T5	1
all_values[8]	auto[0]	auto[1]	13660	1			T1	229		T3	2		T4	2
all_values[8]	auto[1]	auto[0]	28520	1			T1	53		T3	1104		T6	35
all_values[8]	auto[1]	auto[1]	11907	1			T1	261		T3	11		T5	2