Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2585

1

T1

2

T2

1

T3

1

auto[UartRx]

2585

1

T1

2

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4476	1			T1	4		T2	2		T3	2
values[1]	44	1			T29	1		T33	1		T90	1
values[2]	51	1			T12	1		T22	1		T30	1
values[3]	47	1			T6	1		T34	2		T90	2
values[4]	69	1			T12	1		T29	1		T30	2
values[5]	71	1			T12	1		T22	1		T29	1
values[6]	45	1			T6	1		T12	1		T22	1
values[7]	60	1			T6	3		T22	1		T33	1
values[8]	78	1			T6	2		T21	1		T32	1
values[9]	68	1			T6	2		T29	2		T33	2
values[10]	105	1			T12	1		T21	1		T29	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2343	1			T1	2		T2	1		T3	1
auto[UartTx]	values[1]	16	1			T92	1		T105	1		T95	1
auto[UartTx]	values[2]	23	1			T12	1		T22	1		T32	1
auto[UartTx]	values[3]	18	1			T90	2		T304	1		T249	1
auto[UartTx]	values[4]	19	1			T30	1		T33	1		T41	1
auto[UartTx]	values[5]	25	1			T12	1		T22	1		T31	1
auto[UartTx]	values[6]	17	1			T6	1		T91	2		T95	2
auto[UartTx]	values[7]	17	1			T6	1		T34	2		T304	1
auto[UartTx]	values[8]	32	1			T6	1		T32	1		T33	1
auto[UartTx]	values[9]	20	1			T29	1		T33	1		T34	1
auto[UartTx]	values[10]	36	1			T285	1		T88	1		T105	1
auto[UartRx]	values[0]	2133	1			T1	2		T2	1		T3	1
auto[UartRx]	values[1]	28	1			T29	1		T33	1		T90	1
auto[UartRx]	values[2]	28	1			T30	1		T31	1		T32	1
auto[UartRx]	values[3]	29	1			T6	1		T34	2		T139	1
auto[UartRx]	values[4]	50	1			T12	1		T29	1		T30	1
auto[UartRx]	values[5]	46	1			T29	1		T30	1		T32	1
auto[UartRx]	values[6]	28	1			T12	1		T22	1		T30	1
auto[UartRx]	values[7]	43	1			T6	2		T22	1		T33	1
auto[UartRx]	values[8]	46	1			T6	1		T21	1		T34	2
auto[UartRx]	values[9]	48	1			T6	2		T29	1		T33	1
auto[UartRx]	values[10]	69	1			T12	1		T21	1		T29	2