Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1997	1			T1	11		T6	3		T8	6
auto[BaudRate115200]	1648	1			T1	13		T3	2		T5	2
auto[BaudRate230400]	1576	1			T1	17		T4	1		T5	1
auto[BaudRate128Kbps]	1693	1			T1	14		T4	1		T8	6
auto[BaudRate256Kbps]	1784	1			T1	15		T3	2		T5	2
auto[BaudRate1Mbps]	1460	1			T1	13		T3	1		T5	3
auto[BaudRate1p5Mbps]	1049	1			T1	6		T3	1		T8	6

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1389	1			T23	6		T36	5		T113	10
freqs[25]	884	1			T6	11		T20	18		T325	20
freqs[48]	548	1			T10	10		T38	10		T102	42
freqs[50]	506	1			T12	13		T324	6		T115	6
freqs[100]	828	1			T3	6		T9	3		T109	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	250	1			T36	2		T113	1		T116	1
auto[BaudRate9600]	freqs[25]	214	1			T6	3		T20	18		T325	20
auto[BaudRate9600]	freqs[48]	82	1			T10	1		T38	3		T102	4
auto[BaudRate9600]	freqs[50]	79	1			T12	3		T324	2		T33	3
auto[BaudRate9600]	freqs[100]	135	1			T109	3		T114	1		T296	1
auto[BaudRate115200]	freqs[24]	224	1			T36	2		T113	3		T244	1
auto[BaudRate115200]	freqs[25]	128	1			T6	4		T326	9		T108	4
auto[BaudRate115200]	freqs[48]	83	1			T10	2		T38	1		T102	4
auto[BaudRate115200]	freqs[50]	71	1			T12	4		T115	1		T33	3
auto[BaudRate115200]	freqs[100]	124	1			T3	2		T9	1		T255	2
auto[BaudRate230400]	freqs[24]	202	1			T113	2		T256	1		T244	2
auto[BaudRate230400]	freqs[25]	114	1			T6	2		T326	6		T290	2
auto[BaudRate230400]	freqs[48]	78	1			T38	1		T102	11		T245	1
auto[BaudRate230400]	freqs[50]	63	1			T12	2		T324	2		T115	1
auto[BaudRate230400]	freqs[100]	118	1			T9	1		T109	1		T114	1
auto[BaudRate128Kbps]	freqs[24]	210	1			T113	1		T256	4		T244	2
auto[BaudRate128Kbps]	freqs[25]	116	1			T326	9		T108	3		T183	2
auto[BaudRate128Kbps]	freqs[48]	80	1			T10	3		T38	2		T102	5
auto[BaudRate128Kbps]	freqs[50]	67	1			T12	2		T115	3		T33	5
auto[BaudRate128Kbps]	freqs[100]	112	1			T9	1		T109	1		T255	3
auto[BaudRate256Kbps]	freqs[24]	209	1			T23	1		T256	2		T244	3
auto[BaudRate256Kbps]	freqs[25]	116	1			T6	1		T326	6		T108	1
auto[BaudRate256Kbps]	freqs[48]	84	1			T10	1		T38	2		T102	5
auto[BaudRate256Kbps]	freqs[50]	76	1			T324	1		T115	1		T246	2
auto[BaudRate256Kbps]	freqs[100]	112	1			T3	2		T109	2		T114	1
auto[BaudRate1Mbps]	freqs[24]	192	1			T23	4		T36	1		T113	2
auto[BaudRate1Mbps]	freqs[25]	127	1			T6	1		T326	15		T108	1
auto[BaudRate1Mbps]	freqs[48]	72	1			T10	2		T38	1		T102	8
auto[BaudRate1Mbps]	freqs[50]	73	1			T12	1		T33	3		T122	1
auto[BaudRate1Mbps]	freqs[100]	116	1			T3	1		T114	2		T255	1
auto[BaudRate1p5Mbps]	freqs[25]	69	1			T326	3		T108	2		T40	1
auto[BaudRate1p5Mbps]	freqs[48]	69	1			T10	1		T102	5		T119	1
auto[BaudRate1p5Mbps]	freqs[50]	77	1			T12	1		T324	1		T246	2
auto[BaudRate1p5Mbps]	freqs[100]	111	1			T3	1		T255	1		T254	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded