Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.39	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	15	115	88.46

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	15	115	88.46	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	20745933	1			T1	247652		T3	162759		T5	19
all_levels[1]	150622	1			T1	5277		T3	13		T10	1
all_levels[2]	2138	1			T1	24		T11	1		T24	5
all_levels[3]	951	1			T1	2		T11	1		T24	3
all_levels[4]	660	1			T6	1		T24	4		T16	1
all_levels[5]	469	1			T6	1		T16	1		T70	1
all_levels[6]	365	1			T6	1		T16	1		T107	1
all_levels[7]	306	1			T70	2		T37	1		T108	1
all_levels[8]	275	1			T10	1		T37	1		T108	1
all_levels[9]	218	1			T10	2		T22	1		T37	1
all_levels[10]	201	1			T10	1		T22	1		T29	1
all_levels[11]	175	1			T22	1		T109	1		T108	2
all_levels[12]	164	1			T22	1		T97	1		T110	1
all_levels[13]	138	1			T108	1		T97	3		T98	1
all_levels[14]	131	1			T10	2		T97	1		T107	1
all_levels[15]	101	1			T99	1		T111	3		T112	1
all_levels[16]	111	1			T100	3		T97	1		T98	1
all_levels[17]	98	1			T97	1		T98	3		T99	1
all_levels[18]	92	1			T113	1		T111	2		T101	1
all_levels[19]	70	1			T99	1		T114	1		T113	1
all_levels[20]	67	1			T97	1		T107	1		T98	1
all_levels[21]	72	1			T99	1		T111	1		T115	1
all_levels[22]	65	1			T10	2		T109	3		T99	1
all_levels[23]	58	1			T113	1		T112	3		T96	1
all_levels[24]	47	1			T10	1		T116	1		T117	1
all_levels[25]	57	1			T100	1		T118	1		T119	1
all_levels[26]	45	1			T99	1		T111	1		T101	1
all_levels[27]	36	1			T98	1		T102	2		T120	1
all_levels[28]	26	1			T98	1		T113	1		T115	1
all_levels[29]	23	1			T99	1		T85	1		T121	1
all_levels[30]	34	1			T111	1		T101	1		T116	2
all_levels[31]	37	1			T99	1		T38	1		T101	2
all_levels[32]	23	1			T122	1		T123	1		T124	1
all_levels[33]	32	1			T125	1		T102	1		T126	2
all_levels[34]	28	1			T97	1		T99	1		T127	1
all_levels[35]	16	1			T97	1		T128	2		T85	1
all_levels[36]	10	1			T129	1		T130	1		T131	1
all_levels[37]	26	1			T113	2		T102	1		T128	1
all_levels[38]	17	1			T38	1		T132	1		T123	1
all_levels[39]	16	1			T132	1		T133	1		T134	1
all_levels[40]	12	1			T129	1		T85	1		T46	1
all_levels[41]	20	1			T135	2		T136	2		T137	1
all_levels[42]	22	1			T37	1		T138	1		T132	1
all_levels[43]	18	1			T114	1		T102	1		T139	1
all_levels[44]	14	1			T10	1		T140	1		T136	1
all_levels[45]	10	1			T132	1		T94	1		T141	2
all_levels[46]	7	1			T142	1		T143	1		T144	1
all_levels[47]	12	1			T145	1		T85	1		T127	1
all_levels[48]	10	1			T146	1		T141	1		T147	1
all_levels[49]	6	1			T148	2		T149	1		T150	2
all_levels[50]	13	1			T24	1		T102	5		T151	1
all_levels[51]	14	1			T85	1		T152	2		T153	1
all_levels[52]	6	1			T117	1		T154	1		T155	1
all_levels[53]	11	1			T156	5		T85	3		T120	1
all_levels[54]	7	1			T104	1		T157	1		T158	1
all_levels[55]	7	1			T159	2		T160	1		T161	1
all_levels[56]	3	1			T162	1		T163	1		T164	1
all_levels[57]	2	1			T165	1		T166	1		-	-
all_levels[58]	6	1			T102	1		T167	1		T168	1
all_levels[59]	2	1			T158	1		T169	1		-	-
all_levels[60]	3	1			T170	1		T171	1		T172	1
all_levels[61]	2	1			T104	1		T173	1		-	-
all_levels[62]	5	1			T174	1		T169	1		T175	1
all_levels[63]	17	1			T176	3		T177	1		T178	1
all_levels[64]	78	1			T13	1		T14	3		T117	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20900285

1

T1

252946

T3

162772

T5

15

auto[1]

3975

1

T1

9

T5

4

T6

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	15	115	88.46	15

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[44] , all_levels[45] , all_levels[46] , all_levels[47] , all_levels[48]]	[auto[1]]	--	--	5
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[56] , all_levels[57] , all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61] , all_levels[62]]	[auto[1]]	--	--	7

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	20742412	1			T1	247643		T3	162759		T5	15
all_levels[0]	auto[1]	3521	1			T1	9		T5	4		T6	1
all_levels[1]	auto[0]	150546	1			T1	5277		T3	13		T10	1
all_levels[1]	auto[1]	76	1			T35	1		T38	2		T112	1
all_levels[2]	auto[0]	2105	1			T1	24		T11	1		T24	5
all_levels[2]	auto[1]	33	1			T179	1		T180	2		T124	1
all_levels[3]	auto[0]	931	1			T1	2		T11	1		T24	3
all_levels[3]	auto[1]	20	1			T113	1		T176	1		T126	1
all_levels[4]	auto[0]	638	1			T6	1		T24	4		T16	1
all_levels[4]	auto[1]	22	1			T107	1		T110	1		T181	2
all_levels[5]	auto[0]	459	1			T6	1		T16	1		T70	1
all_levels[5]	auto[1]	10	1			T97	1		T98	2		T146	1
all_levels[6]	auto[0]	347	1			T6	1		T16	1		T107	1
all_levels[6]	auto[1]	18	1			T113	3		T180	1		T182	1
all_levels[7]	auto[0]	282	1			T70	2		T37	1		T108	1
all_levels[7]	auto[1]	24	1			T183	1		T138	1		T184	2
all_levels[8]	auto[0]	256	1			T10	1		T37	1		T108	1
all_levels[8]	auto[1]	19	1			T177	1		T184	1		T185	1
all_levels[9]	auto[0]	206	1			T10	1		T22	1		T37	1
all_levels[9]	auto[1]	12	1			T10	1		T111	1		T186	1
all_levels[10]	auto[0]	195	1			T10	1		T22	1		T29	1
all_levels[10]	auto[1]	6	1			T107	2		T187	3		T188	1
all_levels[11]	auto[0]	162	1			T22	1		T109	1		T108	2
all_levels[11]	auto[1]	13	1			T146	1		T189	2		T190	2
all_levels[12]	auto[0]	149	1			T22	1		T97	1		T110	1
all_levels[12]	auto[1]	15	1			T141	1		T191	1		T192	1
all_levels[13]	auto[0]	128	1			T108	1		T97	3		T98	1
all_levels[13]	auto[1]	10	1			T183	1		T193	1		T194	1
all_levels[14]	auto[0]	122	1			T10	1		T97	1		T107	1
all_levels[14]	auto[1]	9	1			T10	1		T195	3		T188	1
all_levels[15]	auto[0]	97	1			T99	1		T111	3		T112	1
all_levels[15]	auto[1]	4	1			T196	1		T197	1		T198	1
all_levels[16]	auto[0]	104	1			T100	1		T97	1		T98	1
all_levels[16]	auto[1]	7	1			T100	2		T199	2		T200	1
all_levels[17]	auto[0]	91	1			T97	1		T98	2		T99	1
all_levels[17]	auto[1]	7	1			T98	1		T89	1		T201	1
all_levels[18]	auto[0]	80	1			T113	1		T111	2		T101	1
all_levels[18]	auto[1]	12	1			T46	1		T189	1		T202	2
all_levels[19]	auto[0]	64	1			T99	1		T114	1		T113	1
all_levels[19]	auto[1]	6	1			T203	1		T204	1		T205	2
all_levels[20]	auto[0]	60	1			T97	1		T107	1		T98	1
all_levels[20]	auto[1]	7	1			T179	1		T162	1		T206	1
all_levels[21]	auto[0]	65	1			T99	1		T111	1		T115	1
all_levels[21]	auto[1]	7	1			T207	1		T121	1		T208	1
all_levels[22]	auto[0]	54	1			T10	1		T109	1		T99	1
all_levels[22]	auto[1]	11	1			T10	1		T109	2		T189	2
all_levels[23]	auto[0]	54	1			T113	1		T112	1		T96	1
all_levels[23]	auto[1]	4	1			T112	2		T209	1		T210	1
all_levels[24]	auto[0]	36	1			T10	1		T116	1		T117	1
all_levels[24]	auto[1]	11	1			T211	1		T212	1		T150	4
all_levels[25]	auto[0]	49	1			T100	1		T118	1		T119	1
all_levels[25]	auto[1]	8	1			T129	2		T46	1		T213	1
all_levels[26]	auto[0]	44	1			T99	1		T111	1		T101	1
all_levels[26]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[27]	auto[0]	35	1			T98	1		T102	2		T120	1
all_levels[27]	auto[1]	1	1			T215	1		-	-		-	-
all_levels[28]	auto[0]	25	1			T98	1		T113	1		T115	1
all_levels[28]	auto[1]	1	1			T216	1		-	-		-	-
all_levels[29]	auto[0]	22	1			T99	1		T85	1		T121	1
all_levels[29]	auto[1]	1	1			T191	1		-	-		-	-
all_levels[30]	auto[0]	30	1			T111	1		T101	1		T116	1
all_levels[30]	auto[1]	4	1			T116	1		T129	1		T217	1
all_levels[31]	auto[0]	33	1			T99	1		T38	1		T101	2
all_levels[31]	auto[1]	4	1			T87	1		T218	1		T219	2
all_levels[32]	auto[0]	21	1			T122	1		T123	1		T124	1
all_levels[32]	auto[1]	2	1			T216	2		-	-		-	-
all_levels[33]	auto[0]	26	1			T125	1		T102	1		T126	1
all_levels[33]	auto[1]	6	1			T126	1		T197	3		T220	1
all_levels[34]	auto[0]	23	1			T97	1		T99	1		T127	1
all_levels[34]	auto[1]	5	1			T167	1		T221	2		T222	1
all_levels[35]	auto[0]	16	1			T97	1		T128	2		T85	1
all_levels[36]	auto[0]	9	1			T129	1		T130	1		T131	1
all_levels[36]	auto[1]	1	1			T223	1		-	-		-	-
all_levels[37]	auto[0]	24	1			T113	2		T102	1		T128	1
all_levels[37]	auto[1]	2	1			T224	2		-	-		-	-
all_levels[38]	auto[0]	13	1			T38	1		T132	1		T123	1
all_levels[38]	auto[1]	4	1			T182	2		T225	2		-	-
all_levels[39]	auto[0]	14	1			T132	1		T133	1		T134	1
all_levels[39]	auto[1]	2	1			T226	1		T227	1		-	-
all_levels[40]	auto[0]	12	1			T129	1		T85	1		T46	1
all_levels[41]	auto[0]	14	1			T135	1		T136	2		T137	1
all_levels[41]	auto[1]	6	1			T135	1		T228	3		T229	1
all_levels[42]	auto[0]	18	1			T37	1		T138	1		T132	1
all_levels[42]	auto[1]	4	1			T230	2		T231	1		T232	1
all_levels[43]	auto[0]	17	1			T114	1		T102	1		T139	1
all_levels[43]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[44]	auto[0]	14	1			T10	1		T140	1		T136	1
all_levels[45]	auto[0]	10	1			T132	1		T94	1		T141	2
all_levels[46]	auto[0]	7	1			T142	1		T143	1		T144	1
all_levels[47]	auto[0]	12	1			T145	1		T85	1		T127	1
all_levels[48]	auto[0]	10	1			T146	1		T141	1		T147	1
all_levels[49]	auto[0]	4	1			T148	1		T149	1		T150	1
all_levels[49]	auto[1]	2	1			T148	1		T150	1		-	-
all_levels[50]	auto[0]	6	1			T24	1		T102	1		T151	1
all_levels[50]	auto[1]	7	1			T102	4		T233	3		-	-
all_levels[51]	auto[0]	11	1			T85	1		T152	1		T153	1
all_levels[51]	auto[1]	3	1			T152	1		T234	1		T235	1
all_levels[52]	auto[0]	6	1			T117	1		T154	1		T155	1
all_levels[53]	auto[0]	5	1			T156	1		T85	1		T120	1
all_levels[53]	auto[1]	6	1			T156	4		T85	2		-	-
all_levels[54]	auto[0]	5	1			T104	1		T157	1		T158	1
all_levels[54]	auto[1]	2	1			T236	2		-	-		-	-
all_levels[55]	auto[0]	6	1			T159	1		T160	1		T161	1
all_levels[55]	auto[1]	1	1			T159	1		-	-		-	-
all_levels[56]	auto[0]	3	1			T162	1		T163	1		T164	1
all_levels[57]	auto[0]	2	1			T165	1		T166	1		-	-
all_levels[58]	auto[0]	6	1			T102	1		T167	1		T168	1
all_levels[59]	auto[0]	2	1			T158	1		T169	1		-	-
all_levels[60]	auto[0]	3	1			T170	1		T171	1		T172	1
all_levels[61]	auto[0]	2	1			T104	1		T173	1		-	-
all_levels[62]	auto[0]	5	1			T174	1		T169	1		T175	1
all_levels[63]	auto[0]	12	1			T176	1		T177	1		T178	1
all_levels[63]	auto[1]	5	1			T176	2		T224	1		T237	1
all_levels[64]	auto[0]	66	1			T13	1		T14	1		T117	1
all_levels[64]	auto[1]	12	1			T14	2		T117	1		T204	2