Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	76861	1			T1	1043		T3	1278		T4	2
all_pins[1]	76861	1			T1	1043		T3	1278		T4	2
all_pins[2]	76861	1			T1	1043		T3	1278		T4	2
all_pins[3]	76861	1			T1	1043		T3	1278		T4	2
all_pins[4]	76861	1			T1	1043		T3	1278		T4	2
all_pins[5]	76861	1			T1	1043		T3	1278		T4	2
all_pins[6]	76861	1			T1	1043		T3	1278		T4	2
all_pins[7]	76861	1			T1	1043		T3	1278		T4	2
all_pins[8]	76861	1			T1	1043		T3	1278		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	659085	1			T1	8647		T3	11480		T4	18
values[0x1]	32664	1			T1	740		T3	22		T5	8
transitions[0x0=>0x1]	26123	1			T1	530		T3	22		T5	6
transitions[0x1=>0x0]	25929	1			T1	530		T3	22		T5	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	61608	1			T1	591		T3	1272		T4	2
all_pins[0]	values[0x1]	15253	1			T1	452		T3	6		T5	4
all_pins[0]	transitions[0x0=>0x1]	14690	1			T1	452		T3	6		T5	4
all_pins[0]	transitions[0x1=>0x0]	811	1			T6	1		T12	1		T16	3
all_pins[1]	values[0x0]	75487	1			T1	1043		T3	1278		T4	2
all_pins[1]	values[0x1]	1374	1			T6	1		T12	1		T16	19
all_pins[1]	transitions[0x0=>0x1]	1289	1			T6	1		T12	1		T16	19
all_pins[1]	transitions[0x1=>0x0]	2089	1			T1	11		T3	2		T5	1
all_pins[2]	values[0x0]	74687	1			T1	1032		T3	1276		T4	2
all_pins[2]	values[0x1]	2174	1			T1	11		T3	2		T5	1
all_pins[2]	transitions[0x0=>0x1]	2123	1			T1	11		T3	2		T5	1
all_pins[2]	transitions[0x1=>0x0]	189	1			T9	1		T12	2		T13	2
all_pins[3]	values[0x0]	76621	1			T1	1043		T3	1278		T4	2
all_pins[3]	values[0x1]	240	1			T9	1		T12	2		T13	2
all_pins[3]	transitions[0x0=>0x1]	202	1			T9	1		T12	1		T13	2
all_pins[3]	transitions[0x1=>0x0]	322	1			T1	2		T6	2		T9	1
all_pins[4]	values[0x0]	76501	1			T1	1041		T3	1278		T4	2
all_pins[4]	values[0x1]	360	1			T1	2		T6	2		T9	1
all_pins[4]	transitions[0x0=>0x1]	302	1			T1	1		T6	1		T9	1
all_pins[4]	transitions[0x1=>0x0]	96	1			T1	4		T6	1		T12	3
all_pins[5]	values[0x0]	76707	1			T1	1038		T3	1278		T4	2
all_pins[5]	values[0x1]	154	1			T1	5		T6	2		T12	5
all_pins[5]	transitions[0x0=>0x1]	111	1			T1	3		T6	1		T12	3
all_pins[5]	transitions[0x1=>0x0]	791	1			T1	4		T5	1		T6	4
all_pins[6]	values[0x0]	76027	1			T1	1037		T3	1278		T4	2
all_pins[6]	values[0x1]	834	1			T1	6		T5	1		T6	5
all_pins[6]	transitions[0x0=>0x1]	782	1			T1	6		T5	1		T6	5
all_pins[6]	transitions[0x1=>0x0]	255	1			T1	3		T6	1		T12	2
all_pins[7]	values[0x0]	76554	1			T1	1040		T3	1278		T4	2
all_pins[7]	values[0x1]	307	1			T1	3		T6	1		T12	2
all_pins[7]	transitions[0x0=>0x1]	189	1			T1	1		T6	1		T103	2
all_pins[7]	transitions[0x1=>0x0]	11850	1			T1	259		T3	14		T5	2
all_pins[8]	values[0x0]	64893	1			T1	782		T3	1264		T4	2
all_pins[8]	values[0x1]	11968	1			T1	261		T3	14		T5	2
all_pins[8]	transitions[0x0=>0x1]	6435	1			T1	56		T3	14		T6	6
all_pins[8]	transitions[0x1=>0x0]	9526	1			T1	247		T3	6		T5	1