Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5155447	1			T1	144079		T3	4613		T5	13
all_levels[1]	1133721	1			T1	39891		T3	4622		T6	264
all_levels[2]	457909	1			T1	1576		T3	4586		T6	539
all_levels[3]	131369	1			T1	902		T3	4595		T6	509
all_levels[4]	295125	1			T1	906		T3	4598		T6	504
all_levels[5]	160572	1			T1	916		T3	4608		T10	2
all_levels[6]	161199	1			T1	909		T3	4619		T6	2
all_levels[7]	141319	1			T1	882		T3	4601		T6	1
all_levels[8]	216866	1			T1	854		T3	4622		T6	1
all_levels[9]	129008	1			T1	862		T3	4615		T6	4
all_levels[10]	316546	1			T1	868		T3	4597		T6	1
all_levels[11]	201393	1			T1	883		T3	4618		T11	1
all_levels[12]	144127	1			T1	3397		T3	4607		T6	1
all_levels[13]	129657	1			T1	875		T3	4608		T5	3
all_levels[14]	153331	1			T1	884		T3	4594		T6	3
all_levels[15]	272895	1			T1	904		T3	4592		T10	2
all_levels[16]	490873	1			T1	861		T3	4610		T6	1
all_levels[17]	194288	1			T1	857		T3	4611		T12	2
all_levels[18]	125877	1			T1	901		T3	4618		T11	2
all_levels[19]	254336	1			T1	926		T3	4591		T12	2
all_levels[20]	132459	1			T1	887		T3	4618		T6	2
all_levels[21]	131290	1			T1	885		T3	4606		T11	16
all_levels[22]	141002	1			T1	892		T3	4592		T12	2
all_levels[23]	178127	1			T1	877		T3	4600		T6	2
all_levels[24]	289302	1			T1	869		T3	4618		T6	1
all_levels[25]	122545	1			T1	871		T3	4572		T11	1
all_levels[26]	148171	1			T1	847		T3	4606		T12	2
all_levels[27]	286583	1			T1	888		T3	4604		T6	4
all_levels[28]	120883	1			T1	909		T3	4613		T6	2
all_levels[29]	140028	1			T1	854		T3	4585		T12	2
all_levels[30]	243182	1			T1	900		T3	4614		T12	2
all_levels[31]	424885	1			T1	2674		T3	4808		T6	111
all_levels[32]	8279740	1			T1	37461		T3	15211		T5	6

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20900285

1

T1

252946

T3

162772

T5

15

auto[1]

3770

1

T1

1

T5

7

T6

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5153409	1			T1	144079		T3	4613		T5	9
all_levels[0]	auto[1]	2038	1			T5	4		T6	1		T9	24
all_levels[1]	auto[0]	1133457	1			T1	39891		T3	4622		T6	264
all_levels[1]	auto[1]	264	1			T9	3		T10	1		T13	1
all_levels[2]	auto[0]	457863	1			T1	1576		T3	4586		T6	539
all_levels[2]	auto[1]	46	1			T259	1		T279	1		T217	1
all_levels[3]	auto[0]	131288	1			T1	902		T3	4595		T6	509
all_levels[3]	auto[1]	81	1			T17	7		T321	3		T303	11
all_levels[4]	auto[0]	295102	1			T1	906		T3	4598		T6	504
all_levels[4]	auto[1]	23	1			T176	1		T248	1		T179	1
all_levels[5]	auto[0]	160545	1			T1	916		T3	4608		T10	2
all_levels[5]	auto[1]	27	1			T324	1		T177	1		T85	1
all_levels[6]	auto[0]	161167	1			T1	909		T3	4619		T6	2
all_levels[6]	auto[1]	32	1			T30	2		T261	1		T98	1
all_levels[7]	auto[0]	141195	1			T1	882		T3	4601		T6	1
all_levels[7]	auto[1]	124	1			T10	2		T14	2		T110	2
all_levels[8]	auto[0]	216844	1			T1	854		T3	4622		T6	1
all_levels[8]	auto[1]	22	1			T183	1		T138	1		T269	1
all_levels[9]	auto[0]	128992	1			T1	862		T3	4615		T6	4
all_levels[9]	auto[1]	16	1			T38	1		T165	1		T191	4
all_levels[10]	auto[0]	316527	1			T1	868		T3	4597		T6	1
all_levels[10]	auto[1]	19	1			T253	1		T181	2		T186	1
all_levels[11]	auto[0]	201357	1			T1	883		T3	4618		T11	1
all_levels[11]	auto[1]	36	1			T207	1		T102	1		T279	1
all_levels[12]	auto[0]	144106	1			T1	3397		T3	4607		T6	1
all_levels[12]	auto[1]	21	1			T24	1		T207	2		T199	2
all_levels[13]	auto[0]	129634	1			T1	875		T3	4608		T5	2
all_levels[13]	auto[1]	23	1			T5	1		T85	1		T306	1
all_levels[14]	auto[0]	153303	1			T1	884		T3	4594		T6	3
all_levels[14]	auto[1]	28	1			T273	1		T332	1		T333	2
all_levels[15]	auto[0]	272796	1			T1	904		T3	4592		T10	2
all_levels[15]	auto[1]	99	1			T100	2		T108	1		T98	1
all_levels[16]	auto[0]	490842	1			T1	861		T3	4610		T6	1
all_levels[16]	auto[1]	31	1			T98	1		T87	1		T334	1
all_levels[17]	auto[0]	194264	1			T1	857		T3	4611		T12	2
all_levels[17]	auto[1]	24	1			T109	1		T117	3		T199	1
all_levels[18]	auto[0]	125859	1			T1	901		T3	4618		T11	2
all_levels[18]	auto[1]	18	1			T126	1		T82	1		T335	1
all_levels[19]	auto[0]	254311	1			T1	926		T3	4591		T12	2
all_levels[19]	auto[1]	25	1			T263	1		T259	1		T204	2
all_levels[20]	auto[0]	132442	1			T1	887		T3	4618		T6	2
all_levels[20]	auto[1]	17	1			T110	1		T182	1		T336	1
all_levels[21]	auto[0]	131265	1			T1	885		T3	4606		T11	15
all_levels[21]	auto[1]	25	1			T11	1		T36	1		T260	1
all_levels[22]	auto[0]	140976	1			T1	892		T3	4592		T12	2
all_levels[22]	auto[1]	26	1			T263	1		T143	3		T337	2
all_levels[23]	auto[0]	178111	1			T1	877		T3	4600		T6	2
all_levels[23]	auto[1]	16	1			T107	2		T101	1		T176	2
all_levels[24]	auto[0]	289291	1			T1	869		T3	4618		T6	1
all_levels[24]	auto[1]	11	1			T107	1		T184	1		T88	1
all_levels[25]	auto[0]	122523	1			T1	871		T3	4572		T11	1
all_levels[25]	auto[1]	22	1			T242	1		T217	4		T120	1
all_levels[26]	auto[0]	148156	1			T1	847		T3	4606		T12	2
all_levels[26]	auto[1]	15	1			T112	1		T256	1		T133	1
all_levels[27]	auto[0]	286547	1			T1	888		T3	4604		T6	4
all_levels[27]	auto[1]	36	1			T261	1		T176	1		T309	1
all_levels[28]	auto[0]	120861	1			T1	909		T3	4613		T6	2
all_levels[28]	auto[1]	22	1			T261	1		T123	3		T81	1
all_levels[29]	auto[0]	140003	1			T1	854		T3	4585		T12	2
all_levels[29]	auto[1]	25	1			T98	3		T259	4		T85	1
all_levels[30]	auto[0]	243142	1			T1	900		T3	4614		T12	2
all_levels[30]	auto[1]	40	1			T35	1		T112	2		T138	3
all_levels[31]	auto[0]	424863	1			T1	2674		T3	4808		T6	111
all_levels[31]	auto[1]	22	1			T97	2		T14	2		T275	1
all_levels[32]	auto[0]	8279244	1			T1	37460		T3	15211		T5	4
all_levels[32]	auto[1]	496	1			T1	1		T5	2		T10	2