Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	606	1			T1	7		T6	11		T12	14
all_values[1]	606	1			T1	7		T6	11		T12	14
all_values[2]	606	1			T1	7		T6	11		T12	14
all_values[3]	606	1			T1	7		T6	11		T12	14
all_values[4]	606	1			T1	7		T6	11		T12	14
all_values[5]	606	1			T1	7		T6	11		T12	14
all_values[6]	606	1			T1	7		T6	11		T12	14
all_values[7]	606	1			T1	7		T6	11		T12	14
all_values[8]	606	1			T1	7		T6	11		T12	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3052

1

T1

35

T6

59

T12

62

auto[1]

2402

1

T1

28

T6

40

T12

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1741

1

T1

7

T6

33

T12

57

auto[1]

3713

1

T1

56

T6

66

T12

69

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3216

1

T1

30

T6

61

T12

84

auto[1]

2238

1

T1

33

T6

38

T12

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	205	1			T6	3		T12	5		T98	2
all_values[0]	auto[0]	auto[1]	auto[1]	153	1			T1	4		T6	2		T12	3
all_values[0]	auto[1]	auto[0]	auto[1]	143	1			T6	4		T12	5		T98	2
all_values[0]	auto[1]	auto[1]	auto[1]	105	1			T1	3		T6	2		T12	1
all_values[1]	auto[0]	auto[0]	auto[0]	220	1			T1	1		T6	6		T12	3
all_values[1]	auto[0]	auto[1]	auto[0]	160	1			T1	5		T6	2		T12	6
all_values[1]	auto[1]	auto[0]	auto[1]	145	1			T1	1		T6	2		T12	3
all_values[1]	auto[1]	auto[1]	auto[1]	81	1			T6	1		T12	2		T98	2
all_values[2]	auto[0]	auto[0]	auto[0]	140	1			T12	7		T98	1		T32	1
all_values[2]	auto[0]	auto[0]	auto[1]	63	1			T1	4		T6	4		T105	1
all_values[2]	auto[0]	auto[1]	auto[0]	94	1			T6	1		T12	4		T98	1
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T6	3		T98	1		T32	1
all_values[2]	auto[1]	auto[0]	auto[1]	162	1			T1	2		T6	2		T12	3
all_values[2]	auto[1]	auto[1]	auto[1]	86	1			T1	1		T6	1		T98	1
all_values[3]	auto[0]	auto[0]	auto[0]	114	1			T1	1		T6	3		T12	6
all_values[3]	auto[0]	auto[0]	auto[1]	54	1			T1	3		T6	1		T12	1
all_values[3]	auto[0]	auto[1]	auto[0]	121	1			T6	4		T12	4		T98	3
all_values[3]	auto[0]	auto[1]	auto[1]	65	1			T98	1		T32	3		T106	2
all_values[3]	auto[1]	auto[0]	auto[1]	130	1			T1	3		T6	2		T98	1
all_values[3]	auto[1]	auto[1]	auto[1]	122	1			T6	1		T12	3		T98	1
all_values[4]	auto[0]	auto[0]	auto[0]	110	1			T6	2		T12	3		T98	2
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T1	2		T12	4		T98	1
all_values[4]	auto[0]	auto[1]	auto[0]	86	1			T6	5		T12	1		T32	1
all_values[4]	auto[0]	auto[1]	auto[1]	57	1			T1	1		T12	1		T98	1
all_values[4]	auto[1]	auto[0]	auto[1]	155	1			T1	4		T6	2		T12	2
all_values[4]	auto[1]	auto[1]	auto[1]	111	1			T6	2		T12	3		T98	2
all_values[5]	auto[0]	auto[0]	auto[0]	137	1			T6	2		T12	2		T98	3
all_values[5]	auto[0]	auto[0]	auto[1]	59	1			T6	3		T32	1		T33	1
all_values[5]	auto[0]	auto[1]	auto[0]	114	1			T12	4		T98	3		T32	2
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T1	1		T12	2		T32	1
all_values[5]	auto[1]	auto[0]	auto[1]	141	1			T1	1		T6	3		T12	1
all_values[5]	auto[1]	auto[1]	auto[1]	97	1			T1	5		T6	3		T12	5
all_values[6]	auto[0]	auto[0]	auto[0]	113	1			T6	2		T12	3		T32	2
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T1	1		T6	2		T12	1
all_values[6]	auto[0]	auto[1]	auto[0]	98	1			T6	1		T12	6		T98	1
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T1	1		T6	1		T12	1
all_values[6]	auto[1]	auto[0]	auto[1]	143	1			T1	3		T98	3		T32	2
all_values[6]	auto[1]	auto[1]	auto[1]	113	1			T1	2		T6	5		T12	3
all_values[7]	auto[0]	auto[0]	auto[0]	135	1			T6	4		T12	5		T98	4
all_values[7]	auto[0]	auto[0]	auto[1]	55	1			T1	1		T6	2		T12	1
all_values[7]	auto[0]	auto[1]	auto[0]	99	1			T6	1		T12	3		T32	1
all_values[7]	auto[0]	auto[1]	auto[1]	66	1			T12	1		T98	1		T33	2
all_values[7]	auto[1]	auto[0]	auto[1]	132	1			T1	3		T6	4		T12	3
all_values[7]	auto[1]	auto[1]	auto[1]	119	1			T1	3		T12	1		T98	1
all_values[8]	auto[0]	auto[0]	auto[1]	207	1			T1	4		T6	4		T12	3
all_values[8]	auto[0]	auto[1]	auto[1]	146	1			T1	1		T6	3		T12	4
all_values[8]	auto[1]	auto[0]	auto[1]	134	1			T1	1		T6	2		T12	1
all_values[8]	auto[1]	auto[1]	auto[1]	119	1			T1	1		T6	2		T12	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal