Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.10 97.65 100.00 98.38 100.00 99.44


Total test records in report: 1315
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T1254 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1215863092 Aug 19 04:35:42 PM PDT 24 Aug 19 04:35:43 PM PDT 24 28016314 ps
T1255 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4006944309 Aug 19 04:35:44 PM PDT 24 Aug 19 04:35:45 PM PDT 24 15560821 ps
T59 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1254624786 Aug 19 04:35:31 PM PDT 24 Aug 19 04:35:32 PM PDT 24 179697207 ps
T1256 /workspace/coverage/cover_reg_top/28.uart_intr_test.3169195861 Aug 19 04:35:57 PM PDT 24 Aug 19 04:35:57 PM PDT 24 51603114 ps
T1257 /workspace/coverage/cover_reg_top/0.uart_intr_test.3410534633 Aug 19 04:35:45 PM PDT 24 Aug 19 04:35:45 PM PDT 24 79858607 ps
T1258 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1051690235 Aug 19 04:35:26 PM PDT 24 Aug 19 04:35:27 PM PDT 24 260942156 ps
T1259 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.780211501 Aug 19 04:35:38 PM PDT 24 Aug 19 04:35:39 PM PDT 24 92706840 ps
T1260 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.706052499 Aug 19 04:35:27 PM PDT 24 Aug 19 04:35:28 PM PDT 24 17363255 ps
T1261 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2439982421 Aug 19 04:35:47 PM PDT 24 Aug 19 04:35:48 PM PDT 24 19526856 ps
T1262 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4155809253 Aug 19 04:35:32 PM PDT 24 Aug 19 04:35:38 PM PDT 24 73339896 ps
T1263 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1267571034 Aug 19 04:35:51 PM PDT 24 Aug 19 04:35:52 PM PDT 24 177385940 ps
T1264 /workspace/coverage/cover_reg_top/2.uart_intr_test.2480025224 Aug 19 04:35:31 PM PDT 24 Aug 19 04:35:31 PM PDT 24 34999461 ps
T1265 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3411528659 Aug 19 04:35:41 PM PDT 24 Aug 19 04:35:42 PM PDT 24 24647200 ps
T1266 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1983856160 Aug 19 04:35:35 PM PDT 24 Aug 19 04:35:36 PM PDT 24 118140568 ps
T1267 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1078980570 Aug 19 04:35:46 PM PDT 24 Aug 19 04:35:47 PM PDT 24 80470358 ps
T1268 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.746194046 Aug 19 04:35:47 PM PDT 24 Aug 19 04:35:49 PM PDT 24 688425935 ps
T1269 /workspace/coverage/cover_reg_top/11.uart_intr_test.2446133217 Aug 19 04:35:56 PM PDT 24 Aug 19 04:35:56 PM PDT 24 21735734 ps
T1270 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.667449943 Aug 19 04:35:48 PM PDT 24 Aug 19 04:35:49 PM PDT 24 33381179 ps
T1271 /workspace/coverage/cover_reg_top/1.uart_intr_test.2560044719 Aug 19 04:35:41 PM PDT 24 Aug 19 04:35:41 PM PDT 24 52846521 ps
T1272 /workspace/coverage/cover_reg_top/25.uart_intr_test.3092725336 Aug 19 04:35:49 PM PDT 24 Aug 19 04:35:50 PM PDT 24 32569933 ps
T1273 /workspace/coverage/cover_reg_top/44.uart_intr_test.4212578911 Aug 19 04:36:07 PM PDT 24 Aug 19 04:36:08 PM PDT 24 24100518 ps
T1274 /workspace/coverage/cover_reg_top/35.uart_intr_test.1707554363 Aug 19 04:36:01 PM PDT 24 Aug 19 04:36:02 PM PDT 24 101162819 ps
T1275 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2001036843 Aug 19 04:35:54 PM PDT 24 Aug 19 04:35:54 PM PDT 24 89932157 ps
T1276 /workspace/coverage/cover_reg_top/37.uart_intr_test.147028064 Aug 19 04:36:15 PM PDT 24 Aug 19 04:36:16 PM PDT 24 11781125 ps
T1277 /workspace/coverage/cover_reg_top/32.uart_intr_test.1270638063 Aug 19 04:36:08 PM PDT 24 Aug 19 04:36:09 PM PDT 24 37149768 ps
T1278 /workspace/coverage/cover_reg_top/3.uart_intr_test.1206872597 Aug 19 04:35:41 PM PDT 24 Aug 19 04:35:42 PM PDT 24 25336405 ps
T1279 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2792535363 Aug 19 04:35:38 PM PDT 24 Aug 19 04:35:39 PM PDT 24 25192468 ps
T1280 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1347505414 Aug 19 04:35:25 PM PDT 24 Aug 19 04:35:26 PM PDT 24 16784263 ps
T1281 /workspace/coverage/cover_reg_top/42.uart_intr_test.3927993251 Aug 19 04:36:01 PM PDT 24 Aug 19 04:36:02 PM PDT 24 32475079 ps
T1282 /workspace/coverage/cover_reg_top/2.uart_tl_errors.1698350672 Aug 19 04:35:39 PM PDT 24 Aug 19 04:35:40 PM PDT 24 196125705 ps
T1283 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1222542144 Aug 19 04:35:46 PM PDT 24 Aug 19 04:35:47 PM PDT 24 73449305 ps
T1284 /workspace/coverage/cover_reg_top/2.uart_csr_rw.202111481 Aug 19 04:35:41 PM PDT 24 Aug 19 04:35:42 PM PDT 24 18783700 ps
T1285 /workspace/coverage/cover_reg_top/10.uart_intr_test.771195087 Aug 19 04:35:44 PM PDT 24 Aug 19 04:35:44 PM PDT 24 35027524 ps
T1286 /workspace/coverage/cover_reg_top/16.uart_intr_test.817351450 Aug 19 04:35:46 PM PDT 24 Aug 19 04:35:47 PM PDT 24 18513690 ps
T1287 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2909145967 Aug 19 04:35:27 PM PDT 24 Aug 19 04:35:28 PM PDT 24 23933149 ps
T239 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1492054658 Aug 19 04:35:57 PM PDT 24 Aug 19 04:35:59 PM PDT 24 131872797 ps
T1288 /workspace/coverage/cover_reg_top/22.uart_intr_test.4077938062 Aug 19 04:36:01 PM PDT 24 Aug 19 04:36:02 PM PDT 24 44719451 ps
T1289 /workspace/coverage/cover_reg_top/14.uart_tl_errors.131240536 Aug 19 04:35:46 PM PDT 24 Aug 19 04:35:47 PM PDT 24 105055338 ps
T1290 /workspace/coverage/cover_reg_top/47.uart_intr_test.1279199599 Aug 19 04:36:04 PM PDT 24 Aug 19 04:36:05 PM PDT 24 107150577 ps
T1291 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3751224568 Aug 19 04:35:43 PM PDT 24 Aug 19 04:35:44 PM PDT 24 88862469 ps
T1292 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3459966885 Aug 19 04:35:34 PM PDT 24 Aug 19 04:35:37 PM PDT 24 834603832 ps
T1293 /workspace/coverage/cover_reg_top/5.uart_csr_rw.58769149 Aug 19 04:35:41 PM PDT 24 Aug 19 04:35:42 PM PDT 24 132354680 ps
T1294 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1221192191 Aug 19 04:35:38 PM PDT 24 Aug 19 04:35:40 PM PDT 24 43150216 ps
T1295 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1848689811 Aug 19 04:35:47 PM PDT 24 Aug 19 04:35:48 PM PDT 24 272386565 ps
T1296 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3867415392 Aug 19 04:35:31 PM PDT 24 Aug 19 04:35:32 PM PDT 24 25383036 ps
T1297 /workspace/coverage/cover_reg_top/40.uart_intr_test.680158103 Aug 19 04:36:03 PM PDT 24 Aug 19 04:36:03 PM PDT 24 13668667 ps
T1298 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1304793499 Aug 19 04:35:32 PM PDT 24 Aug 19 04:35:44 PM PDT 24 137184955 ps
T1299 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2387609880 Aug 19 04:35:32 PM PDT 24 Aug 19 04:35:34 PM PDT 24 239822756 ps
T1300 /workspace/coverage/cover_reg_top/13.uart_intr_test.1914369180 Aug 19 04:36:04 PM PDT 24 Aug 19 04:36:04 PM PDT 24 28380838 ps
T1301 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1705562872 Aug 19 04:35:34 PM PDT 24 Aug 19 04:35:35 PM PDT 24 75530400 ps
T1302 /workspace/coverage/cover_reg_top/17.uart_intr_test.1140232892 Aug 19 04:35:53 PM PDT 24 Aug 19 04:35:59 PM PDT 24 13782995 ps
T1303 /workspace/coverage/cover_reg_top/9.uart_intr_test.2994344516 Aug 19 04:36:00 PM PDT 24 Aug 19 04:36:02 PM PDT 24 48734179 ps
T1304 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3484107078 Aug 19 04:35:36 PM PDT 24 Aug 19 04:35:37 PM PDT 24 68972892 ps
T1305 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1876215320 Aug 19 04:35:38 PM PDT 24 Aug 19 04:35:39 PM PDT 24 144552999 ps
T1306 /workspace/coverage/cover_reg_top/5.uart_intr_test.138559809 Aug 19 04:35:47 PM PDT 24 Aug 19 04:35:47 PM PDT 24 14765249 ps
T1307 /workspace/coverage/cover_reg_top/38.uart_intr_test.1296829852 Aug 19 04:36:15 PM PDT 24 Aug 19 04:36:16 PM PDT 24 11653192 ps
T1308 /workspace/coverage/cover_reg_top/49.uart_intr_test.2000401887 Aug 19 04:36:11 PM PDT 24 Aug 19 04:36:12 PM PDT 24 16336586 ps
T60 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3578397434 Aug 19 04:35:46 PM PDT 24 Aug 19 04:35:52 PM PDT 24 50972930 ps
T1309 /workspace/coverage/cover_reg_top/43.uart_intr_test.356135601 Aug 19 04:36:09 PM PDT 24 Aug 19 04:36:09 PM PDT 24 16123649 ps
T1310 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1532734841 Aug 19 04:35:47 PM PDT 24 Aug 19 04:35:48 PM PDT 24 18364798 ps
T1311 /workspace/coverage/cover_reg_top/6.uart_intr_test.670056430 Aug 19 04:35:27 PM PDT 24 Aug 19 04:35:31 PM PDT 24 14975194 ps
T1312 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.181371711 Aug 19 04:35:31 PM PDT 24 Aug 19 04:35:32 PM PDT 24 320104682 ps
T1313 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2498392782 Aug 19 04:35:36 PM PDT 24 Aug 19 04:35:37 PM PDT 24 298117341 ps
T1314 /workspace/coverage/cover_reg_top/24.uart_intr_test.3202224965 Aug 19 04:35:59 PM PDT 24 Aug 19 04:36:00 PM PDT 24 12134384 ps
T1315 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1453959715 Aug 19 04:35:51 PM PDT 24 Aug 19 04:35:51 PM PDT 24 323605418 ps

Test location /workspace/coverage/default/6.uart_stress_all.82678569
Short name T1
Test name
Test status
Simulation time 367561965984 ps
CPU time 812.84 seconds
Started Aug 19 06:05:21 PM PDT 24
Finished Aug 19 06:18:54 PM PDT 24
Peak memory 209320 kb
Host smart-0a3971ac-ac49-4654-9186-655aa4a19407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82678569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.82678569
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all.112129526
Short name T102
Test name
Test status
Simulation time 323145932101 ps
CPU time 619.06 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:16:20 PM PDT 24
Peak memory 211984 kb
Host smart-4c5a41d4-966e-4429-b78c-20b4f8c07361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112129526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.112129526
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3590349587
Short name T32
Test name
Test status
Simulation time 10044521102 ps
CPU time 50.75 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:09:23 PM PDT 24
Peak memory 210116 kb
Host smart-c6ca5a47-dc59-4ca9-bd1a-ca01cc81b180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590349587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3590349587
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.19420620
Short name T176
Test name
Test status
Simulation time 449739985763 ps
CPU time 459.42 seconds
Started Aug 19 06:05:03 PM PDT 24
Finished Aug 19 06:12:43 PM PDT 24
Peak memory 217296 kb
Host smart-38496edd-d1c3-4b0c-a745-7d5dd3c49160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.19420620
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all.1080813525
Short name T98
Test name
Test status
Simulation time 309486276960 ps
CPU time 143.38 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:08:03 PM PDT 24
Peak memory 200924 kb
Host smart-d0c2d62c-fb0b-41d2-984e-396ad780e413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080813525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1080813525
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all.2163353384
Short name T16
Test name
Test status
Simulation time 451154473762 ps
CPU time 716.1 seconds
Started Aug 19 06:06:38 PM PDT 24
Finished Aug 19 06:18:35 PM PDT 24
Peak memory 200900 kb
Host smart-beb1ccde-7d9b-4af3-8f3d-1dc3bc7efc02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163353384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2163353384
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2306119753
Short name T217
Test name
Test status
Simulation time 105605472149 ps
CPU time 100.7 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:10:00 PM PDT 24
Peak memory 200976 kb
Host smart-5bafb288-3b8c-4bb5-a205-4115fd266dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306119753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2306119753
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2915105206
Short name T26
Test name
Test status
Simulation time 126809427 ps
CPU time 0.74 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:05:02 PM PDT 24
Peak memory 218944 kb
Host smart-0fef46bc-d1a2-463a-996c-6b09eaddcac8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915105206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2915105206
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/24.uart_stress_all.3851109488
Short name T85
Test name
Test status
Simulation time 256568391820 ps
CPU time 1019.08 seconds
Started Aug 19 06:06:34 PM PDT 24
Finished Aug 19 06:23:34 PM PDT 24
Peak memory 200948 kb
Host smart-aea402aa-8c49-49db-b1e2-1c59fe91caeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851109488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3851109488
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_perf.2650433349
Short name T254
Test name
Test status
Simulation time 32104933284 ps
CPU time 1533.05 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:31:11 PM PDT 24
Peak memory 201008 kb
Host smart-b1890be7-b9ca-48c7-89ca-846568e8c663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650433349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2650433349
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3920472823
Short name T178
Test name
Test status
Simulation time 230228498717 ps
CPU time 40.09 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:06:07 PM PDT 24
Peak memory 200908 kb
Host smart-4eebf3c1-702d-4bde-8a36-3544f311e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920472823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3920472823
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.711376663
Short name T29
Test name
Test status
Simulation time 28924764007 ps
CPU time 18.29 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:40 PM PDT 24
Peak memory 211184 kb
Host smart-ed6adf90-06ff-427f-8d3f-54f9f0796f45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711376663 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.711376663
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1809766619
Short name T54
Test name
Test status
Simulation time 500865506 ps
CPU time 0.77 seconds
Started Aug 19 04:35:30 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 196484 kb
Host smart-a1a60c0e-9d1f-41ae-910b-0cf36256e21c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809766619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1809766619
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/default/12.uart_intr.3165459401
Short name T303
Test name
Test status
Simulation time 46984087141 ps
CPU time 20.37 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:05:59 PM PDT 24
Peak memory 200960 kb
Host smart-205b679b-d824-408e-96f7-bbb2e8a46c40
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165459401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3165459401
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/43.uart_perf.2257211484
Short name T244
Test name
Test status
Simulation time 20155239393 ps
CPU time 214.87 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:11:12 PM PDT 24
Peak memory 200956 kb
Host smart-b48bf76a-3a6f-495a-9cad-06db461291af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257211484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2257211484
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1739956456
Short name T240
Test name
Test status
Simulation time 157443268419 ps
CPU time 327.89 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:13:04 PM PDT 24
Peak memory 200976 kb
Host smart-92fa3bc4-74c6-4f7d-982b-d00cbaa972ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739956456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1739956456
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1155705412
Short name T96
Test name
Test status
Simulation time 104404760734 ps
CPU time 190.98 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:08:50 PM PDT 24
Peak memory 200968 kb
Host smart-6625b805-86c3-44e1-a4dd-33f7fb100b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155705412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1155705412
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.758094298
Short name T37
Test name
Test status
Simulation time 237476662801 ps
CPU time 236.43 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:10:04 PM PDT 24
Peak memory 200980 kb
Host smart-d4750322-77e7-48ae-aaa5-c8d7ee10760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758094298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.758094298
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_stress_all.2309154449
Short name T272
Test name
Test status
Simulation time 206983673960 ps
CPU time 885.58 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:20:47 PM PDT 24
Peak memory 200952 kb
Host smart-05a066de-c933-481f-af90-6583b1ee9fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309154449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2309154449
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2158982758
Short name T74
Test name
Test status
Simulation time 67609057 ps
CPU time 1.33 seconds
Started Aug 19 04:36:00 PM PDT 24
Finished Aug 19 04:36:02 PM PDT 24
Peak memory 199832 kb
Host smart-0e2a8ace-839d-4525-987f-536998050e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158982758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2158982758
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2623782513
Short name T118
Test name
Test status
Simulation time 35825095410 ps
CPU time 61.14 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:08:08 PM PDT 24
Peak memory 200920 kb
Host smart-227455a5-1f77-481d-a681-c6d7768eaa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623782513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2623782513
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_alert_test.1194521700
Short name T341
Test name
Test status
Simulation time 24671548 ps
CPU time 0.54 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:05:41 PM PDT 24
Peak memory 195712 kb
Host smart-e9ccf5cd-a36d-46a5-92d1-06889627b51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194521700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1194521700
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.665921069
Short name T146
Test name
Test status
Simulation time 49271249117 ps
CPU time 23.5 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:09:22 PM PDT 24
Peak memory 200956 kb
Host smart-aab361e7-f0bb-4f98-8876-bc1bc9bbb566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665921069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.665921069
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2763078935
Short name T117
Test name
Test status
Simulation time 73830634713 ps
CPU time 31.75 seconds
Started Aug 19 06:09:29 PM PDT 24
Finished Aug 19 06:10:01 PM PDT 24
Peak memory 200932 kb
Host smart-e7daa441-5509-460b-89ea-f43953730062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763078935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2763078935
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_tx_rx.196519694
Short name T108
Test name
Test status
Simulation time 52486356932 ps
CPU time 26.41 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:06:17 PM PDT 24
Peak memory 200940 kb
Host smart-8bb57d99-6ed8-4c5c-a9e0-8636184b5b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196519694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.196519694
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2023621059
Short name T360
Test name
Test status
Simulation time 92489417030 ps
CPU time 550.49 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:14:12 PM PDT 24
Peak memory 200936 kb
Host smart-0cc7b6ed-8daa-4bb2-8dac-0e3517b9bff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023621059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2023621059
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.553114181
Short name T167
Test name
Test status
Simulation time 95344420005 ps
CPU time 130.89 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:11:32 PM PDT 24
Peak memory 200880 kb
Host smart-cab8fd8e-305c-44e3-8b39-c7e7e315c91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553114181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.553114181
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1637909057
Short name T110
Test name
Test status
Simulation time 115347831816 ps
CPU time 177.62 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:11:30 PM PDT 24
Peak memory 200984 kb
Host smart-23fd19fe-f125-49f4-9eb5-0961a803d3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637909057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1637909057
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3409346346
Short name T53
Test name
Test status
Simulation time 14224613 ps
CPU time 0.59 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 195652 kb
Host smart-e0cb8471-6a1b-464f-82fa-2a7df258dd07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409346346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3409346346
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3669547373
Short name T33
Test name
Test status
Simulation time 7317159981 ps
CPU time 50.8 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:06:43 PM PDT 24
Peak memory 217560 kb
Host smart-95376f51-db0a-4e11-86ef-49a9738d5b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669547373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3669547373
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1115616120
Short name T132
Test name
Test status
Simulation time 82503907619 ps
CPU time 137.55 seconds
Started Aug 19 06:07:19 PM PDT 24
Finished Aug 19 06:09:36 PM PDT 24
Peak memory 200952 kb
Host smart-c5cd7a8d-f8e3-4f4b-8f48-292b4c5d9c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115616120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1115616120
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_perf.1504656223
Short name T86
Test name
Test status
Simulation time 26332762870 ps
CPU time 72.81 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:07:05 PM PDT 24
Peak memory 200948 kb
Host smart-f7257525-e8d9-420e-920a-6406b00dac96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504656223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1504656223
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3187973891
Short name T109
Test name
Test status
Simulation time 100528444706 ps
CPU time 165.74 seconds
Started Aug 19 06:08:50 PM PDT 24
Finished Aug 19 06:11:36 PM PDT 24
Peak memory 200988 kb
Host smart-bab618ca-02cf-4de6-bd23-03124c1c8336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187973891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3187973891
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2449771636
Short name T123
Test name
Test status
Simulation time 215588595880 ps
CPU time 44.84 seconds
Started Aug 19 06:06:06 PM PDT 24
Finished Aug 19 06:06:51 PM PDT 24
Peak memory 201084 kb
Host smart-c25d155d-7751-4b43-9bef-2767c46b824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449771636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2449771636
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2826698845
Short name T253
Test name
Test status
Simulation time 160144790522 ps
CPU time 74.51 seconds
Started Aug 19 06:08:00 PM PDT 24
Finished Aug 19 06:09:14 PM PDT 24
Peak memory 200944 kb
Host smart-72279fa3-ba76-43db-a268-14680e67a063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826698845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2826698845
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_stress_all.3055436791
Short name T158
Test name
Test status
Simulation time 244684264720 ps
CPU time 428.88 seconds
Started Aug 19 06:08:07 PM PDT 24
Finished Aug 19 06:15:16 PM PDT 24
Peak memory 201000 kb
Host smart-e80188b8-a781-4b73-9794-1de3fe4502c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055436791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3055436791
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2683866888
Short name T170
Test name
Test status
Simulation time 32229692434 ps
CPU time 16.64 seconds
Started Aug 19 06:05:00 PM PDT 24
Finished Aug 19 06:05:16 PM PDT 24
Peak memory 200968 kb
Host smart-75e12c8c-bef5-400b-a399-b2c5e7f13697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683866888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2683866888
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3408574329
Short name T87
Test name
Test status
Simulation time 28827328236 ps
CPU time 33.95 seconds
Started Aug 19 06:09:32 PM PDT 24
Finished Aug 19 06:10:06 PM PDT 24
Peak memory 200948 kb
Host smart-0dc87f19-e828-4268-8ea5-a1cb35ac2888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408574329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3408574329
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all.2747495100
Short name T149
Test name
Test status
Simulation time 244953096712 ps
CPU time 248.24 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:11:35 PM PDT 24
Peak memory 200980 kb
Host smart-174cd390-4a9e-4234-8f7a-887ea3eb6d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747495100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2747495100
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1297192165
Short name T77
Test name
Test status
Simulation time 160141334 ps
CPU time 0.94 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 198908 kb
Host smart-8a5057c0-0c31-4bc2-97c1-e3847896f4fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297192165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1297192165
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3807153009
Short name T439
Test name
Test status
Simulation time 14732518320 ps
CPU time 51.72 seconds
Started Aug 19 06:07:18 PM PDT 24
Finished Aug 19 06:08:10 PM PDT 24
Peak memory 217636 kb
Host smart-4943f276-65e9-464c-8b3a-051c1ecfbed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807153009 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3807153009
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2936178176
Short name T10
Test name
Test status
Simulation time 160440714434 ps
CPU time 119.04 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:10:31 PM PDT 24
Peak memory 200912 kb
Host smart-124e7879-4d5c-44e1-ae69-f6e7ed328baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936178176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2936178176
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1979138956
Short name T273
Test name
Test status
Simulation time 110866430959 ps
CPU time 17.53 seconds
Started Aug 19 06:08:50 PM PDT 24
Finished Aug 19 06:09:07 PM PDT 24
Peak memory 200824 kb
Host smart-00b50d77-b7e6-4186-b4de-b2f6109e3953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979138956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1979138956
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.792598530
Short name T308
Test name
Test status
Simulation time 15777415313 ps
CPU time 39.65 seconds
Started Aug 19 06:08:21 PM PDT 24
Finished Aug 19 06:09:01 PM PDT 24
Peak memory 217324 kb
Host smart-8f35f145-302a-46f4-9006-bcbdc8eb961c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792598530 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.792598530
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.2396977357
Short name T104
Test name
Test status
Simulation time 320723862749 ps
CPU time 429.59 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:12:10 PM PDT 24
Peak memory 200916 kb
Host smart-6c71ff60-380c-4e85-9915-654e8236b162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396977357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2396977357
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2442243919
Short name T194
Test name
Test status
Simulation time 51980834549 ps
CPU time 46.17 seconds
Started Aug 19 06:08:57 PM PDT 24
Finished Aug 19 06:09:43 PM PDT 24
Peak memory 200936 kb
Host smart-cf78567b-748c-4bce-81b0-bbf2fc3ddbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442243919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2442243919
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1640122253
Short name T177
Test name
Test status
Simulation time 68039123945 ps
CPU time 40.71 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:09:22 PM PDT 24
Peak memory 200996 kb
Host smart-6b500d04-2e87-4eaf-9edd-d97121f86f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640122253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1640122253
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3142755318
Short name T229
Test name
Test status
Simulation time 117901240954 ps
CPU time 51.97 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:09:33 PM PDT 24
Peak memory 200968 kb
Host smart-66a9d9c3-dde4-483f-996b-6b84456b81b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142755318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3142755318
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.186696560
Short name T214
Test name
Test status
Simulation time 36584325454 ps
CPU time 54.09 seconds
Started Aug 19 06:09:01 PM PDT 24
Finished Aug 19 06:09:55 PM PDT 24
Peak memory 200992 kb
Host smart-fb9f9b86-dcb4-439c-9649-a03ee6539d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186696560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.186696560
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2255301049
Short name T148
Test name
Test status
Simulation time 37674313529 ps
CPU time 28.96 seconds
Started Aug 19 06:09:11 PM PDT 24
Finished Aug 19 06:09:41 PM PDT 24
Peak memory 200728 kb
Host smart-13208be0-617b-4976-bb2d-32e7414b1269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255301049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2255301049
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3939341142
Short name T202
Test name
Test status
Simulation time 25096115461 ps
CPU time 48.37 seconds
Started Aug 19 06:09:15 PM PDT 24
Finished Aug 19 06:10:03 PM PDT 24
Peak memory 200940 kb
Host smart-c58e7a85-babc-47ea-94c5-2ac54f700385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939341142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3939341142
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2692860667
Short name T159
Test name
Test status
Simulation time 135097967501 ps
CPU time 14.93 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:34 PM PDT 24
Peak memory 200860 kb
Host smart-569e60cb-f378-45ea-b10d-666296d64753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692860667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2692860667
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.1429837370
Short name T536
Test name
Test status
Simulation time 488114554614 ps
CPU time 212.52 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:09:01 PM PDT 24
Peak memory 209388 kb
Host smart-8522ff9b-9a5e-41f9-80d9-877b3df3cb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429837370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1429837370
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4052031600
Short name T216
Test name
Test status
Simulation time 82300476604 ps
CPU time 30.19 seconds
Started Aug 19 06:08:50 PM PDT 24
Finished Aug 19 06:09:20 PM PDT 24
Peak memory 200960 kb
Host smart-51409ede-dc29-490e-9bc2-9cc3ad7aa38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052031600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4052031600
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_perf.841038538
Short name T251
Test name
Test status
Simulation time 8698630016 ps
CPU time 308.41 seconds
Started Aug 19 06:06:04 PM PDT 24
Finished Aug 19 06:11:13 PM PDT 24
Peak memory 200992 kb
Host smart-fd11972a-817a-440b-b1cb-12965ef6fb90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841038538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.841038538
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1273362617
Short name T169
Test name
Test status
Simulation time 238941590667 ps
CPU time 36.88 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:06:44 PM PDT 24
Peak memory 200880 kb
Host smart-9c85c76c-eab9-4452-b01d-44383d16e402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273362617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1273362617
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1451761899
Short name T419
Test name
Test status
Simulation time 84097946150 ps
CPU time 85.81 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:07:33 PM PDT 24
Peak memory 200972 kb
Host smart-3b8f136f-f87b-423a-a35b-d4f48e378221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451761899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1451761899
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.992136774
Short name T163
Test name
Test status
Simulation time 124130034112 ps
CPU time 225.68 seconds
Started Aug 19 06:06:23 PM PDT 24
Finished Aug 19 06:10:09 PM PDT 24
Peak memory 200984 kb
Host smart-53817263-eac6-42eb-a041-75ce7951fe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992136774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.992136774
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.666705354
Short name T230
Test name
Test status
Simulation time 178505292157 ps
CPU time 17.82 seconds
Started Aug 19 06:09:20 PM PDT 24
Finished Aug 19 06:09:38 PM PDT 24
Peak memory 200968 kb
Host smart-04ae3c9d-e5e7-4fcc-8061-6b444eec011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666705354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.666705354
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_noise_filter.4000616079
Short name T270
Test name
Test status
Simulation time 94852861137 ps
CPU time 242.17 seconds
Started Aug 19 06:06:31 PM PDT 24
Finished Aug 19 06:10:33 PM PDT 24
Peak memory 201164 kb
Host smart-c323067e-61ff-4ae2-afae-0bbe380114ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000616079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4000616079
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2870628461
Short name T165
Test name
Test status
Simulation time 87134781961 ps
CPU time 28.39 seconds
Started Aug 19 06:07:24 PM PDT 24
Finished Aug 19 06:07:53 PM PDT 24
Peak memory 200944 kb
Host smart-8de187f0-7bc5-474f-a52b-6a5dd8dbe896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870628461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2870628461
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4204105553
Short name T223
Test name
Test status
Simulation time 31353559026 ps
CPU time 37.48 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:08:57 PM PDT 24
Peak memory 200924 kb
Host smart-b63933ab-004d-4447-8385-e0e208e45b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204105553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4204105553
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.226813245
Short name T73
Test name
Test status
Simulation time 316106255 ps
CPU time 0.87 seconds
Started Aug 19 04:35:31 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 199108 kb
Host smart-254febaf-ae2a-4e13-9a38-304a2a016554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226813245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.226813245
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.986836838
Short name T186
Test name
Test status
Simulation time 78169281112 ps
CPU time 64.77 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:05:59 PM PDT 24
Peak memory 200928 kb
Host smart-e93a4fa5-fd87-4816-a62f-57ea78ccd2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986836838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.986836838
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2014191676
Short name T115
Test name
Test status
Simulation time 19546231538 ps
CPU time 14.38 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:05:08 PM PDT 24
Peak memory 200612 kb
Host smart-301251ed-6e19-40c5-9a68-b6650c070a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014191676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2014191676
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.349740242
Short name T1094
Test name
Test status
Simulation time 92012734863 ps
CPU time 54.11 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:09:36 PM PDT 24
Peak memory 201000 kb
Host smart-d80ea8cd-8ede-468d-8bfe-c204e9c68ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349740242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.349740242
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.919692750
Short name T210
Test name
Test status
Simulation time 220507059710 ps
CPU time 25.15 seconds
Started Aug 19 06:08:52 PM PDT 24
Finished Aug 19 06:09:17 PM PDT 24
Peak memory 200972 kb
Host smart-7b1c5ea5-bbce-478e-9cc9-03c76ccaea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919692750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.919692750
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2238657702
Short name T757
Test name
Test status
Simulation time 15311051047 ps
CPU time 36.31 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:09:19 PM PDT 24
Peak memory 200920 kb
Host smart-40fdc2c3-91e2-4eb6-9034-e3ea2b1c6760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238657702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2238657702
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.106137445
Short name T986
Test name
Test status
Simulation time 91281502031 ps
CPU time 188.94 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:11:57 PM PDT 24
Peak memory 200976 kb
Host smart-5f53eed9-f8aa-4fdf-bb57-9bdefb07529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106137445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.106137445
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2524554369
Short name T205
Test name
Test status
Simulation time 11226507881 ps
CPU time 21.03 seconds
Started Aug 19 06:05:51 PM PDT 24
Finished Aug 19 06:06:12 PM PDT 24
Peak memory 200952 kb
Host smart-9f31bc7b-cd51-4b47-b3ff-1086b9db7f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524554369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2524554369
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2928119586
Short name T211
Test name
Test status
Simulation time 125282673371 ps
CPU time 111.09 seconds
Started Aug 19 06:08:46 PM PDT 24
Finished Aug 19 06:10:37 PM PDT 24
Peak memory 200928 kb
Host smart-cd6bd375-05a7-4d65-a7d9-f8776eea4cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928119586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2928119586
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3558139364
Short name T235
Test name
Test status
Simulation time 66015005940 ps
CPU time 111.25 seconds
Started Aug 19 06:08:46 PM PDT 24
Finished Aug 19 06:10:37 PM PDT 24
Peak memory 200948 kb
Host smart-3d86b85d-c011-4f38-9a15-9d1782e806d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558139364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3558139364
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3705305937
Short name T191
Test name
Test status
Simulation time 111624928277 ps
CPU time 212.59 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:12:31 PM PDT 24
Peak memory 201008 kb
Host smart-9e913340-6e82-4355-b63f-b5af6c00d31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705305937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3705305937
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.184185931
Short name T225
Test name
Test status
Simulation time 37745468145 ps
CPU time 27.89 seconds
Started Aug 19 06:09:19 PM PDT 24
Finished Aug 19 06:09:47 PM PDT 24
Peak memory 200984 kb
Host smart-fdb0fa46-6d67-4a41-a16e-efbe87eccd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184185931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.184185931
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3796359011
Short name T442
Test name
Test status
Simulation time 4778575248 ps
CPU time 53.15 seconds
Started Aug 19 06:06:29 PM PDT 24
Finished Aug 19 06:07:23 PM PDT 24
Peak memory 209412 kb
Host smart-6921d5ff-cebb-44df-abaa-d4121a44a327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796359011 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3796359011
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.92127415
Short name T188
Test name
Test status
Simulation time 70088341331 ps
CPU time 80.35 seconds
Started Aug 19 06:09:22 PM PDT 24
Finished Aug 19 06:10:42 PM PDT 24
Peak memory 200884 kb
Host smart-0a0f9a29-0a54-4528-98e2-24f985ccce73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92127415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.92127415
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3758177481
Short name T226
Test name
Test status
Simulation time 229787880174 ps
CPU time 289.93 seconds
Started Aug 19 06:09:30 PM PDT 24
Finished Aug 19 06:14:20 PM PDT 24
Peak memory 200976 kb
Host smart-017c7ad1-59b3-4a26-8a53-24e46bff2c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758177481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3758177481
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.600787338
Short name T236
Test name
Test status
Simulation time 19587058460 ps
CPU time 38.67 seconds
Started Aug 19 06:09:34 PM PDT 24
Finished Aug 19 06:10:13 PM PDT 24
Peak memory 200908 kb
Host smart-77a1af28-8074-471b-8bea-eb1657bdbb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600787338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.600787338
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3819263150
Short name T224
Test name
Test status
Simulation time 26425830394 ps
CPU time 11.86 seconds
Started Aug 19 06:08:10 PM PDT 24
Finished Aug 19 06:08:22 PM PDT 24
Peak memory 200976 kb
Host smart-32d37f99-151e-4654-8b65-c35faec1ef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819263150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3819263150
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4202437951
Short name T215
Test name
Test status
Simulation time 18103034066 ps
CPU time 26.24 seconds
Started Aug 19 06:08:23 PM PDT 24
Finished Aug 19 06:08:49 PM PDT 24
Peak memory 200980 kb
Host smart-dcad217a-8de6-482d-8c3e-64646ede2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202437951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4202437951
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3581877188
Short name T56
Test name
Test status
Simulation time 112868095 ps
CPU time 0.82 seconds
Started Aug 19 04:35:54 PM PDT 24
Finished Aug 19 04:35:55 PM PDT 24
Peak memory 196420 kb
Host smart-440b7af2-ba60-404a-9a56-bcc5c46e0eec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581877188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3581877188
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2149721059
Short name T1228
Test name
Test status
Simulation time 218527051 ps
CPU time 1.52 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:40 PM PDT 24
Peak memory 198240 kb
Host smart-60bd56fb-b085-436d-907d-54c66c1ad4e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149721059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2149721059
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3778005138
Short name T52
Test name
Test status
Simulation time 1048994033 ps
CPU time 1.23 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:39 PM PDT 24
Peak memory 195580 kb
Host smart-11834b55-620c-4522-8b13-fb16d27b1081
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778005138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3778005138
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.935840727
Short name T1243
Test name
Test status
Simulation time 47941461 ps
CPU time 0.76 seconds
Started Aug 19 04:35:40 PM PDT 24
Finished Aug 19 04:35:41 PM PDT 24
Peak memory 199520 kb
Host smart-d4ba7bd5-a21a-408b-aec2-3f5d8de4c922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935840727 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.935840727
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2882951255
Short name T1191
Test name
Test status
Simulation time 21259411 ps
CPU time 0.6 seconds
Started Aug 19 04:35:55 PM PDT 24
Finished Aug 19 04:35:56 PM PDT 24
Peak memory 195592 kb
Host smart-8caaae77-0af6-4d51-8928-3643fad01d28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882951255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2882951255
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3410534633
Short name T1257
Test name
Test status
Simulation time 79858607 ps
CPU time 0.58 seconds
Started Aug 19 04:35:45 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 194580 kb
Host smart-58cf9063-bcab-4322-8c8b-63874ec21520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410534633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3410534633
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.620803795
Short name T1240
Test name
Test status
Simulation time 44475666 ps
CPU time 0.67 seconds
Started Aug 19 04:36:06 PM PDT 24
Finished Aug 19 04:36:07 PM PDT 24
Peak memory 195080 kb
Host smart-3534615b-c322-4784-bc2b-7fe7981cc46a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620803795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.620803795
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2387609880
Short name T1299
Test name
Test status
Simulation time 239822756 ps
CPU time 2.04 seconds
Started Aug 19 04:35:32 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 200196 kb
Host smart-01bc211a-37c0-4213-8299-efedf1358035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387609880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2387609880
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3503352661
Short name T1213
Test name
Test status
Simulation time 66078285 ps
CPU time 0.98 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 199172 kb
Host smart-7b01885f-1f27-4802-96c1-cb5fdc9884b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503352661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3503352661
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2658630123
Short name T1232
Test name
Test status
Simulation time 32968306 ps
CPU time 0.8 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 196332 kb
Host smart-027aeb51-9af4-4b8e-a8a8-5333c45d4977
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658630123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2658630123
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2910988412
Short name T1193
Test name
Test status
Simulation time 67961428 ps
CPU time 1.36 seconds
Started Aug 19 04:35:24 PM PDT 24
Finished Aug 19 04:35:25 PM PDT 24
Peak memory 198040 kb
Host smart-4d2a6ff1-de18-4fa8-8d93-eab553830afc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910988412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2910988412
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.667449943
Short name T1270
Test name
Test status
Simulation time 33381179 ps
CPU time 0.6 seconds
Started Aug 19 04:35:48 PM PDT 24
Finished Aug 19 04:35:49 PM PDT 24
Peak memory 195524 kb
Host smart-2ce078dc-9199-42a6-a71d-c268c77fc7c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667449943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.667449943
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.282575081
Short name T1194
Test name
Test status
Simulation time 121822104 ps
CPU time 0.87 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 200016 kb
Host smart-195887bc-7042-4a7f-bc6d-72ff13e37119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282575081 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.282575081
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1347505414
Short name T1280
Test name
Test status
Simulation time 16784263 ps
CPU time 0.62 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 195584 kb
Host smart-bf6beea8-acf7-4e10-a713-a5a5d62325bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347505414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1347505414
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2560044719
Short name T1271
Test name
Test status
Simulation time 52846521 ps
CPU time 0.6 seconds
Started Aug 19 04:35:41 PM PDT 24
Finished Aug 19 04:35:41 PM PDT 24
Peak memory 194572 kb
Host smart-147ae02a-49e0-4f8d-b6c0-a3a85735d7b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560044719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2560044719
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3865751035
Short name T1230
Test name
Test status
Simulation time 98719179 ps
CPU time 0.75 seconds
Started Aug 19 04:35:49 PM PDT 24
Finished Aug 19 04:35:50 PM PDT 24
Peak memory 197084 kb
Host smart-04af3c6e-8d40-4965-adab-79b77b740f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865751035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3865751035
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1750007421
Short name T1203
Test name
Test status
Simulation time 62205796 ps
CPU time 2.14 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:49 PM PDT 24
Peak memory 200132 kb
Host smart-9935ccec-3018-41a6-8c8c-bece99262a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750007421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1750007421
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3555490070
Short name T1206
Test name
Test status
Simulation time 28595430 ps
CPU time 0.75 seconds
Started Aug 19 04:35:37 PM PDT 24
Finished Aug 19 04:35:38 PM PDT 24
Peak memory 199172 kb
Host smart-ca058a3d-b3ea-43c6-bcff-d4f8f1936835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555490070 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3555490070
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2001036843
Short name T1275
Test name
Test status
Simulation time 89932157 ps
CPU time 0.6 seconds
Started Aug 19 04:35:54 PM PDT 24
Finished Aug 19 04:35:54 PM PDT 24
Peak memory 195540 kb
Host smart-45ba4fe3-8def-4611-be61-f9dac502754e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001036843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2001036843
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.771195087
Short name T1285
Test name
Test status
Simulation time 35027524 ps
CPU time 0.55 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 194576 kb
Host smart-d421316c-5505-41bf-8954-627939d8bba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771195087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.771195087
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1215863092
Short name T1254
Test name
Test status
Simulation time 28016314 ps
CPU time 0.64 seconds
Started Aug 19 04:35:42 PM PDT 24
Finished Aug 19 04:35:43 PM PDT 24
Peak memory 194740 kb
Host smart-bbaab45c-7593-40f3-9435-471e0a4d2a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215863092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1215863092
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3411528659
Short name T1265
Test name
Test status
Simulation time 24647200 ps
CPU time 1.16 seconds
Started Aug 19 04:35:41 PM PDT 24
Finished Aug 19 04:35:42 PM PDT 24
Peak memory 200252 kb
Host smart-9512622b-adeb-40cb-9e55-5d95f4a6881e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411528659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3411528659
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1453959715
Short name T1315
Test name
Test status
Simulation time 323605418 ps
CPU time 0.88 seconds
Started Aug 19 04:35:51 PM PDT 24
Finished Aug 19 04:35:51 PM PDT 24
Peak memory 199068 kb
Host smart-0749d61d-c599-4a08-8769-e8591efd8521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453959715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1453959715
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2971628099
Short name T1197
Test name
Test status
Simulation time 79652576 ps
CPU time 0.63 seconds
Started Aug 19 04:35:32 PM PDT 24
Finished Aug 19 04:35:33 PM PDT 24
Peak memory 197532 kb
Host smart-04d77c99-c723-4a15-bb13-e0929a759359
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971628099 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2971628099
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2446133217
Short name T1269
Test name
Test status
Simulation time 21735734 ps
CPU time 0.55 seconds
Started Aug 19 04:35:56 PM PDT 24
Finished Aug 19 04:35:56 PM PDT 24
Peak memory 194524 kb
Host smart-fcddfe9f-c63d-442b-a381-fedb3c59ede7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446133217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2446133217
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.360508756
Short name T1220
Test name
Test status
Simulation time 18572024 ps
CPU time 0.71 seconds
Started Aug 19 04:35:33 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 197388 kb
Host smart-272f7b28-c97e-4fe6-99e3-f37356809b25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360508756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.360508756
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1304793499
Short name T1298
Test name
Test status
Simulation time 137184955 ps
CPU time 1.94 seconds
Started Aug 19 04:35:32 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 200252 kb
Host smart-e5656b74-646d-4d4c-b8a9-b483a4ef9019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304793499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1304793499
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1267571034
Short name T1263
Test name
Test status
Simulation time 177385940 ps
CPU time 0.92 seconds
Started Aug 19 04:35:51 PM PDT 24
Finished Aug 19 04:35:52 PM PDT 24
Peak memory 198704 kb
Host smart-176f5993-b312-4edd-ac70-0e7f35723152
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267571034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1267571034
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3867415392
Short name T1296
Test name
Test status
Simulation time 25383036 ps
CPU time 0.74 seconds
Started Aug 19 04:35:31 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 198492 kb
Host smart-2c3a5d75-fc22-4a3c-9430-b14063d42096
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867415392 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3867415392
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.890238161
Short name T69
Test name
Test status
Simulation time 50125157 ps
CPU time 0.63 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:43 PM PDT 24
Peak memory 195772 kb
Host smart-4016ef88-bd38-4d19-9049-a0b1cc1515d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890238161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.890238161
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.395296777
Short name T1246
Test name
Test status
Simulation time 34167052 ps
CPU time 0.58 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 194580 kb
Host smart-4cade8aa-1477-431c-b479-cfaca6e5bd26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395296777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.395296777
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2792535363
Short name T1279
Test name
Test status
Simulation time 25192468 ps
CPU time 0.67 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:39 PM PDT 24
Peak memory 197724 kb
Host smart-da5edc40-d1df-4b66-848a-62b18e50b688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792535363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2792535363
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3628298109
Short name T1201
Test name
Test status
Simulation time 204660690 ps
CPU time 2.23 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 200240 kb
Host smart-83df7a2d-cf15-41f6-aa13-f391303819ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628298109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3628298109
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3088192059
Short name T76
Test name
Test status
Simulation time 55773837 ps
CPU time 1.02 seconds
Started Aug 19 04:35:48 PM PDT 24
Finished Aug 19 04:35:50 PM PDT 24
Peak memory 199328 kb
Host smart-4dff2967-4ee6-42b3-9da4-ca83841fe756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088192059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3088192059
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4037466719
Short name T1180
Test name
Test status
Simulation time 102326415 ps
CPU time 0.74 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 198496 kb
Host smart-51b6ff44-3f8c-4a55-bacd-f79f12efb5e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037466719 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.4037466719
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.659668974
Short name T61
Test name
Test status
Simulation time 33303449 ps
CPU time 0.59 seconds
Started Aug 19 04:36:03 PM PDT 24
Finished Aug 19 04:36:04 PM PDT 24
Peak memory 195536 kb
Host smart-8862bd47-02da-4ab4-9f30-88932f3e0bb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659668974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.659668974
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1914369180
Short name T1300
Test name
Test status
Simulation time 28380838 ps
CPU time 0.57 seconds
Started Aug 19 04:36:04 PM PDT 24
Finished Aug 19 04:36:04 PM PDT 24
Peak memory 194584 kb
Host smart-9944c8d4-284a-450d-8ad7-730e4161dcf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914369180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1914369180
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.723826088
Short name T63
Test name
Test status
Simulation time 33968317 ps
CPU time 0.78 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 197124 kb
Host smart-1ccbb46e-5cf6-41d8-af49-ef7af2c80a6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723826088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.723826088
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2256163691
Short name T1187
Test name
Test status
Simulation time 468461939 ps
CPU time 1.89 seconds
Started Aug 19 04:36:11 PM PDT 24
Finished Aug 19 04:36:13 PM PDT 24
Peak memory 200268 kb
Host smart-474f530f-4818-4be8-b232-0ffa91bfff7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256163691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2256163691
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1492054658
Short name T239
Test name
Test status
Simulation time 131872797 ps
CPU time 1.14 seconds
Started Aug 19 04:35:57 PM PDT 24
Finished Aug 19 04:35:59 PM PDT 24
Peak memory 199440 kb
Host smart-76db3967-71c7-4620-a386-2e1716433c95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492054658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1492054658
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2601393441
Short name T1250
Test name
Test status
Simulation time 44808359 ps
CPU time 0.74 seconds
Started Aug 19 04:35:59 PM PDT 24
Finished Aug 19 04:36:00 PM PDT 24
Peak memory 199188 kb
Host smart-842eed96-d42d-4061-b221-c87fa8224ce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601393441 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2601393441
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1802198308
Short name T1238
Test name
Test status
Simulation time 13785894 ps
CPU time 0.61 seconds
Started Aug 19 04:35:45 PM PDT 24
Finished Aug 19 04:35:46 PM PDT 24
Peak memory 195556 kb
Host smart-e3dd985f-9511-4b02-924e-8d8ea134bb33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802198308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1802198308
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.998880676
Short name T1235
Test name
Test status
Simulation time 10548028 ps
CPU time 0.57 seconds
Started Aug 19 04:36:01 PM PDT 24
Finished Aug 19 04:36:02 PM PDT 24
Peak memory 194580 kb
Host smart-254d87f6-83b7-47a2-a415-f757ff39b164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998880676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.998880676
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2334563453
Short name T1215
Test name
Test status
Simulation time 21940340 ps
CPU time 0.68 seconds
Started Aug 19 04:36:00 PM PDT 24
Finished Aug 19 04:36:01 PM PDT 24
Peak memory 195768 kb
Host smart-b3497535-7988-4635-b087-39c7ab9f912c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334563453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2334563453
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.131240536
Short name T1289
Test name
Test status
Simulation time 105055338 ps
CPU time 1.18 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 200076 kb
Host smart-85e1b30d-b51c-4958-aad9-d77d3350d81f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131240536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.131240536
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1334476972
Short name T1192
Test name
Test status
Simulation time 79110339 ps
CPU time 0.99 seconds
Started Aug 19 04:35:45 PM PDT 24
Finished Aug 19 04:35:46 PM PDT 24
Peak memory 200008 kb
Host smart-6ae7b957-4eff-4277-960a-4c351940f162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334476972 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1334476972
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3578397434
Short name T60
Test name
Test status
Simulation time 50972930 ps
CPU time 0.58 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:52 PM PDT 24
Peak memory 195428 kb
Host smart-4e70d5c0-14c1-4958-8733-37d9362d89a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578397434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3578397434
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.44668975
Short name T1208
Test name
Test status
Simulation time 37505451 ps
CPU time 0.59 seconds
Started Aug 19 04:35:51 PM PDT 24
Finished Aug 19 04:35:51 PM PDT 24
Peak memory 194556 kb
Host smart-d1625f25-4c84-4e83-91b8-b869c0a23f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44668975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.44668975
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1876215320
Short name T1305
Test name
Test status
Simulation time 144552999 ps
CPU time 0.76 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:39 PM PDT 24
Peak memory 197244 kb
Host smart-4f77c4c7-1005-431b-8a22-ca059ee3787b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876215320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1876215320
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.574104017
Short name T1188
Test name
Test status
Simulation time 39792684 ps
CPU time 1.9 seconds
Started Aug 19 04:36:07 PM PDT 24
Finished Aug 19 04:36:09 PM PDT 24
Peak memory 200264 kb
Host smart-998d52d6-7df0-4c77-a1da-84f45753e98a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574104017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.574104017
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2785784868
Short name T238
Test name
Test status
Simulation time 128116912 ps
CPU time 1.01 seconds
Started Aug 19 04:36:02 PM PDT 24
Finished Aug 19 04:36:03 PM PDT 24
Peak memory 199132 kb
Host smart-e22b9bc0-e971-4d04-b263-2e3b24377ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785784868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2785784868
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2439982421
Short name T1261
Test name
Test status
Simulation time 19526856 ps
CPU time 0.73 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 198236 kb
Host smart-c8fb94fb-c2ec-4579-a08d-209e53d83eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439982421 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2439982421
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4112180899
Short name T1227
Test name
Test status
Simulation time 24266276 ps
CPU time 0.58 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 195544 kb
Host smart-c363b762-0b84-427c-a67d-a7f080e4cd3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112180899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4112180899
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.817351450
Short name T1286
Test name
Test status
Simulation time 18513690 ps
CPU time 0.58 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 194568 kb
Host smart-50cb856c-53fd-4272-b021-79a4e2612cbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817351450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.817351450
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2795885745
Short name T1221
Test name
Test status
Simulation time 51235862 ps
CPU time 0.76 seconds
Started Aug 19 04:36:07 PM PDT 24
Finished Aug 19 04:36:08 PM PDT 24
Peak memory 197228 kb
Host smart-aeebdf23-6f08-41db-ae3c-ef9f1aaea831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795885745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2795885745
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3908148344
Short name T1184
Test name
Test status
Simulation time 57325474 ps
CPU time 1.62 seconds
Started Aug 19 04:36:07 PM PDT 24
Finished Aug 19 04:36:08 PM PDT 24
Peak memory 200072 kb
Host smart-bad80d5f-943c-44f9-839f-5f90a7170f13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908148344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3908148344
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.746194046
Short name T1268
Test name
Test status
Simulation time 688425935 ps
CPU time 1 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:49 PM PDT 24
Peak memory 199252 kb
Host smart-3b78d2b5-2d36-409b-af04-ef83a73c32ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746194046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.746194046
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2435080726
Short name T1205
Test name
Test status
Simulation time 54692184 ps
CPU time 1.33 seconds
Started Aug 19 04:35:53 PM PDT 24
Finished Aug 19 04:35:54 PM PDT 24
Peak memory 200248 kb
Host smart-fcf592cd-a820-496d-bdfc-cc16d9f65ee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435080726 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2435080726
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2679750803
Short name T68
Test name
Test status
Simulation time 32271195 ps
CPU time 0.63 seconds
Started Aug 19 04:35:52 PM PDT 24
Finished Aug 19 04:35:53 PM PDT 24
Peak memory 195660 kb
Host smart-89818b53-0580-4b83-b279-3a146a519203
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679750803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2679750803
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1140232892
Short name T1302
Test name
Test status
Simulation time 13782995 ps
CPU time 0.54 seconds
Started Aug 19 04:35:53 PM PDT 24
Finished Aug 19 04:35:59 PM PDT 24
Peak memory 194536 kb
Host smart-d90bc4e4-2d3f-43a6-aaf6-91c87cb0a5d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140232892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1140232892
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3521512591
Short name T1241
Test name
Test status
Simulation time 33604289 ps
CPU time 0.69 seconds
Started Aug 19 04:35:55 PM PDT 24
Finished Aug 19 04:35:55 PM PDT 24
Peak memory 197716 kb
Host smart-5a47f1c4-3400-4a6a-8152-8ea234aed450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521512591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3521512591
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3305714465
Short name T1236
Test name
Test status
Simulation time 43358930 ps
CPU time 1.16 seconds
Started Aug 19 04:36:03 PM PDT 24
Finished Aug 19 04:36:04 PM PDT 24
Peak memory 200148 kb
Host smart-f46cb0eb-e4e9-47f7-b13c-9f1cd2ddf258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305714465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3305714465
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1848689811
Short name T1295
Test name
Test status
Simulation time 272386565 ps
CPU time 0.95 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 199248 kb
Host smart-c7dd8551-9199-435a-9ac3-34b783156a90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848689811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1848689811
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1532734841
Short name T1310
Test name
Test status
Simulation time 18364798 ps
CPU time 0.75 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 197928 kb
Host smart-8f1e26f9-f770-4712-ac4f-20ecde600837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532734841 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1532734841
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3820481805
Short name T64
Test name
Test status
Simulation time 40719048 ps
CPU time 0.57 seconds
Started Aug 19 04:35:49 PM PDT 24
Finished Aug 19 04:35:49 PM PDT 24
Peak memory 195572 kb
Host smart-c2822d22-095b-4e5a-999d-e140a638c471
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820481805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3820481805
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2568102577
Short name T1224
Test name
Test status
Simulation time 13150898 ps
CPU time 0.57 seconds
Started Aug 19 04:35:42 PM PDT 24
Finished Aug 19 04:35:43 PM PDT 24
Peak memory 194584 kb
Host smart-91b04681-44e0-4825-8f88-37052e9e737a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568102577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2568102577
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2730340243
Short name T1222
Test name
Test status
Simulation time 29421219 ps
CPU time 0.72 seconds
Started Aug 19 04:35:53 PM PDT 24
Finished Aug 19 04:35:54 PM PDT 24
Peak memory 197312 kb
Host smart-ef063948-1a11-4ad5-a8e0-b409468d9f77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730340243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2730340243
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2190964117
Short name T1185
Test name
Test status
Simulation time 124788032 ps
CPU time 1.35 seconds
Started Aug 19 04:35:52 PM PDT 24
Finished Aug 19 04:35:53 PM PDT 24
Peak memory 200240 kb
Host smart-2e4acd6b-a35d-4fa1-be49-ec0b5aaa3ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190964117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2190964117
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2904598884
Short name T1226
Test name
Test status
Simulation time 486839685 ps
CPU time 1.27 seconds
Started Aug 19 04:35:58 PM PDT 24
Finished Aug 19 04:36:00 PM PDT 24
Peak memory 199432 kb
Host smart-c17496be-036f-40c5-a51a-06ae4b744a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904598884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2904598884
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2371815822
Short name T1248
Test name
Test status
Simulation time 17825259 ps
CPU time 0.93 seconds
Started Aug 19 04:35:58 PM PDT 24
Finished Aug 19 04:35:59 PM PDT 24
Peak memory 200000 kb
Host smart-4e1648cd-52d5-4361-ac5a-5dc55195b574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371815822 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2371815822
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.822283964
Short name T1209
Test name
Test status
Simulation time 39286038 ps
CPU time 0.56 seconds
Started Aug 19 04:35:51 PM PDT 24
Finished Aug 19 04:35:51 PM PDT 24
Peak memory 195336 kb
Host smart-fd9af7c7-3c17-499e-9306-699ffa04b753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822283964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.822283964
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2686202298
Short name T1204
Test name
Test status
Simulation time 13248642 ps
CPU time 0.55 seconds
Started Aug 19 04:36:15 PM PDT 24
Finished Aug 19 04:36:16 PM PDT 24
Peak memory 194608 kb
Host smart-d04897e4-28cb-4a86-af06-4452a3f15906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686202298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2686202298
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3236323508
Short name T62
Test name
Test status
Simulation time 110830768 ps
CPU time 0.73 seconds
Started Aug 19 04:36:11 PM PDT 24
Finished Aug 19 04:36:12 PM PDT 24
Peak memory 197204 kb
Host smart-9259c9c0-2884-4645-9ab8-a892cfd52b7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236323508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3236323508
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3271633804
Short name T1229
Test name
Test status
Simulation time 701675266 ps
CPU time 2.65 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:49 PM PDT 24
Peak memory 200244 kb
Host smart-955ff734-c09d-4984-8143-d9ffdea57d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271633804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3271633804
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3264315270
Short name T57
Test name
Test status
Simulation time 19222468 ps
CPU time 0.64 seconds
Started Aug 19 04:35:25 PM PDT 24
Finished Aug 19 04:35:26 PM PDT 24
Peak memory 195156 kb
Host smart-88dd4076-35c8-404b-9ca6-c2ee9a85182a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264315270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3264315270
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1983856160
Short name T1266
Test name
Test status
Simulation time 118140568 ps
CPU time 1.56 seconds
Started Aug 19 04:35:35 PM PDT 24
Finished Aug 19 04:35:36 PM PDT 24
Peak memory 198240 kb
Host smart-8e0b0b59-3536-4ed0-b294-c5e904c4934c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983856160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1983856160
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1806010797
Short name T51
Test name
Test status
Simulation time 45761284 ps
CPU time 0.56 seconds
Started Aug 19 04:35:27 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 195552 kb
Host smart-919899fc-6dc2-4a65-be1f-53bd41dbbbbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806010797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1806010797
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2498392782
Short name T1313
Test name
Test status
Simulation time 298117341 ps
CPU time 0.87 seconds
Started Aug 19 04:35:36 PM PDT 24
Finished Aug 19 04:35:37 PM PDT 24
Peak memory 199900 kb
Host smart-5fa1aa23-1459-4ea7-99e4-bb1b2d0aed23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498392782 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2498392782
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.202111481
Short name T1284
Test name
Test status
Simulation time 18783700 ps
CPU time 0.61 seconds
Started Aug 19 04:35:41 PM PDT 24
Finished Aug 19 04:35:42 PM PDT 24
Peak memory 195520 kb
Host smart-68ee0db4-9e25-45d5-8b56-c7a1cbbbf5c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202111481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.202111481
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2480025224
Short name T1264
Test name
Test status
Simulation time 34999461 ps
CPU time 0.58 seconds
Started Aug 19 04:35:31 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 194600 kb
Host smart-15091731-ba59-44cb-ae02-5791b805b41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480025224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2480025224
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.706052499
Short name T1260
Test name
Test status
Simulation time 17363255 ps
CPU time 0.64 seconds
Started Aug 19 04:35:27 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 194740 kb
Host smart-3b260838-7921-4f03-9f14-9e337d4c9ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706052499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.706052499
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1698350672
Short name T1282
Test name
Test status
Simulation time 196125705 ps
CPU time 1.77 seconds
Started Aug 19 04:35:39 PM PDT 24
Finished Aug 19 04:35:40 PM PDT 24
Peak memory 200176 kb
Host smart-adf4bf7e-2923-4722-a9b4-213324c034f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698350672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1698350672
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4093140097
Short name T71
Test name
Test status
Simulation time 73909361 ps
CPU time 0.93 seconds
Started Aug 19 04:35:45 PM PDT 24
Finished Aug 19 04:35:51 PM PDT 24
Peak memory 199272 kb
Host smart-ce4a35c8-eaee-415b-bf34-7a6df134bbab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093140097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4093140097
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.559416309
Short name T1223
Test name
Test status
Simulation time 137419758 ps
CPU time 0.56 seconds
Started Aug 19 04:35:53 PM PDT 24
Finished Aug 19 04:35:53 PM PDT 24
Peak memory 194576 kb
Host smart-4a57fd11-d5c0-4455-a80f-33ccc1722fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559416309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.559416309
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.261626188
Short name T1237
Test name
Test status
Simulation time 14910778 ps
CPU time 0.66 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 194560 kb
Host smart-6e269e7a-25d7-4b32-b0b8-285aa94c973e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261626188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.261626188
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.4077938062
Short name T1288
Test name
Test status
Simulation time 44719451 ps
CPU time 0.59 seconds
Started Aug 19 04:36:01 PM PDT 24
Finished Aug 19 04:36:02 PM PDT 24
Peak memory 194584 kb
Host smart-f12f0a6c-21f5-47eb-b9cb-cbda26c27ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077938062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.4077938062
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3238754887
Short name T1245
Test name
Test status
Simulation time 24042593 ps
CPU time 0.59 seconds
Started Aug 19 04:35:59 PM PDT 24
Finished Aug 19 04:36:00 PM PDT 24
Peak memory 194552 kb
Host smart-fdcc93da-c847-4af3-a8d9-7e5c352654df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238754887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3238754887
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3202224965
Short name T1314
Test name
Test status
Simulation time 12134384 ps
CPU time 0.54 seconds
Started Aug 19 04:35:59 PM PDT 24
Finished Aug 19 04:36:00 PM PDT 24
Peak memory 194524 kb
Host smart-5c0caab4-406f-4675-9db3-51d937db55bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202224965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3202224965
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3092725336
Short name T1272
Test name
Test status
Simulation time 32569933 ps
CPU time 0.55 seconds
Started Aug 19 04:35:49 PM PDT 24
Finished Aug 19 04:35:50 PM PDT 24
Peak memory 194572 kb
Host smart-9a3ac216-26d6-43d3-8f96-0e8b34744aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092725336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3092725336
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3267013401
Short name T1182
Test name
Test status
Simulation time 32396122 ps
CPU time 0.54 seconds
Started Aug 19 04:35:55 PM PDT 24
Finished Aug 19 04:35:56 PM PDT 24
Peak memory 194540 kb
Host smart-aae7ef7a-19d9-4083-a4bf-fbfb7cd46069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267013401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3267013401
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3349903815
Short name T1195
Test name
Test status
Simulation time 22052345 ps
CPU time 0.57 seconds
Started Aug 19 04:36:03 PM PDT 24
Finished Aug 19 04:36:04 PM PDT 24
Peak memory 194548 kb
Host smart-b5f320c9-3c77-4d21-bb46-abc67363bee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349903815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3349903815
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3169195861
Short name T1256
Test name
Test status
Simulation time 51603114 ps
CPU time 0.57 seconds
Started Aug 19 04:35:57 PM PDT 24
Finished Aug 19 04:35:57 PM PDT 24
Peak memory 194588 kb
Host smart-dae742e4-31a5-4897-ac8f-4ecac069405c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169195861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3169195861
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2682656785
Short name T1234
Test name
Test status
Simulation time 11090519 ps
CPU time 0.59 seconds
Started Aug 19 04:36:00 PM PDT 24
Finished Aug 19 04:36:01 PM PDT 24
Peak memory 194548 kb
Host smart-a6df8e52-a269-411f-8709-d749019e45cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682656785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2682656785
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.423203811
Short name T1189
Test name
Test status
Simulation time 221727349 ps
CPU time 2.23 seconds
Started Aug 19 04:36:04 PM PDT 24
Finished Aug 19 04:36:06 PM PDT 24
Peak memory 197808 kb
Host smart-cee884eb-54fc-45dd-bdd1-8f5207a54148
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423203811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.423203811
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1705562872
Short name T1301
Test name
Test status
Simulation time 75530400 ps
CPU time 0.58 seconds
Started Aug 19 04:35:34 PM PDT 24
Finished Aug 19 04:35:35 PM PDT 24
Peak memory 195544 kb
Host smart-4ad42a24-a6cd-4b03-8bd8-cdb512d4b1b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705562872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1705562872
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4155809253
Short name T1262
Test name
Test status
Simulation time 73339896 ps
CPU time 0.63 seconds
Started Aug 19 04:35:32 PM PDT 24
Finished Aug 19 04:35:38 PM PDT 24
Peak memory 197596 kb
Host smart-adb4c852-786c-4fde-a40c-4bd17e72ee58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155809253 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4155809253
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3568141088
Short name T58
Test name
Test status
Simulation time 209053874 ps
CPU time 0.58 seconds
Started Aug 19 04:35:35 PM PDT 24
Finished Aug 19 04:35:36 PM PDT 24
Peak memory 195532 kb
Host smart-8b6b5311-9d36-402a-b627-07ca632d3ed4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568141088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3568141088
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1206872597
Short name T1278
Test name
Test status
Simulation time 25336405 ps
CPU time 0.57 seconds
Started Aug 19 04:35:41 PM PDT 24
Finished Aug 19 04:35:42 PM PDT 24
Peak memory 194552 kb
Host smart-7853ef53-8692-46ea-9a11-af05507a9d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206872597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1206872597
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.780211501
Short name T1259
Test name
Test status
Simulation time 92706840 ps
CPU time 0.71 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:39 PM PDT 24
Peak memory 195888 kb
Host smart-a3642452-77e2-4e89-ada5-8228d1f8704e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780211501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.780211501
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1051690235
Short name T1258
Test name
Test status
Simulation time 260942156 ps
CPU time 1.37 seconds
Started Aug 19 04:35:26 PM PDT 24
Finished Aug 19 04:35:27 PM PDT 24
Peak memory 200260 kb
Host smart-a6751c11-3dc2-4b01-b940-2f55cce1f503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051690235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1051690235
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.181371711
Short name T1312
Test name
Test status
Simulation time 320104682 ps
CPU time 1 seconds
Started Aug 19 04:35:31 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 198812 kb
Host smart-ebe1de59-e769-4c89-836f-96742d177090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181371711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.181371711
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3182097416
Short name T1253
Test name
Test status
Simulation time 35261967 ps
CPU time 0.57 seconds
Started Aug 19 04:35:53 PM PDT 24
Finished Aug 19 04:35:54 PM PDT 24
Peak memory 194556 kb
Host smart-bc57c795-c145-4a7a-9540-c91ea53ad1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182097416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3182097416
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1891004313
Short name T1214
Test name
Test status
Simulation time 31780976 ps
CPU time 0.58 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:46 PM PDT 24
Peak memory 194588 kb
Host smart-82f60c64-6e6f-4fc8-b1b9-6d2aa766ffe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891004313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1891004313
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1270638063
Short name T1277
Test name
Test status
Simulation time 37149768 ps
CPU time 0.59 seconds
Started Aug 19 04:36:08 PM PDT 24
Finished Aug 19 04:36:09 PM PDT 24
Peak memory 194596 kb
Host smart-4e9242a2-8a44-464b-85dd-6c21b505dff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270638063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1270638063
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2454892852
Short name T1231
Test name
Test status
Simulation time 78460446 ps
CPU time 0.56 seconds
Started Aug 19 04:36:06 PM PDT 24
Finished Aug 19 04:36:06 PM PDT 24
Peak memory 194536 kb
Host smart-27bd9e3c-667c-4de3-9606-852d12f09840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454892852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2454892852
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2828884122
Short name T1251
Test name
Test status
Simulation time 55109682 ps
CPU time 0.57 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 194580 kb
Host smart-745d58ad-a104-45cb-96d7-9d3a5b08c3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828884122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2828884122
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1707554363
Short name T1274
Test name
Test status
Simulation time 101162819 ps
CPU time 0.57 seconds
Started Aug 19 04:36:01 PM PDT 24
Finished Aug 19 04:36:02 PM PDT 24
Peak memory 194536 kb
Host smart-9b24ee2e-00bd-4e47-a83a-86103e84d7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707554363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1707554363
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.297043463
Short name T1225
Test name
Test status
Simulation time 38461404 ps
CPU time 0.57 seconds
Started Aug 19 04:36:00 PM PDT 24
Finished Aug 19 04:36:01 PM PDT 24
Peak memory 194576 kb
Host smart-c2af0da7-67b2-41b5-95ca-388e5f1621eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297043463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.297043463
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.147028064
Short name T1276
Test name
Test status
Simulation time 11781125 ps
CPU time 0.59 seconds
Started Aug 19 04:36:15 PM PDT 24
Finished Aug 19 04:36:16 PM PDT 24
Peak memory 194580 kb
Host smart-bf90ce60-fa00-415d-aa1b-700e3f5b101e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147028064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.147028064
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1296829852
Short name T1307
Test name
Test status
Simulation time 11653192 ps
CPU time 0.6 seconds
Started Aug 19 04:36:15 PM PDT 24
Finished Aug 19 04:36:16 PM PDT 24
Peak memory 194580 kb
Host smart-886aaa32-202f-48d9-8f86-fbc6a13159ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296829852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1296829852
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.42221608
Short name T1202
Test name
Test status
Simulation time 55750758 ps
CPU time 0.54 seconds
Started Aug 19 04:36:07 PM PDT 24
Finished Aug 19 04:36:07 PM PDT 24
Peak memory 194584 kb
Host smart-285cbbd8-12af-4579-86d3-b4b4e64f64ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42221608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.42221608
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1961729279
Short name T1218
Test name
Test status
Simulation time 18404937 ps
CPU time 0.67 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 194848 kb
Host smart-fca2b3b7-6e21-49cd-b2a8-a431c2e27c1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961729279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1961729279
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1172157435
Short name T1196
Test name
Test status
Simulation time 61098880 ps
CPU time 1.43 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:48 PM PDT 24
Peak memory 197912 kb
Host smart-3420b917-2f50-48c1-91c5-038466e9b20e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172157435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1172157435
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1523032881
Short name T1198
Test name
Test status
Simulation time 40086059 ps
CPU time 0.59 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 195548 kb
Host smart-46c11582-7fb5-4a61-80b7-38f1f2d7c87f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523032881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1523032881
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1222542144
Short name T1283
Test name
Test status
Simulation time 73449305 ps
CPU time 1.23 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 200196 kb
Host smart-e38e2f3e-2324-4b76-866c-9018d6c55091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222542144 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1222542144
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1254624786
Short name T59
Test name
Test status
Simulation time 179697207 ps
CPU time 0.6 seconds
Started Aug 19 04:35:31 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 195524 kb
Host smart-73046eb9-df71-416f-8394-40df284c09f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254624786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1254624786
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.232980037
Short name T1216
Test name
Test status
Simulation time 17171521 ps
CPU time 0.59 seconds
Started Aug 19 04:35:31 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 194604 kb
Host smart-a51a2a9f-e5ce-487d-9c56-9535f2a2ddb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232980037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.232980037
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1395994643
Short name T66
Test name
Test status
Simulation time 30793595 ps
CPU time 0.67 seconds
Started Aug 19 04:35:30 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 196624 kb
Host smart-3711b265-c92f-43ea-b83d-3f3dc6034244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395994643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1395994643
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1190051188
Short name T1186
Test name
Test status
Simulation time 63982972 ps
CPU time 1.57 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:46 PM PDT 24
Peak memory 200132 kb
Host smart-3e91ffc6-692d-43ff-82ea-6a79e07f192c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190051188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1190051188
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.545252339
Short name T78
Test name
Test status
Simulation time 265606260 ps
CPU time 1.32 seconds
Started Aug 19 04:35:32 PM PDT 24
Finished Aug 19 04:35:33 PM PDT 24
Peak memory 199676 kb
Host smart-8d56c11c-7778-4226-977b-0a3c2de6def8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545252339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.545252339
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.680158103
Short name T1297
Test name
Test status
Simulation time 13668667 ps
CPU time 0.6 seconds
Started Aug 19 04:36:03 PM PDT 24
Finished Aug 19 04:36:03 PM PDT 24
Peak memory 194576 kb
Host smart-a3d3d113-2652-4483-8e62-f79398570035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680158103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.680158103
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3453986356
Short name T1190
Test name
Test status
Simulation time 13779908 ps
CPU time 0.56 seconds
Started Aug 19 04:35:58 PM PDT 24
Finished Aug 19 04:35:59 PM PDT 24
Peak memory 194480 kb
Host smart-5158135e-169f-4d62-94ee-646ea76594d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453986356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3453986356
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3927993251
Short name T1281
Test name
Test status
Simulation time 32475079 ps
CPU time 0.54 seconds
Started Aug 19 04:36:01 PM PDT 24
Finished Aug 19 04:36:02 PM PDT 24
Peak memory 194572 kb
Host smart-d248c595-7f9b-4e94-8b6e-8670cbcafd54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927993251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3927993251
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.356135601
Short name T1309
Test name
Test status
Simulation time 16123649 ps
CPU time 0.55 seconds
Started Aug 19 04:36:09 PM PDT 24
Finished Aug 19 04:36:09 PM PDT 24
Peak memory 194524 kb
Host smart-7624c927-1357-4016-96d3-8c2e79386ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356135601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.356135601
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.4212578911
Short name T1273
Test name
Test status
Simulation time 24100518 ps
CPU time 0.6 seconds
Started Aug 19 04:36:07 PM PDT 24
Finished Aug 19 04:36:08 PM PDT 24
Peak memory 194600 kb
Host smart-d8e406ae-2fd7-430e-8a6f-492354857d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212578911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.4212578911
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2853563682
Short name T1210
Test name
Test status
Simulation time 27091466 ps
CPU time 0.55 seconds
Started Aug 19 04:36:09 PM PDT 24
Finished Aug 19 04:36:09 PM PDT 24
Peak memory 194572 kb
Host smart-43b856f7-03f1-41d7-84d6-7171a0380022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853563682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2853563682
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2979249123
Short name T1217
Test name
Test status
Simulation time 14484872 ps
CPU time 0.58 seconds
Started Aug 19 04:36:09 PM PDT 24
Finished Aug 19 04:36:09 PM PDT 24
Peak memory 194592 kb
Host smart-e7fe46b9-5d50-4ce7-9209-a0ab5b74fe96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979249123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2979249123
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1279199599
Short name T1290
Test name
Test status
Simulation time 107150577 ps
CPU time 0.56 seconds
Started Aug 19 04:36:04 PM PDT 24
Finished Aug 19 04:36:05 PM PDT 24
Peak memory 194560 kb
Host smart-06c6ab35-faf5-4fa8-9899-3b61a17f9dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279199599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1279199599
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1537294065
Short name T1207
Test name
Test status
Simulation time 16182451 ps
CPU time 0.58 seconds
Started Aug 19 04:35:51 PM PDT 24
Finished Aug 19 04:35:51 PM PDT 24
Peak memory 194560 kb
Host smart-c7ff50e6-9b94-4b2d-8fb2-1d177e04effd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537294065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1537294065
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2000401887
Short name T1308
Test name
Test status
Simulation time 16336586 ps
CPU time 0.61 seconds
Started Aug 19 04:36:11 PM PDT 24
Finished Aug 19 04:36:12 PM PDT 24
Peak memory 194600 kb
Host smart-5f8ae39e-d8bc-4c90-bbdf-7f50baaa9271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000401887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2000401887
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1078980570
Short name T1267
Test name
Test status
Simulation time 80470358 ps
CPU time 0.74 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 198968 kb
Host smart-69f15fb6-67dc-4c84-bc74-4ac166e3815d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078980570 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1078980570
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.58769149
Short name T1293
Test name
Test status
Simulation time 132354680 ps
CPU time 0.6 seconds
Started Aug 19 04:35:41 PM PDT 24
Finished Aug 19 04:35:42 PM PDT 24
Peak memory 195592 kb
Host smart-d75ec44a-998f-41c3-a7d4-e3da3ceefbb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58769149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.58769149
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.138559809
Short name T1306
Test name
Test status
Simulation time 14765249 ps
CPU time 0.54 seconds
Started Aug 19 04:35:47 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 194540 kb
Host smart-97fb400b-214a-48a0-a342-c0d3511ecf7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138559809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.138559809
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4006944309
Short name T1255
Test name
Test status
Simulation time 15560821 ps
CPU time 0.63 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 195828 kb
Host smart-9f601f6b-ccb5-4efe-91bc-f60019227918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006944309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4006944309
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1221192191
Short name T1294
Test name
Test status
Simulation time 43150216 ps
CPU time 1.06 seconds
Started Aug 19 04:35:38 PM PDT 24
Finished Aug 19 04:35:40 PM PDT 24
Peak memory 199988 kb
Host smart-40eb8445-3e28-4950-a491-e75655530c59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221192191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1221192191
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1561318615
Short name T1247
Test name
Test status
Simulation time 226004802 ps
CPU time 1.34 seconds
Started Aug 19 04:35:51 PM PDT 24
Finished Aug 19 04:35:53 PM PDT 24
Peak memory 199532 kb
Host smart-46ac2ff7-d760-4493-9b60-ec997e618f24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561318615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1561318615
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1863805374
Short name T1199
Test name
Test status
Simulation time 51744687 ps
CPU time 0.63 seconds
Started Aug 19 04:35:23 PM PDT 24
Finished Aug 19 04:35:24 PM PDT 24
Peak memory 198312 kb
Host smart-5a5136f0-3122-4c58-8861-b8a4ed66a4c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863805374 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1863805374
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2498449152
Short name T1233
Test name
Test status
Simulation time 22569147 ps
CPU time 0.57 seconds
Started Aug 19 04:35:32 PM PDT 24
Finished Aug 19 04:35:32 PM PDT 24
Peak memory 195540 kb
Host smart-f5d044f1-566b-4021-8be3-d810ed9b89eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498449152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2498449152
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.670056430
Short name T1311
Test name
Test status
Simulation time 14975194 ps
CPU time 0.56 seconds
Started Aug 19 04:35:27 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 194516 kb
Host smart-b74a3a9c-cdb2-4d49-842b-f99635789610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670056430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.670056430
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.567557131
Short name T67
Test name
Test status
Simulation time 30959002 ps
CPU time 0.71 seconds
Started Aug 19 04:35:33 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 197344 kb
Host smart-7cd13706-126d-462c-8112-ce6020453c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567557131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.567557131
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3459966885
Short name T1292
Test name
Test status
Simulation time 834603832 ps
CPU time 2.02 seconds
Started Aug 19 04:35:34 PM PDT 24
Finished Aug 19 04:35:37 PM PDT 24
Peak memory 200276 kb
Host smart-770017a6-7c02-42c2-8670-90e5ac0e2ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459966885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3459966885
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3751224568
Short name T1291
Test name
Test status
Simulation time 88862469 ps
CPU time 0.98 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 199156 kb
Host smart-67ce2297-fe20-4dd2-a001-03b9134f1ae7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751224568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3751224568
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2909145967
Short name T1287
Test name
Test status
Simulation time 23933149 ps
CPU time 0.77 seconds
Started Aug 19 04:35:27 PM PDT 24
Finished Aug 19 04:35:28 PM PDT 24
Peak memory 198968 kb
Host smart-5c8f9de9-cad7-4d0b-b67e-d61730feac22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909145967 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2909145967
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3966322567
Short name T1211
Test name
Test status
Simulation time 13772452 ps
CPU time 0.56 seconds
Started Aug 19 04:35:46 PM PDT 24
Finished Aug 19 04:35:47 PM PDT 24
Peak memory 195532 kb
Host smart-4c5de23e-30f3-4324-b126-872aa9633c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966322567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3966322567
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2189508028
Short name T1181
Test name
Test status
Simulation time 17933037 ps
CPU time 0.57 seconds
Started Aug 19 04:35:50 PM PDT 24
Finished Aug 19 04:35:50 PM PDT 24
Peak memory 194572 kb
Host smart-28d3f968-495b-43ea-9f7d-3ff5cc1bd757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189508028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2189508028
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1076527939
Short name T1244
Test name
Test status
Simulation time 102575305 ps
CPU time 0.77 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 196688 kb
Host smart-cf06c88a-f690-4ae7-9738-f703472c708f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076527939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1076527939
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1729355314
Short name T1249
Test name
Test status
Simulation time 94236263 ps
CPU time 1.21 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:46 PM PDT 24
Peak memory 200236 kb
Host smart-bcc016dc-26bc-43c8-850d-df1aa5aed792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729355314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1729355314
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3484107078
Short name T1304
Test name
Test status
Simulation time 68972892 ps
CPU time 1.26 seconds
Started Aug 19 04:35:36 PM PDT 24
Finished Aug 19 04:35:37 PM PDT 24
Peak memory 199592 kb
Host smart-834e54cc-a30a-47b3-a2a9-896e586d10b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484107078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3484107078
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.911866934
Short name T1183
Test name
Test status
Simulation time 21935753 ps
CPU time 0.69 seconds
Started Aug 19 04:35:30 PM PDT 24
Finished Aug 19 04:35:31 PM PDT 24
Peak memory 198536 kb
Host smart-f658592d-ab39-416d-981e-e97ca35b5161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911866934 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.911866934
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3575134155
Short name T55
Test name
Test status
Simulation time 12873198 ps
CPU time 0.6 seconds
Started Aug 19 04:35:52 PM PDT 24
Finished Aug 19 04:35:53 PM PDT 24
Peak memory 195540 kb
Host smart-c2b6434a-539e-4992-af6b-3c12d3238259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575134155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3575134155
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3620370732
Short name T1212
Test name
Test status
Simulation time 19025151 ps
CPU time 0.52 seconds
Started Aug 19 04:35:30 PM PDT 24
Finished Aug 19 04:35:30 PM PDT 24
Peak memory 194468 kb
Host smart-1d148347-ac78-40de-b0d5-bbb7ff0d0b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620370732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3620370732
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1973681020
Short name T1239
Test name
Test status
Simulation time 52689582 ps
CPU time 0.76 seconds
Started Aug 19 04:35:49 PM PDT 24
Finished Aug 19 04:35:50 PM PDT 24
Peak memory 197228 kb
Host smart-1929d023-f199-42fd-874b-6fef569443bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973681020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1973681020
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3698642680
Short name T1200
Test name
Test status
Simulation time 269146652 ps
CPU time 1.4 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:46 PM PDT 24
Peak memory 199972 kb
Host smart-f923f095-db0a-4fbe-af6b-c8542d8ca224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698642680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3698642680
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.267581023
Short name T72
Test name
Test status
Simulation time 247849681 ps
CPU time 0.9 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:45 PM PDT 24
Peak memory 198904 kb
Host smart-a3daa401-c633-4b28-9f52-ab0fed1e8c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267581023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.267581023
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2666169316
Short name T1252
Test name
Test status
Simulation time 62764000 ps
CPU time 0.79 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 199880 kb
Host smart-3a02d611-db8e-4afc-8ea1-f5f3d89a2b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666169316 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2666169316
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3105307049
Short name T1219
Test name
Test status
Simulation time 49343001 ps
CPU time 0.59 seconds
Started Aug 19 04:35:43 PM PDT 24
Finished Aug 19 04:35:44 PM PDT 24
Peak memory 195612 kb
Host smart-c095985f-2988-49c9-a24f-d142057ea657
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105307049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3105307049
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2994344516
Short name T1303
Test name
Test status
Simulation time 48734179 ps
CPU time 0.62 seconds
Started Aug 19 04:36:00 PM PDT 24
Finished Aug 19 04:36:02 PM PDT 24
Peak memory 194592 kb
Host smart-4c1b2d8a-2f23-4c5a-8ce8-6fb7852caf0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994344516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2994344516
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4031557298
Short name T65
Test name
Test status
Simulation time 48711755 ps
CPU time 0.69 seconds
Started Aug 19 04:35:37 PM PDT 24
Finished Aug 19 04:35:37 PM PDT 24
Peak memory 197656 kb
Host smart-f85711df-6fc8-478a-a290-b342cd5b117b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031557298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4031557298
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.368899906
Short name T1242
Test name
Test status
Simulation time 143349633 ps
CPU time 2.06 seconds
Started Aug 19 04:35:44 PM PDT 24
Finished Aug 19 04:35:46 PM PDT 24
Peak memory 200252 kb
Host smart-85330dee-f51e-4a97-8ddc-9ff094af36d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368899906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.368899906
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2891830037
Short name T75
Test name
Test status
Simulation time 321472703 ps
CPU time 1.32 seconds
Started Aug 19 04:35:51 PM PDT 24
Finished Aug 19 04:35:53 PM PDT 24
Peak memory 199620 kb
Host smart-b3f0311f-e8f8-4d79-b0db-af1b8d2cb367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891830037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2891830037
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2279283670
Short name T1034
Test name
Test status
Simulation time 10571817 ps
CPU time 0.54 seconds
Started Aug 19 06:05:06 PM PDT 24
Finished Aug 19 06:05:06 PM PDT 24
Peak memory 195252 kb
Host smart-e07b94fc-b40f-4dac-8066-cf0a172618fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279283670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2279283670
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3822360619
Short name T288
Test name
Test status
Simulation time 152519036284 ps
CPU time 160.05 seconds
Started Aug 19 06:04:50 PM PDT 24
Finished Aug 19 06:07:30 PM PDT 24
Peak memory 200916 kb
Host smart-24aa7a19-52ac-4edd-9257-082435e5d840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822360619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3822360619
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2646182264
Short name T1000
Test name
Test status
Simulation time 81357347668 ps
CPU time 38.68 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:05:33 PM PDT 24
Peak memory 200908 kb
Host smart-23681f9e-4c8e-4d7c-8545-8082b3af2b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646182264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2646182264
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.1153101307
Short name T761
Test name
Test status
Simulation time 300274456994 ps
CPU time 110.21 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:06:44 PM PDT 24
Peak memory 199128 kb
Host smart-df1b96dd-b1a3-40a4-b556-16b27672d578
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153101307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1153101307
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1677006802
Short name T615
Test name
Test status
Simulation time 224803460849 ps
CPU time 383.28 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:11:18 PM PDT 24
Peak memory 200988 kb
Host smart-2c8837d4-40ba-454b-839b-d602671e4925
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677006802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1677006802
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.722034363
Short name T1153
Test name
Test status
Simulation time 4440340637 ps
CPU time 4.04 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:04:58 PM PDT 24
Peak memory 200920 kb
Host smart-f6e46dfb-d2e7-4505-a43a-c80070d98277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722034363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.722034363
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3514468483
Short name T258
Test name
Test status
Simulation time 52023925175 ps
CPU time 22.61 seconds
Started Aug 19 06:04:55 PM PDT 24
Finished Aug 19 06:05:17 PM PDT 24
Peak memory 201172 kb
Host smart-f2faaf4a-bcb3-41af-b5ad-134da2ab6835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514468483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3514468483
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1052564778
Short name T248
Test name
Test status
Simulation time 11284980580 ps
CPU time 157.79 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:07:32 PM PDT 24
Peak memory 201008 kb
Host smart-4c8d526c-d9e5-42ce-92f7-797c7bee58a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052564778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1052564778
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.504263384
Short name T352
Test name
Test status
Simulation time 6125670721 ps
CPU time 14.63 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:05:08 PM PDT 24
Peak memory 199812 kb
Host smart-ce6d719b-2544-4b2a-937d-a8d5a2910371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504263384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.504263384
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.795100131
Short name T762
Test name
Test status
Simulation time 5106442733 ps
CPU time 2.78 seconds
Started Aug 19 06:04:53 PM PDT 24
Finished Aug 19 06:04:56 PM PDT 24
Peak memory 197280 kb
Host smart-dded8540-805b-45fd-a35a-e3e09b9a16f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795100131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.795100131
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.4073432898
Short name T80
Test name
Test status
Simulation time 126154830 ps
CPU time 0.78 seconds
Started Aug 19 06:05:05 PM PDT 24
Finished Aug 19 06:05:06 PM PDT 24
Peak memory 219072 kb
Host smart-5141f54d-5204-41c4-b803-5621acdea170
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073432898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.4073432898
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1197372375
Short name T1171
Test name
Test status
Simulation time 505023324 ps
CPU time 2.02 seconds
Started Aug 19 06:04:52 PM PDT 24
Finished Aug 19 06:04:54 PM PDT 24
Peak memory 199852 kb
Host smart-5bf34f11-26f8-4c5a-b7a8-a674426e398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197372375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1197372375
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3262163921
Short name T409
Test name
Test status
Simulation time 11652410625 ps
CPU time 84.34 seconds
Started Aug 19 06:04:54 PM PDT 24
Finished Aug 19 06:06:18 PM PDT 24
Peak memory 217556 kb
Host smart-61fe95d7-adc5-473e-a882-d0b9a9add616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262163921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3262163921
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2155367757
Short name T798
Test name
Test status
Simulation time 4471460571 ps
CPU time 1.5 seconds
Started Aug 19 06:04:50 PM PDT 24
Finished Aug 19 06:04:52 PM PDT 24
Peak memory 200028 kb
Host smart-540681cf-b575-4ccf-9c26-7eb642c86568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155367757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2155367757
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1089605928
Short name T292
Test name
Test status
Simulation time 13430994499 ps
CPU time 21.78 seconds
Started Aug 19 06:04:51 PM PDT 24
Finished Aug 19 06:05:13 PM PDT 24
Peak memory 200988 kb
Host smart-6bb78c42-207d-434a-ba7c-7b2da994d4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089605928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1089605928
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3876595099
Short name T775
Test name
Test status
Simulation time 21816180 ps
CPU time 0.54 seconds
Started Aug 19 06:04:59 PM PDT 24
Finished Aug 19 06:05:00 PM PDT 24
Peak memory 196252 kb
Host smart-02662e9d-75a8-4d4f-9c3b-b66a70bbf8c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876595099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3876595099
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1353454201
Short name T488
Test name
Test status
Simulation time 163285881692 ps
CPU time 251.17 seconds
Started Aug 19 06:05:04 PM PDT 24
Finished Aug 19 06:09:15 PM PDT 24
Peak memory 200928 kb
Host smart-083b3fe5-7c7e-4756-9944-2e53d32a2d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353454201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1353454201
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3225242168
Short name T495
Test name
Test status
Simulation time 34168893816 ps
CPU time 13.22 seconds
Started Aug 19 06:04:57 PM PDT 24
Finished Aug 19 06:05:10 PM PDT 24
Peak memory 200332 kb
Host smart-c8a45407-20f7-4f56-afb2-7573d3379708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225242168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3225242168
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.2139743216
Short name T830
Test name
Test status
Simulation time 10957029204 ps
CPU time 7.18 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:10 PM PDT 24
Peak memory 196500 kb
Host smart-ee576bc0-b075-41d3-a186-795c45990902
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139743216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2139743216
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1538916816
Short name T711
Test name
Test status
Simulation time 95500479525 ps
CPU time 596.7 seconds
Started Aug 19 06:05:00 PM PDT 24
Finished Aug 19 06:14:57 PM PDT 24
Peak memory 200996 kb
Host smart-dd9ed3f3-e679-4318-be22-ad06505ef806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538916816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1538916816
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.372927341
Short name T354
Test name
Test status
Simulation time 2477042744 ps
CPU time 2.8 seconds
Started Aug 19 06:05:00 PM PDT 24
Finished Aug 19 06:05:03 PM PDT 24
Peak memory 196792 kb
Host smart-d8ad020f-9f92-4350-98c4-2f1002c67343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372927341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.372927341
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.539150639
Short name T935
Test name
Test status
Simulation time 42118742466 ps
CPU time 77.15 seconds
Started Aug 19 06:05:00 PM PDT 24
Finished Aug 19 06:06:18 PM PDT 24
Peak memory 200176 kb
Host smart-5e6fa1df-53d3-4b1b-8b25-d8755aae4613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539150639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.539150639
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2468966674
Short name T472
Test name
Test status
Simulation time 12089866683 ps
CPU time 681.56 seconds
Started Aug 19 06:05:06 PM PDT 24
Finished Aug 19 06:16:28 PM PDT 24
Peak memory 200896 kb
Host smart-63e928de-0f30-4c36-9adc-396ba1886a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2468966674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2468966674
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3989890795
Short name T441
Test name
Test status
Simulation time 2967772599 ps
CPU time 9.14 seconds
Started Aug 19 06:05:04 PM PDT 24
Finished Aug 19 06:05:13 PM PDT 24
Peak memory 200152 kb
Host smart-57a65e3c-dd78-4e65-9890-c56b93282228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989890795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3989890795
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2070311533
Short name T1154
Test name
Test status
Simulation time 79644181324 ps
CPU time 30.82 seconds
Started Aug 19 06:05:06 PM PDT 24
Finished Aug 19 06:05:37 PM PDT 24
Peak memory 200984 kb
Host smart-d41d1a24-21b4-45ec-aee5-db9747a999f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070311533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2070311533
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1575313021
Short name T426
Test name
Test status
Simulation time 4837099301 ps
CPU time 4.02 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:05:05 PM PDT 24
Peak memory 197252 kb
Host smart-153f030c-07ba-4e46-a92b-284ce4f253ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575313021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1575313021
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.679334104
Short name T27
Test name
Test status
Simulation time 524551117 ps
CPU time 0.77 seconds
Started Aug 19 06:05:00 PM PDT 24
Finished Aug 19 06:05:01 PM PDT 24
Peak memory 219084 kb
Host smart-5fb76164-cc4b-4d74-83aa-8db0b3579af1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679334104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.679334104
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2460368004
Short name T739
Test name
Test status
Simulation time 848418402 ps
CPU time 4.01 seconds
Started Aug 19 06:05:06 PM PDT 24
Finished Aug 19 06:05:10 PM PDT 24
Peak memory 199904 kb
Host smart-a94fd1d8-3355-45a4-ac9e-2b648e17bc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460368004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2460368004
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2598146512
Short name T41
Test name
Test status
Simulation time 10447294881 ps
CPU time 73.42 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:06:16 PM PDT 24
Peak memory 217616 kb
Host smart-55be4418-1381-4605-a654-c034644cb9d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598146512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2598146512
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.286775604
Short name T836
Test name
Test status
Simulation time 942447686 ps
CPU time 1.28 seconds
Started Aug 19 06:05:04 PM PDT 24
Finished Aug 19 06:05:05 PM PDT 24
Peak memory 199636 kb
Host smart-c27d00e3-dbee-4ec6-b5cb-a3416a17e080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286775604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.286775604
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.550912786
Short name T661
Test name
Test status
Simulation time 78712261759 ps
CPU time 41.82 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:05:43 PM PDT 24
Peak memory 200864 kb
Host smart-e44a0347-934d-4813-afe1-114408568846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550912786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.550912786
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.4091995639
Short name T382
Test name
Test status
Simulation time 14136780 ps
CPU time 0.54 seconds
Started Aug 19 06:05:22 PM PDT 24
Finished Aug 19 06:05:23 PM PDT 24
Peak memory 196240 kb
Host smart-82618f40-251a-4d58-bad0-b66ec2faae72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091995639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.4091995639
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2181419208
Short name T122
Test name
Test status
Simulation time 67383033616 ps
CPU time 59.74 seconds
Started Aug 19 06:05:25 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 200980 kb
Host smart-bf4f065f-c111-44c0-a78d-607e92d19486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181419208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2181419208
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3298617465
Short name T1152
Test name
Test status
Simulation time 41062021353 ps
CPU time 68.78 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:06:36 PM PDT 24
Peak memory 200916 kb
Host smart-b1a29a3b-210c-47e8-9a86-70fff1acc314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298617465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3298617465
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1456149176
Short name T814
Test name
Test status
Simulation time 279133775309 ps
CPU time 45.64 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:06:11 PM PDT 24
Peak memory 200956 kb
Host smart-b041ac22-cbd7-4ff7-9f46-d0726e71acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456149176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1456149176
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3043967617
Short name T897
Test name
Test status
Simulation time 176244383826 ps
CPU time 73.06 seconds
Started Aug 19 06:05:29 PM PDT 24
Finished Aug 19 06:06:42 PM PDT 24
Peak memory 199548 kb
Host smart-81e225ea-eec5-45de-a011-65d72501caf0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043967617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3043967617
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3163077342
Short name T314
Test name
Test status
Simulation time 116567459975 ps
CPU time 459.4 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:13:07 PM PDT 24
Peak memory 200980 kb
Host smart-527c0f4d-7afe-4f5d-8b55-06ef24165fab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163077342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3163077342
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.285997564
Short name T363
Test name
Test status
Simulation time 8223646952 ps
CPU time 10.07 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:38 PM PDT 24
Peak memory 199560 kb
Host smart-7f76958f-b3b8-431e-93ba-9c40d7bbebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285997564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.285997564
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1643193188
Short name T963
Test name
Test status
Simulation time 41006950088 ps
CPU time 35.59 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:06:03 PM PDT 24
Peak memory 200448 kb
Host smart-9bace262-43d3-4878-aed0-829f3e9aed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643193188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1643193188
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3322401182
Short name T932
Test name
Test status
Simulation time 8896612160 ps
CPU time 175.09 seconds
Started Aug 19 06:05:30 PM PDT 24
Finished Aug 19 06:08:25 PM PDT 24
Peak memory 200984 kb
Host smart-d75711ab-6ef4-4365-8868-9d95c7f43f59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322401182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3322401182
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1167892865
Short name T693
Test name
Test status
Simulation time 7181750839 ps
CPU time 17.84 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:45 PM PDT 24
Peak memory 200172 kb
Host smart-228eaebd-b45f-468f-9235-9684ea2840a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167892865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1167892865
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3413446688
Short name T1041
Test name
Test status
Simulation time 69757704969 ps
CPU time 28.13 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:55 PM PDT 24
Peak memory 200480 kb
Host smart-6a50d13b-476d-40c1-9cbd-d262180fc774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413446688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3413446688
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2305930717
Short name T839
Test name
Test status
Simulation time 3024070581 ps
CPU time 1.77 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:30 PM PDT 24
Peak memory 197460 kb
Host smart-fa317ace-369a-4f4a-a180-f7e8c3839645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305930717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2305930717
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1459296319
Short name T852
Test name
Test status
Simulation time 535498001 ps
CPU time 1.52 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:30 PM PDT 24
Peak memory 200904 kb
Host smart-7ef670e0-7116-41ff-951b-f868e9d61130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459296319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1459296319
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2922542422
Short name T557
Test name
Test status
Simulation time 3524080450 ps
CPU time 54 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:06:22 PM PDT 24
Peak memory 210448 kb
Host smart-f94049db-dfee-4de2-911d-7fd03f48ea45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922542422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2922542422
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.633179782
Short name T403
Test name
Test status
Simulation time 2280951051 ps
CPU time 1.95 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:30 PM PDT 24
Peak memory 200472 kb
Host smart-fe2d0617-269f-4fe3-94aa-83cd94ec0401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633179782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.633179782
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1989300223
Short name T874
Test name
Test status
Simulation time 32924322167 ps
CPU time 12.05 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:39 PM PDT 24
Peak memory 197920 kb
Host smart-e12f8c2e-7a01-4f39-8973-374b6c76478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989300223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1989300223
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2420560587
Short name T232
Test name
Test status
Simulation time 11040846103 ps
CPU time 19.83 seconds
Started Aug 19 06:08:43 PM PDT 24
Finished Aug 19 06:09:03 PM PDT 24
Peak memory 201100 kb
Host smart-1dd1e94f-68e2-435f-bee0-67472e60b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420560587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2420560587
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3009413577
Short name T579
Test name
Test status
Simulation time 196397896784 ps
CPU time 19.54 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 200984 kb
Host smart-1b0ba6ef-af72-4b21-9fb1-964035446195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009413577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3009413577
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1580277409
Short name T590
Test name
Test status
Simulation time 114729301581 ps
CPU time 30.67 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:09:12 PM PDT 24
Peak memory 200904 kb
Host smart-23e06059-31d5-4a08-ae91-414244f9789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580277409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1580277409
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1640113274
Short name T663
Test name
Test status
Simulation time 47566362760 ps
CPU time 18.2 seconds
Started Aug 19 06:08:40 PM PDT 24
Finished Aug 19 06:08:58 PM PDT 24
Peak memory 200720 kb
Host smart-eb624ca8-6a5e-4064-94f6-bc2aff023655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640113274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1640113274
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1490149816
Short name T431
Test name
Test status
Simulation time 22907281983 ps
CPU time 9.95 seconds
Started Aug 19 06:08:52 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 200928 kb
Host smart-3a97ea4a-dc6c-4bff-997c-b447ed59a7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490149816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1490149816
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1800531838
Short name T184
Test name
Test status
Simulation time 110966990480 ps
CPU time 158.41 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:11:21 PM PDT 24
Peak memory 200916 kb
Host smart-ffb9fc46-d5e1-465e-b32e-0d5fa549d0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800531838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1800531838
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1119816924
Short name T1055
Test name
Test status
Simulation time 202494625420 ps
CPU time 150.87 seconds
Started Aug 19 06:08:37 PM PDT 24
Finished Aug 19 06:11:08 PM PDT 24
Peak memory 200984 kb
Host smart-2d42df4e-ff9a-4a78-ac6a-d7b6cce04ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119816924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1119816924
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1835908524
Short name T915
Test name
Test status
Simulation time 119137745600 ps
CPU time 199.71 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:12:01 PM PDT 24
Peak memory 200936 kb
Host smart-410a3476-18fb-404d-b552-e1d43ab743c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835908524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1835908524
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2897230468
Short name T1017
Test name
Test status
Simulation time 23854085373 ps
CPU time 19.78 seconds
Started Aug 19 06:08:52 PM PDT 24
Finished Aug 19 06:09:12 PM PDT 24
Peak memory 200960 kb
Host smart-144bdaf5-e4d7-4499-8562-3935e617dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897230468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2897230468
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3794223732
Short name T683
Test name
Test status
Simulation time 46348482 ps
CPU time 0.58 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:05:37 PM PDT 24
Peak memory 196272 kb
Host smart-4e6dde31-89b0-4d9d-a43c-af0e22c33a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794223732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3794223732
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3740457086
Short name T576
Test name
Test status
Simulation time 113842284902 ps
CPU time 50.15 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:06:19 PM PDT 24
Peak memory 200972 kb
Host smart-2dc70430-7a30-4ff3-ac46-52ad1f0b193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740457086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3740457086
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1264205884
Short name T846
Test name
Test status
Simulation time 75030133938 ps
CPU time 212.31 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:09:01 PM PDT 24
Peak memory 200892 kb
Host smart-f44b9899-afdd-4c4a-b0f0-891b68ea9e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264205884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1264205884
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3683455675
Short name T842
Test name
Test status
Simulation time 303137302916 ps
CPU time 57 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 200988 kb
Host smart-3a49ecb5-e28f-4836-8cf1-159bc714ea1d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683455675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3683455675
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.552240996
Short name T1175
Test name
Test status
Simulation time 111241432267 ps
CPU time 337.08 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:11:16 PM PDT 24
Peak memory 200972 kb
Host smart-43dffe36-a7ec-45c1-a4eb-43bcf508ce15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552240996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.552240996
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.105364006
Short name T1177
Test name
Test status
Simulation time 7484317727 ps
CPU time 4.17 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:32 PM PDT 24
Peak memory 200888 kb
Host smart-bab8bdc4-ce97-4f4d-a5fd-9948489594f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105364006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.105364006
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3818734320
Short name T1142
Test name
Test status
Simulation time 34048501278 ps
CPU time 28.65 seconds
Started Aug 19 06:05:32 PM PDT 24
Finished Aug 19 06:06:00 PM PDT 24
Peak memory 198908 kb
Host smart-d95b165f-3cae-4af8-bf51-594f504e0ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818734320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3818734320
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.383303445
Short name T902
Test name
Test status
Simulation time 3145469843 ps
CPU time 22.57 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:50 PM PDT 24
Peak memory 199972 kb
Host smart-3f0f2f8f-9a9f-4e33-9b24-df8e257ca907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383303445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.383303445
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1503356384
Short name T153
Test name
Test status
Simulation time 19851599999 ps
CPU time 32.94 seconds
Started Aug 19 06:05:29 PM PDT 24
Finished Aug 19 06:06:02 PM PDT 24
Peak memory 200912 kb
Host smart-c00bee2d-76d8-41ab-9f3b-e1a4b046b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503356384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1503356384
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3676280787
Short name T311
Test name
Test status
Simulation time 1367412534 ps
CPU time 1.2 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:28 PM PDT 24
Peak memory 196464 kb
Host smart-415134ce-2689-426b-bbd5-d9ff716a4d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676280787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3676280787
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.4142121641
Short name T719
Test name
Test status
Simulation time 269616512 ps
CPU time 1.41 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:29 PM PDT 24
Peak memory 199772 kb
Host smart-78217faa-e8f7-4ba3-85f3-89e429e287c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142121641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4142121641
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3117919381
Short name T812
Test name
Test status
Simulation time 230871271414 ps
CPU time 442.73 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:13:00 PM PDT 24
Peak memory 200964 kb
Host smart-cf9e764c-1121-4618-97dc-d5328c046fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117919381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3117919381
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.4239658653
Short name T1124
Test name
Test status
Simulation time 4287501115 ps
CPU time 51.21 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:06:31 PM PDT 24
Peak memory 217392 kb
Host smart-ce90b8b8-ffcc-4df9-bf92-be261a458685
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239658653 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.4239658653
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1485775258
Short name T397
Test name
Test status
Simulation time 1356894521 ps
CPU time 2.81 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:31 PM PDT 24
Peak memory 199812 kb
Host smart-366cb954-22d8-4edf-ad64-4ac5a19e9649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485775258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1485775258
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.219237924
Short name T788
Test name
Test status
Simulation time 135714287465 ps
CPU time 28.33 seconds
Started Aug 19 06:05:30 PM PDT 24
Finished Aug 19 06:05:58 PM PDT 24
Peak memory 200956 kb
Host smart-403b10b0-c243-4644-939a-36e907f042dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219237924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.219237924
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.207885255
Short name T213
Test name
Test status
Simulation time 41606862737 ps
CPU time 21.74 seconds
Started Aug 19 06:08:52 PM PDT 24
Finished Aug 19 06:09:14 PM PDT 24
Peak memory 200972 kb
Host smart-07b8ff8a-c5d7-4d8e-8827-915f7a8f6d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207885255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.207885255
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2272449708
Short name T587
Test name
Test status
Simulation time 233238122813 ps
CPU time 87.86 seconds
Started Aug 19 06:08:40 PM PDT 24
Finished Aug 19 06:10:08 PM PDT 24
Peak memory 200916 kb
Host smart-0622d60d-c6d4-4e33-907a-5b3b77dd0756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272449708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2272449708
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3851466352
Short name T903
Test name
Test status
Simulation time 14549435378 ps
CPU time 25.82 seconds
Started Aug 19 06:08:52 PM PDT 24
Finished Aug 19 06:09:18 PM PDT 24
Peak memory 200976 kb
Host smart-b24c81f8-b9fe-440b-a94d-f82d1eda1864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851466352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3851466352
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2113865414
Short name T778
Test name
Test status
Simulation time 64097205381 ps
CPU time 40.86 seconds
Started Aug 19 06:08:40 PM PDT 24
Finished Aug 19 06:09:21 PM PDT 24
Peak memory 201004 kb
Host smart-e20e936a-8f57-4a3c-a9fb-eaa9936fe013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113865414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2113865414
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3102154952
Short name T129
Test name
Test status
Simulation time 37679049062 ps
CPU time 17.61 seconds
Started Aug 19 06:08:43 PM PDT 24
Finished Aug 19 06:09:00 PM PDT 24
Peak memory 200972 kb
Host smart-932cf4bd-5751-45d7-a36e-315737aa8126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102154952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3102154952
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1504290060
Short name T294
Test name
Test status
Simulation time 157139428096 ps
CPU time 22.09 seconds
Started Aug 19 06:08:40 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 200716 kb
Host smart-9e1ca01d-fa32-41c3-a19d-4bd0e91bbf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504290060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1504290060
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3922054867
Short name T584
Test name
Test status
Simulation time 17328819861 ps
CPU time 29.39 seconds
Started Aug 19 06:08:38 PM PDT 24
Finished Aug 19 06:09:08 PM PDT 24
Peak memory 200996 kb
Host smart-fdc34eb9-0463-4f1e-8571-6c727283a91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922054867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3922054867
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3088380918
Short name T36
Test name
Test status
Simulation time 118265784626 ps
CPU time 47.69 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:06:27 PM PDT 24
Peak memory 200944 kb
Host smart-3444ef3a-7dbe-4dec-b6ae-96c762a1f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088380918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3088380918
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.773414347
Short name T939
Test name
Test status
Simulation time 27544627857 ps
CPU time 46.07 seconds
Started Aug 19 06:05:36 PM PDT 24
Finished Aug 19 06:06:23 PM PDT 24
Peak memory 201000 kb
Host smart-2c121835-b15d-4d2f-babb-fff4fc87e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773414347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.773414347
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1736608653
Short name T686
Test name
Test status
Simulation time 18626612678 ps
CPU time 31.09 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:06:08 PM PDT 24
Peak memory 200920 kb
Host smart-7b1e8628-dd5a-43b1-b6dd-7e7534313320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736608653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1736608653
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2726351326
Short name T458
Test name
Test status
Simulation time 42744878885 ps
CPU time 226.3 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:09:26 PM PDT 24
Peak memory 200920 kb
Host smart-9a86d294-b9b6-4492-96a8-ee1746f9ccc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726351326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2726351326
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1896664489
Short name T672
Test name
Test status
Simulation time 270878668 ps
CPU time 0.62 seconds
Started Aug 19 06:05:36 PM PDT 24
Finished Aug 19 06:05:36 PM PDT 24
Peak memory 196600 kb
Host smart-0c8214f1-9b8f-4a94-b0f9-dc545adc9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896664489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1896664489
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.231661442
Short name T741
Test name
Test status
Simulation time 162989131201 ps
CPU time 35.82 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:06:14 PM PDT 24
Peak memory 201148 kb
Host smart-d296965a-baa8-4ed1-bfd8-f51b9a17b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231661442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.231661442
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3372084408
Short name T1093
Test name
Test status
Simulation time 11424465703 ps
CPU time 152 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:08:09 PM PDT 24
Peak memory 200996 kb
Host smart-1d9e46a8-bdb9-45cf-b087-484a7be4e3ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372084408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3372084408
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4276733274
Short name T342
Test name
Test status
Simulation time 2440540006 ps
CPU time 15.9 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:05:55 PM PDT 24
Peak memory 200104 kb
Host smart-16e94334-61e1-4582-ba60-fcb4e6a00ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4276733274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4276733274
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3275626367
Short name T1049
Test name
Test status
Simulation time 67111280630 ps
CPU time 48.15 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 200984 kb
Host smart-8e444643-581e-4776-8a25-1820f0d54c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275626367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3275626367
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1723605948
Short name T372
Test name
Test status
Simulation time 3989498290 ps
CPU time 6.8 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:05:44 PM PDT 24
Peak memory 197252 kb
Host smart-a616f980-3b1d-45e0-a2c2-5bcff339462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723605948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1723605948
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.978412483
Short name T944
Test name
Test status
Simulation time 5758610340 ps
CPU time 7.13 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:05:47 PM PDT 24
Peak memory 200148 kb
Host smart-152dad2a-d355-4336-9ace-4bd45b4c379b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978412483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.978412483
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3682997600
Short name T737
Test name
Test status
Simulation time 78665456231 ps
CPU time 23.91 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:06:02 PM PDT 24
Peak memory 200936 kb
Host smart-5781aedb-2c61-4d97-8a1f-475cdcc87262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682997600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3682997600
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2585767272
Short name T91
Test name
Test status
Simulation time 2371972734 ps
CPU time 41.35 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:06:19 PM PDT 24
Peak memory 209444 kb
Host smart-0f03df4c-20c4-4cd6-a503-3ee6b874fa3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585767272 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2585767272
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1163177790
Short name T1131
Test name
Test status
Simulation time 825736901 ps
CPU time 1.69 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:05:39 PM PDT 24
Peak memory 200088 kb
Host smart-69ef26f5-769d-4a43-9dc3-35715e5b6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163177790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1163177790
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.199649682
Short name T414
Test name
Test status
Simulation time 130909194438 ps
CPU time 39 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:06:18 PM PDT 24
Peak memory 200960 kb
Host smart-84743394-b1ce-4698-a6ba-660a0ded46eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199649682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.199649682
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3572476303
Short name T401
Test name
Test status
Simulation time 26882236188 ps
CPU time 47.06 seconds
Started Aug 19 06:08:39 PM PDT 24
Finished Aug 19 06:09:27 PM PDT 24
Peak memory 200992 kb
Host smart-29f57ac5-9194-485f-bf2d-6658feab3460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572476303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3572476303
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2593207149
Short name T531
Test name
Test status
Simulation time 36451761130 ps
CPU time 14.29 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:08:56 PM PDT 24
Peak memory 200916 kb
Host smart-c3244408-03b8-4880-8827-ff226ae86460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593207149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2593207149
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1934201553
Short name T625
Test name
Test status
Simulation time 118008487573 ps
CPU time 246.1 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:12:48 PM PDT 24
Peak memory 200948 kb
Host smart-2d95b509-ad77-4a28-8923-6daf25105633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934201553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1934201553
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.59180259
Short name T771
Test name
Test status
Simulation time 16376531189 ps
CPU time 31.08 seconds
Started Aug 19 06:08:40 PM PDT 24
Finished Aug 19 06:09:11 PM PDT 24
Peak memory 201000 kb
Host smart-a27f8ff4-bf04-4f0e-a9ac-46cbc2a22330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59180259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.59180259
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2677514829
Short name T489
Test name
Test status
Simulation time 27164926796 ps
CPU time 48.83 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:09:30 PM PDT 24
Peak memory 200996 kb
Host smart-0c3cbc42-8c11-4cd3-8dbe-447ff856c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677514829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2677514829
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.191910723
Short name T111
Test name
Test status
Simulation time 19137827812 ps
CPU time 34.66 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:09:15 PM PDT 24
Peak memory 200900 kb
Host smart-143cd56c-da58-4b3d-9cf1-4a952281d8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191910723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.191910723
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3534062717
Short name T1020
Test name
Test status
Simulation time 107890876600 ps
CPU time 129.55 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:10:52 PM PDT 24
Peak memory 201100 kb
Host smart-8931fbfe-abf6-47bb-b276-7f109646b621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534062717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3534062717
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1538286317
Short name T193
Test name
Test status
Simulation time 28815601866 ps
CPU time 52.06 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:09:35 PM PDT 24
Peak memory 200900 kb
Host smart-549e8baa-6e1a-4fd0-aac9-97eafce5585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538286317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1538286317
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1137754309
Short name T179
Test name
Test status
Simulation time 131497815466 ps
CPU time 89.42 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:10:11 PM PDT 24
Peak memory 200964 kb
Host smart-61c59409-23f4-497e-8a0a-312bbe863444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137754309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1137754309
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.770658839
Short name T339
Test name
Test status
Simulation time 22133771 ps
CPU time 0.69 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:05:38 PM PDT 24
Peak memory 195716 kb
Host smart-4d5ce0d4-a08f-4292-9975-b6abbcd34e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770658839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.770658839
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.397346002
Short name T1038
Test name
Test status
Simulation time 105407701648 ps
CPU time 37.93 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:06:17 PM PDT 24
Peak memory 200980 kb
Host smart-81392689-a408-428a-b4a6-48f3ffc99c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397346002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.397346002
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.195471418
Short name T667
Test name
Test status
Simulation time 91914068271 ps
CPU time 148.15 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:08:08 PM PDT 24
Peak memory 200892 kb
Host smart-b4d5dbf7-175a-47f6-934c-67d5ee5285e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195471418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.195471418
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.4270424369
Short name T596
Test name
Test status
Simulation time 59100969128 ps
CPU time 110.48 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:07:27 PM PDT 24
Peak memory 200856 kb
Host smart-b808f28e-af80-40d9-a867-332fd1cc8e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270424369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4270424369
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3441928455
Short name T664
Test name
Test status
Simulation time 28098110793 ps
CPU time 46.99 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 200624 kb
Host smart-b3846828-07f2-464b-8766-064eef789f33
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441928455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3441928455
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2887923967
Short name T381
Test name
Test status
Simulation time 253053030737 ps
CPU time 426.19 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:12:46 PM PDT 24
Peak memory 200984 kb
Host smart-680eecae-6f2e-4eb9-99fa-1d674a7d63b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2887923967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2887923967
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1404862534
Short name T386
Test name
Test status
Simulation time 5607180309 ps
CPU time 7.2 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:05:45 PM PDT 24
Peak memory 197344 kb
Host smart-89b52a80-81a3-4ce5-96b6-ba2ce6789ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404862534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1404862534
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1470222756
Short name T283
Test name
Test status
Simulation time 145171392760 ps
CPU time 75.12 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:06:53 PM PDT 24
Peak memory 209188 kb
Host smart-0edacce7-aebe-435c-b18f-619381c2d85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470222756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1470222756
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3639509464
Short name T792
Test name
Test status
Simulation time 9472677582 ps
CPU time 510.22 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:14:07 PM PDT 24
Peak memory 200972 kb
Host smart-4ed8db7c-8895-4676-8d6f-6f2584396635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639509464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3639509464
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.703671837
Short name T928
Test name
Test status
Simulation time 4754880996 ps
CPU time 11.23 seconds
Started Aug 19 06:05:36 PM PDT 24
Finished Aug 19 06:05:47 PM PDT 24
Peak memory 199164 kb
Host smart-582f6712-4305-4526-ae88-42f2c9a37f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703671837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.703671837
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.363306715
Short name T1147
Test name
Test status
Simulation time 44925021836 ps
CPU time 25.82 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:06:03 PM PDT 24
Peak memory 197268 kb
Host smart-305a990e-3551-45c7-9d44-24ebd0bffea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363306715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.363306715
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1195381079
Short name T1025
Test name
Test status
Simulation time 5773106650 ps
CPU time 13.18 seconds
Started Aug 19 06:05:36 PM PDT 24
Finished Aug 19 06:05:50 PM PDT 24
Peak memory 200776 kb
Host smart-4194db07-e50d-48fb-a71f-72678aa98fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195381079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1195381079
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.519673021
Short name T1178
Test name
Test status
Simulation time 2632756378 ps
CPU time 25.07 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:06:02 PM PDT 24
Peak memory 216692 kb
Host smart-d9cac0ba-b85e-4c86-9327-a33db773fc48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519673021 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.519673021
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3065569812
Short name T350
Test name
Test status
Simulation time 1245216360 ps
CPU time 2.13 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:05:41 PM PDT 24
Peak memory 199764 kb
Host smart-85eaf767-2176-4b9e-9c84-ab6e13562c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065569812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3065569812
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.437582181
Short name T637
Test name
Test status
Simulation time 76860845630 ps
CPU time 55.8 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:06:35 PM PDT 24
Peak memory 200980 kb
Host smart-dfd71030-35f8-4cfb-a24a-d077c3b2ab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437582181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.437582181
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2191963241
Short name T279
Test name
Test status
Simulation time 80814856560 ps
CPU time 78.45 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:09:59 PM PDT 24
Peak memory 200936 kb
Host smart-4d9a8584-fbe7-4a04-a959-92d422f447ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191963241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2191963241
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1286682925
Short name T1074
Test name
Test status
Simulation time 178528609333 ps
CPU time 55.28 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:09:38 PM PDT 24
Peak memory 200888 kb
Host smart-d1d4c1cc-4c18-448f-99cd-bf82d5899ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286682925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1286682925
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.4267385634
Short name T124
Test name
Test status
Simulation time 35830442947 ps
CPU time 47.64 seconds
Started Aug 19 06:08:43 PM PDT 24
Finished Aug 19 06:09:30 PM PDT 24
Peak memory 200848 kb
Host smart-312ea120-fa08-43d2-8b62-a982c36a1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267385634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.4267385634
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3496995439
Short name T143
Test name
Test status
Simulation time 77040443235 ps
CPU time 156.98 seconds
Started Aug 19 06:08:40 PM PDT 24
Finished Aug 19 06:11:17 PM PDT 24
Peak memory 201008 kb
Host smart-66a5bc21-72ea-483e-a01d-9e3f65a98628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496995439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3496995439
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3619690582
Short name T715
Test name
Test status
Simulation time 16908370093 ps
CPU time 14.57 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:08:57 PM PDT 24
Peak memory 201000 kb
Host smart-6755adf8-ee89-438d-a01f-705fe148cdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619690582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3619690582
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1717304211
Short name T316
Test name
Test status
Simulation time 97051897221 ps
CPU time 167.37 seconds
Started Aug 19 06:08:52 PM PDT 24
Finished Aug 19 06:11:40 PM PDT 24
Peak memory 200916 kb
Host smart-8c5360f4-e127-4341-a4de-00aace8871b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717304211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1717304211
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2255695095
Short name T135
Test name
Test status
Simulation time 286827321325 ps
CPU time 164.16 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:11:26 PM PDT 24
Peak memory 200956 kb
Host smart-e2dd3898-0861-4049-b6f0-ce0a49426114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255695095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2255695095
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.59413666
Short name T990
Test name
Test status
Simulation time 15158614120 ps
CPU time 26.29 seconds
Started Aug 19 06:08:40 PM PDT 24
Finished Aug 19 06:09:06 PM PDT 24
Peak memory 200932 kb
Host smart-3d668eb1-a67a-4345-85aa-84f84a62db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59413666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.59413666
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.4114813513
Short name T709
Test name
Test status
Simulation time 83209543696 ps
CPU time 23.88 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:09:06 PM PDT 24
Peak memory 200968 kb
Host smart-7292f8f4-f2d6-4819-a3cb-29416bb86c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114813513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.4114813513
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3261946633
Short name T209
Test name
Test status
Simulation time 68233270603 ps
CPU time 155.83 seconds
Started Aug 19 06:08:47 PM PDT 24
Finished Aug 19 06:11:23 PM PDT 24
Peak memory 200896 kb
Host smart-54cddad0-0316-47a6-a3bd-7dcd9aba3074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261946633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3261946633
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.283539941
Short name T1048
Test name
Test status
Simulation time 39220371 ps
CPU time 0.57 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:05:53 PM PDT 24
Peak memory 196252 kb
Host smart-dc8a2b56-fa16-4c67-b2d9-aac7c6d7f6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283539941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.283539941
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4243076893
Short name T1075
Test name
Test status
Simulation time 92410203719 ps
CPU time 47.91 seconds
Started Aug 19 06:05:36 PM PDT 24
Finished Aug 19 06:06:24 PM PDT 24
Peak memory 200992 kb
Host smart-d0ec09ed-deba-4b8d-9543-2ac72c594c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243076893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4243076893
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3482703498
Short name T541
Test name
Test status
Simulation time 185322546062 ps
CPU time 87.56 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:07:05 PM PDT 24
Peak memory 200980 kb
Host smart-96044d1f-5412-4a11-8066-cdaecd361a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482703498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3482703498
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2040626661
Short name T843
Test name
Test status
Simulation time 4664715590 ps
CPU time 8.76 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:05:49 PM PDT 24
Peak memory 200976 kb
Host smart-36ae160e-51fd-4291-a738-88df9edb4d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040626661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2040626661
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.938261248
Short name T17
Test name
Test status
Simulation time 47285760114 ps
CPU time 22.73 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:06:03 PM PDT 24
Peak memory 200904 kb
Host smart-4ac17ee5-0a8e-458b-a03e-5957dfb08705
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938261248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.938261248
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.125308769
Short name T427
Test name
Test status
Simulation time 48561424295 ps
CPU time 74.67 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:07:05 PM PDT 24
Peak memory 200916 kb
Host smart-0a4f1a2b-2851-4472-879c-629ffe1882af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=125308769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.125308769
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.583978810
Short name T340
Test name
Test status
Simulation time 8897387167 ps
CPU time 10.83 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:05:50 PM PDT 24
Peak memory 200680 kb
Host smart-fc28820c-9dc9-4535-a2fb-4bde34b54450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583978810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.583978810
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.2590443595
Short name T691
Test name
Test status
Simulation time 118256615703 ps
CPU time 58.62 seconds
Started Aug 19 06:05:39 PM PDT 24
Finished Aug 19 06:06:38 PM PDT 24
Peak memory 201168 kb
Host smart-b7ac0144-af3d-481d-85a4-6694228fb5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590443595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2590443595
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3081025507
Short name T1080
Test name
Test status
Simulation time 3842638524 ps
CPU time 211.65 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:09:12 PM PDT 24
Peak memory 200996 kb
Host smart-43f98959-a8b8-48e4-bce1-9df90218227d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081025507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3081025507
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.535980181
Short name T891
Test name
Test status
Simulation time 4106451169 ps
CPU time 7.77 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:05:45 PM PDT 24
Peak memory 198988 kb
Host smart-50f58564-7ee2-4952-9dc8-5b11b3aaf195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535980181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.535980181
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2238662495
Short name T1108
Test name
Test status
Simulation time 62006610080 ps
CPU time 104.61 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:07:22 PM PDT 24
Peak memory 200924 kb
Host smart-e8069cf2-f32a-4a7b-9233-70ec87e1e433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238662495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2238662495
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4084853895
Short name T349
Test name
Test status
Simulation time 558144420 ps
CPU time 1.02 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:05:41 PM PDT 24
Peak memory 196464 kb
Host smart-6e61b6a1-8bf4-4331-872f-523ce95990f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084853895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4084853895
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2521710446
Short name T701
Test name
Test status
Simulation time 10545323716 ps
CPU time 15.55 seconds
Started Aug 19 06:05:38 PM PDT 24
Finished Aug 19 06:05:54 PM PDT 24
Peak memory 200800 kb
Host smart-bf134723-3b7f-47a7-a56b-3915120a1be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521710446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2521710446
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3944659349
Short name T481
Test name
Test status
Simulation time 495106265487 ps
CPU time 180.42 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:08:51 PM PDT 24
Peak memory 200940 kb
Host smart-75f3ce4b-8aed-4c97-93fb-20d3f9392e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944659349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3944659349
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2535076136
Short name T1072
Test name
Test status
Simulation time 1200264165 ps
CPU time 2.15 seconds
Started Aug 19 06:05:40 PM PDT 24
Finished Aug 19 06:05:42 PM PDT 24
Peak memory 199536 kb
Host smart-e6bd6ffb-dc30-4934-bdb8-60b79e4b4a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535076136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2535076136
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1606830052
Short name T246
Test name
Test status
Simulation time 17759991843 ps
CPU time 14.64 seconds
Started Aug 19 06:05:37 PM PDT 24
Finished Aug 19 06:05:52 PM PDT 24
Peak memory 200900 kb
Host smart-4c817a21-2be2-4222-88b5-aa25d6545b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606830052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1606830052
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.149938813
Short name T305
Test name
Test status
Simulation time 107542090207 ps
CPU time 65.36 seconds
Started Aug 19 06:08:53 PM PDT 24
Finished Aug 19 06:09:59 PM PDT 24
Peak memory 200972 kb
Host smart-c8f62dbd-6b1e-4319-9625-17d94fb2c2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149938813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.149938813
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2784416231
Short name T1053
Test name
Test status
Simulation time 32478857493 ps
CPU time 12.97 seconds
Started Aug 19 06:08:51 PM PDT 24
Finished Aug 19 06:09:04 PM PDT 24
Peak memory 200940 kb
Host smart-24579f45-fffe-4241-98c1-5a8d93804194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784416231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2784416231
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.92834139
Short name T796
Test name
Test status
Simulation time 11171247750 ps
CPU time 13.97 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 200980 kb
Host smart-f874f43b-4af3-4433-b5e1-4a90c67b3807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92834139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.92834139
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.445910682
Short name T424
Test name
Test status
Simulation time 139367747639 ps
CPU time 148.78 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:11:17 PM PDT 24
Peak memory 200948 kb
Host smart-d3fb6c86-93d4-4bf8-b537-016aa4d1d28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445910682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.445910682
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.112658483
Short name T688
Test name
Test status
Simulation time 48666760803 ps
CPU time 78.75 seconds
Started Aug 19 06:08:46 PM PDT 24
Finished Aug 19 06:10:05 PM PDT 24
Peak memory 200944 kb
Host smart-9eaf0328-ca00-4e72-a438-465a4517b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112658483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.112658483
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.903113094
Short name T1105
Test name
Test status
Simulation time 180869609706 ps
CPU time 139.41 seconds
Started Aug 19 06:08:49 PM PDT 24
Finished Aug 19 06:11:08 PM PDT 24
Peak memory 200928 kb
Host smart-4a058e89-9b88-499c-9a2c-4ccc5a63105c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903113094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.903113094
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.598113426
Short name T696
Test name
Test status
Simulation time 22062296563 ps
CPU time 37.22 seconds
Started Aug 19 06:08:49 PM PDT 24
Finished Aug 19 06:09:27 PM PDT 24
Peak memory 200960 kb
Host smart-5ae7697b-e823-465b-b910-2574bd92d91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598113426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.598113426
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.833265227
Short name T936
Test name
Test status
Simulation time 24838450998 ps
CPU time 24.99 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:09:13 PM PDT 24
Peak memory 200960 kb
Host smart-1a051a80-d6f6-4d13-a39e-ba07e679cca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833265227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.833265227
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1658851102
Short name T981
Test name
Test status
Simulation time 33931636 ps
CPU time 0.53 seconds
Started Aug 19 06:05:51 PM PDT 24
Finished Aug 19 06:05:51 PM PDT 24
Peak memory 196264 kb
Host smart-a5514836-fcde-4170-93b8-c5830923221c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658851102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1658851102
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.337707527
Short name T790
Test name
Test status
Simulation time 180461975964 ps
CPU time 70.13 seconds
Started Aug 19 06:05:53 PM PDT 24
Finished Aug 19 06:07:03 PM PDT 24
Peak memory 200920 kb
Host smart-49b4cb6f-ed36-43f7-9cf2-c453da1a85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337707527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.337707527
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2161656346
Short name T376
Test name
Test status
Simulation time 9912639686 ps
CPU time 15.25 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:06:07 PM PDT 24
Peak memory 200572 kb
Host smart-f4bd2087-7a0a-4692-8a72-61a0fc6d61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161656346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2161656346
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.441202488
Short name T13
Test name
Test status
Simulation time 22173470498 ps
CPU time 12.15 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:06:03 PM PDT 24
Peak memory 200992 kb
Host smart-ee7b5fc3-588f-4676-abbc-9f273c4562e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441202488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.441202488
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1482585834
Short name T462
Test name
Test status
Simulation time 10427285632 ps
CPU time 4.42 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:05:57 PM PDT 24
Peak memory 198752 kb
Host smart-77edbd5d-3936-46e2-a088-2355955e196b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482585834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1482585834
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2222134588
Short name T977
Test name
Test status
Simulation time 57470923877 ps
CPU time 135.95 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:08:06 PM PDT 24
Peak memory 200956 kb
Host smart-65314028-9726-4733-91cc-2df8a3681538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2222134588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2222134588
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2963434674
Short name T722
Test name
Test status
Simulation time 9810598671 ps
CPU time 7.5 seconds
Started Aug 19 06:05:51 PM PDT 24
Finished Aug 19 06:05:59 PM PDT 24
Peak memory 199636 kb
Host smart-832b8e9e-7e8f-4bd4-a572-9c6e0b07cbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963434674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2963434674
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2997400053
Short name T919
Test name
Test status
Simulation time 103073092046 ps
CPU time 180.03 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:08:50 PM PDT 24
Peak memory 200464 kb
Host smart-9df26601-7881-4b6f-b086-ad8f48e65fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997400053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2997400053
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1838467409
Short name T373
Test name
Test status
Simulation time 3175836321 ps
CPU time 2.9 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:05:55 PM PDT 24
Peak memory 200120 kb
Host smart-e81b0f2d-ed74-4111-a548-f0961a814f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838467409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1838467409
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1759485779
Short name T299
Test name
Test status
Simulation time 25244569047 ps
CPU time 37.31 seconds
Started Aug 19 06:05:53 PM PDT 24
Finished Aug 19 06:06:30 PM PDT 24
Peak memory 200920 kb
Host smart-8679aec0-72f0-497d-9e67-3ce18ff396e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759485779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1759485779
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3400508199
Short name T950
Test name
Test status
Simulation time 42608682269 ps
CPU time 17.5 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:06:09 PM PDT 24
Peak memory 197068 kb
Host smart-d5dda7a9-8ef6-4658-a6cb-42a8db8d5e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400508199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3400508199
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1096691286
Short name T4
Test name
Test status
Simulation time 712215300 ps
CPU time 1.63 seconds
Started Aug 19 06:05:51 PM PDT 24
Finished Aug 19 06:05:53 PM PDT 24
Peak memory 200380 kb
Host smart-87665658-ae1d-4910-bfc0-bb4c2dd18db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096691286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1096691286
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.4231079531
Short name T1010
Test name
Test status
Simulation time 196697687672 ps
CPU time 291.63 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:10:42 PM PDT 24
Peak memory 200980 kb
Host smart-9be029fa-bbc1-4de7-b204-780fd26b01c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231079531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.4231079531
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.943531451
Short name T1157
Test name
Test status
Simulation time 17582603882 ps
CPU time 61.77 seconds
Started Aug 19 06:05:54 PM PDT 24
Finished Aug 19 06:06:56 PM PDT 24
Peak memory 211064 kb
Host smart-eeb88e66-7c99-4250-8a17-42eb950ed2bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943531451 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.943531451
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1655677411
Short name T717
Test name
Test status
Simulation time 2060771707 ps
CPU time 2.37 seconds
Started Aug 19 06:05:51 PM PDT 24
Finished Aug 19 06:05:54 PM PDT 24
Peak memory 199504 kb
Host smart-5b886dd4-78ce-4e65-b5e8-009fa3a012cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655677411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1655677411
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.885291282
Short name T207
Test name
Test status
Simulation time 60649672481 ps
CPU time 85.56 seconds
Started Aug 19 06:08:50 PM PDT 24
Finished Aug 19 06:10:15 PM PDT 24
Peak memory 200968 kb
Host smart-59f18f03-e2a4-4597-98c5-8209c75bcde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885291282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.885291282
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1604974344
Short name T1089
Test name
Test status
Simulation time 103477132936 ps
CPU time 239.26 seconds
Started Aug 19 06:08:57 PM PDT 24
Finished Aug 19 06:12:56 PM PDT 24
Peak memory 200792 kb
Host smart-7ae513c8-ee0d-43ad-bb05-f316cc37879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604974344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1604974344
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2695009629
Short name T1079
Test name
Test status
Simulation time 9518641829 ps
CPU time 19.5 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:09:07 PM PDT 24
Peak memory 200964 kb
Host smart-48ce21db-f129-4f7a-9cb7-bdc5a378794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695009629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2695009629
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3680981497
Short name T861
Test name
Test status
Simulation time 65073986711 ps
CPU time 32.28 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:09:21 PM PDT 24
Peak memory 200948 kb
Host smart-8a3d05ab-fe13-476a-8da9-893126cfdc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680981497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3680981497
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3285880018
Short name T206
Test name
Test status
Simulation time 171402042554 ps
CPU time 73.29 seconds
Started Aug 19 06:08:49 PM PDT 24
Finished Aug 19 06:10:03 PM PDT 24
Peak memory 200928 kb
Host smart-4d6cc3d1-70fe-44e4-ad60-f04f49f342ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285880018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3285880018
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.433362502
Short name T1013
Test name
Test status
Simulation time 4374079866 ps
CPU time 10.32 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:08:59 PM PDT 24
Peak memory 200988 kb
Host smart-81e3986d-c7d5-4be2-ab2e-5e0b2255a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433362502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.433362502
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.919674130
Short name T220
Test name
Test status
Simulation time 122831183982 ps
CPU time 51.75 seconds
Started Aug 19 06:08:51 PM PDT 24
Finished Aug 19 06:09:43 PM PDT 24
Peak memory 200988 kb
Host smart-92ed2328-ce9f-4b4a-adf1-2ae9813df28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919674130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.919674130
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3868182674
Short name T885
Test name
Test status
Simulation time 53833382931 ps
CPU time 89.75 seconds
Started Aug 19 06:08:49 PM PDT 24
Finished Aug 19 06:10:19 PM PDT 24
Peak memory 201000 kb
Host smart-11b25dc6-3092-4a74-a8ee-94ce29dfb967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868182674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3868182674
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2022526880
Short name T575
Test name
Test status
Simulation time 145012955497 ps
CPU time 60.34 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:09:48 PM PDT 24
Peak memory 200944 kb
Host smart-97072770-d7af-4dbc-8720-917c11e0a162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022526880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2022526880
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.4265584902
Short name T609
Test name
Test status
Simulation time 18210115 ps
CPU time 0.55 seconds
Started Aug 19 06:05:53 PM PDT 24
Finished Aug 19 06:05:54 PM PDT 24
Peak memory 196576 kb
Host smart-eac68784-b6ca-4d6f-8a20-3331bf50c925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265584902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.4265584902
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3708275177
Short name T773
Test name
Test status
Simulation time 176664186450 ps
CPU time 144.29 seconds
Started Aug 19 06:05:49 PM PDT 24
Finished Aug 19 06:08:14 PM PDT 24
Peak memory 200952 kb
Host smart-a6ea730f-9990-4962-b37b-007727f39c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708275177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3708275177
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1557098661
Short name T120
Test name
Test status
Simulation time 72915715352 ps
CPU time 60.51 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:06:51 PM PDT 24
Peak memory 200896 kb
Host smart-19e33419-adcc-44d1-b163-fe92d678efcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557098661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1557098661
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.1457542933
Short name T619
Test name
Test status
Simulation time 22088053689 ps
CPU time 37.06 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:06:29 PM PDT 24
Peak memory 200352 kb
Host smart-de942d4d-5328-4c90-abb9-1d942c53e47e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457542933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1457542933
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.22177085
Short name T901
Test name
Test status
Simulation time 96439866352 ps
CPU time 523.24 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:14:34 PM PDT 24
Peak memory 200944 kb
Host smart-abb5e3da-db1c-4327-9bde-235237516cbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22177085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.22177085
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2023984648
Short name T600
Test name
Test status
Simulation time 7620467344 ps
CPU time 15.29 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:06:06 PM PDT 24
Peak memory 200196 kb
Host smart-2e018f3b-0176-456a-943b-b786bad964b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023984648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2023984648
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2997357564
Short name T267
Test name
Test status
Simulation time 109819133590 ps
CPU time 102.93 seconds
Started Aug 19 06:05:51 PM PDT 24
Finished Aug 19 06:07:34 PM PDT 24
Peak memory 200712 kb
Host smart-a46f574c-a874-45f5-bceb-b194e1db1e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997357564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2997357564
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1655685948
Short name T43
Test name
Test status
Simulation time 4305032368 ps
CPU time 244.12 seconds
Started Aug 19 06:05:51 PM PDT 24
Finished Aug 19 06:09:55 PM PDT 24
Peak memory 200972 kb
Host smart-bc551c78-1673-4b4c-9bac-99e38e18552a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655685948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1655685948
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3140487895
Short name T19
Test name
Test status
Simulation time 3168434558 ps
CPU time 3.88 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:05:56 PM PDT 24
Peak memory 198996 kb
Host smart-f560c0be-8230-47dc-87f3-cf9023fc8f6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140487895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3140487895
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3047190572
Short name T379
Test name
Test status
Simulation time 21146270773 ps
CPU time 42.32 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:06:32 PM PDT 24
Peak memory 200988 kb
Host smart-723acce8-5e02-4988-84ea-03cac6501645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047190572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3047190572
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2042071343
Short name T606
Test name
Test status
Simulation time 1597979156 ps
CPU time 3.33 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:05:56 PM PDT 24
Peak memory 196612 kb
Host smart-ba43610a-2607-4dba-bf33-c9eab23c77ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042071343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2042071343
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3923967460
Short name T482
Test name
Test status
Simulation time 121342837 ps
CPU time 1.06 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:05:53 PM PDT 24
Peak memory 199528 kb
Host smart-0d8666cc-9dc3-4975-9e5e-953a6223e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923967460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3923967460
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2701279556
Short name T448
Test name
Test status
Simulation time 86841639328 ps
CPU time 620.08 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:16:12 PM PDT 24
Peak memory 200908 kb
Host smart-a318f188-febd-4cbc-ba73-4e056ec12bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701279556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2701279556
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.914340140
Short name T1084
Test name
Test status
Simulation time 7737284141 ps
CPU time 14.94 seconds
Started Aug 19 06:05:52 PM PDT 24
Finished Aug 19 06:06:07 PM PDT 24
Peak memory 200744 kb
Host smart-21342e5d-2737-45a6-9ccc-2010b543995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914340140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.914340140
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2693253268
Short name T942
Test name
Test status
Simulation time 30519351042 ps
CPU time 32.82 seconds
Started Aug 19 06:05:50 PM PDT 24
Finished Aug 19 06:06:23 PM PDT 24
Peak memory 200936 kb
Host smart-d3b2b2b3-de30-4ebc-b06d-da347964ab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693253268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2693253268
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3705247644
Short name T138
Test name
Test status
Simulation time 39534956639 ps
CPU time 18 seconds
Started Aug 19 06:08:50 PM PDT 24
Finished Aug 19 06:09:08 PM PDT 24
Peak memory 200932 kb
Host smart-9dcae043-40f2-4735-b5c4-b44d586ae795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705247644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3705247644
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1975616748
Short name T1054
Test name
Test status
Simulation time 159583011760 ps
CPU time 247.72 seconds
Started Aug 19 06:08:47 PM PDT 24
Finished Aug 19 06:12:55 PM PDT 24
Peak memory 200912 kb
Host smart-51b79aa0-89a1-4660-9eaa-591521faf7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975616748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1975616748
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1056944735
Short name T574
Test name
Test status
Simulation time 50766498632 ps
CPU time 20.91 seconds
Started Aug 19 06:08:49 PM PDT 24
Finished Aug 19 06:09:10 PM PDT 24
Peak memory 200656 kb
Host smart-7c558055-78c9-4d31-90fd-8e74badfe00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056944735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1056944735
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2405969003
Short name T1165
Test name
Test status
Simulation time 19488133852 ps
CPU time 51.15 seconds
Started Aug 19 06:08:50 PM PDT 24
Finished Aug 19 06:09:41 PM PDT 24
Peak memory 200964 kb
Host smart-f04a4585-a9ac-4699-bf2e-32252dd2fee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405969003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2405969003
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.987276593
Short name T784
Test name
Test status
Simulation time 18855441971 ps
CPU time 39.95 seconds
Started Aug 19 06:08:49 PM PDT 24
Finished Aug 19 06:09:29 PM PDT 24
Peak memory 200912 kb
Host smart-8c631d4c-4610-4112-94eb-d721114f2e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987276593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.987276593
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.4250248927
Short name T161
Test name
Test status
Simulation time 27724535668 ps
CPU time 25.84 seconds
Started Aug 19 06:08:50 PM PDT 24
Finished Aug 19 06:09:16 PM PDT 24
Peak memory 200996 kb
Host smart-3efcd0f9-f267-4d3d-8196-aef6378a94f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250248927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.4250248927
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.435684148
Short name T1140
Test name
Test status
Simulation time 177503538094 ps
CPU time 285.17 seconds
Started Aug 19 06:08:51 PM PDT 24
Finished Aug 19 06:13:36 PM PDT 24
Peak memory 200904 kb
Host smart-3e237454-1d99-471c-9fcc-5aa209751210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435684148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.435684148
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.483535957
Short name T782
Test name
Test status
Simulation time 26918707 ps
CPU time 0.64 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:02 PM PDT 24
Peak memory 196268 kb
Host smart-89d5f4d0-1691-4b50-9879-ea141115ce4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483535957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.483535957
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2078078248
Short name T779
Test name
Test status
Simulation time 35415352456 ps
CPU time 32.27 seconds
Started Aug 19 06:06:03 PM PDT 24
Finished Aug 19 06:06:36 PM PDT 24
Peak memory 200992 kb
Host smart-9e2cc833-5aef-4b3b-90fb-206e6883b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078078248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2078078248
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1259473734
Short name T242
Test name
Test status
Simulation time 171042782209 ps
CPU time 256.03 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:10:17 PM PDT 24
Peak memory 200892 kb
Host smart-3438ad2f-c40c-4366-bf6c-f78d18b27248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259473734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1259473734
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3230312288
Short name T832
Test name
Test status
Simulation time 103097906899 ps
CPU time 39.29 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:06:38 PM PDT 24
Peak memory 200944 kb
Host smart-c2665824-6390-473b-b563-287db3b9494a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230312288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3230312288
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.4135322938
Short name T329
Test name
Test status
Simulation time 34115581552 ps
CPU time 26.33 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:27 PM PDT 24
Peak memory 200788 kb
Host smart-2bb10f9f-a6c2-4f1a-9ec2-0ded8d480e0b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135322938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.4135322938
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.827240561
Short name T23
Test name
Test status
Simulation time 91255478784 ps
CPU time 218.94 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:09:39 PM PDT 24
Peak memory 200988 kb
Host smart-2770aa43-495d-4be8-a9e4-c5f6e9a500dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827240561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.827240561
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.465060456
Short name T855
Test name
Test status
Simulation time 2682639942 ps
CPU time 1.43 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:06:01 PM PDT 24
Peak memory 198628 kb
Host smart-47507098-7dcb-4d14-8c48-d4e8107b8316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465060456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.465060456
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.380784517
Short name T451
Test name
Test status
Simulation time 141871390157 ps
CPU time 119.58 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 209160 kb
Host smart-5cabd58b-f415-413b-af61-9e4036e541ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380784517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.380784517
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.3588607034
Short name T443
Test name
Test status
Simulation time 15224487910 ps
CPU time 116.3 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:07:56 PM PDT 24
Peak memory 200976 kb
Host smart-2b84223b-fc55-4187-a479-4aeabf598493
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588607034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3588607034
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2139923225
Short name T641
Test name
Test status
Simulation time 4623364828 ps
CPU time 10.53 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:06:11 PM PDT 24
Peak memory 200216 kb
Host smart-56b7dde8-07d0-48e9-b129-12c979361b29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139923225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2139923225
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2918720579
Short name T1095
Test name
Test status
Simulation time 78057714673 ps
CPU time 34.12 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:35 PM PDT 24
Peak memory 200972 kb
Host smart-65e6d75a-b21a-4d75-9b16-d75f16daa593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918720579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2918720579
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2692640048
Short name T562
Test name
Test status
Simulation time 1848233587 ps
CPU time 1.37 seconds
Started Aug 19 06:06:02 PM PDT 24
Finished Aug 19 06:06:03 PM PDT 24
Peak memory 196452 kb
Host smart-32e54507-0343-43eb-99b1-b2cddf26bd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692640048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2692640048
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.580896599
Short name T1088
Test name
Test status
Simulation time 294476433 ps
CPU time 0.92 seconds
Started Aug 19 06:05:51 PM PDT 24
Finished Aug 19 06:05:52 PM PDT 24
Peak memory 199608 kb
Host smart-35e69c98-045a-4235-9f34-f154328c1fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580896599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.580896599
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.179174122
Short name T732
Test name
Test status
Simulation time 2196594798 ps
CPU time 29.06 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:06:28 PM PDT 24
Peak memory 209172 kb
Host smart-d7cb1dbc-19f7-4763-966d-6b5c86ad2f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179174122 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.179174122
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1726751764
Short name T1037
Test name
Test status
Simulation time 947694762 ps
CPU time 3.54 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:06:03 PM PDT 24
Peak memory 199820 kb
Host smart-009a6328-167a-4897-ac47-d0195245156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726751764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1726751764
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.122186624
Short name T752
Test name
Test status
Simulation time 50664397520 ps
CPU time 68.63 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:07:10 PM PDT 24
Peak memory 200896 kb
Host smart-6ef12ccf-16d9-496d-ad4b-e99c328a4205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122186624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.122186624
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.884624176
Short name T948
Test name
Test status
Simulation time 15448785548 ps
CPU time 6.29 seconds
Started Aug 19 06:08:51 PM PDT 24
Finished Aug 19 06:08:58 PM PDT 24
Peak memory 199952 kb
Host smart-932f6401-4d99-476c-b99f-c5231831ae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884624176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.884624176
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2062707082
Short name T835
Test name
Test status
Simulation time 33763768145 ps
CPU time 13.71 seconds
Started Aug 19 06:08:53 PM PDT 24
Finished Aug 19 06:09:07 PM PDT 24
Peak memory 200960 kb
Host smart-6e9c876f-82a8-43f9-9bb8-e16f9f1a9500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062707082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2062707082
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1016464692
Short name T1143
Test name
Test status
Simulation time 121004104014 ps
CPU time 105.3 seconds
Started Aug 19 06:08:48 PM PDT 24
Finished Aug 19 06:10:33 PM PDT 24
Peak memory 200952 kb
Host smart-3937c363-8629-43e4-b196-5bb9417d5732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016464692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1016464692
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.183804926
Short name T393
Test name
Test status
Simulation time 148821662949 ps
CPU time 242 seconds
Started Aug 19 06:08:47 PM PDT 24
Finished Aug 19 06:12:50 PM PDT 24
Peak memory 200884 kb
Host smart-2e2ccfb3-bdee-411e-9300-6607b9489333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183804926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.183804926
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1292935966
Short name T552
Test name
Test status
Simulation time 50382361448 ps
CPU time 42.29 seconds
Started Aug 19 06:08:57 PM PDT 24
Finished Aug 19 06:09:39 PM PDT 24
Peak memory 200828 kb
Host smart-b9210f31-63ad-462e-b4b3-ea8abd2ead9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292935966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1292935966
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1103914224
Short name T690
Test name
Test status
Simulation time 27946173599 ps
CPU time 31.56 seconds
Started Aug 19 06:08:56 PM PDT 24
Finished Aug 19 06:09:28 PM PDT 24
Peak memory 200920 kb
Host smart-40632c35-0c71-4307-a61a-77f45a80d149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103914224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1103914224
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1200796492
Short name T1014
Test name
Test status
Simulation time 28650858718 ps
CPU time 12.22 seconds
Started Aug 19 06:08:50 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 200960 kb
Host smart-31184375-ceb7-4f64-b963-453473339f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200796492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1200796492
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1089689972
Short name T525
Test name
Test status
Simulation time 38279648317 ps
CPU time 53.15 seconds
Started Aug 19 06:08:49 PM PDT 24
Finished Aug 19 06:09:42 PM PDT 24
Peak memory 200988 kb
Host smart-b0e4ddbe-26fe-4e55-8e7d-9b8c9b652061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089689972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1089689972
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3401958323
Short name T714
Test name
Test status
Simulation time 388309019792 ps
CPU time 39.81 seconds
Started Aug 19 06:09:02 PM PDT 24
Finished Aug 19 06:09:42 PM PDT 24
Peak memory 200940 kb
Host smart-48dbb37d-62c1-4fec-91c3-7a47b04f2285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401958323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3401958323
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2739877632
Short name T347
Test name
Test status
Simulation time 12257667 ps
CPU time 0.55 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:06:00 PM PDT 24
Peak memory 196284 kb
Host smart-5a5b1993-4232-4a12-a2f0-b3f22feaafcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739877632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2739877632
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.4079613570
Short name T428
Test name
Test status
Simulation time 28588885335 ps
CPU time 43.01 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:06:43 PM PDT 24
Peak memory 200868 kb
Host smart-6578c1d5-afd0-4767-b101-e3e0a79d4096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079613570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.4079613570
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3552255469
Short name T140
Test name
Test status
Simulation time 98448732818 ps
CPU time 38.41 seconds
Started Aug 19 06:05:58 PM PDT 24
Finished Aug 19 06:06:37 PM PDT 24
Peak memory 201116 kb
Host smart-a38048b5-e911-4640-a372-a473bab91e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552255469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3552255469
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1251003512
Short name T49
Test name
Test status
Simulation time 68009176243 ps
CPU time 38.25 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:06:37 PM PDT 24
Peak memory 200932 kb
Host smart-a4bb616e-6196-4d9e-a848-1f7cd0f5bf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251003512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1251003512
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3387133840
Short name T467
Test name
Test status
Simulation time 248888447718 ps
CPU time 390.83 seconds
Started Aug 19 06:05:58 PM PDT 24
Finished Aug 19 06:12:29 PM PDT 24
Peak memory 200744 kb
Host smart-c750680b-347e-4c8f-a287-99077881cce6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387133840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3387133840
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2032682851
Short name T643
Test name
Test status
Simulation time 36514977538 ps
CPU time 316.26 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:11:17 PM PDT 24
Peak memory 200868 kb
Host smart-7c9ce3c2-0b54-4411-874b-6e8906997c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032682851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2032682851
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.113181798
Short name T734
Test name
Test status
Simulation time 5100635044 ps
CPU time 5.45 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:06 PM PDT 24
Peak memory 199584 kb
Host smart-f6006cbd-0179-49aa-93f1-2c1075114b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113181798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.113181798
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1491995082
Short name T1086
Test name
Test status
Simulation time 14093329035 ps
CPU time 23.12 seconds
Started Aug 19 06:06:04 PM PDT 24
Finished Aug 19 06:06:27 PM PDT 24
Peak memory 199128 kb
Host smart-e5f3e459-a837-4c7b-aeef-64dd36f26ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491995082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1491995082
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.795194138
Short name T1135
Test name
Test status
Simulation time 9410033644 ps
CPU time 87.74 seconds
Started Aug 19 06:06:04 PM PDT 24
Finished Aug 19 06:07:31 PM PDT 24
Peak memory 201000 kb
Host smart-0cb646fe-e138-4e6e-a7c5-1526e4b9ded5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795194138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.795194138
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3192029846
Short name T1062
Test name
Test status
Simulation time 6977654731 ps
CPU time 58.55 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:07:00 PM PDT 24
Peak memory 199084 kb
Host smart-3fac8dc3-2050-4119-a3f0-d53a21ba3d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3192029846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3192029846
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.726154388
Short name T624
Test name
Test status
Simulation time 192993943901 ps
CPU time 652.6 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:16:51 PM PDT 24
Peak memory 200892 kb
Host smart-267f91cd-bb27-4474-8ba8-60d35914e75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726154388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.726154388
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2892041997
Short name T284
Test name
Test status
Simulation time 5621636576 ps
CPU time 7.33 seconds
Started Aug 19 06:06:02 PM PDT 24
Finished Aug 19 06:06:10 PM PDT 24
Peak memory 197460 kb
Host smart-51258fea-31b1-4875-977f-70835dd63134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892041997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2892041997
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1373970006
Short name T626
Test name
Test status
Simulation time 5543091374 ps
CPU time 6.77 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:07 PM PDT 24
Peak memory 200872 kb
Host smart-ac00821a-6b39-4641-a91c-1102582fadd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373970006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1373970006
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2105802596
Short name T720
Test name
Test status
Simulation time 15144863546 ps
CPU time 47.31 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:06:47 PM PDT 24
Peak memory 210408 kb
Host smart-6b2fe5e6-c1c3-4cef-b2bf-7bab7da81f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105802596 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2105802596
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3927676810
Short name T653
Test name
Test status
Simulation time 975605341 ps
CPU time 3.87 seconds
Started Aug 19 06:05:58 PM PDT 24
Finished Aug 19 06:06:02 PM PDT 24
Peak memory 200492 kb
Host smart-79d8627b-a544-49b5-a178-ef4d0b0b7f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927676810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3927676810
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1502125438
Short name T323
Test name
Test status
Simulation time 99438471602 ps
CPU time 152.48 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:08:32 PM PDT 24
Peak memory 200964 kb
Host smart-30f25a73-ec9f-43b4-bd7c-3d2b21f4c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502125438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1502125438
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.205106774
Short name T97
Test name
Test status
Simulation time 23691225348 ps
CPU time 44.04 seconds
Started Aug 19 06:08:59 PM PDT 24
Finished Aug 19 06:09:44 PM PDT 24
Peak memory 200996 kb
Host smart-bac55a65-e97e-4970-a817-ecc790a152e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205106774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.205106774
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2926133369
Short name T793
Test name
Test status
Simulation time 45956049470 ps
CPU time 64.15 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:10:02 PM PDT 24
Peak memory 201004 kb
Host smart-e0f85d8f-ad5c-4d50-b6b5-aa4eb4689a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926133369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2926133369
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.507561152
Short name T1046
Test name
Test status
Simulation time 123144756643 ps
CPU time 104.12 seconds
Started Aug 19 06:09:00 PM PDT 24
Finished Aug 19 06:10:44 PM PDT 24
Peak memory 200972 kb
Host smart-78a1bccf-2e9c-49f8-8c12-eb34a4825292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507561152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.507561152
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2642578325
Short name T563
Test name
Test status
Simulation time 11402019581 ps
CPU time 17.84 seconds
Started Aug 19 06:09:00 PM PDT 24
Finished Aug 19 06:09:18 PM PDT 24
Peak memory 200936 kb
Host smart-ef354b3b-cb39-4bdb-89c4-1dd2348e0e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642578325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2642578325
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3633708078
Short name T1015
Test name
Test status
Simulation time 101895891716 ps
CPU time 31.95 seconds
Started Aug 19 06:08:59 PM PDT 24
Finished Aug 19 06:09:31 PM PDT 24
Peak memory 200876 kb
Host smart-7026633a-f90c-4a03-8f05-eb287de4851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633708078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3633708078
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3657874793
Short name T133
Test name
Test status
Simulation time 160480572128 ps
CPU time 102.73 seconds
Started Aug 19 06:08:59 PM PDT 24
Finished Aug 19 06:10:42 PM PDT 24
Peak memory 200948 kb
Host smart-97f0aa8a-13a3-4dc9-b01f-6280014d0105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657874793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3657874793
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.951235363
Short name T199
Test name
Test status
Simulation time 112570324625 ps
CPU time 21.09 seconds
Started Aug 19 06:09:01 PM PDT 24
Finished Aug 19 06:09:22 PM PDT 24
Peak memory 200936 kb
Host smart-82a15af5-30aa-4062-a310-370891ba5ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951235363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.951235363
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.483386910
Short name T911
Test name
Test status
Simulation time 49703896520 ps
CPU time 71.16 seconds
Started Aug 19 06:09:00 PM PDT 24
Finished Aug 19 06:10:11 PM PDT 24
Peak memory 200988 kb
Host smart-476d0c54-e8c8-4113-8a01-6d2b4d7d5d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483386910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.483386910
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3388358697
Short name T841
Test name
Test status
Simulation time 154965303711 ps
CPU time 126.63 seconds
Started Aug 19 06:08:57 PM PDT 24
Finished Aug 19 06:11:04 PM PDT 24
Peak memory 200892 kb
Host smart-67a27d6d-475b-451d-9e0b-cb2584eae266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388358697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3388358697
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2829207320
Short name T976
Test name
Test status
Simulation time 50352186920 ps
CPU time 43.74 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:09:42 PM PDT 24
Peak memory 200828 kb
Host smart-e07b2e80-bb9f-4a2c-b9fc-42f5988c97b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829207320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2829207320
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2437111393
Short name T471
Test name
Test status
Simulation time 44162957 ps
CPU time 0.54 seconds
Started Aug 19 06:06:04 PM PDT 24
Finished Aug 19 06:06:05 PM PDT 24
Peak memory 196292 kb
Host smart-78c67573-67c2-4994-b04c-c17660092299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437111393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2437111393
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3331203865
Short name T895
Test name
Test status
Simulation time 64978408789 ps
CPU time 66.75 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:07:07 PM PDT 24
Peak memory 200872 kb
Host smart-eafd3c1e-c2a6-4a8e-997a-a91a9c83cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331203865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3331203865
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.313184347
Short name T1042
Test name
Test status
Simulation time 9292240000 ps
CPU time 25.62 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 200996 kb
Host smart-43c85f58-f50b-4e2b-8002-89e5c37de2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313184347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.313184347
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3792743456
Short name T992
Test name
Test status
Simulation time 31300264903 ps
CPU time 25.48 seconds
Started Aug 19 06:06:02 PM PDT 24
Finished Aug 19 06:06:28 PM PDT 24
Peak memory 200832 kb
Host smart-ff71e437-3ec5-4e9a-9eff-c290b6cb53f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792743456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3792743456
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1492983726
Short name T912
Test name
Test status
Simulation time 59963718368 ps
CPU time 35.23 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:06:35 PM PDT 24
Peak memory 200844 kb
Host smart-68233927-5cbe-498b-b6ae-7c84b478eeb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492983726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1492983726
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3764479261
Short name T1123
Test name
Test status
Simulation time 68584103216 ps
CPU time 148.62 seconds
Started Aug 19 06:06:04 PM PDT 24
Finished Aug 19 06:08:33 PM PDT 24
Peak memory 200980 kb
Host smart-a876f2e9-d875-4d2b-af9c-ae070b07e608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764479261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3764479261
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4027853398
Short name T960
Test name
Test status
Simulation time 6435581029 ps
CPU time 16.44 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:18 PM PDT 24
Peak memory 200416 kb
Host smart-f812c419-3768-4d46-9337-54d2a3949df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027853398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4027853398
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.712822925
Short name T649
Test name
Test status
Simulation time 14035158162 ps
CPU time 5.78 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:06 PM PDT 24
Peak memory 195612 kb
Host smart-0c4be8cf-753a-4e62-8672-c94d94b5bb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712822925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.712822925
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.364054459
Short name T498
Test name
Test status
Simulation time 4769105264 ps
CPU time 10.55 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:06:11 PM PDT 24
Peak memory 200336 kb
Host smart-765dea5b-2603-4871-932d-2e8076f995b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364054459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.364054459
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1868711576
Short name T755
Test name
Test status
Simulation time 33976053962 ps
CPU time 14.07 seconds
Started Aug 19 06:06:02 PM PDT 24
Finished Aug 19 06:06:17 PM PDT 24
Peak memory 200848 kb
Host smart-f08b12c5-2d2d-4eea-8541-bee5f4917e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868711576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1868711576
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3415716684
Short name T840
Test name
Test status
Simulation time 39556939069 ps
CPU time 53.6 seconds
Started Aug 19 06:06:03 PM PDT 24
Finished Aug 19 06:06:57 PM PDT 24
Peak memory 197200 kb
Host smart-8182e004-da63-4031-b64a-afc64cb586b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415716684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3415716684
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.950982088
Short name T383
Test name
Test status
Simulation time 917423742 ps
CPU time 2.53 seconds
Started Aug 19 06:06:02 PM PDT 24
Finished Aug 19 06:06:05 PM PDT 24
Peak memory 200820 kb
Host smart-22f2a081-7044-4a9b-b9bc-4af637e9386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950982088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.950982088
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2821745463
Short name T1081
Test name
Test status
Simulation time 63701647898 ps
CPU time 144.05 seconds
Started Aug 19 06:06:02 PM PDT 24
Finished Aug 19 06:08:26 PM PDT 24
Peak memory 200940 kb
Host smart-dbb2fb81-c28f-4e9a-aad5-95ee7d43588b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821745463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2821745463
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1169871619
Short name T728
Test name
Test status
Simulation time 14253948491 ps
CPU time 85.55 seconds
Started Aug 19 06:06:03 PM PDT 24
Finished Aug 19 06:07:29 PM PDT 24
Peak memory 217556 kb
Host smart-f9d63c35-79d8-4774-852b-500c91185ee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169871619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1169871619
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1610737564
Short name T1047
Test name
Test status
Simulation time 13164095597 ps
CPU time 26.99 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:28 PM PDT 24
Peak memory 200700 kb
Host smart-c2878f07-29b2-48ea-83cc-392e3f8d3f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610737564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1610737564
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2701698378
Short name T971
Test name
Test status
Simulation time 45015681402 ps
CPU time 75.96 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:07:16 PM PDT 24
Peak memory 200952 kb
Host smart-bdaf8396-e27d-414e-bdc2-e7f1fd86c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701698378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2701698378
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1402470024
Short name T420
Test name
Test status
Simulation time 121967985933 ps
CPU time 204.86 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:12:23 PM PDT 24
Peak memory 200960 kb
Host smart-1893eda3-d010-4110-9732-61cbe4e55712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402470024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1402470024
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.618605285
Short name T320
Test name
Test status
Simulation time 150460409835 ps
CPU time 103.39 seconds
Started Aug 19 06:08:59 PM PDT 24
Finished Aug 19 06:10:43 PM PDT 24
Peak memory 200968 kb
Host smart-6f1c23cf-aaa1-4d1d-aaf3-278a72c78c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618605285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.618605285
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3043595579
Short name T453
Test name
Test status
Simulation time 66531367678 ps
CPU time 121.38 seconds
Started Aug 19 06:08:57 PM PDT 24
Finished Aug 19 06:10:58 PM PDT 24
Peak memory 200944 kb
Host smart-0bd93954-7f76-4cd1-a332-c52dbb5ec9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043595579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3043595579
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1791704723
Short name T1096
Test name
Test status
Simulation time 115905979906 ps
CPU time 25.44 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:09:23 PM PDT 24
Peak memory 200944 kb
Host smart-1a462b82-6e7c-4e1c-98e0-9861d888879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791704723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1791704723
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3062776773
Short name T24
Test name
Test status
Simulation time 68111653521 ps
CPU time 28.15 seconds
Started Aug 19 06:08:57 PM PDT 24
Finished Aug 19 06:09:26 PM PDT 24
Peak memory 200960 kb
Host smart-aca63216-4efd-4f5d-b6f3-a554d8cc4569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062776773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3062776773
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4222287655
Short name T538
Test name
Test status
Simulation time 202735915618 ps
CPU time 416.67 seconds
Started Aug 19 06:08:59 PM PDT 24
Finished Aug 19 06:15:55 PM PDT 24
Peak memory 200980 kb
Host smart-3e0d2da4-fa57-4de5-86b8-24ef60137f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222287655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4222287655
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.134286108
Short name T907
Test name
Test status
Simulation time 25068685196 ps
CPU time 20.41 seconds
Started Aug 19 06:08:56 PM PDT 24
Finished Aug 19 06:09:17 PM PDT 24
Peak memory 200972 kb
Host smart-f195ae92-9102-4f44-85ca-0a10090e0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134286108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.134286108
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.515721526
Short name T651
Test name
Test status
Simulation time 53531384687 ps
CPU time 132.25 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:11:11 PM PDT 24
Peak memory 200876 kb
Host smart-8dcfae13-32e6-4d05-9281-7ba0d13837cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515721526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.515721526
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.274628147
Short name T680
Test name
Test status
Simulation time 13827412 ps
CPU time 0.55 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:03 PM PDT 24
Peak memory 195572 kb
Host smart-9cb0308e-bcdc-4620-a075-7502fee1f4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274628147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.274628147
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2274107885
Short name T604
Test name
Test status
Simulation time 80329074907 ps
CPU time 35.27 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:37 PM PDT 24
Peak memory 200888 kb
Host smart-19b96199-8940-48b6-95f6-f93b238dcf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274107885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2274107885
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2656147092
Short name T853
Test name
Test status
Simulation time 56545442209 ps
CPU time 34.84 seconds
Started Aug 19 06:04:59 PM PDT 24
Finished Aug 19 06:05:34 PM PDT 24
Peak memory 200920 kb
Host smart-cacbc37d-7f8c-4e12-bc3e-dcbb0b80d277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656147092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2656147092
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.287964224
Short name T747
Test name
Test status
Simulation time 91035865616 ps
CPU time 235.57 seconds
Started Aug 19 06:05:03 PM PDT 24
Finished Aug 19 06:08:59 PM PDT 24
Peak memory 200996 kb
Host smart-7165183b-7385-4468-9843-81954123ae55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287964224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.287964224
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.775023172
Short name T795
Test name
Test status
Simulation time 39997382808 ps
CPU time 40.9 seconds
Started Aug 19 06:05:04 PM PDT 24
Finished Aug 19 06:05:45 PM PDT 24
Peak memory 200988 kb
Host smart-ff3efa93-c3e5-42fb-bb18-5fe044fb5cf4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775023172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.775023172
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1138522094
Short name T768
Test name
Test status
Simulation time 131340716734 ps
CPU time 458.48 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:12:40 PM PDT 24
Peak memory 200972 kb
Host smart-6d763cf5-c34f-426f-acc0-f36096ed6c89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138522094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1138522094
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.4077694598
Short name T404
Test name
Test status
Simulation time 13160667705 ps
CPU time 8.26 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:10 PM PDT 24
Peak memory 200888 kb
Host smart-7a2e4655-aab7-4c6f-80db-219d682be428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077694598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.4077694598
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3668433639
Short name T738
Test name
Test status
Simulation time 48819051336 ps
CPU time 47.63 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:05:49 PM PDT 24
Peak memory 209388 kb
Host smart-90290893-3b25-46ba-aba7-71672d9ce89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668433639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3668433639
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.28345610
Short name T1139
Test name
Test status
Simulation time 8416113134 ps
CPU time 352.65 seconds
Started Aug 19 06:05:00 PM PDT 24
Finished Aug 19 06:10:53 PM PDT 24
Peak memory 200944 kb
Host smart-c68ac8db-9470-43f5-a85e-d1d2a1ad5f65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28345610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.28345610
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3066336197
Short name T478
Test name
Test status
Simulation time 1788542928 ps
CPU time 2.56 seconds
Started Aug 19 06:05:00 PM PDT 24
Finished Aug 19 06:05:03 PM PDT 24
Peak memory 198996 kb
Host smart-643ea1ba-90a3-41a0-85c5-2a504c99c51e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066336197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3066336197
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1823521451
Short name T260
Test name
Test status
Simulation time 13310182633 ps
CPU time 24.77 seconds
Started Aug 19 06:05:00 PM PDT 24
Finished Aug 19 06:05:25 PM PDT 24
Peak memory 200972 kb
Host smart-9a8e9c6f-1ef3-4feb-8fdb-cfa85f3d2baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823521451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1823521451
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2743358461
Short name T280
Test name
Test status
Simulation time 1434047989 ps
CPU time 2.8 seconds
Started Aug 19 06:05:03 PM PDT 24
Finished Aug 19 06:05:06 PM PDT 24
Peak memory 196464 kb
Host smart-246eb77a-3ae8-48ba-8ecb-a4394b908c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743358461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2743358461
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.537512956
Short name T28
Test name
Test status
Simulation time 59835372 ps
CPU time 0.9 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:03 PM PDT 24
Peak memory 219044 kb
Host smart-ccd2db40-2d5b-4cf6-b276-cc89ec08384b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537512956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.537512956
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.538401222
Short name T368
Test name
Test status
Simulation time 315232509 ps
CPU time 1.12 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:05:02 PM PDT 24
Peak memory 199508 kb
Host smart-95c90359-98b2-4cfe-b4c2-3f23fce2093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538401222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.538401222
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.963418229
Short name T1166
Test name
Test status
Simulation time 24373594547 ps
CPU time 67.15 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:06:08 PM PDT 24
Peak memory 201136 kb
Host smart-aaee4c73-caaf-4ded-99dc-8081540e0db1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963418229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.963418229
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2901789669
Short name T511
Test name
Test status
Simulation time 46308118843 ps
CPU time 41.66 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:44 PM PDT 24
Peak memory 217404 kb
Host smart-2c1274fa-d06e-4534-a88f-4eb23576c479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901789669 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2901789669
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.661620443
Short name T374
Test name
Test status
Simulation time 798964781 ps
CPU time 2.51 seconds
Started Aug 19 06:04:59 PM PDT 24
Finished Aug 19 06:05:02 PM PDT 24
Peak memory 199312 kb
Host smart-43596108-528b-479d-8ffe-15f63fc56bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661620443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.661620443
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1626121334
Short name T943
Test name
Test status
Simulation time 95380487291 ps
CPU time 38.8 seconds
Started Aug 19 06:05:01 PM PDT 24
Finished Aug 19 06:05:40 PM PDT 24
Peak memory 200964 kb
Host smart-b5038077-c999-4ba1-923f-ca238bf1718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626121334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1626121334
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1787108406
Short name T357
Test name
Test status
Simulation time 132221359 ps
CPU time 0.59 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:06:11 PM PDT 24
Peak memory 196292 kb
Host smart-330374ba-d894-4817-b196-1a464123da8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787108406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1787108406
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1301192876
Short name T1109
Test name
Test status
Simulation time 180583770771 ps
CPU time 261 seconds
Started Aug 19 06:06:06 PM PDT 24
Finished Aug 19 06:10:28 PM PDT 24
Peak memory 200924 kb
Host smart-0a90c5e0-45f9-4d16-a2ae-01e9a3ca48e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301192876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1301192876
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2390285557
Short name T1168
Test name
Test status
Simulation time 43488519034 ps
CPU time 31.86 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:06:39 PM PDT 24
Peak memory 200964 kb
Host smart-07c14ed6-71a0-4dac-b155-a2321d990011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390285557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2390285557
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3682990953
Short name T437
Test name
Test status
Simulation time 23406384617 ps
CPU time 40.83 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:06:48 PM PDT 24
Peak memory 200628 kb
Host smart-646cdc2d-4f03-48ab-b57c-e4bf6eaac5f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682990953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3682990953
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1029988823
Short name T834
Test name
Test status
Simulation time 134754515293 ps
CPU time 581.97 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:15:51 PM PDT 24
Peak memory 200980 kb
Host smart-804794a0-ba4b-4155-aa36-39924b6805fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1029988823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1029988823
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3402777966
Short name T410
Test name
Test status
Simulation time 6317243142 ps
CPU time 4.38 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:06:11 PM PDT 24
Peak memory 199136 kb
Host smart-5a319529-4fa2-44a3-8599-f8980e3ead32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402777966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3402777966
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3782663176
Short name T968
Test name
Test status
Simulation time 11087308132 ps
CPU time 17.94 seconds
Started Aug 19 06:06:00 PM PDT 24
Finished Aug 19 06:06:18 PM PDT 24
Peak memory 198080 kb
Host smart-6733e43c-35d8-4156-951f-173ce1f5b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782663176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3782663176
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3741609709
Short name T369
Test name
Test status
Simulation time 11608485056 ps
CPU time 290.43 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:11:01 PM PDT 24
Peak memory 200992 kb
Host smart-236aa020-6798-4045-8b00-25007dbde93a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741609709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3741609709
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1177228738
Short name T1173
Test name
Test status
Simulation time 5594961025 ps
CPU time 24.6 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:06:32 PM PDT 24
Peak memory 200916 kb
Host smart-c0ce9553-0a45-4e5c-8d94-09c93ef94fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177228738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1177228738
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3280194936
Short name T875
Test name
Test status
Simulation time 34869058996 ps
CPU time 29.01 seconds
Started Aug 19 06:06:03 PM PDT 24
Finished Aug 19 06:06:32 PM PDT 24
Peak memory 200872 kb
Host smart-a2c7f81c-8f21-4219-88dc-ea31e97b769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280194936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3280194936
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3305586577
Short name T364
Test name
Test status
Simulation time 50446010984 ps
CPU time 4.63 seconds
Started Aug 19 06:05:59 PM PDT 24
Finished Aug 19 06:06:04 PM PDT 24
Peak memory 196892 kb
Host smart-0af5cd4c-8841-4446-bde6-391732ff5e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305586577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3305586577
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.967531183
Short name T746
Test name
Test status
Simulation time 5912517319 ps
CPU time 11.9 seconds
Started Aug 19 06:06:01 PM PDT 24
Finished Aug 19 06:06:13 PM PDT 24
Peak memory 200736 kb
Host smart-5fe76c61-ce62-4991-8f09-dedbcac3ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967531183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.967531183
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2378855955
Short name T804
Test name
Test status
Simulation time 163707476921 ps
CPU time 230.8 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:10:01 PM PDT 24
Peak memory 200984 kb
Host smart-d8357078-20ab-4f18-a792-1ed40471bfe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378855955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2378855955
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3790343208
Short name T555
Test name
Test status
Simulation time 5219685904 ps
CPU time 21.16 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:06:29 PM PDT 24
Peak memory 216672 kb
Host smart-a5c0fa48-d80a-4dcd-9c0b-fd5189d106c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790343208 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3790343208
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2199763174
Short name T969
Test name
Test status
Simulation time 1387108255 ps
CPU time 1.5 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:06:09 PM PDT 24
Peak memory 199188 kb
Host smart-c0e6fda2-52e0-4799-b0e1-21da634a4d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199763174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2199763174
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2922281504
Short name T506
Test name
Test status
Simulation time 59007926507 ps
CPU time 26.55 seconds
Started Aug 19 06:06:03 PM PDT 24
Finished Aug 19 06:06:30 PM PDT 24
Peak memory 200756 kb
Host smart-97eadd61-8ce1-4e96-8a2b-c4b19b0a9d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922281504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2922281504
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1794916923
Short name T534
Test name
Test status
Simulation time 76693680189 ps
CPU time 66.98 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:10:05 PM PDT 24
Peak memory 200896 kb
Host smart-d5b79122-2047-427c-abaf-ebf1ac9cdaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794916923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1794916923
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.336550447
Short name T910
Test name
Test status
Simulation time 133426215668 ps
CPU time 112.58 seconds
Started Aug 19 06:09:02 PM PDT 24
Finished Aug 19 06:10:54 PM PDT 24
Peak memory 200992 kb
Host smart-6aa55485-2585-4dca-a340-5450f40be703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336550447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.336550447
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1493101608
Short name T913
Test name
Test status
Simulation time 7046955125 ps
CPU time 4.44 seconds
Started Aug 19 06:08:58 PM PDT 24
Finished Aug 19 06:09:03 PM PDT 24
Peak memory 200844 kb
Host smart-ba4bdaf9-4d90-4a90-9a3b-471bb25acc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493101608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1493101608
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.632103233
Short name T893
Test name
Test status
Simulation time 67581883683 ps
CPU time 44.91 seconds
Started Aug 19 06:09:03 PM PDT 24
Finished Aug 19 06:09:48 PM PDT 24
Peak memory 200996 kb
Host smart-ce80acc8-ad28-43e2-879d-1534976a03b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632103233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.632103233
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.290026507
Short name T262
Test name
Test status
Simulation time 29969255984 ps
CPU time 12.48 seconds
Started Aug 19 06:09:00 PM PDT 24
Finished Aug 19 06:09:13 PM PDT 24
Peak memory 200992 kb
Host smart-a9ea9b20-138a-4f4c-afc4-c72883ce3aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290026507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.290026507
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1342327102
Short name T685
Test name
Test status
Simulation time 120395742934 ps
CPU time 182.63 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:12:11 PM PDT 24
Peak memory 200936 kb
Host smart-8fe2b8f4-a481-4517-8ce6-81fb6d880d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342327102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1342327102
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1871077250
Short name T38
Test name
Test status
Simulation time 80891568882 ps
CPU time 58.74 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:10:07 PM PDT 24
Peak memory 200776 kb
Host smart-bf104d2c-b569-402b-810e-6087c652be7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871077250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1871077250
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3096124838
Short name T815
Test name
Test status
Simulation time 15975774603 ps
CPU time 12.67 seconds
Started Aug 19 06:09:09 PM PDT 24
Finished Aug 19 06:09:21 PM PDT 24
Peak memory 200476 kb
Host smart-c7dbbaa0-9f8e-408c-a9e3-a46d4e96d264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096124838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3096124838
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3396310674
Short name T47
Test name
Test status
Simulation time 30109309925 ps
CPU time 13.67 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:09:22 PM PDT 24
Peak memory 201008 kb
Host smart-ece9308a-72e7-4c6f-a1d2-851a3f0fec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396310674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3396310674
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1238955836
Short name T1076
Test name
Test status
Simulation time 44411475 ps
CPU time 0.57 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:06:11 PM PDT 24
Peak memory 196280 kb
Host smart-dc86c469-367e-492c-8bec-2fa3d5d90447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238955836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1238955836
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2959367761
Short name T484
Test name
Test status
Simulation time 102371074660 ps
CPU time 143.09 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:08:30 PM PDT 24
Peak memory 200968 kb
Host smart-215e0a19-6b3b-445a-86e0-dc4283b6ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959367761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2959367761
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.4224952659
Short name T335
Test name
Test status
Simulation time 50506394013 ps
CPU time 56.56 seconds
Started Aug 19 06:06:06 PM PDT 24
Finished Aug 19 06:07:03 PM PDT 24
Peak memory 200948 kb
Host smart-2e723f3b-85ca-443f-8ead-5d103afd3a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224952659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.4224952659
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.195515476
Short name T740
Test name
Test status
Simulation time 8974632482 ps
CPU time 8.45 seconds
Started Aug 19 06:06:09 PM PDT 24
Finished Aug 19 06:06:17 PM PDT 24
Peak memory 200720 kb
Host smart-7ae4b902-4590-4378-b56b-b5d64de18652
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195515476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.195515476
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3198231083
Short name T589
Test name
Test status
Simulation time 170826851232 ps
CPU time 567.53 seconds
Started Aug 19 06:06:06 PM PDT 24
Finished Aug 19 06:15:34 PM PDT 24
Peak memory 201160 kb
Host smart-fe0617c2-bf35-424d-af98-9231ecb4980d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198231083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3198231083
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2912234753
Short name T925
Test name
Test status
Simulation time 4435376063 ps
CPU time 3.15 seconds
Started Aug 19 06:06:11 PM PDT 24
Finished Aug 19 06:06:14 PM PDT 24
Peak memory 199032 kb
Host smart-3e06d0d4-1d1d-4fb6-b497-9d3a04722236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912234753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2912234753
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.310029793
Short name T877
Test name
Test status
Simulation time 53483372216 ps
CPU time 59.05 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:07:09 PM PDT 24
Peak memory 201140 kb
Host smart-ea28a06b-0c13-4f33-9aa9-6d01dc055f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310029793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.310029793
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3783847046
Short name T857
Test name
Test status
Simulation time 20363041730 ps
CPU time 557.48 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:15:25 PM PDT 24
Peak memory 201004 kb
Host smart-d9ee0e21-78ca-4f48-a7db-4251fb766635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783847046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3783847046
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.672359732
Short name T529
Test name
Test status
Simulation time 5335359851 ps
CPU time 12.34 seconds
Started Aug 19 06:06:09 PM PDT 24
Finished Aug 19 06:06:21 PM PDT 24
Peak memory 200860 kb
Host smart-49cfaba0-5b8c-4509-93e6-f08efac416c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672359732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.672359732
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3645178476
Short name T174
Test name
Test status
Simulation time 33210716025 ps
CPU time 26.43 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:06:37 PM PDT 24
Peak memory 200544 kb
Host smart-7c4b24c7-7c78-404b-892e-ff00e37e3235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645178476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3645178476
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1721582847
Short name T1039
Test name
Test status
Simulation time 2361190001 ps
CPU time 1.61 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:06:10 PM PDT 24
Peak memory 196620 kb
Host smart-c92d0cd9-faee-429b-b4e2-797106d9072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721582847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1721582847
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2264095102
Short name T989
Test name
Test status
Simulation time 6287182096 ps
CPU time 15.59 seconds
Started Aug 19 06:06:14 PM PDT 24
Finished Aug 19 06:06:30 PM PDT 24
Peak memory 200788 kb
Host smart-d60c2d64-6a0a-4beb-9299-e628e694372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264095102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2264095102
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3033877205
Short name T548
Test name
Test status
Simulation time 204128359228 ps
CPU time 342.91 seconds
Started Aug 19 06:06:07 PM PDT 24
Finished Aug 19 06:11:50 PM PDT 24
Peak memory 200924 kb
Host smart-a3c958c6-f2c4-4a7d-a737-0aa1d0fd8576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033877205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3033877205
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3560720606
Short name T868
Test name
Test status
Simulation time 23222251958 ps
CPU time 44.88 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:06:55 PM PDT 24
Peak memory 217552 kb
Host smart-356eac5d-cc73-445a-9bdb-e55b10e9ac1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560720606 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3560720606
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.876436775
Short name T483
Test name
Test status
Simulation time 12775037579 ps
CPU time 43.96 seconds
Started Aug 19 06:06:11 PM PDT 24
Finished Aug 19 06:06:55 PM PDT 24
Peak memory 200984 kb
Host smart-8a73e34f-c4f6-4c78-a4b7-8c22e1038019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876436775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.876436775
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1116598629
Short name T504
Test name
Test status
Simulation time 110719340049 ps
CPU time 130.73 seconds
Started Aug 19 06:06:14 PM PDT 24
Finished Aug 19 06:08:25 PM PDT 24
Peak memory 200896 kb
Host smart-6a8bb6b6-e597-4b7b-90f3-09ba47c54729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116598629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1116598629
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1918841292
Short name T692
Test name
Test status
Simulation time 81322320624 ps
CPU time 32.26 seconds
Started Aug 19 06:09:10 PM PDT 24
Finished Aug 19 06:09:43 PM PDT 24
Peak memory 201064 kb
Host smart-ffe87da0-7afe-474e-bf76-3cdf7c0b2580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918841292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1918841292
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1317894749
Short name T310
Test name
Test status
Simulation time 95157519003 ps
CPU time 16.25 seconds
Started Aug 19 06:09:11 PM PDT 24
Finished Aug 19 06:09:28 PM PDT 24
Peak memory 200956 kb
Host smart-b71cf629-2292-4ecf-b750-8383aa8ad6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317894749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1317894749
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2400814725
Short name T833
Test name
Test status
Simulation time 36246478184 ps
CPU time 16.03 seconds
Started Aug 19 06:09:09 PM PDT 24
Finished Aug 19 06:09:25 PM PDT 24
Peak memory 200952 kb
Host smart-fe9f7286-eb4a-41f5-b47b-fa37f745cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400814725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2400814725
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.481516226
Short name T150
Test name
Test status
Simulation time 94354079431 ps
CPU time 49.39 seconds
Started Aug 19 06:09:09 PM PDT 24
Finished Aug 19 06:09:58 PM PDT 24
Peak memory 200972 kb
Host smart-2a7b4cf6-bc3b-4f46-ad3e-fdae5ce3e9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481516226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.481516226
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4246861319
Short name T126
Test name
Test status
Simulation time 89459033062 ps
CPU time 438.99 seconds
Started Aug 19 06:09:15 PM PDT 24
Finished Aug 19 06:16:34 PM PDT 24
Peak memory 200936 kb
Host smart-88bcc4fd-a778-42aa-bc42-3b2c8d093e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246861319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4246861319
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.4222090510
Short name T116
Test name
Test status
Simulation time 91926074574 ps
CPU time 63.84 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:10:12 PM PDT 24
Peak memory 200964 kb
Host smart-eb191836-6879-4339-bdbd-8d7d912a0c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222090510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.4222090510
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3555742088
Short name T675
Test name
Test status
Simulation time 32127889353 ps
CPU time 26.02 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:09:34 PM PDT 24
Peak memory 200884 kb
Host smart-10eefc8e-e43a-46bc-85d7-e1d5991c46ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555742088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3555742088
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3548328809
Short name T758
Test name
Test status
Simulation time 35941981953 ps
CPU time 30.03 seconds
Started Aug 19 06:09:16 PM PDT 24
Finished Aug 19 06:09:46 PM PDT 24
Peak memory 200932 kb
Host smart-3d1c8b10-657b-4bc6-b586-17ac275f6963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548328809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3548328809
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4039673387
Short name T721
Test name
Test status
Simulation time 46473503604 ps
CPU time 16.18 seconds
Started Aug 19 06:09:11 PM PDT 24
Finished Aug 19 06:09:28 PM PDT 24
Peak memory 200920 kb
Host smart-3c353d35-482d-4c32-89b9-3eaaefcee40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039673387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4039673387
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4203544513
Short name T358
Test name
Test status
Simulation time 28838335 ps
CPU time 0.53 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:23 PM PDT 24
Peak memory 196280 kb
Host smart-b194ff3d-7395-42e8-8216-363e7a363534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203544513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4203544513
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.654059141
Short name T99
Test name
Test status
Simulation time 55657706102 ps
CPU time 62.93 seconds
Started Aug 19 06:06:14 PM PDT 24
Finished Aug 19 06:07:17 PM PDT 24
Peak memory 200884 kb
Host smart-6eab2d23-b88d-45a4-bfeb-803947f27976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654059141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.654059141
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3832948376
Short name T1136
Test name
Test status
Simulation time 46076112624 ps
CPU time 85.31 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:07:34 PM PDT 24
Peak memory 200980 kb
Host smart-4a78f8fd-4ac3-4df1-bcd0-7aaf352642b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832948376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3832948376
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.732930526
Short name T797
Test name
Test status
Simulation time 43769151906 ps
CPU time 16.99 seconds
Started Aug 19 06:06:11 PM PDT 24
Finished Aug 19 06:06:28 PM PDT 24
Peak memory 200832 kb
Host smart-ac37901a-df0b-472a-b673-8c2338044c1d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732930526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.732930526
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1854901099
Short name T695
Test name
Test status
Simulation time 106472912477 ps
CPU time 592.2 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:16:03 PM PDT 24
Peak memory 200976 kb
Host smart-560073c4-486e-4044-bef3-ee521acf1c64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854901099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1854901099
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2747335455
Short name T1065
Test name
Test status
Simulation time 99044639 ps
CPU time 0.64 seconds
Started Aug 19 06:06:11 PM PDT 24
Finished Aug 19 06:06:12 PM PDT 24
Peak memory 196916 kb
Host smart-ae6ab0fc-6d64-4358-80f0-7b77c61c3a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747335455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2747335455
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.112327397
Short name T716
Test name
Test status
Simulation time 106584270359 ps
CPU time 188.71 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:09:17 PM PDT 24
Peak memory 209340 kb
Host smart-4d6007fc-3ee0-4402-949b-e83990ff6a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112327397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.112327397
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.4017254753
Short name T805
Test name
Test status
Simulation time 13056577029 ps
CPU time 330.95 seconds
Started Aug 19 06:06:14 PM PDT 24
Finished Aug 19 06:11:45 PM PDT 24
Peak memory 200996 kb
Host smart-97957e4a-8c58-4a83-adb0-387fdec2be23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017254753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4017254753
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.4148537
Short name T353
Test name
Test status
Simulation time 2113380223 ps
CPU time 11.99 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:06:20 PM PDT 24
Peak memory 199024 kb
Host smart-9584700d-bdef-4273-9400-e2108cbbbc31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4148537
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1289545874
Short name T114
Test name
Test status
Simulation time 4743743932 ps
CPU time 8.6 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:06:16 PM PDT 24
Peak memory 200164 kb
Host smart-eaf50dc0-610e-4410-9170-eb5fa5bc8c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289545874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1289545874
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.500858559
Short name T389
Test name
Test status
Simulation time 76607450506 ps
CPU time 12.38 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:06:20 PM PDT 24
Peak memory 197292 kb
Host smart-4ef064f4-6718-4ba2-a84b-a7c964218f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500858559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.500858559
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2282309261
Short name T544
Test name
Test status
Simulation time 5359123201 ps
CPU time 15.95 seconds
Started Aug 19 06:06:08 PM PDT 24
Finished Aug 19 06:06:24 PM PDT 24
Peak memory 200824 kb
Host smart-27f03847-010d-4d1d-b6e5-69b64e2ca80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282309261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2282309261
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2026699233
Short name T137
Test name
Test status
Simulation time 78986433698 ps
CPU time 19.06 seconds
Started Aug 19 06:06:18 PM PDT 24
Finished Aug 19 06:06:38 PM PDT 24
Peak memory 200908 kb
Host smart-9f15302e-a1dc-4c36-ab56-051c2586ff86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026699233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2026699233
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2577107776
Short name T850
Test name
Test status
Simulation time 1120764283 ps
CPU time 2.33 seconds
Started Aug 19 06:06:10 PM PDT 24
Finished Aug 19 06:06:12 PM PDT 24
Peak memory 199864 kb
Host smart-bc649c99-4718-483b-b35e-134c5e56f392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577107776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2577107776
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.4285647813
Short name T388
Test name
Test status
Simulation time 61356846401 ps
CPU time 13.93 seconds
Started Aug 19 06:09:15 PM PDT 24
Finished Aug 19 06:09:29 PM PDT 24
Peak memory 200924 kb
Host smart-217f4b9a-93df-4145-9590-15bb13614baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285647813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4285647813
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2950424531
Short name T112
Test name
Test status
Simulation time 48127549278 ps
CPU time 63.67 seconds
Started Aug 19 06:09:10 PM PDT 24
Finished Aug 19 06:10:13 PM PDT 24
Peak memory 200832 kb
Host smart-a6ac4275-16ba-4de5-9257-df35a3cdc0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950424531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2950424531
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4222751608
Short name T89
Test name
Test status
Simulation time 19213276910 ps
CPU time 35.36 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:09:44 PM PDT 24
Peak memory 200924 kb
Host smart-975c04ff-eab7-45f5-9d34-af3a1ea8f6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222751608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4222751608
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.62816512
Short name T869
Test name
Test status
Simulation time 203225366124 ps
CPU time 46.17 seconds
Started Aug 19 06:09:10 PM PDT 24
Finished Aug 19 06:09:57 PM PDT 24
Peak memory 200992 kb
Host smart-fb57206f-55ed-4a90-835f-0165a2160dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62816512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.62816512
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1590187213
Short name T736
Test name
Test status
Simulation time 92979704129 ps
CPU time 21.68 seconds
Started Aug 19 06:09:14 PM PDT 24
Finished Aug 19 06:09:36 PM PDT 24
Peak memory 200864 kb
Host smart-6763f9a8-833a-432d-947e-3e2dc8424bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590187213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1590187213
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3152787092
Short name T974
Test name
Test status
Simulation time 48110349559 ps
CPU time 18.63 seconds
Started Aug 19 06:09:14 PM PDT 24
Finished Aug 19 06:09:33 PM PDT 24
Peak memory 200852 kb
Host smart-87537ae8-4b4a-4888-b666-1b8212f25300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152787092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3152787092
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2469152818
Short name T151
Test name
Test status
Simulation time 127042579439 ps
CPU time 20.04 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:09:29 PM PDT 24
Peak memory 200960 kb
Host smart-e4f6e2a5-8d12-4f70-a164-4aee4d51e25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469152818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2469152818
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2670081418
Short name T147
Test name
Test status
Simulation time 30848369458 ps
CPU time 10.05 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:09:19 PM PDT 24
Peak memory 200908 kb
Host smart-05ec8e13-2c0f-4bf8-9073-a160d825c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670081418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2670081418
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3479743221
Short name T408
Test name
Test status
Simulation time 39134790431 ps
CPU time 15.65 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:09:24 PM PDT 24
Peak memory 200008 kb
Host smart-d6d08d0d-1d5e-4846-9bc5-e43390431cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479743221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3479743221
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3526916195
Short name T553
Test name
Test status
Simulation time 69320252741 ps
CPU time 38.9 seconds
Started Aug 19 06:09:08 PM PDT 24
Finished Aug 19 06:09:47 PM PDT 24
Peak memory 200932 kb
Host smart-f95995ee-5f77-4db5-8ad8-211ceb5e8301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526916195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3526916195
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.248930734
Short name T763
Test name
Test status
Simulation time 50517161 ps
CPU time 0.56 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:23 PM PDT 24
Peak memory 196268 kb
Host smart-07712261-be4e-4c3d-b895-5cceb443fc53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248930734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.248930734
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2422797202
Short name T438
Test name
Test status
Simulation time 34370877027 ps
CPU time 59.82 seconds
Started Aug 19 06:06:20 PM PDT 24
Finished Aug 19 06:07:20 PM PDT 24
Peak memory 200960 kb
Host smart-93c7db22-06e9-48c3-b05f-f491752b86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422797202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2422797202
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3030860382
Short name T870
Test name
Test status
Simulation time 34417286824 ps
CPU time 85.03 seconds
Started Aug 19 06:06:19 PM PDT 24
Finished Aug 19 06:07:44 PM PDT 24
Peak memory 200984 kb
Host smart-e1b9275f-dc6d-4fd3-ba8f-5018614f4900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030860382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3030860382
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3555315013
Short name T543
Test name
Test status
Simulation time 82939583345 ps
CPU time 25.95 seconds
Started Aug 19 06:06:23 PM PDT 24
Finished Aug 19 06:06:49 PM PDT 24
Peak memory 200892 kb
Host smart-04e80992-a2a5-426c-822e-9f9c69058f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555315013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3555315013
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2182530049
Short name T961
Test name
Test status
Simulation time 7242706366 ps
CPU time 2.7 seconds
Started Aug 19 06:06:20 PM PDT 24
Finished Aug 19 06:06:23 PM PDT 24
Peak memory 197520 kb
Host smart-36654f7e-80f6-4680-ad64-bee5dab6dec5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182530049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2182530049
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.814952015
Short name T278
Test name
Test status
Simulation time 104053318485 ps
CPU time 503.64 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:14:46 PM PDT 24
Peak memory 200976 kb
Host smart-1c4a8610-5d3a-4ce3-af94-ed1190af7caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814952015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.814952015
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1371179769
Short name T542
Test name
Test status
Simulation time 1768193764 ps
CPU time 2.31 seconds
Started Aug 19 06:06:23 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 199548 kb
Host smart-6ed5e131-39c1-48c5-a463-7c1e7d692430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371179769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1371179769
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3720890315
Short name T633
Test name
Test status
Simulation time 78837069635 ps
CPU time 124.78 seconds
Started Aug 19 06:06:24 PM PDT 24
Finished Aug 19 06:08:29 PM PDT 24
Peak memory 201200 kb
Host smart-4ebaa656-9d1e-4f87-bd0c-3648fa379241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720890315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3720890315
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.219946295
Short name T682
Test name
Test status
Simulation time 3136511974 ps
CPU time 175.89 seconds
Started Aug 19 06:06:20 PM PDT 24
Finished Aug 19 06:09:16 PM PDT 24
Peak memory 201000 kb
Host smart-6f8a8871-3f65-4c13-8f6c-f0e01bb38d74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219946295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.219946295
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2819127565
Short name T479
Test name
Test status
Simulation time 3670101659 ps
CPU time 31.25 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:53 PM PDT 24
Peak memory 198904 kb
Host smart-46524e1b-2d5c-4564-9502-72aad44b50fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2819127565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2819127565
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3951003412
Short name T257
Test name
Test status
Simulation time 13699218066 ps
CPU time 30.42 seconds
Started Aug 19 06:06:24 PM PDT 24
Finished Aug 19 06:06:54 PM PDT 24
Peak memory 200980 kb
Host smart-d9a55871-7ad3-41ce-aa4c-bcbd1fd185fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951003412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3951003412
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1624345751
Short name T487
Test name
Test status
Simulation time 3649548741 ps
CPU time 4.9 seconds
Started Aug 19 06:06:19 PM PDT 24
Finished Aug 19 06:06:24 PM PDT 24
Peak memory 197064 kb
Host smart-eba76626-f447-4bc0-8306-5471e9b9d608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624345751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1624345751
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1613501794
Short name T838
Test name
Test status
Simulation time 269312560 ps
CPU time 1.66 seconds
Started Aug 19 06:06:23 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 200028 kb
Host smart-6c948731-11eb-42ff-a81a-bb62b7a9d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613501794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1613501794
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2602618439
Short name T924
Test name
Test status
Simulation time 24149996506 ps
CPU time 18.46 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:41 PM PDT 24
Peak memory 200904 kb
Host smart-33ee323c-45e2-4e22-b858-ffdd58056e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602618439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2602618439
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.75451432
Short name T512
Test name
Test status
Simulation time 2713283735 ps
CPU time 66.44 seconds
Started Aug 19 06:06:19 PM PDT 24
Finished Aug 19 06:07:26 PM PDT 24
Peak memory 209420 kb
Host smart-b574d11b-b4d0-4a92-89d3-762d73cc31a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75451432 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.75451432
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3881483948
Short name T756
Test name
Test status
Simulation time 2391632754 ps
CPU time 2.21 seconds
Started Aug 19 06:06:21 PM PDT 24
Finished Aug 19 06:06:23 PM PDT 24
Peak memory 199796 kb
Host smart-a2e8aae5-aa33-470a-a271-49006975b3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881483948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3881483948
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.130531292
Short name T1116
Test name
Test status
Simulation time 106167310052 ps
CPU time 22.67 seconds
Started Aug 19 06:06:24 PM PDT 24
Finished Aug 19 06:06:46 PM PDT 24
Peak memory 200904 kb
Host smart-e7c3d487-c82c-4c82-b0a6-b49ac1ad8317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130531292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.130531292
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2206570681
Short name T259
Test name
Test status
Simulation time 45444213007 ps
CPU time 64.07 seconds
Started Aug 19 06:09:07 PM PDT 24
Finished Aug 19 06:10:11 PM PDT 24
Peak memory 200944 kb
Host smart-d875161f-353b-414a-9277-d9ce3063ac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206570681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2206570681
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.908585470
Short name T1070
Test name
Test status
Simulation time 79284438657 ps
CPU time 199.62 seconds
Started Aug 19 06:09:11 PM PDT 24
Finished Aug 19 06:12:31 PM PDT 24
Peak memory 200976 kb
Host smart-ffc8e30d-60d1-4fd7-9db3-eb3e4821d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908585470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.908585470
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2310888126
Short name T1099
Test name
Test status
Simulation time 140046359949 ps
CPU time 210.87 seconds
Started Aug 19 06:09:15 PM PDT 24
Finished Aug 19 06:12:46 PM PDT 24
Peak memory 200936 kb
Host smart-79330d44-1d75-41fb-931b-e970f0257dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310888126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2310888126
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3569234507
Short name T723
Test name
Test status
Simulation time 16255683171 ps
CPU time 34.17 seconds
Started Aug 19 06:09:15 PM PDT 24
Finished Aug 19 06:09:50 PM PDT 24
Peak memory 200888 kb
Host smart-e059ded5-7abd-41db-87ee-711efd4eaf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569234507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3569234507
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.633803358
Short name T1058
Test name
Test status
Simulation time 12477002734 ps
CPU time 20.42 seconds
Started Aug 19 06:09:09 PM PDT 24
Finished Aug 19 06:09:30 PM PDT 24
Peak memory 200892 kb
Host smart-41c7858b-4644-4f09-b5b2-09aa58b01cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633803358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.633803358
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.16907225
Short name T1110
Test name
Test status
Simulation time 121093008910 ps
CPU time 205.01 seconds
Started Aug 19 06:09:09 PM PDT 24
Finished Aug 19 06:12:34 PM PDT 24
Peak memory 200932 kb
Host smart-621c6ade-d123-446b-8adf-e390dc1d28c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16907225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.16907225
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.683519559
Short name T955
Test name
Test status
Simulation time 112756417725 ps
CPU time 198.51 seconds
Started Aug 19 06:09:16 PM PDT 24
Finished Aug 19 06:12:34 PM PDT 24
Peak memory 200876 kb
Host smart-ea69b8f2-f485-4ac2-bd41-7b69c8fc9cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683519559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.683519559
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1910403317
Short name T1026
Test name
Test status
Simulation time 112636857869 ps
CPU time 88.88 seconds
Started Aug 19 06:09:18 PM PDT 24
Finished Aug 19 06:10:47 PM PDT 24
Peak memory 200932 kb
Host smart-e500aa7c-af97-4922-a446-b6603061dd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910403317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1910403317
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1371994156
Short name T337
Test name
Test status
Simulation time 127679571465 ps
CPU time 36.78 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:09:58 PM PDT 24
Peak memory 200928 kb
Host smart-9fa99a2f-c695-4bde-b349-db2bfa00cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371994156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1371994156
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2506576430
Short name T930
Test name
Test status
Simulation time 34345579 ps
CPU time 0.55 seconds
Started Aug 19 06:06:29 PM PDT 24
Finished Aug 19 06:06:29 PM PDT 24
Peak memory 196268 kb
Host smart-6948c4ac-24a0-45b4-b383-39b79fbba9bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506576430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2506576430
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.733877986
Short name T317
Test name
Test status
Simulation time 249278038894 ps
CPU time 224.48 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:10:07 PM PDT 24
Peak memory 200972 kb
Host smart-c7cbc882-eaa9-420c-b5cb-03b43fd19166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733877986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.733877986
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3303832005
Short name T1104
Test name
Test status
Simulation time 151438816145 ps
CPU time 123.36 seconds
Started Aug 19 06:06:24 PM PDT 24
Finished Aug 19 06:08:27 PM PDT 24
Peak memory 200952 kb
Host smart-0d29315f-14b2-42b6-a0b9-62e9643dc3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303832005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3303832005
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1861632000
Short name T759
Test name
Test status
Simulation time 180001923132 ps
CPU time 332.4 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:11:55 PM PDT 24
Peak memory 200976 kb
Host smart-e21f923b-013b-4a4e-9451-45f9895988f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861632000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1861632000
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1415633851
Short name T905
Test name
Test status
Simulation time 44252713620 ps
CPU time 19.57 seconds
Started Aug 19 06:06:20 PM PDT 24
Finished Aug 19 06:06:40 PM PDT 24
Peak memory 200852 kb
Host smart-27de28aa-50ad-42fa-8626-9d459379497d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415633851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1415633851
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1177215435
Short name T628
Test name
Test status
Simulation time 88944507782 ps
CPU time 791.55 seconds
Started Aug 19 06:06:23 PM PDT 24
Finished Aug 19 06:19:34 PM PDT 24
Peak memory 200892 kb
Host smart-4c234939-3b92-45d1-99aa-30c06d0c0245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177215435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1177215435
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3141422787
Short name T655
Test name
Test status
Simulation time 5549933744 ps
CPU time 4.56 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:26 PM PDT 24
Peak memory 200872 kb
Host smart-868614d6-173f-482e-9a76-f79fa586e023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141422787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3141422787
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1888408573
Short name T526
Test name
Test status
Simulation time 23272925417 ps
CPU time 10.61 seconds
Started Aug 19 06:06:19 PM PDT 24
Finished Aug 19 06:06:29 PM PDT 24
Peak memory 197064 kb
Host smart-8b81d905-ae77-4a3e-b8ea-2d0d48cec4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888408573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1888408573
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.164529145
Short name T83
Test name
Test status
Simulation time 1874185585 ps
CPU time 112.59 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:08:15 PM PDT 24
Peak memory 200912 kb
Host smart-8ade8590-770d-40f0-8fa4-6d379cd6912e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164529145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.164529145
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.961270257
Short name T325
Test name
Test status
Simulation time 6793191296 ps
CPU time 16.53 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:38 PM PDT 24
Peak memory 199200 kb
Host smart-2eab4146-4cd0-4b73-a4d1-0fda873c6f7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961270257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.961270257
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3349438483
Short name T867
Test name
Test status
Simulation time 7444517284 ps
CPU time 11.06 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:33 PM PDT 24
Peak memory 197104 kb
Host smart-8e3d4109-72f9-4a41-8d71-af45beff9a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349438483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3349438483
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1220787494
Short name T447
Test name
Test status
Simulation time 88813869 ps
CPU time 0.87 seconds
Started Aug 19 06:06:24 PM PDT 24
Finished Aug 19 06:06:25 PM PDT 24
Peak memory 197788 kb
Host smart-677da5a6-0422-4d54-bbb1-b7e6f7dac1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220787494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1220787494
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2001849212
Short name T859
Test name
Test status
Simulation time 2269341070 ps
CPU time 28.09 seconds
Started Aug 19 06:06:22 PM PDT 24
Finished Aug 19 06:06:50 PM PDT 24
Peak memory 201100 kb
Host smart-062a0f47-1be2-45b5-8232-1a1195de3a44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001849212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2001849212
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2613649394
Short name T822
Test name
Test status
Simulation time 933191921 ps
CPU time 3.72 seconds
Started Aug 19 06:06:23 PM PDT 24
Finished Aug 19 06:06:27 PM PDT 24
Peak memory 199344 kb
Host smart-80c0bdd6-c36e-4dd7-a31e-4bd6954e9b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613649394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2613649394
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4126704428
Short name T1085
Test name
Test status
Simulation time 189655370878 ps
CPU time 52.67 seconds
Started Aug 19 06:06:20 PM PDT 24
Finished Aug 19 06:07:13 PM PDT 24
Peak memory 200956 kb
Host smart-fc24317b-ac40-4454-80c1-5aea29f6601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126704428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4126704428
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3325051983
Short name T547
Test name
Test status
Simulation time 15918312631 ps
CPU time 26.04 seconds
Started Aug 19 06:09:24 PM PDT 24
Finished Aug 19 06:09:50 PM PDT 24
Peak memory 201008 kb
Host smart-768fe12f-1481-40da-a821-17c9947633fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325051983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3325051983
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1475417239
Short name T192
Test name
Test status
Simulation time 120166034179 ps
CPU time 193.64 seconds
Started Aug 19 06:09:22 PM PDT 24
Finished Aug 19 06:12:36 PM PDT 24
Peak memory 200996 kb
Host smart-cb99ac06-ac26-413c-beac-6245616fe845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475417239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1475417239
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4117496422
Short name T402
Test name
Test status
Simulation time 18134556112 ps
CPU time 28.69 seconds
Started Aug 19 06:09:22 PM PDT 24
Finished Aug 19 06:09:51 PM PDT 24
Peak memory 200908 kb
Host smart-28cf5c91-0a78-4c47-8a6a-5c44161c5e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117496422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4117496422
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4163102423
Short name T610
Test name
Test status
Simulation time 147444523205 ps
CPU time 33.21 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:09:54 PM PDT 24
Peak memory 200876 kb
Host smart-0b5ab7de-b3b8-45a7-b376-cef67208ff47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163102423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4163102423
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1280106929
Short name T233
Test name
Test status
Simulation time 22113303388 ps
CPU time 44.16 seconds
Started Aug 19 06:09:22 PM PDT 24
Finished Aug 19 06:10:06 PM PDT 24
Peak memory 200976 kb
Host smart-c6d2646a-dfd9-468f-a1bd-a6a6216af1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280106929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1280106929
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1690163949
Short name T141
Test name
Test status
Simulation time 187575694428 ps
CPU time 30.15 seconds
Started Aug 19 06:09:24 PM PDT 24
Finished Aug 19 06:09:54 PM PDT 24
Peak memory 200672 kb
Host smart-803f79c3-10ce-475f-a41a-a36f24cbe4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690163949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1690163949
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2212645202
Short name T847
Test name
Test status
Simulation time 84327115537 ps
CPU time 62.44 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:10:23 PM PDT 24
Peak memory 200936 kb
Host smart-751aba90-cefd-4bdb-b86d-c948e12aad48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212645202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2212645202
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.149997961
Short name T198
Test name
Test status
Simulation time 100991932283 ps
CPU time 98.65 seconds
Started Aug 19 06:09:19 PM PDT 24
Finished Aug 19 06:10:58 PM PDT 24
Peak memory 200980 kb
Host smart-a5bc1e18-0dbc-419b-8a5e-d37ee024b8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149997961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.149997961
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.394542369
Short name T2
Test name
Test status
Simulation time 42985134 ps
CPU time 0.53 seconds
Started Aug 19 06:06:28 PM PDT 24
Finished Aug 19 06:06:29 PM PDT 24
Peak memory 196588 kb
Host smart-d41d7c20-1cef-4437-b79e-52d3a973d548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394542369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.394542369
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.940026
Short name T1044
Test name
Test status
Simulation time 46522443142 ps
CPU time 68.83 seconds
Started Aug 19 06:06:30 PM PDT 24
Finished Aug 19 06:07:39 PM PDT 24
Peak memory 200920 kb
Host smart-896e7d59-ea36-4e0f-a1eb-30083bcd1505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.940026
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1831581805
Short name T831
Test name
Test status
Simulation time 73472052214 ps
CPU time 11.07 seconds
Started Aug 19 06:06:34 PM PDT 24
Finished Aug 19 06:06:45 PM PDT 24
Peak memory 200932 kb
Host smart-aae9047b-a9d1-4e54-89af-51425f029f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831581805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1831581805
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2948567906
Short name T46
Test name
Test status
Simulation time 67702640496 ps
CPU time 99.98 seconds
Started Aug 19 06:06:27 PM PDT 24
Finished Aug 19 06:08:07 PM PDT 24
Peak memory 200988 kb
Host smart-f264f4cb-8b75-4944-bb41-37adb7faa496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948567906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2948567906
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2081472107
Short name T331
Test name
Test status
Simulation time 35918899658 ps
CPU time 60.68 seconds
Started Aug 19 06:06:31 PM PDT 24
Finished Aug 19 06:07:32 PM PDT 24
Peak memory 200912 kb
Host smart-683e7f1f-72cc-4f44-b9e9-2157aa03f386
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081472107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2081472107
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3356947626
Short name T264
Test name
Test status
Simulation time 105581864421 ps
CPU time 282.69 seconds
Started Aug 19 06:06:30 PM PDT 24
Finished Aug 19 06:11:12 PM PDT 24
Peak memory 200980 kb
Host smart-d12ca652-5e4a-4337-9f63-31f8b4ae5bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356947626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3356947626
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2790753102
Short name T706
Test name
Test status
Simulation time 7612151361 ps
CPU time 2.5 seconds
Started Aug 19 06:06:32 PM PDT 24
Finished Aug 19 06:06:35 PM PDT 24
Peak memory 199920 kb
Host smart-bffbf133-3a86-4318-8d0a-b429538bdb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790753102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2790753102
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3512949531
Short name T530
Test name
Test status
Simulation time 336109206577 ps
CPU time 49.53 seconds
Started Aug 19 06:06:28 PM PDT 24
Finished Aug 19 06:07:18 PM PDT 24
Peak memory 201180 kb
Host smart-0dbfeffa-ba7b-4ae7-837f-ef0a052cf426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512949531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3512949531
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3871333398
Short name T243
Test name
Test status
Simulation time 13939891085 ps
CPU time 742.75 seconds
Started Aug 19 06:06:29 PM PDT 24
Finished Aug 19 06:18:52 PM PDT 24
Peak memory 200916 kb
Host smart-e1974276-15cd-4154-b3aa-84219b456d26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871333398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3871333398
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.24256067
Short name T872
Test name
Test status
Simulation time 4229910049 ps
CPU time 8.98 seconds
Started Aug 19 06:06:31 PM PDT 24
Finished Aug 19 06:06:40 PM PDT 24
Peak memory 199096 kb
Host smart-6943dda3-e15b-4bd4-863f-5d25e315dd63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24256067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.24256067
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3436118730
Short name T959
Test name
Test status
Simulation time 101424978198 ps
CPU time 40.17 seconds
Started Aug 19 06:06:28 PM PDT 24
Finished Aug 19 06:07:08 PM PDT 24
Peak memory 200928 kb
Host smart-85fe4892-1753-459d-9446-cf95de12517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436118730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3436118730
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2054234555
Short name T700
Test name
Test status
Simulation time 3283326890 ps
CPU time 2.93 seconds
Started Aug 19 06:06:31 PM PDT 24
Finished Aug 19 06:06:34 PM PDT 24
Peak memory 197272 kb
Host smart-41ba9e5f-a55a-4835-81c0-eeec68a25ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054234555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2054234555
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3430763136
Short name T669
Test name
Test status
Simulation time 5602571857 ps
CPU time 4.58 seconds
Started Aug 19 06:06:32 PM PDT 24
Finished Aug 19 06:06:36 PM PDT 24
Peak memory 200956 kb
Host smart-a941abce-014c-40c2-b572-0cf56edab3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430763136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3430763136
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1720743615
Short name T997
Test name
Test status
Simulation time 320046198997 ps
CPU time 520.45 seconds
Started Aug 19 06:06:31 PM PDT 24
Finished Aug 19 06:15:12 PM PDT 24
Peak memory 200904 kb
Host smart-bbefff53-6025-48c5-ba2f-ed254465b481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720743615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1720743615
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2325888754
Short name T454
Test name
Test status
Simulation time 1671705125 ps
CPU time 2.66 seconds
Started Aug 19 06:06:33 PM PDT 24
Finished Aug 19 06:06:36 PM PDT 24
Peak memory 199252 kb
Host smart-d703f193-b93c-4927-b169-6a54e2afc202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325888754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2325888754
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2847296462
Short name T687
Test name
Test status
Simulation time 30484952419 ps
CPU time 25.38 seconds
Started Aug 19 06:06:29 PM PDT 24
Finished Aug 19 06:06:55 PM PDT 24
Peak memory 200892 kb
Host smart-4ec4b094-62f5-4990-8c0f-43d7e0182a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847296462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2847296462
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2018102163
Short name T168
Test name
Test status
Simulation time 227222990805 ps
CPU time 629.99 seconds
Started Aug 19 06:09:20 PM PDT 24
Finished Aug 19 06:19:51 PM PDT 24
Peak memory 201004 kb
Host smart-04cf3ff4-d861-48ac-aa2c-2683305f2bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018102163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2018102163
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.245937990
Short name T645
Test name
Test status
Simulation time 129274675369 ps
CPU time 53.23 seconds
Started Aug 19 06:09:20 PM PDT 24
Finished Aug 19 06:10:14 PM PDT 24
Peak memory 200872 kb
Host smart-b8a70942-3f9b-418c-a98e-a2bce293818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245937990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.245937990
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.711949018
Short name T879
Test name
Test status
Simulation time 46661156427 ps
CPU time 42.65 seconds
Started Aug 19 06:09:20 PM PDT 24
Finished Aug 19 06:10:03 PM PDT 24
Peak memory 200980 kb
Host smart-a51489ee-ef60-4645-854d-77eff96d7dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711949018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.711949018
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1140554224
Short name T195
Test name
Test status
Simulation time 12535071302 ps
CPU time 18.14 seconds
Started Aug 19 06:09:20 PM PDT 24
Finished Aug 19 06:09:39 PM PDT 24
Peak memory 200992 kb
Host smart-bfce64a1-5f39-41a1-bd15-4959c545d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140554224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1140554224
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2131777120
Short name T312
Test name
Test status
Simulation time 87227050330 ps
CPU time 126.71 seconds
Started Aug 19 06:09:23 PM PDT 24
Finished Aug 19 06:11:29 PM PDT 24
Peak memory 200956 kb
Host smart-774ff4a2-0657-401c-8570-9cde4bfdaab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131777120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2131777120
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1077358230
Short name T1090
Test name
Test status
Simulation time 107727077318 ps
CPU time 169.96 seconds
Started Aug 19 06:09:20 PM PDT 24
Finished Aug 19 06:12:10 PM PDT 24
Peak memory 200960 kb
Host smart-f4c9f34d-4c46-4d9c-a0da-4a536357a39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077358230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1077358230
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2649008924
Short name T196
Test name
Test status
Simulation time 12468548374 ps
CPU time 23.21 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:09:45 PM PDT 24
Peak memory 200900 kb
Host smart-3a3e3b54-8c30-443f-8b7b-f5ca8fbd6757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649008924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2649008924
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2297331747
Short name T760
Test name
Test status
Simulation time 318529207652 ps
CPU time 406.65 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:16:08 PM PDT 24
Peak memory 200940 kb
Host smart-62f5f498-0a47-4fed-a77d-13292f6e9164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297331747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2297331747
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2741948474
Short name T343
Test name
Test status
Simulation time 13792371 ps
CPU time 0.56 seconds
Started Aug 19 06:06:37 PM PDT 24
Finished Aug 19 06:06:37 PM PDT 24
Peak memory 195736 kb
Host smart-cf55423b-cf8b-4da5-a703-8c63a972110c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741948474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2741948474
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1659922991
Short name T128
Test name
Test status
Simulation time 473811781974 ps
CPU time 50.96 seconds
Started Aug 19 06:06:29 PM PDT 24
Finished Aug 19 06:07:20 PM PDT 24
Peak memory 200984 kb
Host smart-c4d18c50-f8af-4080-a8ed-722af66a37ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659922991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1659922991
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2458849653
Short name T145
Test name
Test status
Simulation time 89550576134 ps
CPU time 30.28 seconds
Started Aug 19 06:06:33 PM PDT 24
Finished Aug 19 06:07:03 PM PDT 24
Peak memory 200332 kb
Host smart-5d15c98f-ff81-4703-b907-3aaad8cfee1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458849653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2458849653
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1035915651
Short name T1138
Test name
Test status
Simulation time 184060726478 ps
CPU time 301.65 seconds
Started Aug 19 06:06:29 PM PDT 24
Finished Aug 19 06:11:30 PM PDT 24
Peak memory 200896 kb
Host smart-8a283cde-dc7c-40f2-a02b-5813b592b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035915651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1035915651
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.394401860
Short name T351
Test name
Test status
Simulation time 5387273675 ps
CPU time 9.28 seconds
Started Aug 19 06:06:29 PM PDT 24
Finished Aug 19 06:06:38 PM PDT 24
Peak memory 197752 kb
Host smart-802fd920-db66-47ba-8d83-fe2f8836eacc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394401860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.394401860
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2797159023
Short name T387
Test name
Test status
Simulation time 54858984962 ps
CPU time 387.47 seconds
Started Aug 19 06:06:34 PM PDT 24
Finished Aug 19 06:13:02 PM PDT 24
Peak memory 200980 kb
Host smart-29ccff0d-dafc-4a9f-91ee-488b57b1d34b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2797159023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2797159023
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2289416515
Short name T979
Test name
Test status
Simulation time 10476558875 ps
CPU time 17.86 seconds
Started Aug 19 06:06:30 PM PDT 24
Finished Aug 19 06:06:48 PM PDT 24
Peak memory 200336 kb
Host smart-1e551be9-fc87-4dd4-9a8f-998fc82c1ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289416515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2289416515
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.249843979
Short name T864
Test name
Test status
Simulation time 8514781965 ps
CPU time 165.57 seconds
Started Aug 19 06:06:32 PM PDT 24
Finished Aug 19 06:09:18 PM PDT 24
Peak memory 200996 kb
Host smart-becf4b81-85f0-4c69-b14d-1f5ce107d0b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249843979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.249843979
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4086970864
Short name T1002
Test name
Test status
Simulation time 4725983592 ps
CPU time 44.78 seconds
Started Aug 19 06:06:33 PM PDT 24
Finished Aug 19 06:07:18 PM PDT 24
Peak memory 199796 kb
Host smart-d3f4358f-df8c-4d24-9b1d-6d620f1f7c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086970864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4086970864
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3473666286
Short name T155
Test name
Test status
Simulation time 55668761164 ps
CPU time 22.23 seconds
Started Aug 19 06:06:29 PM PDT 24
Finished Aug 19 06:06:51 PM PDT 24
Peak memory 200924 kb
Host smart-e57327b9-9f55-41a9-b5e4-17b4b5c7bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473666286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3473666286
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2865448407
Short name T656
Test name
Test status
Simulation time 3945366610 ps
CPU time 7.17 seconds
Started Aug 19 06:06:34 PM PDT 24
Finished Aug 19 06:06:41 PM PDT 24
Peak memory 197252 kb
Host smart-6d624e13-b389-4203-bff4-0cc144fe2f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865448407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2865448407
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.288899316
Short name T1029
Test name
Test status
Simulation time 10545966623 ps
CPU time 13.23 seconds
Started Aug 19 06:06:31 PM PDT 24
Finished Aug 19 06:06:44 PM PDT 24
Peak memory 200888 kb
Host smart-80d90dc3-76da-4890-bb8d-089bebd0b908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288899316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.288899316
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.114461438
Short name T459
Test name
Test status
Simulation time 300775150655 ps
CPU time 1075.21 seconds
Started Aug 19 06:06:38 PM PDT 24
Finished Aug 19 06:24:34 PM PDT 24
Peak memory 200972 kb
Host smart-46c05c69-db49-4054-afc1-a2ad74cd3ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114461438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.114461438
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1781138625
Short name T34
Test name
Test status
Simulation time 3148882654 ps
CPU time 42.7 seconds
Started Aug 19 06:06:28 PM PDT 24
Finished Aug 19 06:07:11 PM PDT 24
Peak memory 217572 kb
Host smart-bc800ae6-b15e-414d-a939-b7c819172666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781138625 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1781138625
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3699077477
Short name T751
Test name
Test status
Simulation time 7685945307 ps
CPU time 6.6 seconds
Started Aug 19 06:06:34 PM PDT 24
Finished Aug 19 06:06:41 PM PDT 24
Peak memory 200912 kb
Host smart-ac673067-c7db-4582-87aa-656969871a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699077477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3699077477
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2035308093
Short name T499
Test name
Test status
Simulation time 50047231890 ps
CPU time 22.42 seconds
Started Aug 19 06:06:30 PM PDT 24
Finished Aug 19 06:06:53 PM PDT 24
Peak memory 200904 kb
Host smart-aa0822de-bdc4-41c8-9bbc-943b9af453d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035308093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2035308093
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2108708467
Short name T185
Test name
Test status
Simulation time 131698511587 ps
CPU time 50.13 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:10:11 PM PDT 24
Peak memory 200964 kb
Host smart-f77fa343-8c39-4b60-ac76-6e262c12f95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108708467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2108708467
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2619401121
Short name T82
Test name
Test status
Simulation time 147625964179 ps
CPU time 203.51 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:12:44 PM PDT 24
Peak memory 200996 kb
Host smart-d3d6dba1-7655-4d84-80f9-f3cec04767b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619401121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2619401121
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2255538695
Short name T445
Test name
Test status
Simulation time 361709836835 ps
CPU time 46.06 seconds
Started Aug 19 06:09:22 PM PDT 24
Finished Aug 19 06:10:09 PM PDT 24
Peak memory 200940 kb
Host smart-92a22ecb-02bc-4d0e-bcd5-200bf0540b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255538695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2255538695
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3821275341
Short name T733
Test name
Test status
Simulation time 17174023972 ps
CPU time 31.52 seconds
Started Aug 19 06:09:19 PM PDT 24
Finished Aug 19 06:09:51 PM PDT 24
Peak memory 200936 kb
Host smart-9aa30d83-fcad-4b8c-9766-4ced1d236544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821275341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3821275341
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3096582990
Short name T569
Test name
Test status
Simulation time 206402870974 ps
CPU time 286.4 seconds
Started Aug 19 06:09:21 PM PDT 24
Finished Aug 19 06:14:08 PM PDT 24
Peak memory 200956 kb
Host smart-62cd6563-c005-4301-aae0-118e91770029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096582990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3096582990
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.866330456
Short name T934
Test name
Test status
Simulation time 60161965546 ps
CPU time 47.61 seconds
Started Aug 19 06:09:19 PM PDT 24
Finished Aug 19 06:10:07 PM PDT 24
Peak memory 200920 kb
Host smart-99326bbb-f095-444c-8ecb-a4ef8a07362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866330456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.866330456
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2642537167
Short name T1051
Test name
Test status
Simulation time 126963050433 ps
CPU time 136.65 seconds
Started Aug 19 06:09:22 PM PDT 24
Finished Aug 19 06:11:39 PM PDT 24
Peak memory 200920 kb
Host smart-8148f6d1-2563-416f-9305-ad66cba4de89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642537167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2642537167
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2453898945
Short name T234
Test name
Test status
Simulation time 109157304201 ps
CPU time 21.19 seconds
Started Aug 19 06:09:22 PM PDT 24
Finished Aug 19 06:09:44 PM PDT 24
Peak memory 200936 kb
Host smart-7fb17c75-31d3-4477-a3f5-a1e3efd9ab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453898945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2453898945
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.634734332
Short name T1149
Test name
Test status
Simulation time 22891893004 ps
CPU time 34.66 seconds
Started Aug 19 06:09:20 PM PDT 24
Finished Aug 19 06:09:55 PM PDT 24
Peak memory 200976 kb
Host smart-8a73f42b-8bc8-48de-a13c-ed80cec10cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634734332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.634734332
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3651332171
Short name T1009
Test name
Test status
Simulation time 18495728848 ps
CPU time 16.16 seconds
Started Aug 19 06:09:30 PM PDT 24
Finished Aug 19 06:09:46 PM PDT 24
Peak memory 200604 kb
Host smart-e1431560-c6bc-4d51-b2c6-3108a89a60e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651332171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3651332171
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4149806970
Short name T413
Test name
Test status
Simulation time 40076345 ps
CPU time 0.56 seconds
Started Aug 19 06:06:41 PM PDT 24
Finished Aug 19 06:06:42 PM PDT 24
Peak memory 196268 kb
Host smart-da82a6ac-0245-4afd-98ae-63008920fdf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149806970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4149806970
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.731884761
Short name T595
Test name
Test status
Simulation time 30269667598 ps
CPU time 12.16 seconds
Started Aug 19 06:06:42 PM PDT 24
Finished Aug 19 06:06:54 PM PDT 24
Peak memory 200920 kb
Host smart-1c730cb5-7181-4dfb-9faf-8af5313899c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731884761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.731884761
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.4265680601
Short name T749
Test name
Test status
Simulation time 26692150356 ps
CPU time 42.36 seconds
Started Aug 19 06:06:37 PM PDT 24
Finished Aug 19 06:07:20 PM PDT 24
Peak memory 201020 kb
Host smart-26fcf40c-3f8f-4c41-82e8-54976d8778b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265680601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.4265680601
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1525748666
Short name T332
Test name
Test status
Simulation time 118074995159 ps
CPU time 47.7 seconds
Started Aug 19 06:06:36 PM PDT 24
Finished Aug 19 06:07:24 PM PDT 24
Peak memory 201008 kb
Host smart-41ef95d8-b7cd-4f9c-b056-c2a41c609b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525748666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1525748666
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1327018186
Short name T612
Test name
Test status
Simulation time 58050290201 ps
CPU time 87.14 seconds
Started Aug 19 06:06:42 PM PDT 24
Finished Aug 19 06:08:09 PM PDT 24
Peak memory 200972 kb
Host smart-6be60e3b-099b-47bc-9431-987ac7b4b4da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327018186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1327018186
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2310423850
Short name T984
Test name
Test status
Simulation time 148885699741 ps
CPU time 471.38 seconds
Started Aug 19 06:06:44 PM PDT 24
Finished Aug 19 06:14:35 PM PDT 24
Peak memory 200980 kb
Host smart-fe8e316b-f4c6-4463-8076-a6510166baa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310423850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2310423850
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1374883330
Short name T999
Test name
Test status
Simulation time 6175103283 ps
CPU time 9.07 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:06:48 PM PDT 24
Peak memory 200824 kb
Host smart-39a35b2f-bb44-4969-b3ea-97f64754a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374883330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1374883330
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.33753697
Short name T896
Test name
Test status
Simulation time 66290863948 ps
CPU time 28.51 seconds
Started Aug 19 06:06:40 PM PDT 24
Finished Aug 19 06:07:08 PM PDT 24
Peak memory 201092 kb
Host smart-68c5dfc5-c492-427b-8a03-72b40e110e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33753697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.33753697
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2815503443
Short name T1115
Test name
Test status
Simulation time 9596137313 ps
CPU time 97.85 seconds
Started Aug 19 06:06:41 PM PDT 24
Finished Aug 19 06:08:19 PM PDT 24
Peak memory 200968 kb
Host smart-375eddee-717d-4ba2-ac6d-a8d75118f7fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815503443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2815503443
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1172223863
Short name T440
Test name
Test status
Simulation time 4435707868 ps
CPU time 10.48 seconds
Started Aug 19 06:06:36 PM PDT 24
Finished Aug 19 06:06:47 PM PDT 24
Peak memory 200268 kb
Host smart-3a56c4ad-b86b-4f6b-a205-090a09410d65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172223863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1172223863
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2550789691
Short name T678
Test name
Test status
Simulation time 50292530094 ps
CPU time 27.69 seconds
Started Aug 19 06:06:37 PM PDT 24
Finished Aug 19 06:07:04 PM PDT 24
Peak memory 200996 kb
Host smart-1a19235f-0fca-4720-8e8e-de504f3eedbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550789691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2550789691
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3974771203
Short name T400
Test name
Test status
Simulation time 6374600753 ps
CPU time 2.89 seconds
Started Aug 19 06:06:44 PM PDT 24
Finished Aug 19 06:06:47 PM PDT 24
Peak memory 197476 kb
Host smart-1ded9173-b22b-431b-8ac6-8bb1eea07f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974771203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3974771203
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3666586326
Short name T84
Test name
Test status
Simulation time 306701096 ps
CPU time 1.44 seconds
Started Aug 19 06:06:38 PM PDT 24
Finished Aug 19 06:06:39 PM PDT 24
Peak memory 199460 kb
Host smart-c427a374-910b-4b34-9636-ee0fefb9fcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666586326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3666586326
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.4146783665
Short name T93
Test name
Test status
Simulation time 11906778841 ps
CPU time 15.62 seconds
Started Aug 19 06:06:36 PM PDT 24
Finished Aug 19 06:06:52 PM PDT 24
Peak memory 209400 kb
Host smart-7e199fa9-c052-4d9f-85d3-94982a025cd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146783665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.4146783665
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2482938933
Short name T884
Test name
Test status
Simulation time 1935917543 ps
CPU time 1.62 seconds
Started Aug 19 06:06:44 PM PDT 24
Finished Aug 19 06:06:45 PM PDT 24
Peak memory 199132 kb
Host smart-6fcf427e-6b05-4352-b921-5810afb1ed40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482938933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2482938933
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1987718731
Short name T1159
Test name
Test status
Simulation time 77357253047 ps
CPU time 82.72 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:08:02 PM PDT 24
Peak memory 200972 kb
Host smart-b04e4c64-dab8-4bb5-b1f7-806715e02a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987718731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1987718731
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1176715457
Short name T1119
Test name
Test status
Simulation time 105067829862 ps
CPU time 46.53 seconds
Started Aug 19 06:09:34 PM PDT 24
Finished Aug 19 06:10:21 PM PDT 24
Peak memory 200972 kb
Host smart-c8b12c25-4081-4883-b734-18f8fa393a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176715457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1176715457
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.556046689
Short name T131
Test name
Test status
Simulation time 166420802058 ps
CPU time 105.91 seconds
Started Aug 19 06:09:35 PM PDT 24
Finished Aug 19 06:11:21 PM PDT 24
Peak memory 200976 kb
Host smart-a4fec823-2727-409b-90b3-e65ed0ac7c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556046689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.556046689
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1586850760
Short name T819
Test name
Test status
Simulation time 98871292733 ps
CPU time 42.39 seconds
Started Aug 19 06:09:29 PM PDT 24
Finished Aug 19 06:10:11 PM PDT 24
Peak memory 201004 kb
Host smart-4f230b08-3618-4966-a7e7-4f255296d78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586850760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1586850760
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.471293656
Short name T219
Test name
Test status
Simulation time 37619901227 ps
CPU time 63.17 seconds
Started Aug 19 06:09:34 PM PDT 24
Finished Aug 19 06:10:37 PM PDT 24
Peak memory 200976 kb
Host smart-328c997e-6319-4037-b797-d2a35459f1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471293656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.471293656
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.4234676384
Short name T1066
Test name
Test status
Simulation time 8597958747 ps
CPU time 14.73 seconds
Started Aug 19 06:09:34 PM PDT 24
Finished Aug 19 06:09:50 PM PDT 24
Peak memory 200912 kb
Host smart-cb751d5b-899f-4a68-9e30-25604425b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234676384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4234676384
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1284144087
Short name T522
Test name
Test status
Simulation time 164204562626 ps
CPU time 86.74 seconds
Started Aug 19 06:09:31 PM PDT 24
Finished Aug 19 06:10:58 PM PDT 24
Peak memory 200884 kb
Host smart-4b29e98c-cf8a-4d16-bc41-9a1ac2d207b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284144087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1284144087
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2876657098
Short name T127
Test name
Test status
Simulation time 104315778175 ps
CPU time 14.61 seconds
Started Aug 19 06:09:33 PM PDT 24
Finished Aug 19 06:09:48 PM PDT 24
Peak memory 200912 kb
Host smart-9cf6da1a-afa0-4744-8f60-95b66d416e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876657098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2876657098
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2685134227
Short name T545
Test name
Test status
Simulation time 60427073227 ps
CPU time 18.44 seconds
Started Aug 19 06:09:29 PM PDT 24
Finished Aug 19 06:09:48 PM PDT 24
Peak memory 200956 kb
Host smart-1d7e9012-208e-4e97-b154-4f688a1b4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685134227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2685134227
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2481517259
Short name T14
Test name
Test status
Simulation time 17890472279 ps
CPU time 8.27 seconds
Started Aug 19 06:09:32 PM PDT 24
Finished Aug 19 06:09:41 PM PDT 24
Peak memory 200908 kb
Host smart-fa65cb53-6d99-4f54-bf48-db628dabcacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481517259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2481517259
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1852300453
Short name T100
Test name
Test status
Simulation time 25256373262 ps
CPU time 8.96 seconds
Started Aug 19 06:09:33 PM PDT 24
Finished Aug 19 06:09:42 PM PDT 24
Peak memory 200724 kb
Host smart-2f94f8c1-5774-4178-b073-29e06d7167a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852300453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1852300453
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2400050308
Short name T614
Test name
Test status
Simulation time 47056820 ps
CPU time 0.57 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:06:40 PM PDT 24
Peak memory 196344 kb
Host smart-d50f3df3-40fb-473f-86c0-9dd24a3a7ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400050308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2400050308
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3377507060
Short name T629
Test name
Test status
Simulation time 59420815855 ps
CPU time 27.18 seconds
Started Aug 19 06:06:46 PM PDT 24
Finished Aug 19 06:07:13 PM PDT 24
Peak memory 201124 kb
Host smart-f94e7010-a0cf-47a5-a0ea-55d8110d506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377507060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3377507060
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2560115795
Short name T1141
Test name
Test status
Simulation time 163788440076 ps
CPU time 155.92 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:09:15 PM PDT 24
Peak memory 200952 kb
Host smart-d0c8e84a-aaa6-45d4-8371-af50ccc8ad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560115795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2560115795
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.477281983
Short name T509
Test name
Test status
Simulation time 13317506161 ps
CPU time 12.86 seconds
Started Aug 19 06:06:45 PM PDT 24
Finished Aug 19 06:06:57 PM PDT 24
Peak memory 200932 kb
Host smart-77fa4802-e296-4df2-a950-1b2530f24d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477281983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.477281983
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4130999107
Short name T328
Test name
Test status
Simulation time 44475107068 ps
CPU time 20.17 seconds
Started Aug 19 06:06:41 PM PDT 24
Finished Aug 19 06:07:01 PM PDT 24
Peak memory 200976 kb
Host smart-90a7c7dc-aaac-4ce8-bb23-4f685f579e6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130999107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4130999107
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.4263130091
Short name T289
Test name
Test status
Simulation time 150607193772 ps
CPU time 880.18 seconds
Started Aug 19 06:06:42 PM PDT 24
Finished Aug 19 06:21:22 PM PDT 24
Peak memory 200988 kb
Host smart-69efc1b2-09c4-4ae4-a86c-7a6b166bd6cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263130091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.4263130091
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1258813478
Short name T1145
Test name
Test status
Simulation time 4909309400 ps
CPU time 12.4 seconds
Started Aug 19 06:06:44 PM PDT 24
Finished Aug 19 06:06:56 PM PDT 24
Peak memory 199392 kb
Host smart-04efb9d6-8928-4d2d-aca5-4e57903e0fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258813478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1258813478
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1887001836
Short name T306
Test name
Test status
Simulation time 58306040368 ps
CPU time 103.92 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:08:23 PM PDT 24
Peak memory 200244 kb
Host smart-491be1f7-5f6f-490d-8c7f-aa0933de350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887001836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1887001836
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.937895136
Short name T396
Test name
Test status
Simulation time 13176846914 ps
CPU time 105.86 seconds
Started Aug 19 06:06:40 PM PDT 24
Finished Aug 19 06:08:26 PM PDT 24
Peak memory 200996 kb
Host smart-7ff7517a-8fc5-4421-8370-9aaa39614e30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937895136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.937895136
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3258856046
Short name T802
Test name
Test status
Simulation time 3336729089 ps
CPU time 2.1 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:06:41 PM PDT 24
Peak memory 199404 kb
Host smart-fd528b4b-8065-4935-8e37-2c44d250a5e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258856046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3258856046
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1767771794
Short name T766
Test name
Test status
Simulation time 34990716755 ps
CPU time 16.81 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:06:56 PM PDT 24
Peak memory 200948 kb
Host smart-053d6828-446d-4e78-8a01-757efbd6bd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767771794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1767771794
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2940066206
Short name T486
Test name
Test status
Simulation time 48541637878 ps
CPU time 17.73 seconds
Started Aug 19 06:06:41 PM PDT 24
Finished Aug 19 06:06:59 PM PDT 24
Peak memory 196800 kb
Host smart-ed07aa0b-a12d-435c-ba50-10a209743009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940066206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2940066206
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2780281472
Short name T1091
Test name
Test status
Simulation time 10574159567 ps
CPU time 9.91 seconds
Started Aug 19 06:06:37 PM PDT 24
Finished Aug 19 06:06:47 PM PDT 24
Peak memory 200908 kb
Host smart-bd5eff95-2d22-4805-852e-a1743007b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780281472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2780281472
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2364931092
Short name T336
Test name
Test status
Simulation time 171709617694 ps
CPU time 786.15 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:19:45 PM PDT 24
Peak memory 200928 kb
Host smart-1fb92312-024d-4e0a-89f8-524dd36de6d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364931092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2364931092
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2096593595
Short name T405
Test name
Test status
Simulation time 5022918244 ps
CPU time 35.27 seconds
Started Aug 19 06:06:40 PM PDT 24
Finished Aug 19 06:07:15 PM PDT 24
Peak memory 209440 kb
Host smart-777697f2-7297-4365-b990-cf9372e88b62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096593595 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2096593595
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1670779781
Short name T1111
Test name
Test status
Simulation time 6736859191 ps
CPU time 18.54 seconds
Started Aug 19 06:06:40 PM PDT 24
Finished Aug 19 06:06:59 PM PDT 24
Peak memory 200360 kb
Host smart-f25753bb-d193-49b8-b8c3-300a490ebbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670779781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1670779781
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.742762706
Short name T849
Test name
Test status
Simulation time 66212053002 ps
CPU time 125.86 seconds
Started Aug 19 06:06:41 PM PDT 24
Finished Aug 19 06:08:47 PM PDT 24
Peak memory 200940 kb
Host smart-c5ca0397-c25e-4feb-a619-1146b2475b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742762706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.742762706
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.951974126
Short name T1007
Test name
Test status
Simulation time 8632197605 ps
CPU time 22.96 seconds
Started Aug 19 06:09:31 PM PDT 24
Finished Aug 19 06:09:54 PM PDT 24
Peak memory 200932 kb
Host smart-e7eda33e-2239-4f2d-b964-b3d84f3b3a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951974126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.951974126
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1435516026
Short name T1040
Test name
Test status
Simulation time 38841083775 ps
CPU time 63.76 seconds
Started Aug 19 06:09:30 PM PDT 24
Finished Aug 19 06:10:34 PM PDT 24
Peak memory 200932 kb
Host smart-19ab33d0-a126-4c7c-984c-60ae5f739777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435516026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1435516026
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.639450302
Short name T261
Test name
Test status
Simulation time 24425504572 ps
CPU time 36.47 seconds
Started Aug 19 06:09:29 PM PDT 24
Finished Aug 19 06:10:06 PM PDT 24
Peak memory 200616 kb
Host smart-c0cf9d73-5514-415f-941c-da0eb16c0774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639450302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.639450302
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.4275682894
Short name T537
Test name
Test status
Simulation time 57217607634 ps
CPU time 33.29 seconds
Started Aug 19 06:09:29 PM PDT 24
Finished Aug 19 06:10:03 PM PDT 24
Peak memory 200860 kb
Host smart-c9d091d1-90af-4dda-acb2-3c2e9a93fbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275682894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4275682894
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1768225106
Short name T890
Test name
Test status
Simulation time 15454417290 ps
CPU time 25.95 seconds
Started Aug 19 06:09:30 PM PDT 24
Finished Aug 19 06:09:57 PM PDT 24
Peak memory 200968 kb
Host smart-cb756edd-5d29-4870-880e-dd245305a312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768225106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1768225106
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2217042629
Short name T324
Test name
Test status
Simulation time 103330966335 ps
CPU time 67.94 seconds
Started Aug 19 06:09:30 PM PDT 24
Finished Aug 19 06:10:39 PM PDT 24
Peak memory 200912 kb
Host smart-5355d977-5211-48c0-a36c-b8a9689aa98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217042629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2217042629
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.4099698535
Short name T1162
Test name
Test status
Simulation time 36060383000 ps
CPU time 59.92 seconds
Started Aug 19 06:09:30 PM PDT 24
Finished Aug 19 06:10:30 PM PDT 24
Peak memory 201040 kb
Host smart-406b6289-711d-43db-85ed-b1e5700a7ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099698535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.4099698535
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2479771746
Short name T107
Test name
Test status
Simulation time 120094505921 ps
CPU time 40.45 seconds
Started Aug 19 06:09:31 PM PDT 24
Finished Aug 19 06:10:12 PM PDT 24
Peak memory 200964 kb
Host smart-08a6d2fb-a4ea-402e-b49a-5ae368da85c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479771746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2479771746
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3642690627
Short name T823
Test name
Test status
Simulation time 110583248076 ps
CPU time 232.95 seconds
Started Aug 19 06:09:30 PM PDT 24
Finished Aug 19 06:13:23 PM PDT 24
Peak memory 200960 kb
Host smart-7b702916-7629-4376-b619-82e2f1c10673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642690627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3642690627
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4293552867
Short name T800
Test name
Test status
Simulation time 47053744 ps
CPU time 0.53 seconds
Started Aug 19 06:06:47 PM PDT 24
Finished Aug 19 06:06:47 PM PDT 24
Peak memory 196232 kb
Host smart-ee1cbf18-1c0a-4ffc-a251-8aebaf534122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293552867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4293552867
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1082794711
Short name T101
Test name
Test status
Simulation time 24787913177 ps
CPU time 39.56 seconds
Started Aug 19 06:06:37 PM PDT 24
Finished Aug 19 06:07:16 PM PDT 24
Peak memory 200884 kb
Host smart-4c34d488-4518-48cf-baa6-76d1c81c51ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082794711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1082794711
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.4060785204
Short name T657
Test name
Test status
Simulation time 29323793075 ps
CPU time 80.2 seconds
Started Aug 19 06:06:41 PM PDT 24
Finished Aug 19 06:08:02 PM PDT 24
Peak memory 200976 kb
Host smart-e46f90cb-583a-48b6-b39a-16543b8b0cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060785204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4060785204
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1385899209
Short name T674
Test name
Test status
Simulation time 118453987286 ps
CPU time 50.32 seconds
Started Aug 19 06:06:38 PM PDT 24
Finished Aug 19 06:07:28 PM PDT 24
Peak memory 200948 kb
Host smart-0cd8468b-2fd2-4e87-9a93-075396ff2a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385899209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1385899209
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2863809611
Short name T578
Test name
Test status
Simulation time 51218469053 ps
CPU time 29.64 seconds
Started Aug 19 06:06:35 PM PDT 24
Finished Aug 19 06:07:05 PM PDT 24
Peak memory 200940 kb
Host smart-1dcb75b2-a7f4-4562-8316-dc888408f46e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863809611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2863809611
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3584066070
Short name T583
Test name
Test status
Simulation time 116341358067 ps
CPU time 581.55 seconds
Started Aug 19 06:06:50 PM PDT 24
Finished Aug 19 06:16:32 PM PDT 24
Peak memory 200980 kb
Host smart-6b3db937-c79d-4d4a-a597-ecc0adf2b38c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584066070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3584066070
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.583793945
Short name T348
Test name
Test status
Simulation time 111957870 ps
CPU time 0.71 seconds
Started Aug 19 06:06:49 PM PDT 24
Finished Aug 19 06:06:49 PM PDT 24
Peak memory 196996 kb
Host smart-80e539ff-ed1f-473f-b9ab-63f4ed390d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583793945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.583793945
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.4000944146
Short name T1077
Test name
Test status
Simulation time 125097878123 ps
CPU time 68.32 seconds
Started Aug 19 06:06:40 PM PDT 24
Finished Aug 19 06:07:48 PM PDT 24
Peak memory 201108 kb
Host smart-ffb4caa0-6fd1-4bb7-a302-36e38a781caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000944146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.4000944146
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.610871467
Short name T255
Test name
Test status
Simulation time 18118681147 ps
CPU time 926.17 seconds
Started Aug 19 06:06:50 PM PDT 24
Finished Aug 19 06:22:16 PM PDT 24
Peak memory 200968 kb
Host smart-601dd401-f93f-48e4-8988-4ac51a518da5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=610871467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.610871467
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.109906011
Short name T917
Test name
Test status
Simulation time 1367657479 ps
CPU time 0.68 seconds
Started Aug 19 06:06:37 PM PDT 24
Finished Aug 19 06:06:38 PM PDT 24
Peak memory 196612 kb
Host smart-91004712-02e2-4572-a24b-e5b005a5c372
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109906011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.109906011
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2858104055
Short name T631
Test name
Test status
Simulation time 59704703989 ps
CPU time 38.67 seconds
Started Aug 19 06:06:37 PM PDT 24
Finished Aug 19 06:07:16 PM PDT 24
Peak memory 200736 kb
Host smart-e934a299-e94c-4027-9e73-e28c961b3b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858104055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2858104055
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1058773342
Short name T465
Test name
Test status
Simulation time 4162361297 ps
CPU time 6.78 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:06:46 PM PDT 24
Peak memory 197092 kb
Host smart-9a4573e1-525b-44a6-8b9e-0dba432d46f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058773342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1058773342
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.4059099928
Short name T710
Test name
Test status
Simulation time 5635536204 ps
CPU time 11.68 seconds
Started Aug 19 06:06:42 PM PDT 24
Finished Aug 19 06:06:53 PM PDT 24
Peak memory 200756 kb
Host smart-04198940-42f5-48c4-a189-7c8ffea712a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059099928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4059099928
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.431087692
Short name T632
Test name
Test status
Simulation time 196782148347 ps
CPU time 51.74 seconds
Started Aug 19 06:06:49 PM PDT 24
Finished Aug 19 06:07:41 PM PDT 24
Peak memory 200976 kb
Host smart-129e3c3e-dae8-43d1-8239-0582f1e16ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431087692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.431087692
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.658053354
Short name T807
Test name
Test status
Simulation time 4682197156 ps
CPU time 24.47 seconds
Started Aug 19 06:06:47 PM PDT 24
Finished Aug 19 06:07:12 PM PDT 24
Peak memory 216592 kb
Host smart-6a9df84c-bea0-4802-8c2e-816fd31bc985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658053354 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.658053354
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.548959531
Short name T296
Test name
Test status
Simulation time 6605906988 ps
CPU time 27.8 seconds
Started Aug 19 06:06:50 PM PDT 24
Finished Aug 19 06:07:18 PM PDT 24
Peak memory 200856 kb
Host smart-734e6d7c-1c08-4bc4-b154-3ee3aab97397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548959531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.548959531
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3888791676
Short name T941
Test name
Test status
Simulation time 339541062473 ps
CPU time 70.16 seconds
Started Aug 19 06:06:39 PM PDT 24
Finished Aug 19 06:07:49 PM PDT 24
Peak memory 200932 kb
Host smart-9729aade-d62f-4c03-a768-46aba63329d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888791676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3888791676
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2338579516
Short name T699
Test name
Test status
Simulation time 8745493860 ps
CPU time 14.03 seconds
Started Aug 19 06:09:30 PM PDT 24
Finished Aug 19 06:09:44 PM PDT 24
Peak memory 199896 kb
Host smart-af522bda-9d6a-4cc7-8756-cab26ee5fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338579516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2338579516
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3712264357
Short name T212
Test name
Test status
Simulation time 32916644564 ps
CPU time 49.9 seconds
Started Aug 19 06:09:28 PM PDT 24
Finished Aug 19 06:10:18 PM PDT 24
Peak memory 200864 kb
Host smart-35c238c2-d89a-4837-9ffb-209fbd9a3247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712264357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3712264357
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2928974789
Short name T121
Test name
Test status
Simulation time 20085572541 ps
CPU time 17.94 seconds
Started Aug 19 06:09:32 PM PDT 24
Finished Aug 19 06:09:50 PM PDT 24
Peak memory 200944 kb
Host smart-24a77145-a005-4923-8544-69c0bebc6abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928974789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2928974789
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2421486626
Short name T858
Test name
Test status
Simulation time 102174507048 ps
CPU time 150.89 seconds
Started Aug 19 06:09:34 PM PDT 24
Finished Aug 19 06:12:05 PM PDT 24
Peak memory 200624 kb
Host smart-e83f04dd-ce28-45e5-9b30-1d8a29cc69a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421486626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2421486626
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2892698433
Short name T218
Test name
Test status
Simulation time 18435987262 ps
CPU time 27.93 seconds
Started Aug 19 06:09:29 PM PDT 24
Finished Aug 19 06:09:57 PM PDT 24
Peak memory 200544 kb
Host smart-e8295c8d-6d9c-424a-bdcd-8d2f9f4d9f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892698433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2892698433
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.388433417
Short name T152
Test name
Test status
Simulation time 109873292065 ps
CPU time 143.69 seconds
Started Aug 19 06:09:31 PM PDT 24
Finished Aug 19 06:11:55 PM PDT 24
Peak memory 201004 kb
Host smart-d7be1849-4c30-4f5b-a2ec-3ddbe0488cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388433417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.388433417
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3222933728
Short name T189
Test name
Test status
Simulation time 79667165940 ps
CPU time 58.55 seconds
Started Aug 19 06:09:36 PM PDT 24
Finished Aug 19 06:10:35 PM PDT 24
Peak memory 200976 kb
Host smart-dfde2c6a-444d-41a3-b8d2-567719ad6000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222933728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3222933728
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.563525573
Short name T646
Test name
Test status
Simulation time 20271976 ps
CPU time 0.57 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:05:11 PM PDT 24
Peak memory 196264 kb
Host smart-b451618b-e35c-43d6-8704-9da49f9ae503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563525573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.563525573
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.587793466
Short name T592
Test name
Test status
Simulation time 34592815428 ps
CPU time 76.59 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:06:19 PM PDT 24
Peak memory 200936 kb
Host smart-a9ec62b7-b506-4b09-9c02-7c7bcefbf390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587793466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.587793466
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2287601709
Short name T277
Test name
Test status
Simulation time 21744929973 ps
CPU time 16.44 seconds
Started Aug 19 06:05:05 PM PDT 24
Finished Aug 19 06:05:22 PM PDT 24
Peak memory 200804 kb
Host smart-b4642a89-d8e8-4b5f-83a3-da9a8a7b0e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287601709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2287601709
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.4224773318
Short name T197
Test name
Test status
Simulation time 16648383822 ps
CPU time 48.32 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:50 PM PDT 24
Peak memory 200992 kb
Host smart-9a6955f7-cfad-4f87-9a77-3ec2eff0fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224773318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4224773318
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2902791885
Short name T327
Test name
Test status
Simulation time 157880403426 ps
CPU time 103.74 seconds
Started Aug 19 06:05:06 PM PDT 24
Finished Aug 19 06:06:50 PM PDT 24
Peak memory 200940 kb
Host smart-c3468885-26cf-4129-9d65-57350af41e67
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902791885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2902791885
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_loopback.310004948
Short name T1128
Test name
Test status
Simulation time 4512173090 ps
CPU time 3.5 seconds
Started Aug 19 06:05:06 PM PDT 24
Finished Aug 19 06:05:09 PM PDT 24
Peak memory 200556 kb
Host smart-517dc6bc-3a89-424d-9bb6-257d1043ae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310004948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.310004948
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1748664923
Short name T241
Test name
Test status
Simulation time 72914592061 ps
CPU time 50.3 seconds
Started Aug 19 06:05:05 PM PDT 24
Finished Aug 19 06:05:56 PM PDT 24
Peak memory 199740 kb
Host smart-b23eb693-be78-422e-ab2e-08d821576221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748664923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1748664923
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1690222690
Short name T491
Test name
Test status
Simulation time 21245727435 ps
CPU time 434.1 seconds
Started Aug 19 06:05:04 PM PDT 24
Finished Aug 19 06:12:18 PM PDT 24
Peak memory 200972 kb
Host smart-a46d6d51-7c1f-4f22-8f47-7dc31a2aa3f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690222690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1690222690
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1091603212
Short name T659
Test name
Test status
Simulation time 3083182510 ps
CPU time 11.3 seconds
Started Aug 19 06:05:05 PM PDT 24
Finished Aug 19 06:05:16 PM PDT 24
Peak memory 199096 kb
Host smart-b59db0c5-d5f7-46be-81ab-93135119a9b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091603212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1091603212
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1364366283
Short name T125
Test name
Test status
Simulation time 31897337049 ps
CPU time 9.23 seconds
Started Aug 19 06:05:06 PM PDT 24
Finished Aug 19 06:05:15 PM PDT 24
Peak memory 200936 kb
Host smart-e3ef66b2-ab48-4932-a19d-3fb85e5914ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364366283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1364366283
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.403723702
Short name T1160
Test name
Test status
Simulation time 736699763 ps
CPU time 1.72 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:04 PM PDT 24
Peak memory 196444 kb
Host smart-2d99c4e1-d7a6-4306-a84e-8f0cf9e2923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403723702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.403723702
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.4044477855
Short name T1127
Test name
Test status
Simulation time 5996073809 ps
CPU time 23.64 seconds
Started Aug 19 06:04:59 PM PDT 24
Finished Aug 19 06:05:23 PM PDT 24
Peak memory 200712 kb
Host smart-002d96ee-b529-47fe-8788-a21aedd9994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044477855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4044477855
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.4086641768
Short name T748
Test name
Test status
Simulation time 596794261328 ps
CPU time 661.22 seconds
Started Aug 19 06:05:05 PM PDT 24
Finished Aug 19 06:16:06 PM PDT 24
Peak memory 200996 kb
Host smart-d2ff6356-e5d3-47bf-bd75-52ebabbe82bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086641768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.4086641768
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2320633421
Short name T816
Test name
Test status
Simulation time 5179367693 ps
CPU time 33.41 seconds
Started Aug 19 06:05:04 PM PDT 24
Finished Aug 19 06:05:38 PM PDT 24
Peak memory 209416 kb
Host smart-e20bfb61-354f-4e93-846e-30a87e0e3553
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320633421 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2320633421
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1602870093
Short name T1133
Test name
Test status
Simulation time 2167713599 ps
CPU time 1.66 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:05:04 PM PDT 24
Peak memory 200940 kb
Host smart-cbd2f8d9-b6d6-443e-b8ef-7e40f9098252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602870093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1602870093
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1072588714
Short name T1106
Test name
Test status
Simulation time 214954352403 ps
CPU time 61.57 seconds
Started Aug 19 06:05:02 PM PDT 24
Finished Aug 19 06:06:04 PM PDT 24
Peak memory 200984 kb
Host smart-d5851cb5-dfd1-439e-8c6e-4bd2df34f186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072588714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1072588714
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2357911555
Short name T1118
Test name
Test status
Simulation time 12472813 ps
CPU time 0.55 seconds
Started Aug 19 06:06:47 PM PDT 24
Finished Aug 19 06:06:48 PM PDT 24
Peak memory 196524 kb
Host smart-d5243303-c0b4-4528-b3a6-9a855cac8ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357911555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2357911555
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3197530813
Short name T136
Test name
Test status
Simulation time 108218918386 ps
CPU time 41.26 seconds
Started Aug 19 06:06:48 PM PDT 24
Finished Aug 19 06:07:29 PM PDT 24
Peak memory 200972 kb
Host smart-b2a8d6f3-5d3e-4221-bf9e-e1274b70719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197530813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3197530813
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3829885100
Short name T623
Test name
Test status
Simulation time 30363451889 ps
CPU time 58.24 seconds
Started Aug 19 06:06:49 PM PDT 24
Finished Aug 19 06:07:47 PM PDT 24
Peak memory 200936 kb
Host smart-21fe0adb-3456-4326-9b66-19da481731d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829885100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3829885100
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3202602418
Short name T906
Test name
Test status
Simulation time 126443379890 ps
CPU time 21.24 seconds
Started Aug 19 06:06:49 PM PDT 24
Finished Aug 19 06:07:10 PM PDT 24
Peak memory 200920 kb
Host smart-95357e08-8485-4103-805b-e7a1fd0b423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202602418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3202602418
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3302150008
Short name T367
Test name
Test status
Simulation time 168992106651 ps
CPU time 104.82 seconds
Started Aug 19 06:06:48 PM PDT 24
Finished Aug 19 06:08:33 PM PDT 24
Peak memory 198088 kb
Host smart-9f2c63ff-4a79-43a1-b6b7-10e7c8b87c91
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302150008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3302150008
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.108485370
Short name T863
Test name
Test status
Simulation time 80558302585 ps
CPU time 151.26 seconds
Started Aug 19 06:06:49 PM PDT 24
Finished Aug 19 06:09:20 PM PDT 24
Peak memory 200880 kb
Host smart-38082fc0-1143-4450-ab6f-bcaa91e035f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108485370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.108485370
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1502777864
Short name T774
Test name
Test status
Simulation time 10108577437 ps
CPU time 11.9 seconds
Started Aug 19 06:06:48 PM PDT 24
Finished Aug 19 06:07:00 PM PDT 24
Peak memory 200888 kb
Host smart-9d4e750a-fc55-4cc7-985d-61c2c4fba3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502777864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1502777864
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3809209333
Short name T1169
Test name
Test status
Simulation time 89392975160 ps
CPU time 149.28 seconds
Started Aug 19 06:06:45 PM PDT 24
Finished Aug 19 06:09:15 PM PDT 24
Peak memory 201112 kb
Host smart-f689f6f1-2c73-4c34-87e2-d3959bce6847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809209333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3809209333
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2829778333
Short name T586
Test name
Test status
Simulation time 8776150152 ps
CPU time 272.43 seconds
Started Aug 19 06:06:50 PM PDT 24
Finished Aug 19 06:11:23 PM PDT 24
Peak memory 200984 kb
Host smart-a79e5e91-ee8a-4d61-9065-74066f373273
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829778333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2829778333
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2701437388
Short name T346
Test name
Test status
Simulation time 5891293631 ps
CPU time 49.49 seconds
Started Aug 19 06:06:49 PM PDT 24
Finished Aug 19 06:07:38 PM PDT 24
Peak memory 199232 kb
Host smart-91c717d6-17a6-4848-942c-674b784b5b2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701437388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2701437388
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1353364492
Short name T882
Test name
Test status
Simulation time 118296717358 ps
CPU time 29.1 seconds
Started Aug 19 06:06:51 PM PDT 24
Finished Aug 19 06:07:20 PM PDT 24
Peak memory 200384 kb
Host smart-6c96c3af-54ff-4ad5-91f2-6c61ccf6a6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353364492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1353364492
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1424807173
Short name T298
Test name
Test status
Simulation time 41509110211 ps
CPU time 30.09 seconds
Started Aug 19 06:06:47 PM PDT 24
Finished Aug 19 06:07:17 PM PDT 24
Peak memory 196800 kb
Host smart-e84bb52d-2cd2-425b-b358-cbb8f8ee4f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424807173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1424807173
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1815379338
Short name T1068
Test name
Test status
Simulation time 476778434 ps
CPU time 1.35 seconds
Started Aug 19 06:06:47 PM PDT 24
Finished Aug 19 06:06:48 PM PDT 24
Peak memory 199360 kb
Host smart-31481d52-5939-4f6f-a121-9c334e28b5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815379338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1815379338
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2589551079
Short name T392
Test name
Test status
Simulation time 83153412381 ps
CPU time 852.64 seconds
Started Aug 19 06:06:50 PM PDT 24
Finished Aug 19 06:21:03 PM PDT 24
Peak memory 201016 kb
Host smart-cd95797d-c6b8-4ef1-9f3a-a48c49aaab24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589551079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2589551079
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3851539444
Short name T105
Test name
Test status
Simulation time 1139097757 ps
CPU time 24.34 seconds
Started Aug 19 06:06:50 PM PDT 24
Finished Aug 19 06:07:15 PM PDT 24
Peak memory 217540 kb
Host smart-ca974a22-585a-417b-aef9-a4ce45173e62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851539444 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3851539444
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.4165733346
Short name T546
Test name
Test status
Simulation time 1691928390 ps
CPU time 1.73 seconds
Started Aug 19 06:06:47 PM PDT 24
Finished Aug 19 06:06:49 PM PDT 24
Peak memory 200856 kb
Host smart-f717c88f-ac7c-4031-841f-8c5cff748c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165733346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4165733346
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3247699202
Short name T70
Test name
Test status
Simulation time 46846778968 ps
CPU time 83.8 seconds
Started Aug 19 06:06:49 PM PDT 24
Finished Aug 19 06:08:13 PM PDT 24
Peak memory 200908 kb
Host smart-831abda1-353f-4e89-8264-54b26587e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247699202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3247699202
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1482815397
Short name T750
Test name
Test status
Simulation time 20737497 ps
CPU time 0.57 seconds
Started Aug 19 06:06:57 PM PDT 24
Finished Aug 19 06:06:58 PM PDT 24
Peak memory 196284 kb
Host smart-ea6bc7ac-d4d1-411b-8f71-8fc08df6149e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482815397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1482815397
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1418412024
Short name T599
Test name
Test status
Simulation time 93728740966 ps
CPU time 41.79 seconds
Started Aug 19 06:06:46 PM PDT 24
Finished Aug 19 06:07:28 PM PDT 24
Peak memory 200916 kb
Host smart-0939f14f-4ed8-4405-b56d-cd3315d3b381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418412024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1418412024
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3377213397
Short name T1144
Test name
Test status
Simulation time 150657898757 ps
CPU time 59.82 seconds
Started Aug 19 06:06:51 PM PDT 24
Finished Aug 19 06:07:51 PM PDT 24
Peak memory 200900 kb
Host smart-02a09c11-0eef-4198-b5bf-b9fb90af8ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377213397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3377213397
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2936093969
Short name T987
Test name
Test status
Simulation time 158984375733 ps
CPU time 61.19 seconds
Started Aug 19 06:06:49 PM PDT 24
Finished Aug 19 06:07:50 PM PDT 24
Peak memory 201116 kb
Host smart-e59dd8d1-a845-4e90-8d60-441dbd387f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936093969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2936093969
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2563375455
Short name T937
Test name
Test status
Simulation time 4316653776 ps
CPU time 22.93 seconds
Started Aug 19 06:06:50 PM PDT 24
Finished Aug 19 06:07:13 PM PDT 24
Peak memory 200068 kb
Host smart-2b6c4ef7-774b-4860-89db-299f3d3c6cb5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563375455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2563375455
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1056634126
Short name T945
Test name
Test status
Simulation time 82942053047 ps
CPU time 240.58 seconds
Started Aug 19 06:06:51 PM PDT 24
Finished Aug 19 06:10:52 PM PDT 24
Peak memory 200968 kb
Host smart-0d94d8f0-e96f-49db-b5f8-ccb12707b86d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056634126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1056634126
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2192355383
Short name T8
Test name
Test status
Simulation time 7332734011 ps
CPU time 7.75 seconds
Started Aug 19 06:06:48 PM PDT 24
Finished Aug 19 06:06:56 PM PDT 24
Peak memory 200816 kb
Host smart-d8951287-c515-447a-91d7-7b79443b7488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192355383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2192355383
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.4219693852
Short name T559
Test name
Test status
Simulation time 10587820460 ps
CPU time 15.62 seconds
Started Aug 19 06:06:52 PM PDT 24
Finished Aug 19 06:07:07 PM PDT 24
Peak memory 201096 kb
Host smart-6a767340-908c-41d5-8ffc-19afb9ae5c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219693852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.4219693852
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1894538153
Short name T1087
Test name
Test status
Simulation time 9050131293 ps
CPU time 500.3 seconds
Started Aug 19 06:06:47 PM PDT 24
Finished Aug 19 06:15:07 PM PDT 24
Peak memory 200932 kb
Host smart-a627c7ef-ce4b-4717-96a2-a2b892e4b311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1894538153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1894538153
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3949301150
Short name T813
Test name
Test status
Simulation time 3097490764 ps
CPU time 6.28 seconds
Started Aug 19 06:06:51 PM PDT 24
Finished Aug 19 06:06:57 PM PDT 24
Peak memory 198960 kb
Host smart-f168c915-302a-41c9-94fd-87f9ba055485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949301150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3949301150
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1687845555
Short name T1126
Test name
Test status
Simulation time 35685952198 ps
CPU time 60.17 seconds
Started Aug 19 06:06:48 PM PDT 24
Finished Aug 19 06:07:49 PM PDT 24
Peak memory 200924 kb
Host smart-35f04543-85f9-4a30-a753-c590cf4482a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687845555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1687845555
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1021163492
Short name T390
Test name
Test status
Simulation time 2314827811 ps
CPU time 4.11 seconds
Started Aug 19 06:06:45 PM PDT 24
Finished Aug 19 06:06:49 PM PDT 24
Peak memory 196624 kb
Host smart-256706f0-221b-42fb-a0a6-2fc6e3db424e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021163492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1021163492
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.952311299
Short name T1125
Test name
Test status
Simulation time 498010699 ps
CPU time 2.44 seconds
Started Aug 19 06:06:51 PM PDT 24
Finished Aug 19 06:06:53 PM PDT 24
Peak memory 199896 kb
Host smart-00d0bf8e-f708-472c-afcb-21ea7c1afe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952311299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.952311299
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2971937327
Short name T463
Test name
Test status
Simulation time 95003014681 ps
CPU time 171.1 seconds
Started Aug 19 06:06:59 PM PDT 24
Finished Aug 19 06:09:50 PM PDT 24
Peak memory 217216 kb
Host smart-4694705b-f81f-4763-9622-061cfc192df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971937327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2971937327
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.15790772
Short name T1043
Test name
Test status
Simulation time 12020257319 ps
CPU time 37.01 seconds
Started Aug 19 06:06:47 PM PDT 24
Finished Aug 19 06:07:24 PM PDT 24
Peak memory 217408 kb
Host smart-0ad5478c-dfb6-4243-b6b3-83e5de91239d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15790772 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.15790772
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2132249660
Short name T45
Test name
Test status
Simulation time 7431768069 ps
CPU time 8.05 seconds
Started Aug 19 06:06:51 PM PDT 24
Finished Aug 19 06:06:59 PM PDT 24
Peak memory 200712 kb
Host smart-45157317-d6a4-47de-81bb-74cbb08dd8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132249660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2132249660
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.938735836
Short name T1061
Test name
Test status
Simulation time 78494005077 ps
CPU time 146.57 seconds
Started Aug 19 06:06:46 PM PDT 24
Finished Aug 19 06:09:13 PM PDT 24
Peak memory 200960 kb
Host smart-ff22eed1-194b-47a3-9237-7af4f71a5a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938735836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.938735836
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3880036869
Short name T1097
Test name
Test status
Simulation time 23376550 ps
CPU time 0.57 seconds
Started Aug 19 06:06:55 PM PDT 24
Finished Aug 19 06:06:55 PM PDT 24
Peak memory 196576 kb
Host smart-a544ef00-c179-457b-b09c-c4098258bca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880036869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3880036869
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2174822452
Short name T616
Test name
Test status
Simulation time 79883179938 ps
CPU time 107 seconds
Started Aug 19 06:06:57 PM PDT 24
Finished Aug 19 06:08:44 PM PDT 24
Peak memory 201004 kb
Host smart-917a2e2d-6941-4c1e-9c4d-97ef0fcec254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174822452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2174822452
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2780195346
Short name T785
Test name
Test status
Simulation time 134902822549 ps
CPU time 64.58 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:08:02 PM PDT 24
Peak memory 200876 kb
Host smart-08df4863-efd8-43c8-ba31-700600cc7166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780195346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2780195346
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3776189924
Short name T477
Test name
Test status
Simulation time 72167229465 ps
CPU time 57.06 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:07:55 PM PDT 24
Peak memory 200976 kb
Host smart-3e52e30f-d6f2-45f9-8b14-1ca6383c1a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776189924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3776189924
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.947077735
Short name T727
Test name
Test status
Simulation time 52898141947 ps
CPU time 86.22 seconds
Started Aug 19 06:07:00 PM PDT 24
Finished Aug 19 06:08:26 PM PDT 24
Peak memory 200952 kb
Host smart-f008af7a-0d1f-476a-a05b-cd275dd05cbe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947077735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.947077735
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1399967242
Short name T634
Test name
Test status
Simulation time 72295275372 ps
CPU time 413.21 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:13:51 PM PDT 24
Peak memory 200896 kb
Host smart-730e1390-a559-4e9f-bcb5-9a2e8897bd4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399967242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1399967242
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.4082657922
Short name T848
Test name
Test status
Simulation time 10791667401 ps
CPU time 5.5 seconds
Started Aug 19 06:07:00 PM PDT 24
Finished Aug 19 06:07:05 PM PDT 24
Peak memory 199712 kb
Host smart-a0e71e38-13b7-46af-a9b1-2a9f3d6b1df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082657922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.4082657922
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.356983874
Short name T767
Test name
Test status
Simulation time 299484623811 ps
CPU time 84.52 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:08:23 PM PDT 24
Peak memory 209380 kb
Host smart-fc298f20-3e99-4a4c-8e81-9635219ea296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356983874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.356983874
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1024521415
Short name T1129
Test name
Test status
Simulation time 14432318987 ps
CPU time 476.5 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:14:55 PM PDT 24
Peak memory 201008 kb
Host smart-1f2ba173-26df-4487-b8a6-13d5524e7132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024521415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1024521415
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3365663785
Short name T781
Test name
Test status
Simulation time 1675194643 ps
CPU time 10.75 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:07:08 PM PDT 24
Peak memory 199000 kb
Host smart-496c3262-1221-4617-b150-e9a58ebd8a97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365663785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3365663785
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.4161550187
Short name T1158
Test name
Test status
Simulation time 118080250108 ps
CPU time 51.06 seconds
Started Aug 19 06:07:06 PM PDT 24
Finished Aug 19 06:07:57 PM PDT 24
Peak memory 200968 kb
Host smart-a846100f-28b7-4b78-ad5b-0a1127d7dfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161550187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.4161550187
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2290916019
Short name T647
Test name
Test status
Simulation time 37220264094 ps
CPU time 6.14 seconds
Started Aug 19 06:06:54 PM PDT 24
Finished Aug 19 06:07:01 PM PDT 24
Peak memory 196952 kb
Host smart-9c79cf8d-fc1d-4cda-8b5c-a6c609ccef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290916019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2290916019
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.382044004
Short name T50
Test name
Test status
Simulation time 430861256 ps
CPU time 1.78 seconds
Started Aug 19 06:06:57 PM PDT 24
Finished Aug 19 06:06:59 PM PDT 24
Peak memory 199324 kb
Host smart-56289094-2d81-4171-a908-d3d73ae92e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382044004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.382044004
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1397910971
Short name T81
Test name
Test status
Simulation time 127100419973 ps
CPU time 92.04 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:08:31 PM PDT 24
Peak memory 200984 kb
Host smart-7601c038-5418-4ef5-91eb-8371ef80ba75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397910971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1397910971
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2560848171
Short name T787
Test name
Test status
Simulation time 4909638822 ps
CPU time 75.63 seconds
Started Aug 19 06:06:59 PM PDT 24
Finished Aug 19 06:08:15 PM PDT 24
Peak memory 217112 kb
Host smart-f98dc4e7-c238-44ec-ac41-44e9b56ea51b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560848171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2560848171
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3665656559
Short name T540
Test name
Test status
Simulation time 445456048 ps
CPU time 1.85 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:09 PM PDT 24
Peak memory 199268 kb
Host smart-a1234e0a-2773-4086-a86c-7e80bfbc2f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665656559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3665656559
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.827447991
Short name T378
Test name
Test status
Simulation time 69930641273 ps
CPU time 25.3 seconds
Started Aug 19 06:06:56 PM PDT 24
Finished Aug 19 06:07:22 PM PDT 24
Peak memory 200944 kb
Host smart-3cb00dd4-be5d-421a-a278-649a28dec8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827447991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.827447991
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3540434915
Short name T344
Test name
Test status
Simulation time 23869242 ps
CPU time 0.54 seconds
Started Aug 19 06:06:57 PM PDT 24
Finished Aug 19 06:06:57 PM PDT 24
Peak memory 196260 kb
Host smart-d10da374-1fd5-422a-b565-449e9013e604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540434915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3540434915
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1531638168
Short name T533
Test name
Test status
Simulation time 231380926267 ps
CPU time 118.96 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:09:06 PM PDT 24
Peak memory 200960 kb
Host smart-76ed722a-c18f-483e-a05d-5acd656d29fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531638168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1531638168
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1072366763
Short name T866
Test name
Test status
Simulation time 89533415903 ps
CPU time 46.21 seconds
Started Aug 19 06:07:00 PM PDT 24
Finished Aug 19 06:07:47 PM PDT 24
Peak memory 200984 kb
Host smart-d71fffa2-4979-406f-a511-2948ba8a6e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072366763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1072366763
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2797489455
Short name T1060
Test name
Test status
Simulation time 73868878242 ps
CPU time 26.31 seconds
Started Aug 19 06:06:57 PM PDT 24
Finished Aug 19 06:07:23 PM PDT 24
Peak memory 200940 kb
Host smart-dbc42151-729d-4202-9701-3fd3ca604d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797489455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2797489455
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3343883053
Short name T395
Test name
Test status
Simulation time 346935106241 ps
CPU time 466.22 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:14:44 PM PDT 24
Peak memory 200236 kb
Host smart-32c991e6-a6a7-4348-a787-5fdeccb8e174
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343883053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3343883053
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3903433424
Short name T1150
Test name
Test status
Simulation time 70191517989 ps
CPU time 173.97 seconds
Started Aug 19 06:06:59 PM PDT 24
Finished Aug 19 06:09:53 PM PDT 24
Peak memory 200904 kb
Host smart-8943238b-f209-48cb-80b0-65eb7f72ef89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903433424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3903433424
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.380401023
Short name T418
Test name
Test status
Simulation time 7824384937 ps
CPU time 4.54 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:12 PM PDT 24
Peak memory 199716 kb
Host smart-4f94d3c7-a2b7-4fae-a901-52982122633c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380401023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.380401023
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4242257464
Short name T1164
Test name
Test status
Simulation time 173623573609 ps
CPU time 234.05 seconds
Started Aug 19 06:06:57 PM PDT 24
Finished Aug 19 06:10:51 PM PDT 24
Peak memory 209368 kb
Host smart-5ec36019-81f5-4d87-9a0e-729b3151d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242257464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4242257464
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3161407205
Short name T1112
Test name
Test status
Simulation time 13130432028 ps
CPU time 788.52 seconds
Started Aug 19 06:07:00 PM PDT 24
Finished Aug 19 06:20:08 PM PDT 24
Peak memory 200920 kb
Host smart-5cd139df-1255-4906-a9f3-e00cb6ddaf7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161407205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3161407205
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3992761573
Short name T524
Test name
Test status
Simulation time 2656786375 ps
CPU time 3.7 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:07:02 PM PDT 24
Peak memory 199056 kb
Host smart-2bca4901-5fdb-4768-b908-1c8b456b94ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3992761573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3992761573
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.60408565
Short name T829
Test name
Test status
Simulation time 71600290561 ps
CPU time 28.58 seconds
Started Aug 19 06:07:06 PM PDT 24
Finished Aug 19 06:07:34 PM PDT 24
Peak memory 200652 kb
Host smart-39b8fdcb-2fab-4c45-a2e4-aefec8870b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60408565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.60408565
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.299623934
Short name T356
Test name
Test status
Simulation time 48689540069 ps
CPU time 73.79 seconds
Started Aug 19 06:07:00 PM PDT 24
Finished Aug 19 06:08:14 PM PDT 24
Peak memory 196804 kb
Host smart-b389d636-532d-48dc-a121-305dd4be286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299623934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.299623934
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2573547798
Short name T916
Test name
Test status
Simulation time 300161532 ps
CPU time 1.14 seconds
Started Aug 19 06:07:00 PM PDT 24
Finished Aug 19 06:07:01 PM PDT 24
Peak memory 199500 kb
Host smart-829b0276-d4aa-4326-867a-2f2adcbcb371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573547798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2573547798
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1247304383
Short name T794
Test name
Test status
Simulation time 227689425765 ps
CPU time 250.79 seconds
Started Aug 19 06:07:06 PM PDT 24
Finished Aug 19 06:11:17 PM PDT 24
Peak memory 201156 kb
Host smart-378492dd-d656-4f0c-8bcc-4aad9a9d5c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247304383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1247304383
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1507516317
Short name T31
Test name
Test status
Simulation time 966920345 ps
CPU time 13.68 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:07:12 PM PDT 24
Peak memory 200968 kb
Host smart-e044da5e-d7b8-4e5d-a21f-8247e33e2bab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507516317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1507516317
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3206806070
Short name T786
Test name
Test status
Simulation time 216724726 ps
CPU time 1.07 seconds
Started Aug 19 06:06:57 PM PDT 24
Finished Aug 19 06:06:58 PM PDT 24
Peak memory 198096 kb
Host smart-eb44a4c9-4a62-4274-b264-16a6a7a584c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206806070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3206806070
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2195179511
Short name T694
Test name
Test status
Simulation time 56795053192 ps
CPU time 13.81 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:07:12 PM PDT 24
Peak memory 197900 kb
Host smart-15624578-06f7-4784-99b0-3d4e481f8c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195179511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2195179511
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2360692909
Short name T514
Test name
Test status
Simulation time 33641751 ps
CPU time 0.55 seconds
Started Aug 19 06:07:08 PM PDT 24
Finished Aug 19 06:07:09 PM PDT 24
Peak memory 195432 kb
Host smart-78fd9ab3-7031-494e-8750-78be4d97a45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360692909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2360692909
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.485930643
Short name T772
Test name
Test status
Simulation time 63942606890 ps
CPU time 61.98 seconds
Started Aug 19 06:06:56 PM PDT 24
Finished Aug 19 06:07:58 PM PDT 24
Peak memory 200920 kb
Host smart-d52f6748-f783-48f0-9ce7-53e9de197f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485930643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.485930643
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2748076183
Short name T222
Test name
Test status
Simulation time 42514600936 ps
CPU time 15.74 seconds
Started Aug 19 06:07:00 PM PDT 24
Finished Aug 19 06:07:16 PM PDT 24
Peak memory 200672 kb
Host smart-44dc1c38-0100-45f1-ac4d-e858202e94a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748076183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2748076183
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3120600127
Short name T1101
Test name
Test status
Simulation time 217759651199 ps
CPU time 83.18 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:08:21 PM PDT 24
Peak memory 198372 kb
Host smart-a5e2a32b-d4cf-40e9-8a9c-c09d61d5d082
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120600127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3120600127
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.4168272650
Short name T978
Test name
Test status
Simulation time 84982198871 ps
CPU time 481.48 seconds
Started Aug 19 06:07:11 PM PDT 24
Finished Aug 19 06:15:12 PM PDT 24
Peak memory 201028 kb
Host smart-d9960bbe-59a6-4a6e-8bcf-efdf6b66405b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168272650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.4168272650
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.139352759
Short name T689
Test name
Test status
Simulation time 6611479017 ps
CPU time 11.19 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:18 PM PDT 24
Peak memory 200140 kb
Host smart-426adeab-9c74-4a0a-b84b-d48cba7407fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139352759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.139352759
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3561263673
Short name T803
Test name
Test status
Simulation time 98886653826 ps
CPU time 47.68 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:54 PM PDT 24
Peak memory 201144 kb
Host smart-07a8d0c6-8dd0-4245-80ec-dea6c560ddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561263673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3561263673
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3281833490
Short name T658
Test name
Test status
Simulation time 10177568164 ps
CPU time 59.27 seconds
Started Aug 19 06:07:06 PM PDT 24
Finished Aug 19 06:08:06 PM PDT 24
Peak memory 200912 kb
Host smart-2152a17a-e7f6-4417-9cbb-ee756abaad3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281833490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3281833490
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.666977284
Short name T876
Test name
Test status
Simulation time 2415857972 ps
CPU time 1.71 seconds
Started Aug 19 06:07:00 PM PDT 24
Finished Aug 19 06:07:02 PM PDT 24
Peak memory 199016 kb
Host smart-161e6e9e-dc69-47fc-9fd9-9b7dbb970e1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666977284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.666977284
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1846887691
Short name T708
Test name
Test status
Simulation time 111953071245 ps
CPU time 75.04 seconds
Started Aug 19 06:07:06 PM PDT 24
Finished Aug 19 06:08:22 PM PDT 24
Peak memory 200876 kb
Host smart-cc4b4a4d-3c3c-4505-9f3b-7f0eabc05da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846887691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1846887691
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.527180868
Short name T523
Test name
Test status
Simulation time 42040890938 ps
CPU time 5.21 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:12 PM PDT 24
Peak memory 197096 kb
Host smart-74c6b196-1de5-4fc4-ae50-de3e2846990c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527180868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.527180868
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2810303342
Short name T705
Test name
Test status
Simulation time 116842401 ps
CPU time 0.8 seconds
Started Aug 19 06:06:59 PM PDT 24
Finished Aug 19 06:07:00 PM PDT 24
Peak memory 197992 kb
Host smart-29111145-32d1-48ce-ae66-44ebaa9691ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810303342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2810303342
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1005827103
Short name T173
Test name
Test status
Simulation time 250564793300 ps
CPU time 178.82 seconds
Started Aug 19 06:07:11 PM PDT 24
Finished Aug 19 06:10:10 PM PDT 24
Peak memory 200928 kb
Host smart-dfe3f1a1-90bd-4035-8b34-eccfd1ae1cf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005827103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1005827103
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3158203022
Short name T666
Test name
Test status
Simulation time 17495834945 ps
CPU time 42.03 seconds
Started Aug 19 06:07:09 PM PDT 24
Finished Aug 19 06:07:51 PM PDT 24
Peak memory 217596 kb
Host smart-4c585ceb-a29f-4627-a510-4f858c785eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158203022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3158203022
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.704207094
Short name T297
Test name
Test status
Simulation time 3545692555 ps
CPU time 2.42 seconds
Started Aug 19 06:07:08 PM PDT 24
Finished Aug 19 06:07:11 PM PDT 24
Peak memory 199504 kb
Host smart-7adc7fe4-3cbc-4a56-a605-99d48b0731fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704207094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.704207094
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3488331610
Short name T929
Test name
Test status
Simulation time 18855017524 ps
CPU time 17.92 seconds
Started Aug 19 06:06:58 PM PDT 24
Finished Aug 19 06:07:16 PM PDT 24
Peak memory 200972 kb
Host smart-5b1e747b-8011-4cad-bb21-bd1a0e3c0de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488331610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3488331610
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2699671668
Short name T811
Test name
Test status
Simulation time 18786178 ps
CPU time 0.56 seconds
Started Aug 19 06:07:13 PM PDT 24
Finished Aug 19 06:07:13 PM PDT 24
Peak memory 196276 kb
Host smart-ab010100-7f67-4ff6-b181-3df0a484ca06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699671668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2699671668
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2081168036
Short name T510
Test name
Test status
Simulation time 46937242425 ps
CPU time 38.74 seconds
Started Aug 19 06:07:13 PM PDT 24
Finished Aug 19 06:07:52 PM PDT 24
Peak memory 200960 kb
Host smart-965682a7-c075-4bec-aba7-038191abefd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081168036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2081168036
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2403439286
Short name T1027
Test name
Test status
Simulation time 34229317610 ps
CPU time 51.01 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:58 PM PDT 24
Peak memory 200932 kb
Host smart-7de61eaa-393f-4281-af3f-80efca07070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403439286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2403439286
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1250383654
Short name T1179
Test name
Test status
Simulation time 74850710354 ps
CPU time 194.09 seconds
Started Aug 19 06:07:09 PM PDT 24
Finished Aug 19 06:10:24 PM PDT 24
Peak memory 200984 kb
Host smart-8ba46f19-0906-410f-89f4-2099e233054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250383654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1250383654
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1313476554
Short name T490
Test name
Test status
Simulation time 182899672040 ps
CPU time 77.22 seconds
Started Aug 19 06:07:10 PM PDT 24
Finished Aug 19 06:08:27 PM PDT 24
Peak memory 200712 kb
Host smart-80656ef2-eadc-44f8-9ca9-404505ea609f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313476554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1313476554
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3048052029
Short name T422
Test name
Test status
Simulation time 128196181789 ps
CPU time 174.08 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:10:01 PM PDT 24
Peak memory 201000 kb
Host smart-3e48f405-ffee-46f4-b83a-1cf53d45a32e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048052029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3048052029
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2280755783
Short name T1083
Test name
Test status
Simulation time 6932714897 ps
CPU time 5.06 seconds
Started Aug 19 06:07:10 PM PDT 24
Finished Aug 19 06:07:16 PM PDT 24
Peak memory 200048 kb
Host smart-9079c64f-25c8-462b-a260-a3e48ddba868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280755783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2280755783
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2013387010
Short name T1045
Test name
Test status
Simulation time 248647639212 ps
CPU time 130.41 seconds
Started Aug 19 06:07:08 PM PDT 24
Finished Aug 19 06:09:18 PM PDT 24
Peak memory 201244 kb
Host smart-daa054d1-9db5-41b2-8358-41b139f7a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013387010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2013387010
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.250428513
Short name T824
Test name
Test status
Simulation time 8642519021 ps
CPU time 108.09 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:08:56 PM PDT 24
Peak memory 200928 kb
Host smart-d8562c73-1ba6-4fc5-8ab4-97d330f534c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250428513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.250428513
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.282085956
Short name T777
Test name
Test status
Simulation time 2019860097 ps
CPU time 15.44 seconds
Started Aug 19 06:07:10 PM PDT 24
Finished Aug 19 06:07:26 PM PDT 24
Peak memory 198748 kb
Host smart-845e27c6-adb7-47f5-b774-2ad36d3ac02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282085956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.282085956
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2729780540
Short name T319
Test name
Test status
Simulation time 18564468223 ps
CPU time 36.66 seconds
Started Aug 19 06:07:11 PM PDT 24
Finished Aug 19 06:07:48 PM PDT 24
Peak memory 200944 kb
Host smart-f957b427-c3e7-4858-96fc-9658474ceb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729780540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2729780540
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2582280644
Short name T991
Test name
Test status
Simulation time 56190510297 ps
CPU time 75.52 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:08:22 PM PDT 24
Peak memory 197772 kb
Host smart-50d11682-2f6b-4d61-9c81-faf553d78ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582280644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2582280644
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.303208882
Short name T281
Test name
Test status
Simulation time 504102588 ps
CPU time 2.18 seconds
Started Aug 19 06:07:09 PM PDT 24
Finished Aug 19 06:07:11 PM PDT 24
Peak memory 199320 kb
Host smart-8f9cbc78-fc8b-4ade-a98d-95faadbe71d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303208882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.303208882
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.378549008
Short name T144
Test name
Test status
Simulation time 450340078305 ps
CPU time 205.48 seconds
Started Aug 19 06:07:08 PM PDT 24
Finished Aug 19 06:10:34 PM PDT 24
Peak memory 200888 kb
Host smart-34060379-a733-4da8-a078-defd3c0b30e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378549008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.378549008
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1041640065
Short name T554
Test name
Test status
Simulation time 3836084861 ps
CPU time 23.42 seconds
Started Aug 19 06:07:09 PM PDT 24
Finished Aug 19 06:07:33 PM PDT 24
Peak memory 217288 kb
Host smart-9b2a9d6f-564f-4e4c-8ff6-140ad65508cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041640065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1041640065
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.475053748
Short name T565
Test name
Test status
Simulation time 1078529310 ps
CPU time 3.74 seconds
Started Aug 19 06:07:10 PM PDT 24
Finished Aug 19 06:07:14 PM PDT 24
Peak memory 199192 kb
Host smart-b680569c-e0c4-4ffb-8dec-cc0344707d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475053748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.475053748
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.504735304
Short name T676
Test name
Test status
Simulation time 9812904340 ps
CPU time 4.91 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:12 PM PDT 24
Peak memory 200964 kb
Host smart-b5f47cb4-bbd9-4713-9ea0-9707d21c92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504735304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.504735304
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.767269548
Short name T725
Test name
Test status
Simulation time 43945750 ps
CPU time 0.55 seconds
Started Aug 19 06:07:11 PM PDT 24
Finished Aug 19 06:07:11 PM PDT 24
Peak memory 195932 kb
Host smart-24807b0c-2403-4678-b257-da0ed51f158f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767269548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.767269548
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3298244620
Short name T886
Test name
Test status
Simulation time 40067646918 ps
CPU time 72.3 seconds
Started Aug 19 06:07:10 PM PDT 24
Finished Aug 19 06:08:23 PM PDT 24
Peak memory 200968 kb
Host smart-f6f99efd-7cab-49fb-bc99-6890d08760d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298244620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3298244620
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.4204241539
Short name T282
Test name
Test status
Simulation time 183166793784 ps
CPU time 51.69 seconds
Started Aug 19 06:07:08 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 200984 kb
Host smart-0862f16b-03ad-4c7d-b903-f6bef15ac2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204241539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.4204241539
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.399786791
Short name T1122
Test name
Test status
Simulation time 23875761912 ps
CPU time 39.07 seconds
Started Aug 19 06:07:11 PM PDT 24
Finished Aug 19 06:07:50 PM PDT 24
Peak memory 200944 kb
Host smart-13fde32c-95fc-454a-96b8-26fb439e9673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399786791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.399786791
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2556175861
Short name T9
Test name
Test status
Simulation time 32984725469 ps
CPU time 52.03 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:59 PM PDT 24
Peak memory 200924 kb
Host smart-0a12d649-e25d-4b03-9ebb-78f4a6c9ecdf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556175861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2556175861
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.456519738
Short name T1151
Test name
Test status
Simulation time 149757288093 ps
CPU time 395.83 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:13:43 PM PDT 24
Peak memory 200944 kb
Host smart-78678bcc-7902-483b-a09f-85748a0ceec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456519738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.456519738
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1070659357
Short name T871
Test name
Test status
Simulation time 2419306088 ps
CPU time 9.05 seconds
Started Aug 19 06:07:09 PM PDT 24
Finished Aug 19 06:07:18 PM PDT 24
Peak memory 199416 kb
Host smart-faf758f3-5877-4f2d-b619-0ff02621a88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070659357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1070659357
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1049967231
Short name T334
Test name
Test status
Simulation time 56095485757 ps
CPU time 26.88 seconds
Started Aug 19 06:07:09 PM PDT 24
Finished Aug 19 06:07:36 PM PDT 24
Peak memory 201172 kb
Host smart-8ab06236-67ed-4377-b861-53ab624a8608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049967231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1049967231
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.317079244
Short name T851
Test name
Test status
Simulation time 5127288678 ps
CPU time 229.87 seconds
Started Aug 19 06:07:09 PM PDT 24
Finished Aug 19 06:10:59 PM PDT 24
Peak memory 200920 kb
Host smart-3ae09de2-96b6-4f05-bc8e-5c374c40f678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317079244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.317079244
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1965071706
Short name T962
Test name
Test status
Simulation time 7060349227 ps
CPU time 35.98 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:43 PM PDT 24
Peak memory 200248 kb
Host smart-b8ec4cab-2eb2-40b7-a87d-e0109db49cf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965071706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1965071706
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1537630686
Short name T501
Test name
Test status
Simulation time 1749638702 ps
CPU time 3.16 seconds
Started Aug 19 06:07:08 PM PDT 24
Finished Aug 19 06:07:12 PM PDT 24
Peak memory 196444 kb
Host smart-ec620988-0a73-4295-bf96-5b38df6fe395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537630686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1537630686
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1028068383
Short name T801
Test name
Test status
Simulation time 734489100 ps
CPU time 2.35 seconds
Started Aug 19 06:07:13 PM PDT 24
Finished Aug 19 06:07:15 PM PDT 24
Peak memory 199240 kb
Host smart-dedfca81-7921-4465-a78d-81d592411cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028068383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1028068383
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1205987259
Short name T175
Test name
Test status
Simulation time 482950611801 ps
CPU time 1605.05 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:33:53 PM PDT 24
Peak memory 209408 kb
Host smart-cc26e3ce-2b24-434a-a61f-806622c7aa71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205987259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1205987259
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2261644165
Short name T295
Test name
Test status
Simulation time 3438331386 ps
CPU time 24.77 seconds
Started Aug 19 06:07:07 PM PDT 24
Finished Aug 19 06:07:32 PM PDT 24
Peak memory 217372 kb
Host smart-e86b14e4-e9e4-4d00-aeb1-e76c17f3ba47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261644165 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2261644165
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3389020272
Short name T650
Test name
Test status
Simulation time 992446834 ps
CPU time 2.18 seconds
Started Aug 19 06:07:08 PM PDT 24
Finished Aug 19 06:07:10 PM PDT 24
Peak memory 199488 kb
Host smart-cc18e5bf-b879-431b-b8c8-586c5e87c899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389020272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3389020272
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2980276402
Short name T679
Test name
Test status
Simulation time 127212889191 ps
CPU time 49.57 seconds
Started Aug 19 06:07:11 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 200912 kb
Host smart-357fdfa2-c03b-44e3-88c8-7c6b4078fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980276402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2980276402
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.4176401974
Short name T517
Test name
Test status
Simulation time 12783854 ps
CPU time 0.57 seconds
Started Aug 19 06:07:16 PM PDT 24
Finished Aug 19 06:07:17 PM PDT 24
Peak memory 196276 kb
Host smart-5f8d5071-d70a-45f5-9cb4-47aea280c0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176401974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.4176401974
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.4230137818
Short name T726
Test name
Test status
Simulation time 137219872144 ps
CPU time 104.18 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:09:04 PM PDT 24
Peak memory 200980 kb
Host smart-dbf37143-0767-4b6a-af83-f798a0be991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230137818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.4230137818
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.807163861
Short name T157
Test name
Test status
Simulation time 130726161261 ps
CPU time 149.79 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:09:47 PM PDT 24
Peak memory 200968 kb
Host smart-cfe065c8-4d28-4a42-8c8b-f249e80504d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807163861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.807163861
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2075754476
Short name T660
Test name
Test status
Simulation time 86520862909 ps
CPU time 93.73 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:08:51 PM PDT 24
Peak memory 200972 kb
Host smart-40588ae1-d071-4026-bfe8-77274d35e0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075754476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2075754476
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2920246611
Short name T521
Test name
Test status
Simulation time 26373395083 ps
CPU time 5.32 seconds
Started Aug 19 06:07:19 PM PDT 24
Finished Aug 19 06:07:25 PM PDT 24
Peak memory 199028 kb
Host smart-234eff00-2087-4863-ac89-fef66fe85667
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920246611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2920246611
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2817772050
Short name T436
Test name
Test status
Simulation time 129091625820 ps
CPU time 351.94 seconds
Started Aug 19 06:07:16 PM PDT 24
Finished Aug 19 06:13:08 PM PDT 24
Peak memory 200984 kb
Host smart-2ff92aa2-22cc-4e17-b525-07e92f645ced
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817772050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2817772050
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.4248846710
Short name T551
Test name
Test status
Simulation time 7334241901 ps
CPU time 5.25 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:07:22 PM PDT 24
Peak memory 200856 kb
Host smart-ef71e309-32cb-4378-927d-08bd1f3535f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248846710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4248846710
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1274577120
Short name T627
Test name
Test status
Simulation time 37193370625 ps
CPU time 35.85 seconds
Started Aug 19 06:07:19 PM PDT 24
Finished Aug 19 06:07:55 PM PDT 24
Peak memory 199472 kb
Host smart-023432d9-3d13-4e4c-ad63-3d1c815415ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274577120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1274577120
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2875893237
Short name T492
Test name
Test status
Simulation time 12454697838 ps
CPU time 101.42 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:08:59 PM PDT 24
Peak memory 201112 kb
Host smart-ff2bff5a-d653-4e0f-8951-4d0a377eac76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875893237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2875893237
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2950933601
Short name T1001
Test name
Test status
Simulation time 5498248997 ps
CPU time 13.15 seconds
Started Aug 19 06:07:15 PM PDT 24
Finished Aug 19 06:07:28 PM PDT 24
Peak memory 200396 kb
Host smart-eb28d2f9-57b4-4c52-a8df-6bc4ab4243a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950933601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2950933601
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1210523353
Short name T856
Test name
Test status
Simulation time 57481524405 ps
CPU time 83.82 seconds
Started Aug 19 06:07:16 PM PDT 24
Finished Aug 19 06:08:39 PM PDT 24
Peak memory 200908 kb
Host smart-ef0f6c66-8514-4c73-9d1d-7deebec3441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210523353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1210523353
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.4074440753
Short name T1146
Test name
Test status
Simulation time 4107650129 ps
CPU time 6.99 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:07:24 PM PDT 24
Peak memory 197284 kb
Host smart-27d5d981-1bbf-4bc8-a368-5b97136bc5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074440753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4074440753
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1248197438
Short name T573
Test name
Test status
Simulation time 671837643 ps
CPU time 1.49 seconds
Started Aug 19 06:07:23 PM PDT 24
Finished Aug 19 06:07:24 PM PDT 24
Peak memory 199688 kb
Host smart-76329c41-4f33-4e73-a0f1-c56c65184f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248197438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1248197438
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.876455708
Short name T673
Test name
Test status
Simulation time 102376145721 ps
CPU time 44.36 seconds
Started Aug 19 06:07:15 PM PDT 24
Finished Aug 19 06:07:59 PM PDT 24
Peak memory 217308 kb
Host smart-8456c0ad-0226-4de8-8727-e3c87fa0cfc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876455708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.876455708
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.265406531
Short name T1019
Test name
Test status
Simulation time 4155178010 ps
CPU time 66.62 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:08:24 PM PDT 24
Peak memory 209292 kb
Host smart-7465929c-b60d-4836-978a-418b2af94168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265406531 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.265406531
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.564967020
Short name T15
Test name
Test status
Simulation time 8066089951 ps
CPU time 10.97 seconds
Started Aug 19 06:07:23 PM PDT 24
Finished Aug 19 06:07:34 PM PDT 24
Peak memory 200884 kb
Host smart-15548eca-9792-419b-bd14-0cabe57cab5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564967020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.564967020
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3932827530
Short name T42
Test name
Test status
Simulation time 103716549634 ps
CPU time 74.69 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:08:32 PM PDT 24
Peak memory 200960 kb
Host smart-ea7efd6d-d3b9-4b69-b605-f6d895f9bbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932827530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3932827530
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1256601862
Short name T765
Test name
Test status
Simulation time 14920645 ps
CPU time 0.6 seconds
Started Aug 19 06:07:18 PM PDT 24
Finished Aug 19 06:07:18 PM PDT 24
Peak memory 196564 kb
Host smart-12ce4618-1c77-4e3d-87ea-6725524bab73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256601862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1256601862
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3201302866
Short name T421
Test name
Test status
Simulation time 119372460528 ps
CPU time 48.92 seconds
Started Aug 19 06:07:18 PM PDT 24
Finished Aug 19 06:08:07 PM PDT 24
Peak memory 200964 kb
Host smart-b812d693-a78f-466e-8056-8a31c569cfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201302866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3201302866
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3823413774
Short name T1033
Test name
Test status
Simulation time 34653539815 ps
CPU time 54.9 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:08:15 PM PDT 24
Peak memory 200952 kb
Host smart-d15d4f91-35b4-4a77-a0b5-f1acdbd14c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823413774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3823413774
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4178807884
Short name T1069
Test name
Test status
Simulation time 12094957829 ps
CPU time 10.68 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:07:31 PM PDT 24
Peak memory 200920 kb
Host smart-75e13db7-cc4a-454f-9c8c-18f5f8639c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178807884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4178807884
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2552455225
Short name T956
Test name
Test status
Simulation time 48519992891 ps
CPU time 20.49 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:07:41 PM PDT 24
Peak memory 200976 kb
Host smart-cbefacd1-1ce9-4df3-8b4a-a93d8fc214ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552455225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2552455225
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_loopback.1496817949
Short name T468
Test name
Test status
Simulation time 9971628691 ps
CPU time 18.93 seconds
Started Aug 19 06:07:19 PM PDT 24
Finished Aug 19 06:07:38 PM PDT 24
Peak memory 200900 kb
Host smart-e3d33d7a-fdc7-49ec-ae38-b0be78087314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496817949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1496817949
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2078967416
Short name T275
Test name
Test status
Simulation time 144606047491 ps
CPU time 74.97 seconds
Started Aug 19 06:07:19 PM PDT 24
Finished Aug 19 06:08:34 PM PDT 24
Peak memory 209544 kb
Host smart-2b2c2a22-1a40-41df-b343-9dbc4dba263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078967416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2078967416
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3220198080
Short name T697
Test name
Test status
Simulation time 27575700509 ps
CPU time 338.42 seconds
Started Aug 19 06:07:19 PM PDT 24
Finished Aug 19 06:12:57 PM PDT 24
Peak memory 200984 kb
Host smart-4f55da25-8366-47ba-bac8-d2ed099cc0a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220198080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3220198080
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.224057252
Short name T1078
Test name
Test status
Simulation time 2924656903 ps
CPU time 9.83 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:07:29 PM PDT 24
Peak memory 199024 kb
Host smart-b984c6ca-de45-4331-8722-40cd331a1b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224057252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.224057252
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1894854836
Short name T966
Test name
Test status
Simulation time 49730852432 ps
CPU time 37.62 seconds
Started Aug 19 06:07:18 PM PDT 24
Finished Aug 19 06:07:56 PM PDT 24
Peak memory 200960 kb
Host smart-0dc81567-0880-4d00-b8c6-a5614f5ff7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894854836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1894854836
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2989344247
Short name T996
Test name
Test status
Simulation time 51707022040 ps
CPU time 83.46 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:08:43 PM PDT 24
Peak memory 196752 kb
Host smart-9b57f532-0b72-4394-954f-f5b847233f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989344247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2989344247
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.122626982
Short name T1132
Test name
Test status
Simulation time 5364125935 ps
CPU time 30.01 seconds
Started Aug 19 06:07:21 PM PDT 24
Finished Aug 19 06:07:51 PM PDT 24
Peak memory 200680 kb
Host smart-933ed0c9-fab9-4c44-b78c-7e16da7f787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122626982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.122626982
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1621837672
Short name T263
Test name
Test status
Simulation time 159330054879 ps
CPU time 181.26 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:10:22 PM PDT 24
Peak memory 200932 kb
Host smart-cc1639a4-2e4f-48ff-b51b-252167a048dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621837672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1621837672
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2644723396
Short name T630
Test name
Test status
Simulation time 3022072518 ps
CPU time 2.69 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:07:23 PM PDT 24
Peak memory 200148 kb
Host smart-055e810a-cf2f-489b-874e-99cd466f63fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644723396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2644723396
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.671473522
Short name T425
Test name
Test status
Simulation time 136084778940 ps
CPU time 218.77 seconds
Started Aug 19 06:07:23 PM PDT 24
Finished Aug 19 06:11:02 PM PDT 24
Peak memory 200932 kb
Host smart-e417d27d-4193-4a84-8ca3-b82d6de031ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671473522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.671473522
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2429113973
Short name T594
Test name
Test status
Simulation time 30899307 ps
CPU time 0.56 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:07:27 PM PDT 24
Peak memory 196576 kb
Host smart-ea3ecead-e9ff-4cb6-8bd1-d8a74f8ae954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429113973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2429113973
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2209668432
Short name T1059
Test name
Test status
Simulation time 143978441438 ps
CPU time 588.78 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:17:09 PM PDT 24
Peak memory 200976 kb
Host smart-b4bf2dca-db90-4ab5-b1b5-63803d29073f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209668432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2209668432
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1460545902
Short name T1008
Test name
Test status
Simulation time 109066100888 ps
CPU time 158.22 seconds
Started Aug 19 06:07:18 PM PDT 24
Finished Aug 19 06:09:56 PM PDT 24
Peak memory 200984 kb
Host smart-2593e52d-3c9f-4a09-83f7-f52c999a0ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460545902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1460545902
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.480195913
Short name T181
Test name
Test status
Simulation time 28888158961 ps
CPU time 24.38 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:07:45 PM PDT 24
Peak memory 200900 kb
Host smart-e4778ecd-645a-4181-b3b4-67689daf16fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480195913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.480195913
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1509701362
Short name T103
Test name
Test status
Simulation time 22688756704 ps
CPU time 2.97 seconds
Started Aug 19 06:07:19 PM PDT 24
Finished Aug 19 06:07:22 PM PDT 24
Peak memory 198188 kb
Host smart-aaa922c3-abc9-479f-b083-57e9cd7a5d2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509701362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1509701362
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.353541959
Short name T1170
Test name
Test status
Simulation time 102709374263 ps
CPU time 865.48 seconds
Started Aug 19 06:07:28 PM PDT 24
Finished Aug 19 06:21:54 PM PDT 24
Peak memory 200988 kb
Host smart-0b473719-f010-40d0-a94b-edbac29d3375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=353541959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.353541959
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.592068801
Short name T620
Test name
Test status
Simulation time 8507629258 ps
CPU time 13.82 seconds
Started Aug 19 06:07:30 PM PDT 24
Finished Aug 19 06:07:44 PM PDT 24
Peak memory 199656 kb
Host smart-6d8ef068-ead0-4971-bbff-3e94f47ce3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592068801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.592068801
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3989601944
Short name T1134
Test name
Test status
Simulation time 18871305938 ps
CPU time 33.71 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:07:54 PM PDT 24
Peak memory 200212 kb
Host smart-51e91ee4-922f-482b-bae2-ace8e65fe6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989601944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3989601944
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.829479565
Short name T513
Test name
Test status
Simulation time 5177870408 ps
CPU time 220.42 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:11:07 PM PDT 24
Peak memory 200904 kb
Host smart-43d66dd9-6450-42d1-96c2-54d9f78c824b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829479565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.829479565
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3233120673
Short name T20
Test name
Test status
Simulation time 6757945277 ps
CPU time 16.52 seconds
Started Aug 19 06:07:18 PM PDT 24
Finished Aug 19 06:07:35 PM PDT 24
Peak memory 199808 kb
Host smart-b6db66b4-6279-48e4-bea4-e70e6c1caa4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233120673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3233120673
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.841867843
Short name T355
Test name
Test status
Simulation time 15103401932 ps
CPU time 12.08 seconds
Started Aug 19 06:07:20 PM PDT 24
Finished Aug 19 06:07:32 PM PDT 24
Peak memory 200760 kb
Host smart-e4219cf2-f8e4-47d3-8c14-d5448a35d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841867843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.841867843
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1299444927
Short name T474
Test name
Test status
Simulation time 4950855355 ps
CPU time 4.86 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:07:22 PM PDT 24
Peak memory 197456 kb
Host smart-6aa7ffda-354f-4b3a-8e86-6c32c9ef0475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299444927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1299444927
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1426524326
Short name T496
Test name
Test status
Simulation time 11618228974 ps
CPU time 37.72 seconds
Started Aug 19 06:07:17 PM PDT 24
Finished Aug 19 06:07:55 PM PDT 24
Peak memory 200680 kb
Host smart-34b6d78a-2480-4bdd-b2ec-62879810dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426524326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1426524326
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3800158393
Short name T287
Test name
Test status
Simulation time 202202319736 ps
CPU time 371.14 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:13:37 PM PDT 24
Peak memory 200976 kb
Host smart-8491bf3c-b45c-4fca-9606-b7419bbf4d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800158393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3800158393
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3060169026
Short name T988
Test name
Test status
Simulation time 52181103777 ps
CPU time 50.08 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:08:16 PM PDT 24
Peak memory 213732 kb
Host smart-0dc33fc1-da58-4db4-ae84-13325ff1c6da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060169026 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3060169026
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.612429183
Short name T476
Test name
Test status
Simulation time 4569733703 ps
CPU time 2.29 seconds
Started Aug 19 06:07:16 PM PDT 24
Finished Aug 19 06:07:19 PM PDT 24
Peak memory 200364 kb
Host smart-323c4882-9042-4898-8399-fe12532e7f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612429183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.612429183
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1607770134
Short name T252
Test name
Test status
Simulation time 46652717657 ps
CPU time 17.26 seconds
Started Aug 19 06:07:18 PM PDT 24
Finished Aug 19 06:07:35 PM PDT 24
Peak memory 198624 kb
Host smart-d252dc20-05ef-4a0e-b4ba-7eeb4c2be527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607770134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1607770134
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2765989843
Short name T827
Test name
Test status
Simulation time 93442451 ps
CPU time 0.58 seconds
Started Aug 19 06:05:11 PM PDT 24
Finished Aug 19 06:05:12 PM PDT 24
Peak memory 195256 kb
Host smart-4bc7ac88-9bc8-480d-a452-1462375379aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765989843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2765989843
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.599959058
Short name T621
Test name
Test status
Simulation time 29207299884 ps
CPU time 54.01 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:06:04 PM PDT 24
Peak memory 201128 kb
Host smart-27565f4c-5eff-46df-8837-d76a645b81c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599959058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.599959058
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.887889600
Short name T519
Test name
Test status
Simulation time 61745438172 ps
CPU time 95.42 seconds
Started Aug 19 06:05:15 PM PDT 24
Finished Aug 19 06:06:50 PM PDT 24
Peak memory 200592 kb
Host smart-6db6fa01-7441-4e0d-b2cd-e437865a2e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887889600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.887889600
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2962009595
Short name T221
Test name
Test status
Simulation time 54880974090 ps
CPU time 173.06 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:08:06 PM PDT 24
Peak memory 200944 kb
Host smart-d31d4e4d-d6c9-4c69-9c8c-1a32f996c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962009595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2962009595
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1479307211
Short name T321
Test name
Test status
Simulation time 606922818652 ps
CPU time 981.34 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:21:32 PM PDT 24
Peak memory 200236 kb
Host smart-fa223e40-4684-4ca5-a078-9745c07daca7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479307211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1479307211
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1346332920
Short name T938
Test name
Test status
Simulation time 203879301382 ps
CPU time 218.1 seconds
Started Aug 19 06:05:11 PM PDT 24
Finished Aug 19 06:08:49 PM PDT 24
Peak memory 201012 kb
Host smart-ed37aa51-e058-4e37-be88-88ff63f14460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346332920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1346332920
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.950770025
Short name T1161
Test name
Test status
Simulation time 8018330800 ps
CPU time 14.61 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:05:28 PM PDT 24
Peak memory 200876 kb
Host smart-eebaa384-3911-42a6-af14-3f45ceee8ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950770025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.950770025
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.710064169
Short name T274
Test name
Test status
Simulation time 82656302951 ps
CPU time 174.72 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:08:07 PM PDT 24
Peak memory 209388 kb
Host smart-96dfb932-1151-4ffa-a5a7-81f77ef1f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710064169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.710064169
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.324587672
Short name T931
Test name
Test status
Simulation time 9354017321 ps
CPU time 282.84 seconds
Started Aug 19 06:05:11 PM PDT 24
Finished Aug 19 06:09:54 PM PDT 24
Peak memory 200968 kb
Host smart-0c0ae071-e01c-477a-a30e-59f582401f4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324587672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.324587672
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3119941543
Short name T532
Test name
Test status
Simulation time 5294305000 ps
CPU time 6.47 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:05:18 PM PDT 24
Peak memory 200076 kb
Host smart-135aa993-1cee-484a-bd98-dcedcb1f9d2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119941543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3119941543
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1334825632
Short name T307
Test name
Test status
Simulation time 54531693427 ps
CPU time 38.15 seconds
Started Aug 19 06:05:11 PM PDT 24
Finished Aug 19 06:05:50 PM PDT 24
Peak memory 200964 kb
Host smart-bcc799ea-d214-4d03-a24e-1c9af8197de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334825632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1334825632
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2410775486
Short name T527
Test name
Test status
Simulation time 2642030842 ps
CPU time 2.43 seconds
Started Aug 19 06:05:11 PM PDT 24
Finished Aug 19 06:05:14 PM PDT 24
Peak memory 197468 kb
Host smart-eb248739-ce3a-4160-aeea-634ad4e49c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410775486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2410775486
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.4136991701
Short name T79
Test name
Test status
Simulation time 65278786 ps
CPU time 0.82 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:05:11 PM PDT 24
Peak memory 218984 kb
Host smart-8224be26-4438-4ed0-a95c-411bddced46b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136991701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.4136991701
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.788381191
Short name T635
Test name
Test status
Simulation time 706056880 ps
CPU time 2.38 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:05:16 PM PDT 24
Peak memory 199228 kb
Host smart-32908bcd-fb0a-47f5-b395-6b2c562e67df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788381191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.788381191
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.772120871
Short name T535
Test name
Test status
Simulation time 71484010549 ps
CPU time 68.01 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:06:20 PM PDT 24
Peak memory 200924 kb
Host smart-0e99b600-a9fe-4500-993a-8a0ff53bb6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772120871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.772120871
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.346443849
Short name T648
Test name
Test status
Simulation time 66504404421 ps
CPU time 61.68 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:06:12 PM PDT 24
Peak memory 217344 kb
Host smart-7d8a80f4-a3bf-4f72-9018-19797cb426e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346443849 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.346443849
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2543538373
Short name T411
Test name
Test status
Simulation time 6746469789 ps
CPU time 15.74 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:05:28 PM PDT 24
Peak memory 200860 kb
Host smart-cfe27ee1-4819-4576-a843-02e213cc95ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543538373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2543538373
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.249314283
Short name T432
Test name
Test status
Simulation time 177036150633 ps
CPU time 94.69 seconds
Started Aug 19 06:05:15 PM PDT 24
Finished Aug 19 06:06:50 PM PDT 24
Peak memory 200908 kb
Host smart-46145e1a-9517-4c7a-973e-a4e3471b0032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249314283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.249314283
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3878359159
Short name T926
Test name
Test status
Simulation time 35320365 ps
CPU time 0.54 seconds
Started Aug 19 06:07:32 PM PDT 24
Finished Aug 19 06:07:33 PM PDT 24
Peak memory 195228 kb
Host smart-c0129931-40b1-4603-8b2f-8f2fc5f333d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878359159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3878359159
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2353055569
Short name T119
Test name
Test status
Simulation time 109602684454 ps
CPU time 81.77 seconds
Started Aug 19 06:07:28 PM PDT 24
Finished Aug 19 06:08:50 PM PDT 24
Peak memory 200984 kb
Host smart-3dc5ea2a-edc3-4078-ad16-e09e64067fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353055569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2353055569
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1078631890
Short name T789
Test name
Test status
Simulation time 12430087752 ps
CPU time 31.18 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:07:58 PM PDT 24
Peak memory 200936 kb
Host smart-575b9a4a-58ae-4110-be63-d2db47a9a30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078631890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1078631890
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3789471437
Short name T617
Test name
Test status
Simulation time 31919451062 ps
CPU time 13.62 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:07:40 PM PDT 24
Peak memory 200368 kb
Host smart-0d74a52b-5136-4760-9497-d6a4bd3c775c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789471437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3789471437
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.796097642
Short name T965
Test name
Test status
Simulation time 67716732384 ps
CPU time 430.4 seconds
Started Aug 19 06:07:30 PM PDT 24
Finished Aug 19 06:14:40 PM PDT 24
Peak memory 200908 kb
Host smart-90490f9c-072c-4a00-b152-343882487f9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796097642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.796097642
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2580875222
Short name T338
Test name
Test status
Simulation time 8029211364 ps
CPU time 11.27 seconds
Started Aug 19 06:07:29 PM PDT 24
Finished Aug 19 06:07:40 PM PDT 24
Peak memory 200112 kb
Host smart-1320d50a-0342-4f68-926d-a25a50d94a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580875222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2580875222
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1433642937
Short name T461
Test name
Test status
Simulation time 133252593536 ps
CPU time 294.43 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:12:19 PM PDT 24
Peak memory 209148 kb
Host smart-2c6fdece-c39c-4a89-ba84-bfff01af1d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433642937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1433642937
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3160127526
Short name T947
Test name
Test status
Simulation time 11787614854 ps
CPU time 684.15 seconds
Started Aug 19 06:07:22 PM PDT 24
Finished Aug 19 06:18:46 PM PDT 24
Peak memory 201108 kb
Host smart-40e57131-8d10-4d2d-a1de-629f28fba7ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160127526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3160127526
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3833977294
Short name T415
Test name
Test status
Simulation time 6003676841 ps
CPU time 39.91 seconds
Started Aug 19 06:07:29 PM PDT 24
Finished Aug 19 06:08:10 PM PDT 24
Peak memory 200172 kb
Host smart-fd8be642-06d8-4d9c-b4b8-9187d454c759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833977294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3833977294
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2561986655
Short name T957
Test name
Test status
Simulation time 78040793407 ps
CPU time 129.09 seconds
Started Aug 19 06:07:28 PM PDT 24
Finished Aug 19 06:09:37 PM PDT 24
Peak memory 200928 kb
Host smart-23456e82-9e87-4fdc-97af-d753877ac5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561986655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2561986655
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2531097459
Short name T1121
Test name
Test status
Simulation time 29553598450 ps
CPU time 20.02 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:07:45 PM PDT 24
Peak memory 197104 kb
Host smart-05a059f6-5d8a-4066-9f0f-8ee6e2e3e98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531097459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2531097459
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3133597601
Short name T602
Test name
Test status
Simulation time 271500523 ps
CPU time 1.4 seconds
Started Aug 19 06:07:56 PM PDT 24
Finished Aug 19 06:07:57 PM PDT 24
Peak memory 199972 kb
Host smart-b89bd6d5-5647-4d04-bcd2-92b1d6477161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133597601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3133597601
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1670206750
Short name T456
Test name
Test status
Simulation time 20999704249 ps
CPU time 83.12 seconds
Started Aug 19 06:07:27 PM PDT 24
Finished Aug 19 06:08:50 PM PDT 24
Peak memory 217620 kb
Host smart-16d32a72-b2c5-4796-9d95-0923e74881d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670206750 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1670206750
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3893085955
Short name T718
Test name
Test status
Simulation time 1153498723 ps
CPU time 5.94 seconds
Started Aug 19 06:07:28 PM PDT 24
Finished Aug 19 06:07:34 PM PDT 24
Peak memory 200872 kb
Host smart-a12609fe-a6ad-405b-a25d-f11047e179f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893085955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3893085955
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2827802567
Short name T300
Test name
Test status
Simulation time 14655389899 ps
CPU time 12.61 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:07:37 PM PDT 24
Peak memory 200912 kb
Host smart-5d5647a3-759c-40c6-aec5-b027ef00b21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827802567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2827802567
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.67771191
Short name T1018
Test name
Test status
Simulation time 36189901 ps
CPU time 0.58 seconds
Started Aug 19 06:07:39 PM PDT 24
Finished Aug 19 06:07:40 PM PDT 24
Peak memory 196556 kb
Host smart-51ee06bc-17c2-4c83-ba98-d61c2c475c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67771191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.67771191
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3175512925
Short name T507
Test name
Test status
Simulation time 277693633559 ps
CPU time 180.33 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:10:25 PM PDT 24
Peak memory 200784 kb
Host smart-f3be9877-b0fd-4644-88a9-822f0b96c7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175512925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3175512925
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.4218653170
Short name T1073
Test name
Test status
Simulation time 9796647249 ps
CPU time 45.55 seconds
Started Aug 19 06:07:32 PM PDT 24
Finished Aug 19 06:08:18 PM PDT 24
Peak memory 200876 kb
Host smart-f1770b17-c406-46c7-a9a7-1379863283cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218653170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4218653170
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2167213092
Short name T652
Test name
Test status
Simulation time 37457274435 ps
CPU time 14.66 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:07:41 PM PDT 24
Peak memory 200908 kb
Host smart-64ce8569-491d-4113-bab1-448c77d8439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167213092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2167213092
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3844922794
Short name T845
Test name
Test status
Simulation time 41345147899 ps
CPU time 31.26 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:07:57 PM PDT 24
Peak memory 200912 kb
Host smart-c45f5dd9-c04e-4573-8584-b6b7713a92d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844922794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3844922794
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1578539391
Short name T904
Test name
Test status
Simulation time 164061170614 ps
CPU time 827.65 seconds
Started Aug 19 06:07:28 PM PDT 24
Finished Aug 19 06:21:16 PM PDT 24
Peak memory 200920 kb
Host smart-18668e43-c1cb-44e4-8656-e10f423dd135
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578539391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1578539391
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2011221779
Short name T668
Test name
Test status
Simulation time 134546131 ps
CPU time 0.69 seconds
Started Aug 19 06:07:32 PM PDT 24
Finished Aug 19 06:07:33 PM PDT 24
Peak memory 197048 kb
Host smart-2afb15d2-7e4d-4baf-8155-61251bdf21e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011221779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2011221779
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3805915685
Short name T406
Test name
Test status
Simulation time 53814274827 ps
CPU time 95.39 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:09:01 PM PDT 24
Peak memory 200852 kb
Host smart-117e9fcd-0476-48d6-b1f7-d702c3f67c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805915685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3805915685
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.169207143
Short name T40
Test name
Test status
Simulation time 8006041983 ps
CPU time 102.24 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:09:08 PM PDT 24
Peak memory 201028 kb
Host smart-1a1dfc75-71b9-4b04-89cc-9f3ba6ad96e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169207143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.169207143
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1707093741
Short name T654
Test name
Test status
Simulation time 5528063237 ps
CPU time 13.92 seconds
Started Aug 19 06:07:26 PM PDT 24
Finished Aug 19 06:07:41 PM PDT 24
Peak memory 199012 kb
Host smart-c4b2ba3f-fb49-461f-9a2b-168bfa69806d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707093741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1707093741
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4165860044
Short name T473
Test name
Test status
Simulation time 25695107528 ps
CPU time 48.51 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:08:14 PM PDT 24
Peak memory 200860 kb
Host smart-fc176b27-ec6e-4ccc-9d4b-b90ff7897e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165860044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4165860044
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.4073096037
Short name T407
Test name
Test status
Simulation time 586017357 ps
CPU time 0.87 seconds
Started Aug 19 06:07:25 PM PDT 24
Finished Aug 19 06:07:26 PM PDT 24
Peak memory 196428 kb
Host smart-f8a5e809-3936-4572-9c68-08d6407939e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073096037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.4073096037
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1664111477
Short name T398
Test name
Test status
Simulation time 498940829 ps
CPU time 1.52 seconds
Started Aug 19 06:07:27 PM PDT 24
Finished Aug 19 06:07:28 PM PDT 24
Peak memory 199636 kb
Host smart-28ea6192-0e10-499e-84b4-9cf145351b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664111477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1664111477
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3243170003
Short name T160
Test name
Test status
Simulation time 80024791387 ps
CPU time 124.19 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:09:40 PM PDT 24
Peak memory 200900 kb
Host smart-bf2b0a96-cfc6-4172-a84e-e205d6c6ac34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243170003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3243170003
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3046879374
Short name T585
Test name
Test status
Simulation time 585248538 ps
CPU time 4.98 seconds
Started Aug 19 06:07:34 PM PDT 24
Finished Aug 19 06:07:39 PM PDT 24
Peak memory 209316 kb
Host smart-071e4eb2-5091-48ba-9d12-dc1e25329072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046879374 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3046879374
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1557154996
Short name T949
Test name
Test status
Simulation time 632641057 ps
CPU time 2.06 seconds
Started Aug 19 06:07:29 PM PDT 24
Finished Aug 19 06:07:31 PM PDT 24
Peak memory 199688 kb
Host smart-0d49d49b-b718-472a-b8ca-d32a10bce8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557154996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1557154996
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1659457918
Short name T435
Test name
Test status
Simulation time 38200943721 ps
CPU time 17.17 seconds
Started Aug 19 06:07:22 PM PDT 24
Finished Aug 19 06:07:39 PM PDT 24
Peak memory 201004 kb
Host smart-dab9f918-1a54-4936-8ae5-68de63ed8a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659457918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1659457918
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3126235903
Short name T1102
Test name
Test status
Simulation time 23136372 ps
CPU time 0.56 seconds
Started Aug 19 06:07:37 PM PDT 24
Finished Aug 19 06:07:38 PM PDT 24
Peak memory 196568 kb
Host smart-d95c6150-e7f8-4c0f-84a4-f8cc820fa87b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126235903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3126235903
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1221496304
Short name T1067
Test name
Test status
Simulation time 63607133486 ps
CPU time 102.87 seconds
Started Aug 19 06:07:40 PM PDT 24
Finished Aug 19 06:09:23 PM PDT 24
Peak memory 200928 kb
Host smart-f2435b7a-7eda-4b5d-b233-ea035c0b51e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221496304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1221496304
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.402326759
Short name T558
Test name
Test status
Simulation time 41837691833 ps
CPU time 38.39 seconds
Started Aug 19 06:07:35 PM PDT 24
Finished Aug 19 06:08:14 PM PDT 24
Peak memory 200984 kb
Host smart-867a3394-5568-43bd-918d-e15415968260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402326759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.402326759
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.693898929
Short name T417
Test name
Test status
Simulation time 41311393870 ps
CPU time 13.23 seconds
Started Aug 19 06:07:35 PM PDT 24
Finished Aug 19 06:07:48 PM PDT 24
Peak memory 200980 kb
Host smart-b76cda97-d948-4fb7-9daa-b05b85068d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693898929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.693898929
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2694070787
Short name T817
Test name
Test status
Simulation time 8653487849 ps
CPU time 4.42 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:07:41 PM PDT 24
Peak memory 200800 kb
Host smart-c211019a-22b0-4a30-9f61-eae062ce0e85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694070787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2694070787
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_loopback.2888930029
Short name T702
Test name
Test status
Simulation time 938619987 ps
CPU time 1.07 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:07:37 PM PDT 24
Peak memory 197144 kb
Host smart-163faa70-7df9-4da1-b910-e6f7b48a562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888930029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2888930029
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2681504396
Short name T810
Test name
Test status
Simulation time 103863141005 ps
CPU time 40.21 seconds
Started Aug 19 06:07:40 PM PDT 24
Finished Aug 19 06:08:21 PM PDT 24
Peak memory 199516 kb
Host smart-78efa964-7bc8-4061-9b0d-04e7cb22a88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681504396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2681504396
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.603449412
Short name T571
Test name
Test status
Simulation time 20366369485 ps
CPU time 56.89 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:08:33 PM PDT 24
Peak memory 200936 kb
Host smart-846874cc-8436-4b34-8f51-fb2b8f646912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603449412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.603449412
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.130366990
Short name T1036
Test name
Test status
Simulation time 6689322315 ps
CPU time 63.63 seconds
Started Aug 19 06:07:35 PM PDT 24
Finished Aug 19 06:08:39 PM PDT 24
Peak memory 200224 kb
Host smart-d66a45d8-7728-4410-8be0-73a7f49a6c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130366990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.130366990
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3174107801
Short name T142
Test name
Test status
Simulation time 122650427213 ps
CPU time 49.01 seconds
Started Aug 19 06:07:38 PM PDT 24
Finished Aug 19 06:08:27 PM PDT 24
Peak memory 200928 kb
Host smart-e108ef08-d027-4522-827b-bf04e179be36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174107801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3174107801
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1013639219
Short name T753
Test name
Test status
Simulation time 1891256532 ps
CPU time 1.99 seconds
Started Aug 19 06:07:35 PM PDT 24
Finished Aug 19 06:07:37 PM PDT 24
Peak memory 196428 kb
Host smart-637dfa1f-f77e-4632-bc27-d90b6433d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013639219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1013639219
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1542219136
Short name T493
Test name
Test status
Simulation time 631147318 ps
CPU time 1.88 seconds
Started Aug 19 06:07:38 PM PDT 24
Finished Aug 19 06:07:40 PM PDT 24
Peak memory 200876 kb
Host smart-7dd30a16-ecd0-4b2b-9b6a-556ab8835669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542219136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1542219136
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1600336423
Short name T539
Test name
Test status
Simulation time 371148608635 ps
CPU time 547.89 seconds
Started Aug 19 06:07:40 PM PDT 24
Finished Aug 19 06:16:48 PM PDT 24
Peak memory 216680 kb
Host smart-ee920389-f5db-4f52-9032-12c1c4e3e3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600336423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1600336423
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3107550394
Short name T30
Test name
Test status
Simulation time 33488891835 ps
CPU time 49.33 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:08:26 PM PDT 24
Peak memory 216580 kb
Host smart-3f12a9d7-5d6f-4f00-ba80-d4374f67b194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107550394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3107550394
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2203889654
Short name T837
Test name
Test status
Simulation time 1197156626 ps
CPU time 1.39 seconds
Started Aug 19 06:07:38 PM PDT 24
Finished Aug 19 06:07:39 PM PDT 24
Peak memory 199200 kb
Host smart-59abfed3-6896-46fc-bd25-d1f83b316782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203889654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2203889654
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4015153687
Short name T269
Test name
Test status
Simulation time 66148934204 ps
CPU time 147.62 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:10:04 PM PDT 24
Peak memory 200980 kb
Host smart-9cf31ecb-8f18-4165-9ae3-852c7a83729d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015153687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4015153687
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2744007342
Short name T7
Test name
Test status
Simulation time 85938507 ps
CPU time 0.54 seconds
Started Aug 19 06:07:39 PM PDT 24
Finished Aug 19 06:07:39 PM PDT 24
Peak memory 195256 kb
Host smart-6aefffbb-3dd8-4ef7-8aa3-7c71e16434f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744007342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2744007342
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3624872917
Short name T416
Test name
Test status
Simulation time 122486068009 ps
CPU time 150.82 seconds
Started Aug 19 06:07:38 PM PDT 24
Finished Aug 19 06:10:09 PM PDT 24
Peak memory 200980 kb
Host smart-c07dc009-b2e8-4443-a9fc-4701df9514a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624872917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3624872917
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3662008505
Short name T291
Test name
Test status
Simulation time 103325363303 ps
CPU time 28.5 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:08:04 PM PDT 24
Peak memory 200924 kb
Host smart-c384f944-c6a3-48a5-adb8-4bf12691a04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662008505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3662008505
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2420008450
Short name T130
Test name
Test status
Simulation time 15246463877 ps
CPU time 13.65 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:07:50 PM PDT 24
Peak memory 200900 kb
Host smart-d09a1b36-d753-4f02-bd7e-b35c9e7075c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420008450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2420008450
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2437940728
Short name T452
Test name
Test status
Simulation time 21719039829 ps
CPU time 23.26 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 200972 kb
Host smart-714c1cc2-1c14-42e4-992d-2610e995492a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437940728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2437940728
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1009400875
Short name T1003
Test name
Test status
Simulation time 137562764408 ps
CPU time 202.25 seconds
Started Aug 19 06:07:36 PM PDT 24
Finished Aug 19 06:10:58 PM PDT 24
Peak memory 201000 kb
Host smart-ee38448c-e036-46ca-a634-6cf834b5ae12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009400875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1009400875
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1519932926
Short name T927
Test name
Test status
Simulation time 7536749763 ps
CPU time 14.85 seconds
Started Aug 19 06:07:35 PM PDT 24
Finished Aug 19 06:07:50 PM PDT 24
Peak memory 200904 kb
Host smart-2580c022-6eb3-47bd-b19a-95a860ac75b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519932926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1519932926
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2077087303
Short name T818
Test name
Test status
Simulation time 137125278726 ps
CPU time 63.38 seconds
Started Aug 19 06:07:39 PM PDT 24
Finished Aug 19 06:08:42 PM PDT 24
Peak memory 201108 kb
Host smart-dafead19-1536-4a29-9b4e-b73cffdd82cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077087303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2077087303
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3077525886
Short name T985
Test name
Test status
Simulation time 1488696574 ps
CPU time 2.64 seconds
Started Aug 19 06:07:33 PM PDT 24
Finished Aug 19 06:07:36 PM PDT 24
Peak memory 197696 kb
Host smart-8ceefa3e-6df6-4cbd-b0cc-213b85779247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077525886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3077525886
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1127878888
Short name T593
Test name
Test status
Simulation time 122187211106 ps
CPU time 93.54 seconds
Started Aug 19 06:07:35 PM PDT 24
Finished Aug 19 06:09:09 PM PDT 24
Peak memory 200920 kb
Host smart-afd85737-e8e4-4dea-bf95-efb119ecddf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127878888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1127878888
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1131763899
Short name T745
Test name
Test status
Simulation time 4107826930 ps
CPU time 3.38 seconds
Started Aug 19 06:07:40 PM PDT 24
Finished Aug 19 06:07:44 PM PDT 24
Peak memory 197456 kb
Host smart-bb0da9de-7554-49b6-9495-20f58debcb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131763899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1131763899
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.572007094
Short name T365
Test name
Test status
Simulation time 713300662 ps
CPU time 2.86 seconds
Started Aug 19 06:07:37 PM PDT 24
Finished Aug 19 06:07:40 PM PDT 24
Peak memory 199212 kb
Host smart-88a57a3c-9d4f-430d-a691-27b2c6b26c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572007094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.572007094
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2809221416
Short name T681
Test name
Test status
Simulation time 396270767054 ps
CPU time 134.9 seconds
Started Aug 19 06:07:38 PM PDT 24
Finished Aug 19 06:09:53 PM PDT 24
Peak memory 200924 kb
Host smart-c5b64e90-833d-49ed-81e0-395026c895df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809221416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2809221416
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2555527675
Short name T970
Test name
Test status
Simulation time 4395595761 ps
CPU time 57.66 seconds
Started Aug 19 06:07:38 PM PDT 24
Finished Aug 19 06:08:36 PM PDT 24
Peak memory 217396 kb
Host smart-8b833450-ab1f-4cb3-b9c0-9f0349819801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555527675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2555527675
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1280519396
Short name T983
Test name
Test status
Simulation time 6634677044 ps
CPU time 26.02 seconds
Started Aug 19 06:07:37 PM PDT 24
Finished Aug 19 06:08:03 PM PDT 24
Peak memory 200968 kb
Host smart-c82f58e4-daeb-436f-9730-ea2cbdbba532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280519396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1280519396
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.778664740
Short name T922
Test name
Test status
Simulation time 107965707034 ps
CPU time 73.24 seconds
Started Aug 19 06:07:40 PM PDT 24
Finished Aug 19 06:08:53 PM PDT 24
Peak memory 200960 kb
Host smart-2705a4a5-6689-432b-8600-0267ff8867cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778664740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.778664740
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.236447387
Short name T724
Test name
Test status
Simulation time 20240870 ps
CPU time 0.56 seconds
Started Aug 19 06:07:51 PM PDT 24
Finished Aug 19 06:07:52 PM PDT 24
Peak memory 196276 kb
Host smart-3c378dc8-45bf-4e39-bf71-470feccbbd60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236447387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.236447387
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1123105917
Short name T154
Test name
Test status
Simulation time 203407632633 ps
CPU time 77.7 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:09:08 PM PDT 24
Peak memory 200976 kb
Host smart-baa093b2-9eaa-45ee-99e5-75d508e7c047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123105917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1123105917
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3967323282
Short name T889
Test name
Test status
Simulation time 63835599382 ps
CPU time 85.03 seconds
Started Aug 19 06:07:52 PM PDT 24
Finished Aug 19 06:09:17 PM PDT 24
Peak memory 200944 kb
Host smart-e0681b0f-f1be-40da-a64e-2bc515024fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967323282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3967323282
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1556308
Short name T18
Test name
Test status
Simulation time 51309462349 ps
CPU time 85.63 seconds
Started Aug 19 06:07:51 PM PDT 24
Finished Aug 19 06:09:17 PM PDT 24
Peak memory 200984 kb
Host smart-fffb13f4-fe8c-44c0-acee-064bf1d6648e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1556308
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1996543395
Short name T951
Test name
Test status
Simulation time 140147038169 ps
CPU time 282.69 seconds
Started Aug 19 06:07:52 PM PDT 24
Finished Aug 19 06:12:35 PM PDT 24
Peak memory 200920 kb
Host smart-9cb164f4-acad-4bd3-9a9f-af83cb3dc8ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996543395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1996543395
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.918466074
Short name T1120
Test name
Test status
Simulation time 3407397086 ps
CPU time 1.56 seconds
Started Aug 19 06:07:51 PM PDT 24
Finished Aug 19 06:07:53 PM PDT 24
Peak memory 199528 kb
Host smart-bbd62a18-46f2-4ff5-9bdf-fd3ebbcd2a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918466074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.918466074
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3738969765
Short name T1100
Test name
Test status
Simulation time 78104800626 ps
CPU time 115.01 seconds
Started Aug 19 06:07:47 PM PDT 24
Finished Aug 19 06:09:43 PM PDT 24
Peak memory 200584 kb
Host smart-010d1212-f200-44ec-b661-ec4b47a179f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738969765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3738969765
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1070307991
Short name T265
Test name
Test status
Simulation time 8670503808 ps
CPU time 112.84 seconds
Started Aug 19 06:07:52 PM PDT 24
Finished Aug 19 06:09:45 PM PDT 24
Peak memory 200944 kb
Host smart-1a57ac0e-377a-4d20-a5ad-1dbb35d12c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070307991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1070307991
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1485702476
Short name T894
Test name
Test status
Simulation time 5013973260 ps
CPU time 10.15 seconds
Started Aug 19 06:07:52 PM PDT 24
Finished Aug 19 06:08:03 PM PDT 24
Peak memory 199120 kb
Host smart-0bd79302-02d2-4589-8697-8c6050e02be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485702476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1485702476
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2836668948
Short name T171
Test name
Test status
Simulation time 37204821933 ps
CPU time 14.66 seconds
Started Aug 19 06:07:51 PM PDT 24
Finished Aug 19 06:08:06 PM PDT 24
Peak memory 200928 kb
Host smart-74589aa8-0427-4a8d-bb16-28f0ecfd98fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836668948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2836668948
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3644030550
Short name T582
Test name
Test status
Simulation time 520475973 ps
CPU time 0.91 seconds
Started Aug 19 06:07:52 PM PDT 24
Finished Aug 19 06:07:53 PM PDT 24
Peak memory 196620 kb
Host smart-bd04d684-d09a-419e-98f6-1cf1bc1bbeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644030550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3644030550
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.4102879313
Short name T1148
Test name
Test status
Simulation time 528474360 ps
CPU time 1.27 seconds
Started Aug 19 06:07:37 PM PDT 24
Finished Aug 19 06:07:39 PM PDT 24
Peak memory 199240 kb
Host smart-aa904db2-5aed-4985-953e-12d226f555a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102879313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4102879313
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2301005335
Short name T318
Test name
Test status
Simulation time 139378625840 ps
CPU time 98.35 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:09:28 PM PDT 24
Peak memory 200920 kb
Host smart-7029760a-bc2a-4a79-9677-8fed2eee1737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301005335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2301005335
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1399318594
Short name T662
Test name
Test status
Simulation time 3754370646 ps
CPU time 47.03 seconds
Started Aug 19 06:07:52 PM PDT 24
Finished Aug 19 06:08:39 PM PDT 24
Peak memory 209340 kb
Host smart-cff244b6-6ba4-4b59-bff9-c8122d87fb0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399318594 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1399318594
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2173979246
Short name T290
Test name
Test status
Simulation time 1272103843 ps
CPU time 1.59 seconds
Started Aug 19 06:07:49 PM PDT 24
Finished Aug 19 06:07:51 PM PDT 24
Peak memory 200692 kb
Host smart-4e2aaa21-adb3-4a2d-9926-3d8e82b3b3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173979246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2173979246
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.401906673
Short name T250
Test name
Test status
Simulation time 13753976380 ps
CPU time 21.46 seconds
Started Aug 19 06:07:37 PM PDT 24
Finished Aug 19 06:07:58 PM PDT 24
Peak memory 200952 kb
Host smart-887a4053-fe54-4db3-b07c-e9957255f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401906673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.401906673
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3438735299
Short name T1172
Test name
Test status
Simulation time 36550685 ps
CPU time 0.57 seconds
Started Aug 19 06:07:53 PM PDT 24
Finished Aug 19 06:07:54 PM PDT 24
Peak memory 196276 kb
Host smart-d529c48f-ee7a-4c7e-b2ee-4f83982ad2dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438735299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3438735299
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1236336763
Short name T899
Test name
Test status
Simulation time 26110244381 ps
CPU time 9.45 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:07:59 PM PDT 24
Peak memory 200992 kb
Host smart-5e578085-9e00-42ae-8346-01fe9264b5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236336763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1236336763
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3019138363
Short name T883
Test name
Test status
Simulation time 147320269803 ps
CPU time 60.73 seconds
Started Aug 19 06:07:49 PM PDT 24
Finished Aug 19 06:08:50 PM PDT 24
Peak memory 200916 kb
Host smart-15ec94e1-b077-4518-bcd0-2a3a9b814b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019138363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3019138363
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.45810738
Short name T190
Test name
Test status
Simulation time 70296084967 ps
CPU time 103.48 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:09:34 PM PDT 24
Peak memory 200904 kb
Host smart-aa021179-6703-45e7-a7c3-30fe35ebfae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45810738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.45810738
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2494320828
Short name T330
Test name
Test status
Simulation time 65006257313 ps
CPU time 69.05 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:09:00 PM PDT 24
Peak memory 200972 kb
Host smart-a5a92d60-0d40-4537-a619-e47ec6f6bf4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494320828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2494320828
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.96905089
Short name T1107
Test name
Test status
Simulation time 111669270750 ps
CPU time 226.98 seconds
Started Aug 19 06:07:51 PM PDT 24
Finished Aug 19 06:11:38 PM PDT 24
Peak memory 200932 kb
Host smart-8be880a2-028f-43f5-90da-86ff4ab8e9c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96905089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.96905089
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1120697972
Short name T345
Test name
Test status
Simulation time 9263641875 ps
CPU time 16.3 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:08:06 PM PDT 24
Peak memory 200804 kb
Host smart-8ff8f1d4-6cc0-4cdf-8748-43a7a9a1431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120697972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1120697972
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1143372725
Short name T423
Test name
Test status
Simulation time 35708472771 ps
CPU time 55.07 seconds
Started Aug 19 06:07:49 PM PDT 24
Finished Aug 19 06:08:45 PM PDT 24
Peak memory 201048 kb
Host smart-f1beff1b-2611-42d1-924f-2dadbdd559b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143372725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1143372725
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1485175132
Short name T430
Test name
Test status
Simulation time 14921371505 ps
CPU time 197.82 seconds
Started Aug 19 06:07:53 PM PDT 24
Finished Aug 19 06:11:11 PM PDT 24
Peak memory 200972 kb
Host smart-9b26f7c4-85a2-4c76-bf7f-ca1f8396e8b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485175132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1485175132
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.4280846989
Short name T1021
Test name
Test status
Simulation time 3948656666 ps
CPU time 8.28 seconds
Started Aug 19 06:07:52 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 199088 kb
Host smart-0e009fe8-7648-4b8d-bd1c-2d75e1bdb9d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280846989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4280846989
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2400320186
Short name T412
Test name
Test status
Simulation time 334999168349 ps
CPU time 1298.86 seconds
Started Aug 19 06:07:53 PM PDT 24
Finished Aug 19 06:29:32 PM PDT 24
Peak memory 200984 kb
Host smart-92699b0b-bfe2-46db-beaf-3e66ec3a6d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400320186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2400320186
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.4047295445
Short name T466
Test name
Test status
Simulation time 29774252987 ps
CPU time 12.54 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:08:03 PM PDT 24
Peak memory 197892 kb
Host smart-22c34130-3b56-4723-bcf5-1a1f0686671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047295445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4047295445
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3203996079
Short name T480
Test name
Test status
Simulation time 5977766815 ps
CPU time 18.57 seconds
Started Aug 19 06:07:52 PM PDT 24
Finished Aug 19 06:08:11 PM PDT 24
Peak memory 200716 kb
Host smart-07b9539f-b4e1-4901-963d-c699b0aea6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203996079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3203996079
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2332815982
Short name T266
Test name
Test status
Simulation time 41256090122 ps
CPU time 215.77 seconds
Started Aug 19 06:07:54 PM PDT 24
Finished Aug 19 06:11:30 PM PDT 24
Peak memory 200984 kb
Host smart-2dd67ca7-bfe9-4b42-9040-8e5005862b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332815982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2332815982
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2584427015
Short name T618
Test name
Test status
Simulation time 33737485695 ps
CPU time 63.38 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:08:54 PM PDT 24
Peak memory 216696 kb
Host smart-da0e7521-9886-48a7-8fc8-c8c0d6182803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584427015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2584427015
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.684673228
Short name T742
Test name
Test status
Simulation time 7986228779 ps
CPU time 5.43 seconds
Started Aug 19 06:07:51 PM PDT 24
Finished Aug 19 06:07:57 PM PDT 24
Peak memory 200856 kb
Host smart-7ea263d6-f625-41b5-a738-b2773afe31b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684673228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.684673228
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3402152607
Short name T566
Test name
Test status
Simulation time 40272372826 ps
CPU time 59.98 seconds
Started Aug 19 06:07:50 PM PDT 24
Finished Aug 19 06:08:50 PM PDT 24
Peak memory 200936 kb
Host smart-998dbdae-f36f-418c-8265-9ebe0e26ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402152607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3402152607
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3122264926
Short name T703
Test name
Test status
Simulation time 21589559 ps
CPU time 0.6 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 196580 kb
Host smart-2e193cc6-5aea-498a-b0f5-f6fda874040c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122264926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3122264926
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3655397300
Short name T597
Test name
Test status
Simulation time 174748530051 ps
CPU time 128.66 seconds
Started Aug 19 06:08:00 PM PDT 24
Finished Aug 19 06:10:09 PM PDT 24
Peak memory 200948 kb
Host smart-f4f10324-61bf-4156-93ae-bc64719a95b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655397300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3655397300
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3322882899
Short name T880
Test name
Test status
Simulation time 59178704992 ps
CPU time 25.18 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:08:24 PM PDT 24
Peak memory 200984 kb
Host smart-b60b732c-368e-463c-8d28-4f4ed76b4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322882899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3322882899
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2419127550
Short name T200
Test name
Test status
Simulation time 29009994530 ps
CPU time 35.3 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:08:34 PM PDT 24
Peak memory 200896 kb
Host smart-20a22988-16bd-45a9-8206-3b941ab2b719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419127550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2419127550
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2762023542
Short name T744
Test name
Test status
Simulation time 21603295389 ps
CPU time 10.34 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:08:09 PM PDT 24
Peak memory 200628 kb
Host smart-7456e9a9-0442-4c0e-bbc1-b8dd3a0f96bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762023542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2762023542
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1086993549
Short name T638
Test name
Test status
Simulation time 81507018627 ps
CPU time 566.06 seconds
Started Aug 19 06:08:07 PM PDT 24
Finished Aug 19 06:17:33 PM PDT 24
Peak memory 200964 kb
Host smart-d1047139-6e2a-46ab-b25d-284e31772cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086993549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1086993549
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2998626985
Short name T326
Test name
Test status
Simulation time 10744862099 ps
CPU time 6.64 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:08:05 PM PDT 24
Peak memory 200872 kb
Host smart-6ecb41eb-b49a-49eb-996b-3a0d85249efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998626985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2998626985
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3136498528
Short name T549
Test name
Test status
Simulation time 184982058250 ps
CPU time 91.11 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:09:31 PM PDT 24
Peak memory 209364 kb
Host smart-242669a7-cb11-455b-aa62-c9ba770e9689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136498528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3136498528
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.223232090
Short name T550
Test name
Test status
Simulation time 19234107607 ps
CPU time 209.1 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:11:28 PM PDT 24
Peak memory 200992 kb
Host smart-ec1d4070-aa3a-42d7-ac70-d284928f5322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223232090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.223232090
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1709587617
Short name T954
Test name
Test status
Simulation time 1960850646 ps
CPU time 1.57 seconds
Started Aug 19 06:07:57 PM PDT 24
Finished Aug 19 06:07:59 PM PDT 24
Peak memory 199032 kb
Host smart-4d4bef44-bba9-4786-b29a-868879c8f9a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709587617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1709587617
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3972523402
Short name T276
Test name
Test status
Simulation time 3844752272 ps
CPU time 5.87 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:08:05 PM PDT 24
Peak memory 197076 kb
Host smart-ac0787ec-7626-4662-ac75-3eee81a86fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972523402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3972523402
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2795659278
Short name T642
Test name
Test status
Simulation time 709956745 ps
CPU time 1.66 seconds
Started Aug 19 06:07:51 PM PDT 24
Finished Aug 19 06:07:53 PM PDT 24
Peak memory 200908 kb
Host smart-44795cc4-e43a-4a51-914c-1d252797ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795659278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2795659278
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1201539013
Short name T470
Test name
Test status
Simulation time 1181220196707 ps
CPU time 612.7 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:18:11 PM PDT 24
Peak memory 209396 kb
Host smart-f3880858-ace7-4632-9c89-5c6b329110e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201539013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1201539013
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3183030119
Short name T825
Test name
Test status
Simulation time 3763198968 ps
CPU time 43.85 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:08:42 PM PDT 24
Peak memory 217640 kb
Host smart-1206b3fa-c999-414e-8c89-9a0e83fe4334
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183030119 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3183030119
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1762769595
Short name T362
Test name
Test status
Simulation time 7874291414 ps
CPU time 10.59 seconds
Started Aug 19 06:08:07 PM PDT 24
Finished Aug 19 06:08:17 PM PDT 24
Peak memory 200496 kb
Host smart-4a653683-1126-4cde-b74a-c4064b5d4345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762769595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1762769595
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.582286815
Short name T636
Test name
Test status
Simulation time 91622527944 ps
CPU time 199.75 seconds
Started Aug 19 06:07:54 PM PDT 24
Finished Aug 19 06:11:14 PM PDT 24
Peak memory 200960 kb
Host smart-3ff416f5-00f3-4599-aa05-7efa47a9ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582286815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.582286815
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4177189500
Short name T377
Test name
Test status
Simulation time 18334871 ps
CPU time 0.57 seconds
Started Aug 19 06:07:57 PM PDT 24
Finished Aug 19 06:07:58 PM PDT 24
Peak memory 196632 kb
Host smart-2b98feb8-1274-40f5-94b9-c37cb70ba0c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177189500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4177189500
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2719257649
Short name T1092
Test name
Test status
Simulation time 97905626305 ps
CPU time 36.36 seconds
Started Aug 19 06:08:01 PM PDT 24
Finished Aug 19 06:08:37 PM PDT 24
Peak memory 200956 kb
Host smart-73f04416-14e8-40ae-abbe-7fc4fa152f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719257649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2719257649
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3166377864
Short name T391
Test name
Test status
Simulation time 22036928750 ps
CPU time 28.93 seconds
Started Aug 19 06:08:04 PM PDT 24
Finished Aug 19 06:08:33 PM PDT 24
Peak memory 200932 kb
Host smart-65b04371-20ed-432f-bafe-78fe0844ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166377864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3166377864
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2224698885
Short name T11
Test name
Test status
Simulation time 73821242585 ps
CPU time 121.88 seconds
Started Aug 19 06:07:57 PM PDT 24
Finished Aug 19 06:09:59 PM PDT 24
Peak memory 200908 kb
Host smart-3cdaa492-c8a4-4434-9db0-0d7af8e8b4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224698885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2224698885
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2180890930
Short name T908
Test name
Test status
Simulation time 56886918108 ps
CPU time 66.46 seconds
Started Aug 19 06:07:57 PM PDT 24
Finished Aug 19 06:09:04 PM PDT 24
Peak memory 199792 kb
Host smart-1f075c39-9cc4-43a2-9eeb-e8700df8128f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180890930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2180890930
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4140585309
Short name T505
Test name
Test status
Simulation time 174004485674 ps
CPU time 653.52 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:18:53 PM PDT 24
Peak memory 200900 kb
Host smart-d41deb55-ebc3-4566-a277-a6f3c0cfccf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140585309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4140585309
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1955915162
Short name T516
Test name
Test status
Simulation time 8396301843 ps
CPU time 6.76 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:08:05 PM PDT 24
Peak memory 199512 kb
Host smart-f7c3dc3d-5e5d-428e-a110-e6311957da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955915162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1955915162
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.36990732
Short name T245
Test name
Test status
Simulation time 63964044164 ps
CPU time 67.37 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:09:05 PM PDT 24
Peak memory 200220 kb
Host smart-81d3c82d-df8c-4a2b-9f06-9b8f2bbc4be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36990732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.36990732
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.22738219
Short name T1163
Test name
Test status
Simulation time 11373748210 ps
CPU time 188.97 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:11:07 PM PDT 24
Peak memory 200976 kb
Host smart-8a2c599d-9631-4bfe-bab5-b987f2757aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22738219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.22738219
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3960208609
Short name T434
Test name
Test status
Simulation time 1611186469 ps
CPU time 2.87 seconds
Started Aug 19 06:08:03 PM PDT 24
Finished Aug 19 06:08:06 PM PDT 24
Peak memory 199172 kb
Host smart-a270e2d7-cfe0-4926-b986-50e81a9310c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3960208609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3960208609
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1066595042
Short name T166
Test name
Test status
Simulation time 153908420888 ps
CPU time 68.25 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:09:08 PM PDT 24
Peak memory 200964 kb
Host smart-1a644d34-38c7-4c60-85ad-c8932c117353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066595042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1066595042
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3821824926
Short name T1113
Test name
Test status
Simulation time 3624243021 ps
CPU time 2.21 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:08:01 PM PDT 24
Peak memory 197832 kb
Host smart-12e16ea2-8c4d-482f-bdc2-579c9fe49b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821824926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3821824926
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3830652268
Short name T713
Test name
Test status
Simulation time 465318076 ps
CPU time 1.38 seconds
Started Aug 19 06:08:07 PM PDT 24
Finished Aug 19 06:08:08 PM PDT 24
Peak memory 200464 kb
Host smart-48844751-f752-4a38-90ae-311e5b1ba3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830652268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3830652268
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1001284664
Short name T923
Test name
Test status
Simulation time 241808415356 ps
CPU time 128.6 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:10:07 PM PDT 24
Peak memory 200992 kb
Host smart-0b38aa45-37a5-4fb1-92e6-b10cb9bcb6d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001284664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1001284664
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.625710904
Short name T568
Test name
Test status
Simulation time 8026749005 ps
CPU time 28.8 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:08:28 PM PDT 24
Peak memory 217328 kb
Host smart-357166b3-4329-45bd-8a23-ebee466813b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625710904 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.625710904
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1257009841
Short name T993
Test name
Test status
Simulation time 8267162821 ps
CPU time 11.63 seconds
Started Aug 19 06:08:01 PM PDT 24
Finished Aug 19 06:08:13 PM PDT 24
Peak memory 200972 kb
Host smart-28fb5c50-2f85-4356-9304-e6a989fab9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257009841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1257009841
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.4242600464
Short name T256
Test name
Test status
Simulation time 69255876994 ps
CPU time 27.49 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:08:26 PM PDT 24
Peak memory 200748 kb
Host smart-009856bd-e322-4461-83d3-1215e5b8fc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242600464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.4242600464
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2287265887
Short name T1130
Test name
Test status
Simulation time 15865502 ps
CPU time 0.57 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:08:09 PM PDT 24
Peak memory 196564 kb
Host smart-018addc5-b784-46b2-bc3f-27a36ea60b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287265887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2287265887
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2404138885
Short name T508
Test name
Test status
Simulation time 87518616411 ps
CPU time 147.19 seconds
Started Aug 19 06:08:03 PM PDT 24
Finished Aug 19 06:10:30 PM PDT 24
Peak memory 200980 kb
Host smart-e40a5746-d73c-4cfe-bf22-da0e068fdbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404138885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2404138885
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.541745871
Short name T1056
Test name
Test status
Simulation time 31452592390 ps
CPU time 73.45 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:09:11 PM PDT 24
Peak memory 200976 kb
Host smart-b9582eb7-316d-4108-a3f2-06bf61b122e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541745871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.541745871
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.555009538
Short name T1117
Test name
Test status
Simulation time 97377084952 ps
CPU time 156.48 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:10:35 PM PDT 24
Peak memory 200992 kb
Host smart-1ed2b48d-b59b-4cd9-aec1-c06614a56416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555009538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.555009538
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2526577637
Short name T920
Test name
Test status
Simulation time 388638493866 ps
CPU time 707.14 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:19:46 PM PDT 24
Peak memory 200632 kb
Host smart-69f063c6-2d70-4e3e-99d3-4e0d8a663afe
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526577637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2526577637
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2456523097
Short name T601
Test name
Test status
Simulation time 78729272376 ps
CPU time 179.35 seconds
Started Aug 19 06:07:57 PM PDT 24
Finished Aug 19 06:10:57 PM PDT 24
Peak memory 201116 kb
Host smart-5e5bc3ed-db36-4567-8b99-2ca531ea1af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456523097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2456523097
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2903644401
Short name T644
Test name
Test status
Simulation time 8518684825 ps
CPU time 9.18 seconds
Started Aug 19 06:08:07 PM PDT 24
Finished Aug 19 06:08:16 PM PDT 24
Peak memory 200704 kb
Host smart-ae64d34d-cb6d-4bb1-b802-d31f92f0886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903644401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2903644401
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3809103596
Short name T469
Test name
Test status
Simulation time 90892626955 ps
CPU time 197.48 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:11:15 PM PDT 24
Peak memory 201144 kb
Host smart-7b07598f-06f4-490f-82ff-2da1c1ee4543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809103596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3809103596
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2350006573
Short name T375
Test name
Test status
Simulation time 19889598767 ps
CPU time 959.23 seconds
Started Aug 19 06:07:58 PM PDT 24
Finished Aug 19 06:23:57 PM PDT 24
Peak memory 200948 kb
Host smart-3e49746a-aa6c-4955-8224-c7ea18e3897d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350006573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2350006573
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1316832805
Short name T940
Test name
Test status
Simulation time 1694293040 ps
CPU time 11.49 seconds
Started Aug 19 06:08:02 PM PDT 24
Finished Aug 19 06:08:14 PM PDT 24
Peak memory 198984 kb
Host smart-102b3d4e-aaf1-4345-8680-91897e93650a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1316832805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1316832805
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1221031811
Short name T1071
Test name
Test status
Simulation time 146767423786 ps
CPU time 358.71 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:13:58 PM PDT 24
Peak memory 200972 kb
Host smart-abea0e42-cde7-48de-b831-dbb08e96d3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221031811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1221031811
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.795528845
Short name T444
Test name
Test status
Simulation time 4027747772 ps
CPU time 1 seconds
Started Aug 19 06:08:04 PM PDT 24
Finished Aug 19 06:08:05 PM PDT 24
Peak memory 197052 kb
Host smart-96dca13d-cf94-496d-ba1d-725d66f167e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795528845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.795528845
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.561015572
Short name T799
Test name
Test status
Simulation time 97912487 ps
CPU time 0.8 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:08:00 PM PDT 24
Peak memory 197876 kb
Host smart-a624f538-1051-4792-9d9c-dd19a6610c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561015572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.561015572
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.4066770898
Short name T684
Test name
Test status
Simulation time 6649177550 ps
CPU time 21.52 seconds
Started Aug 19 06:08:10 PM PDT 24
Finished Aug 19 06:08:32 PM PDT 24
Peak memory 216524 kb
Host smart-2dcc55fe-3766-40da-bda3-6536ea5f908f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066770898 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.4066770898
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3447214369
Short name T1137
Test name
Test status
Simulation time 805775937 ps
CPU time 2.45 seconds
Started Aug 19 06:07:59 PM PDT 24
Finished Aug 19 06:08:01 PM PDT 24
Peak memory 199748 kb
Host smart-d0adcd55-49db-426f-88dd-7354c31f57cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447214369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3447214369
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2225740808
Short name T826
Test name
Test status
Simulation time 61094130017 ps
CPU time 105.2 seconds
Started Aug 19 06:08:04 PM PDT 24
Finished Aug 19 06:09:49 PM PDT 24
Peak memory 200952 kb
Host smart-f25b6489-d99d-4f84-b738-83ed2e096e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225740808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2225740808
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2906122963
Short name T821
Test name
Test status
Simulation time 16821972 ps
CPU time 0.62 seconds
Started Aug 19 06:08:07 PM PDT 24
Finished Aug 19 06:08:08 PM PDT 24
Peak memory 196544 kb
Host smart-6dda1370-041b-4b50-82ff-f919faea1345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906122963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2906122963
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3654389156
Short name T735
Test name
Test status
Simulation time 61341621822 ps
CPU time 9.86 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:08:19 PM PDT 24
Peak memory 200968 kb
Host smart-22f8daf9-24a3-4ec5-828b-26b575f25126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654389156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3654389156
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2791527490
Short name T399
Test name
Test status
Simulation time 50721218054 ps
CPU time 34.67 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:08:43 PM PDT 24
Peak memory 200936 kb
Host smart-6657d862-160a-4b38-a539-2b9e654a4918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791527490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2791527490
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2317750330
Short name T429
Test name
Test status
Simulation time 36281996781 ps
CPU time 56.59 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:09:06 PM PDT 24
Peak memory 200976 kb
Host smart-ba7611fd-9f95-4440-b9d5-a4c3b64532a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317750330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2317750330
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.681578548
Short name T806
Test name
Test status
Simulation time 16147643369 ps
CPU time 10.64 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:08:19 PM PDT 24
Peak memory 199928 kb
Host smart-86b79d45-a5a9-4935-88ee-b8869dc37d6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681578548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.681578548
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2879496726
Short name T639
Test name
Test status
Simulation time 167961457061 ps
CPU time 644.73 seconds
Started Aug 19 06:08:10 PM PDT 24
Finished Aug 19 06:18:55 PM PDT 24
Peak memory 200976 kb
Host smart-4b159af2-7dd1-4076-bdc5-98e774929099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879496726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2879496726
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2118669676
Short name T873
Test name
Test status
Simulation time 8361283890 ps
CPU time 5.11 seconds
Started Aug 19 06:08:11 PM PDT 24
Finished Aug 19 06:08:16 PM PDT 24
Peak memory 200920 kb
Host smart-a2800ddd-63f3-4d34-9297-3d5bcbf8c1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118669676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2118669676
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2988730013
Short name T671
Test name
Test status
Simulation time 170290157584 ps
CPU time 62.1 seconds
Started Aug 19 06:08:11 PM PDT 24
Finished Aug 19 06:09:13 PM PDT 24
Peak memory 208736 kb
Host smart-2e7bcb9a-dafd-4f4a-9cfe-896b554b0e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988730013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2988730013
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1857754798
Short name T1012
Test name
Test status
Simulation time 2899439459 ps
CPU time 62.36 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:09:11 PM PDT 24
Peak memory 200924 kb
Host smart-1b6f0881-835c-4593-8a64-8b1b7055a13e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857754798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1857754798
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.240225884
Short name T828
Test name
Test status
Simulation time 3963346652 ps
CPU time 5.28 seconds
Started Aug 19 06:08:07 PM PDT 24
Finished Aug 19 06:08:13 PM PDT 24
Peak memory 200132 kb
Host smart-39d2cc47-b4d7-42bb-a3e2-93d8efcccb5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=240225884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.240225884
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.796216345
Short name T1031
Test name
Test status
Simulation time 31604181541 ps
CPU time 53.15 seconds
Started Aug 19 06:08:11 PM PDT 24
Finished Aug 19 06:09:05 PM PDT 24
Peak memory 200960 kb
Host smart-e6dda526-2be6-4ca4-93cc-ca4c6ad75e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796216345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.796216345
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3811647445
Short name T455
Test name
Test status
Simulation time 521442244 ps
CPU time 1.04 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:08:09 PM PDT 24
Peak memory 196644 kb
Host smart-8bdf0cc0-7c29-48ee-99c1-04fa35c9a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811647445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3811647445
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3642524478
Short name T603
Test name
Test status
Simulation time 117229596 ps
CPU time 1.02 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:08:09 PM PDT 24
Peak memory 199472 kb
Host smart-bd04ba5b-3311-4f6a-9e20-2192dabb69dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642524478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3642524478
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1859283658
Short name T973
Test name
Test status
Simulation time 207736775461 ps
CPU time 365 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:14:13 PM PDT 24
Peak memory 201000 kb
Host smart-146394c9-42cb-4eb8-b05f-7ed29363f481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859283658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1859283658
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1805398542
Short name T6
Test name
Test status
Simulation time 11917996264 ps
CPU time 49.85 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:08:58 PM PDT 24
Peak memory 216980 kb
Host smart-68140519-3feb-4587-a58a-e5111ba29512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805398542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1805398542
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1724948533
Short name T1167
Test name
Test status
Simulation time 6071219068 ps
CPU time 32.49 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:08:42 PM PDT 24
Peak memory 200972 kb
Host smart-ea5864b1-36c4-4d8f-9511-884b6ed51851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724948533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1724948533
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1901333438
Short name T1030
Test name
Test status
Simulation time 51203681486 ps
CPU time 69.16 seconds
Started Aug 19 06:08:10 PM PDT 24
Finished Aug 19 06:09:19 PM PDT 24
Peak memory 201000 kb
Host smart-250fbe2e-7466-40ee-8d01-f9709005daa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901333438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1901333438
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3910616554
Short name T607
Test name
Test status
Simulation time 22742583 ps
CPU time 0.57 seconds
Started Aug 19 06:05:11 PM PDT 24
Finished Aug 19 06:05:12 PM PDT 24
Peak memory 196268 kb
Host smart-7c5c1cf1-871e-45d0-b2fc-32fb1b297c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910616554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3910616554
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.458574079
Short name T933
Test name
Test status
Simulation time 65955790864 ps
CPU time 123.4 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:07:14 PM PDT 24
Peak memory 200916 kb
Host smart-dc709981-cec4-4545-a80c-74bc8889a271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458574079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.458574079
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.412492937
Short name T322
Test name
Test status
Simulation time 41260957013 ps
CPU time 17.45 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:05:30 PM PDT 24
Peak memory 200352 kb
Host smart-cfbb3d1f-e019-490a-8207-c1e47a1fcd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412492937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.412492937
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2612718155
Short name T180
Test name
Test status
Simulation time 19709999523 ps
CPU time 46.66 seconds
Started Aug 19 06:05:14 PM PDT 24
Finished Aug 19 06:06:01 PM PDT 24
Peak memory 200876 kb
Host smart-a38baf2a-3c81-401c-9437-f82a04bb86c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612718155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2612718155
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2423947180
Short name T494
Test name
Test status
Simulation time 101152108492 ps
CPU time 286.26 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:09:59 PM PDT 24
Peak memory 200884 kb
Host smart-7e94820f-4694-4c94-971e-2369293dbca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423947180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2423947180
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.850291398
Short name T370
Test name
Test status
Simulation time 8873535616 ps
CPU time 13.22 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:05:24 PM PDT 24
Peak memory 200952 kb
Host smart-30ea76e1-c921-4e90-bd62-2afc47ecaa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850291398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.850291398
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3626327632
Short name T980
Test name
Test status
Simulation time 53522985302 ps
CPU time 21.28 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:05:32 PM PDT 24
Peak memory 201112 kb
Host smart-ab5d81d5-a7fa-4b29-935b-9a081dc18b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626327632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3626327632
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1325641955
Short name T3
Test name
Test status
Simulation time 14220926663 ps
CPU time 492.22 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:13:25 PM PDT 24
Peak memory 200804 kb
Host smart-0412bf42-1835-459f-967f-58d5575fe95d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325641955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1325641955
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3499674246
Short name T1082
Test name
Test status
Simulation time 2957149366 ps
CPU time 11.42 seconds
Started Aug 19 06:05:11 PM PDT 24
Finished Aug 19 06:05:22 PM PDT 24
Peak memory 199152 kb
Host smart-15c886c0-60b3-4c42-bef9-5e08855332dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499674246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3499674246
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1821651252
Short name T460
Test name
Test status
Simulation time 15891281364 ps
CPU time 23.69 seconds
Started Aug 19 06:05:15 PM PDT 24
Finished Aug 19 06:05:39 PM PDT 24
Peak memory 200720 kb
Host smart-8e81b077-db5c-4d6b-8e79-1162d14b219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821651252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1821651252
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1425679263
Short name T982
Test name
Test status
Simulation time 43384435532 ps
CPU time 60.26 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:06:12 PM PDT 24
Peak memory 196776 kb
Host smart-2b281c84-ed59-4d06-861d-a4c446f9a8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425679263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1425679263
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3848559280
Short name T677
Test name
Test status
Simulation time 645395919 ps
CPU time 3.15 seconds
Started Aug 19 06:05:11 PM PDT 24
Finished Aug 19 06:05:14 PM PDT 24
Peak memory 200720 kb
Host smart-5905bd6b-ef9b-4e60-aee0-006901dd74ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848559280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3848559280
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3244858150
Short name T570
Test name
Test status
Simulation time 170157159178 ps
CPU time 182.34 seconds
Started Aug 19 06:05:14 PM PDT 24
Finished Aug 19 06:08:16 PM PDT 24
Peak memory 200972 kb
Host smart-ccd3d43b-fb34-4e20-9b47-17b1c6f979c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244858150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3244858150
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3109787573
Short name T385
Test name
Test status
Simulation time 2479192348 ps
CPU time 30.13 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:05:42 PM PDT 24
Peak memory 216872 kb
Host smart-9d0ec286-d66e-486d-9921-e2c6dd8b0441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109787573 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3109787573
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1639174159
Short name T394
Test name
Test status
Simulation time 851772903 ps
CPU time 3.7 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:05:16 PM PDT 24
Peak memory 200496 kb
Host smart-f33db45d-619d-4010-9290-4256a8cfb72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639174159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1639174159
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.72934383
Short name T1004
Test name
Test status
Simulation time 102680486055 ps
CPU time 36.77 seconds
Started Aug 19 06:05:20 PM PDT 24
Finished Aug 19 06:05:57 PM PDT 24
Peak memory 200916 kb
Host smart-c4d0ba05-c74e-44eb-8f51-887b04556b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72934383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.72934383
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.604131295
Short name T975
Test name
Test status
Simulation time 14406491616 ps
CPU time 26.59 seconds
Started Aug 19 06:08:10 PM PDT 24
Finished Aug 19 06:08:37 PM PDT 24
Peak memory 200916 kb
Host smart-005fa017-70eb-40d3-8673-296a7282b728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604131295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.604131295
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.321874066
Short name T333
Test name
Test status
Simulation time 232472538612 ps
CPU time 37.09 seconds
Started Aug 19 06:08:07 PM PDT 24
Finished Aug 19 06:08:44 PM PDT 24
Peak memory 200924 kb
Host smart-2d7cf776-4161-44f0-b4c9-e7f6a8daee7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321874066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.321874066
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1264999428
Short name T361
Test name
Test status
Simulation time 2408021212 ps
CPU time 54.43 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:09:03 PM PDT 24
Peak memory 201016 kb
Host smart-cd1008f4-7a1e-426d-8f37-150def945095
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264999428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1264999428
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.123958746
Short name T92
Test name
Test status
Simulation time 3983091082 ps
CPU time 35.6 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:08:45 PM PDT 24
Peak memory 217584 kb
Host smart-0dad156c-f47c-4552-9b12-22735ff5b90e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123958746 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.123958746
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.213794328
Short name T203
Test name
Test status
Simulation time 36957426481 ps
CPU time 40.82 seconds
Started Aug 19 06:08:10 PM PDT 24
Finished Aug 19 06:08:51 PM PDT 24
Peak memory 200968 kb
Host smart-0a442b32-3873-49e3-bf07-1ee7fb0dca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213794328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.213794328
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.464901872
Short name T94
Test name
Test status
Simulation time 24651577350 ps
CPU time 26.54 seconds
Started Aug 19 06:08:10 PM PDT 24
Finished Aug 19 06:08:37 PM PDT 24
Peak memory 209244 kb
Host smart-5b5c0805-7d08-4448-b957-a5b2035bc0d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464901872 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.464901872
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2568277293
Short name T227
Test name
Test status
Simulation time 65654310867 ps
CPU time 56.27 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:09:05 PM PDT 24
Peak memory 200900 kb
Host smart-70c49fdf-57ba-49c7-a51d-5d466fe29e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568277293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2568277293
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1911355960
Short name T640
Test name
Test status
Simulation time 13029488153 ps
CPU time 19.12 seconds
Started Aug 19 06:08:12 PM PDT 24
Finished Aug 19 06:08:31 PM PDT 24
Peak memory 216360 kb
Host smart-7f73ada6-494d-46f9-b939-b3c6eabcac0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911355960 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1911355960
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2773726035
Short name T698
Test name
Test status
Simulation time 58660174060 ps
CPU time 89.18 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:09:37 PM PDT 24
Peak memory 200876 kb
Host smart-9626c76e-ddec-4b1a-b32d-17cec8fd2801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773726035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2773726035
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2952988296
Short name T865
Test name
Test status
Simulation time 10259584155 ps
CPU time 20.76 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:08:30 PM PDT 24
Peak memory 209440 kb
Host smart-270eaef7-c22f-4c80-8ef8-4ad215c81a83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952988296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2952988296
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3022318920
Short name T187
Test name
Test status
Simulation time 44926114115 ps
CPU time 17.79 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:08:25 PM PDT 24
Peak memory 200984 kb
Host smart-061266b4-e0fd-4d54-9156-fe855e5f6e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022318920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3022318920
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1802192724
Short name T286
Test name
Test status
Simulation time 22641346083 ps
CPU time 67.2 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:09:15 PM PDT 24
Peak memory 217600 kb
Host smart-df67fb41-0532-4a59-b10e-7b4aa24bc5ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802192724 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1802192724
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.129178031
Short name T972
Test name
Test status
Simulation time 51689423386 ps
CPU time 70.09 seconds
Started Aug 19 06:08:08 PM PDT 24
Finished Aug 19 06:09:19 PM PDT 24
Peak memory 200968 kb
Host smart-10b5e9b5-ed0b-467d-b90f-a02d61cecf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129178031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.129178031
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1327336957
Short name T22
Test name
Test status
Simulation time 3660582026 ps
CPU time 16.54 seconds
Started Aug 19 06:08:11 PM PDT 24
Finished Aug 19 06:08:28 PM PDT 24
Peak memory 214440 kb
Host smart-d180d482-f964-4ee8-a440-edd5574fc62a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327336957 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1327336957
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.612765396
Short name T302
Test name
Test status
Simulation time 315040030799 ps
CPU time 183.22 seconds
Started Aug 19 06:08:09 PM PDT 24
Finished Aug 19 06:11:12 PM PDT 24
Peak memory 200964 kb
Host smart-d5284d88-f999-448b-a8ce-aabbcfa9d108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612765396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.612765396
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2808883475
Short name T520
Test name
Test status
Simulation time 2039895051 ps
CPU time 13.84 seconds
Started Aug 19 06:08:12 PM PDT 24
Finished Aug 19 06:08:26 PM PDT 24
Peak memory 199648 kb
Host smart-51a2596d-c5ee-4d19-bd50-e7ba78afe710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808883475 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2808883475
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1616473774
Short name T608
Test name
Test status
Simulation time 193609301052 ps
CPU time 537.85 seconds
Started Aug 19 06:08:18 PM PDT 24
Finished Aug 19 06:17:16 PM PDT 24
Peak memory 200864 kb
Host smart-7a421e9b-2035-4cac-8098-50fc4ac87d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616473774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1616473774
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1520835831
Short name T564
Test name
Test status
Simulation time 20293189602 ps
CPU time 47.86 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:09:08 PM PDT 24
Peak memory 217360 kb
Host smart-5b1fad93-855f-4600-a9e3-16b3b59fd168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520835831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1520835831
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2856110662
Short name T958
Test name
Test status
Simulation time 39961891 ps
CPU time 0.58 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:20 PM PDT 24
Peak memory 196580 kb
Host smart-45108a16-c140-4007-8f13-5e3061e0c24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856110662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2856110662
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.69098398
Short name T1063
Test name
Test status
Simulation time 30847350625 ps
CPU time 38.88 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:05:52 PM PDT 24
Peak memory 200996 kb
Host smart-89c76517-f01d-4e82-a35f-8412381b68f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69098398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.69098398
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2083209258
Short name T315
Test name
Test status
Simulation time 85735953209 ps
CPU time 127.87 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:07:21 PM PDT 24
Peak memory 200812 kb
Host smart-df01409a-e97c-4ab6-913d-2d9744b7234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083209258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2083209258
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3944795234
Short name T1011
Test name
Test status
Simulation time 29052974046 ps
CPU time 24.49 seconds
Started Aug 19 06:05:10 PM PDT 24
Finished Aug 19 06:05:35 PM PDT 24
Peak memory 200744 kb
Host smart-eedc0122-8f8d-4926-8ce9-ed89e48e62fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944795234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3944795234
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.444284178
Short name T293
Test name
Test status
Simulation time 33250330827 ps
CPU time 14.2 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:05:26 PM PDT 24
Peak memory 200932 kb
Host smart-4b5c9b9c-535c-4eb1-b9e4-63129e6a94cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444284178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.444284178
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.482097083
Short name T670
Test name
Test status
Simulation time 54958565429 ps
CPU time 419.65 seconds
Started Aug 19 06:05:31 PM PDT 24
Finished Aug 19 06:12:31 PM PDT 24
Peak memory 200916 kb
Host smart-5465fd7b-0b3c-4466-b80e-31b627646ca5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482097083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.482097083
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3372628379
Short name T371
Test name
Test status
Simulation time 2260245365 ps
CPU time 1.16 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:05:13 PM PDT 24
Peak memory 197116 kb
Host smart-8b79368b-58c4-4c3d-9334-8b26d440a38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372628379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3372628379
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1174093523
Short name T1156
Test name
Test status
Simulation time 77335071343 ps
CPU time 24.22 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:05:37 PM PDT 24
Peak memory 197076 kb
Host smart-ff526afc-fe26-4380-8cdf-2077aac82ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174093523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1174093523
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3781587943
Short name T776
Test name
Test status
Simulation time 18855728465 ps
CPU time 243.22 seconds
Started Aug 19 06:05:12 PM PDT 24
Finished Aug 19 06:09:15 PM PDT 24
Peak memory 200980 kb
Host smart-2f31b274-a224-42dc-9bf1-6f157270c2d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781587943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3781587943
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3698574852
Short name T712
Test name
Test status
Simulation time 5066846803 ps
CPU time 3.16 seconds
Started Aug 19 06:05:13 PM PDT 24
Finished Aug 19 06:05:16 PM PDT 24
Peak memory 198964 kb
Host smart-bc527131-7050-4baa-931d-55f2ba96b1cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698574852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3698574852
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1243882243
Short name T164
Test name
Test status
Simulation time 70731219073 ps
CPU time 25 seconds
Started Aug 19 06:05:09 PM PDT 24
Finished Aug 19 06:05:35 PM PDT 24
Peak memory 200956 kb
Host smart-595e6340-a284-41a9-acc6-b5b925d19513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243882243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1243882243
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1850189499
Short name T313
Test name
Test status
Simulation time 5545521788 ps
CPU time 8.54 seconds
Started Aug 19 06:05:15 PM PDT 24
Finished Aug 19 06:05:23 PM PDT 24
Peak memory 197272 kb
Host smart-c33f9cc2-b941-4833-9572-11c6249c4dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850189499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1850189499
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2205018642
Short name T1103
Test name
Test status
Simulation time 117577389 ps
CPU time 0.96 seconds
Started Aug 19 06:05:14 PM PDT 24
Finished Aug 19 06:05:15 PM PDT 24
Peak memory 198908 kb
Host smart-e4695a4b-cd84-49b5-9a14-e76aaec3f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205018642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2205018642
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.221595967
Short name T12
Test name
Test status
Simulation time 5287518028 ps
CPU time 50.19 seconds
Started Aug 19 06:05:25 PM PDT 24
Finished Aug 19 06:06:16 PM PDT 24
Peak memory 209388 kb
Host smart-4250bb37-621a-43b2-973e-ff7255dfc5bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221595967 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.221595967
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2795053355
Short name T1052
Test name
Test status
Simulation time 1438287538 ps
CPU time 3.78 seconds
Started Aug 19 06:05:22 PM PDT 24
Finished Aug 19 06:05:26 PM PDT 24
Peak memory 199400 kb
Host smart-37b9da96-4341-4502-a5e6-9d71c554078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795053355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2795053355
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.4018887315
Short name T770
Test name
Test status
Simulation time 8306523237 ps
CPU time 11.63 seconds
Started Aug 19 06:05:14 PM PDT 24
Finished Aug 19 06:05:25 PM PDT 24
Peak memory 198848 kb
Host smart-c49d60b2-6015-4952-a20c-dd64e696a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018887315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4018887315
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3749475887
Short name T567
Test name
Test status
Simulation time 38761517020 ps
CPU time 68.11 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:09:29 PM PDT 24
Peak memory 200880 kb
Host smart-2fa00c74-30d3-4b62-a1df-713e9fe5c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749475887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3749475887
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1263402884
Short name T898
Test name
Test status
Simulation time 9976188647 ps
CPU time 21.15 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:08:41 PM PDT 24
Peak memory 216848 kb
Host smart-154a08d5-bfd2-4ea2-bac6-ec795612dbbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263402884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1263402884
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3925124084
Short name T309
Test name
Test status
Simulation time 22774518886 ps
CPU time 10.23 seconds
Started Aug 19 06:08:19 PM PDT 24
Finished Aug 19 06:08:30 PM PDT 24
Peak memory 200972 kb
Host smart-eab836dd-f71a-42b0-be00-ba240fe0db84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925124084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3925124084
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2348983526
Short name T605
Test name
Test status
Simulation time 7394238119 ps
CPU time 62.21 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:09:22 PM PDT 24
Peak memory 217432 kb
Host smart-4530f63f-86c4-4837-8f22-b210c5bbf498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348983526 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2348983526
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.4132029814
Short name T918
Test name
Test status
Simulation time 76656968956 ps
CPU time 21.37 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:08:42 PM PDT 24
Peak memory 200980 kb
Host smart-a8b09158-05ed-48ed-9d5a-56725c21a91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132029814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4132029814
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.4091488005
Short name T921
Test name
Test status
Simulation time 11057870763 ps
CPU time 33.79 seconds
Started Aug 19 06:08:19 PM PDT 24
Finished Aug 19 06:08:53 PM PDT 24
Peak memory 217536 kb
Host smart-d4eece91-8498-42b9-b200-c1f6e9a11b0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091488005 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.4091488005
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3976139625
Short name T588
Test name
Test status
Simulation time 117773739397 ps
CPU time 162.39 seconds
Started Aug 19 06:08:21 PM PDT 24
Finished Aug 19 06:11:04 PM PDT 24
Peak memory 200892 kb
Host smart-c5f91c74-0746-4e43-bbf2-0db818e43509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976139625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3976139625
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.186863438
Short name T359
Test name
Test status
Simulation time 1356637375 ps
CPU time 15.33 seconds
Started Aug 19 06:08:21 PM PDT 24
Finished Aug 19 06:08:37 PM PDT 24
Peak memory 209132 kb
Host smart-a47cf418-b416-4512-8bbd-32bae9342714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186863438 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.186863438
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2823227070
Short name T730
Test name
Test status
Simulation time 41359116987 ps
CPU time 84.53 seconds
Started Aug 19 06:08:21 PM PDT 24
Finished Aug 19 06:09:46 PM PDT 24
Peak memory 216764 kb
Host smart-fa7481d5-2518-41c6-8ba9-ab69788337b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823227070 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2823227070
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4068388247
Short name T704
Test name
Test status
Simulation time 73720851306 ps
CPU time 32.03 seconds
Started Aug 19 06:08:21 PM PDT 24
Finished Aug 19 06:08:54 PM PDT 24
Peak memory 200980 kb
Host smart-de226225-c8bd-4c41-b836-0ae4796d1a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068388247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4068388247
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2666061549
Short name T754
Test name
Test status
Simulation time 5263067554 ps
CPU time 101.08 seconds
Started Aug 19 06:08:23 PM PDT 24
Finished Aug 19 06:10:04 PM PDT 24
Peak memory 210436 kb
Host smart-1c1b34c1-bece-4e48-aa26-a4bb7f92b20d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666061549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2666061549
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3351841346
Short name T613
Test name
Test status
Simulation time 37638763418 ps
CPU time 73.24 seconds
Started Aug 19 06:08:26 PM PDT 24
Finished Aug 19 06:09:39 PM PDT 24
Peak memory 200964 kb
Host smart-506bcf86-2ecc-48bb-8e20-2311e1afb759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351841346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3351841346
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1589860861
Short name T1064
Test name
Test status
Simulation time 3210489799 ps
CPU time 37.18 seconds
Started Aug 19 06:08:26 PM PDT 24
Finished Aug 19 06:09:03 PM PDT 24
Peak memory 209428 kb
Host smart-d575e266-d189-4586-80cb-1dfb0281989b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589860861 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1589860861
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.985530661
Short name T204
Test name
Test status
Simulation time 160126516470 ps
CPU time 118.76 seconds
Started Aug 19 06:08:25 PM PDT 24
Finished Aug 19 06:10:24 PM PDT 24
Peak memory 200904 kb
Host smart-a371c103-d2e3-470d-ac5a-ad8e2fa76f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985530661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.985530661
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3011610534
Short name T515
Test name
Test status
Simulation time 11466576659 ps
CPU time 35.15 seconds
Started Aug 19 06:08:27 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 217500 kb
Host smart-6f71ccfd-7e8a-405c-8070-450987f385c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011610534 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3011610534
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.4019624807
Short name T35
Test name
Test status
Simulation time 137511475549 ps
CPU time 240.82 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:12:21 PM PDT 24
Peak memory 200948 kb
Host smart-4b245c88-0dd0-4dc0-beef-f007cfc0a25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019624807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4019624807
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1306677512
Short name T729
Test name
Test status
Simulation time 2858782304 ps
CPU time 51.69 seconds
Started Aug 19 06:08:19 PM PDT 24
Finished Aug 19 06:09:11 PM PDT 24
Peak memory 209216 kb
Host smart-5a7e9afc-8652-4e28-9d8b-16440fa16426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306677512 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1306677512
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1048497110
Short name T528
Test name
Test status
Simulation time 202515576953 ps
CPU time 219.82 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:12:00 PM PDT 24
Peak memory 200956 kb
Host smart-6b1387e0-56ed-46f4-a2b0-e6a7ed40a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048497110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1048497110
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3817343998
Short name T90
Test name
Test status
Simulation time 3304659577 ps
CPU time 42.93 seconds
Started Aug 19 06:08:19 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 217420 kb
Host smart-bc883a06-22c0-48bc-8169-9eb61ae386ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817343998 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3817343998
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.189451673
Short name T1114
Test name
Test status
Simulation time 22573062 ps
CPU time 0.53 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:05:27 PM PDT 24
Peak memory 195216 kb
Host smart-47d28a13-b088-4dd4-a04a-acb9da6216bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189451673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.189451673
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3496745870
Short name T446
Test name
Test status
Simulation time 51887813348 ps
CPU time 74.65 seconds
Started Aug 19 06:05:25 PM PDT 24
Finished Aug 19 06:06:40 PM PDT 24
Peak memory 200888 kb
Host smart-5fb70660-4e12-498f-a954-29ba4b8f0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496745870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3496745870
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2832715688
Short name T1016
Test name
Test status
Simulation time 97782786536 ps
CPU time 39.93 seconds
Started Aug 19 06:05:25 PM PDT 24
Finished Aug 19 06:06:05 PM PDT 24
Peak memory 200956 kb
Host smart-33238f0f-e90b-4dff-805f-16b7902e2770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832715688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2832715688
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.905387850
Short name T1006
Test name
Test status
Simulation time 23311260680 ps
CPU time 40.31 seconds
Started Aug 19 06:05:20 PM PDT 24
Finished Aug 19 06:06:00 PM PDT 24
Peak memory 200944 kb
Host smart-ca0bc036-ff83-4538-a7b7-b059175e7107
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905387850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.905387850
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3807380931
Short name T39
Test name
Test status
Simulation time 67978321443 ps
CPU time 521.58 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:14:07 PM PDT 24
Peak memory 200952 kb
Host smart-09ae207f-3db5-4dc1-883f-824406523e5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807380931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3807380931
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1097979283
Short name T769
Test name
Test status
Simulation time 12388331869 ps
CPU time 14.39 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:33 PM PDT 24
Peak memory 200932 kb
Host smart-5ce4f4d8-1f59-43d8-9af2-20982ff2f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097979283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1097979283
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2619191989
Short name T809
Test name
Test status
Simulation time 63574551919 ps
CPU time 57.11 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:06:16 PM PDT 24
Peak memory 201176 kb
Host smart-d35956ed-e88f-4ebb-b09a-8dcc429ecbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619191989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2619191989
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.4126407820
Short name T1174
Test name
Test status
Simulation time 12682270329 ps
CPU time 624.21 seconds
Started Aug 19 06:05:31 PM PDT 24
Finished Aug 19 06:15:56 PM PDT 24
Peak memory 200916 kb
Host smart-1a782f71-8a7e-443a-9505-a0072f06df60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126407820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.4126407820
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3265559256
Short name T1057
Test name
Test status
Simulation time 6187467138 ps
CPU time 13.49 seconds
Started Aug 19 06:05:18 PM PDT 24
Finished Aug 19 06:05:31 PM PDT 24
Peak memory 200180 kb
Host smart-ba57704e-d1c9-4bcb-9aa8-f005a141c516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265559256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3265559256
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3849249689
Short name T172
Test name
Test status
Simulation time 123496687772 ps
CPU time 166.65 seconds
Started Aug 19 06:05:20 PM PDT 24
Finished Aug 19 06:08:07 PM PDT 24
Peak memory 200936 kb
Host smart-49b4210a-8719-4a99-ae80-51b2f42754f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849249689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3849249689
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.841110695
Short name T581
Test name
Test status
Simulation time 5202844997 ps
CPU time 8.36 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:28 PM PDT 24
Peak memory 197272 kb
Host smart-6c91bb17-c65c-439a-a2f4-9a7fe8cb77f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841110695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.841110695
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.773323943
Short name T808
Test name
Test status
Simulation time 5957081066 ps
CPU time 12.86 seconds
Started Aug 19 06:05:31 PM PDT 24
Finished Aug 19 06:05:44 PM PDT 24
Peak memory 200868 kb
Host smart-241f131c-bf17-4e1e-9cfc-fe2f46af0f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773323943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.773323943
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2702977076
Short name T967
Test name
Test status
Simulation time 29822129637 ps
CPU time 42.42 seconds
Started Aug 19 06:05:18 PM PDT 24
Finished Aug 19 06:06:00 PM PDT 24
Peak memory 200984 kb
Host smart-8af6f183-e2b2-4c6b-a9cc-d336c6cbf427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702977076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2702977076
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.429188457
Short name T1032
Test name
Test status
Simulation time 11072357326 ps
CPU time 74.23 seconds
Started Aug 19 06:05:20 PM PDT 24
Finished Aug 19 06:06:34 PM PDT 24
Peak memory 217396 kb
Host smart-bfdfcea9-79c6-4d86-966e-3095937a9e5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429188457 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.429188457
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3865990675
Short name T994
Test name
Test status
Simulation time 1293645547 ps
CPU time 1.7 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:21 PM PDT 24
Peak memory 199308 kb
Host smart-e62b7805-e4a6-43eb-a688-5a9660fef828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865990675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3865990675
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3622312946
Short name T384
Test name
Test status
Simulation time 73925218255 ps
CPU time 196.79 seconds
Started Aug 19 06:05:31 PM PDT 24
Finished Aug 19 06:08:48 PM PDT 24
Peak memory 200896 kb
Host smart-52f156bf-11ba-4ab1-8a5e-2afe4cf5d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622312946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3622312946
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.489594630
Short name T95
Test name
Test status
Simulation time 4094046581 ps
CPU time 43.31 seconds
Started Aug 19 06:08:19 PM PDT 24
Finished Aug 19 06:09:03 PM PDT 24
Peak memory 216504 kb
Host smart-e277201d-a899-416b-8ee6-0258c6aed772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489594630 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.489594630
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3080702601
Short name T1005
Test name
Test status
Simulation time 38435619574 ps
CPU time 16.28 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:08:36 PM PDT 24
Peak memory 200780 kb
Host smart-e533feed-9916-41e9-95b3-2a060169250e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080702601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3080702601
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2692530963
Short name T909
Test name
Test status
Simulation time 6145280778 ps
CPU time 18.76 seconds
Started Aug 19 06:08:17 PM PDT 24
Finished Aug 19 06:08:36 PM PDT 24
Peak memory 217588 kb
Host smart-ed03bfe5-1900-4082-a632-d47873197f70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692530963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2692530963
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3502312541
Short name T503
Test name
Test status
Simulation time 8741473917 ps
CPU time 11.49 seconds
Started Aug 19 06:08:27 PM PDT 24
Finished Aug 19 06:08:39 PM PDT 24
Peak memory 199716 kb
Host smart-ada8c7ef-79b6-4457-9943-c65a028a8d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502312541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3502312541
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3675372376
Short name T21
Test name
Test status
Simulation time 1404642308 ps
CPU time 22.56 seconds
Started Aug 19 06:08:17 PM PDT 24
Finished Aug 19 06:08:40 PM PDT 24
Peak memory 200944 kb
Host smart-b29bb489-bb4c-4679-9cdc-333e674df8f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675372376 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3675372376
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2229869661
Short name T183
Test name
Test status
Simulation time 28076530526 ps
CPU time 16.1 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:08:36 PM PDT 24
Peak memory 200968 kb
Host smart-5978cd6a-6f83-4f5f-a3e6-4be902226c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229869661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2229869661
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.834018233
Short name T497
Test name
Test status
Simulation time 11414970721 ps
CPU time 82.11 seconds
Started Aug 19 06:08:27 PM PDT 24
Finished Aug 19 06:09:49 PM PDT 24
Peak memory 216628 kb
Host smart-598e3729-a699-439c-b221-13c7eec3e75c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834018233 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.834018233
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1222914630
Short name T881
Test name
Test status
Simulation time 160829749040 ps
CPU time 70.85 seconds
Started Aug 19 06:08:21 PM PDT 24
Finished Aug 19 06:09:32 PM PDT 24
Peak memory 200900 kb
Host smart-ef5751fb-0f20-4283-9f84-f157f137aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222914630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1222914630
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.836145870
Short name T900
Test name
Test status
Simulation time 4417582979 ps
CPU time 48.05 seconds
Started Aug 19 06:08:19 PM PDT 24
Finished Aug 19 06:09:07 PM PDT 24
Peak memory 216440 kb
Host smart-079be146-d8bc-44f0-8758-08e83f27da9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836145870 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.836145870
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1606056590
Short name T780
Test name
Test status
Simulation time 29636231355 ps
CPU time 37.4 seconds
Started Aug 19 06:08:23 PM PDT 24
Finished Aug 19 06:09:01 PM PDT 24
Peak memory 200976 kb
Host smart-191db491-3dfa-457a-b2d4-f5ddf0b50eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606056590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1606056590
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.16997832
Short name T139
Test name
Test status
Simulation time 8484108249 ps
CPU time 26.03 seconds
Started Aug 19 06:08:21 PM PDT 24
Finished Aug 19 06:08:47 PM PDT 24
Peak memory 216844 kb
Host smart-f6cd3b72-d0aa-4e0d-b0db-4e6a8df44f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16997832 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.16997832
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3810643875
Short name T162
Test name
Test status
Simulation time 29076453926 ps
CPU time 44.85 seconds
Started Aug 19 06:08:20 PM PDT 24
Finished Aug 19 06:09:04 PM PDT 24
Peak memory 200960 kb
Host smart-53544520-01fa-4ee5-b957-75d801f18d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810643875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3810643875
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.860096376
Short name T1024
Test name
Test status
Simulation time 1668408290 ps
CPU time 20.14 seconds
Started Aug 19 06:08:26 PM PDT 24
Finished Aug 19 06:08:46 PM PDT 24
Peak memory 200956 kb
Host smart-2dfa3030-d0e3-45f2-8338-4566d056ac86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860096376 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.860096376
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.967143208
Short name T201
Test name
Test status
Simulation time 13234747190 ps
CPU time 8.43 seconds
Started Aug 19 06:08:26 PM PDT 24
Finished Aug 19 06:08:35 PM PDT 24
Peak memory 200632 kb
Host smart-446a3a17-1048-4f96-817f-4d906ed42a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967143208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.967143208
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2715191620
Short name T156
Test name
Test status
Simulation time 290450495499 ps
CPU time 95.04 seconds
Started Aug 19 06:08:19 PM PDT 24
Finished Aug 19 06:09:54 PM PDT 24
Peak memory 200876 kb
Host smart-d0a011a2-4149-4846-880c-6306ff450950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715191620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2715191620
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2019359463
Short name T764
Test name
Test status
Simulation time 5358280678 ps
CPU time 35.17 seconds
Started Aug 19 06:08:21 PM PDT 24
Finished Aug 19 06:08:56 PM PDT 24
Peak memory 217464 kb
Host smart-b4680416-df81-4a9a-aca0-87bef5a1869b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019359463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2019359463
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.763354628
Short name T237
Test name
Test status
Simulation time 117209033974 ps
CPU time 192.81 seconds
Started Aug 19 06:08:19 PM PDT 24
Finished Aug 19 06:11:32 PM PDT 24
Peak memory 200932 kb
Host smart-9487b18d-de47-4ac2-8b30-24ad4df8ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763354628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.763354628
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3554871944
Short name T707
Test name
Test status
Simulation time 1545076572 ps
CPU time 18.98 seconds
Started Aug 19 06:08:27 PM PDT 24
Finished Aug 19 06:08:46 PM PDT 24
Peak memory 200800 kb
Host smart-b1d3ad7f-11e3-4a61-a7f4-232e4126c4a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554871944 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3554871944
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2896412901
Short name T518
Test name
Test status
Simulation time 31588846 ps
CPU time 0.53 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:28 PM PDT 24
Peak memory 196236 kb
Host smart-0b46fb23-6b19-4722-9e04-a07424195aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896412901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2896412901
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.895119644
Short name T449
Test name
Test status
Simulation time 80403251571 ps
CPU time 36.21 seconds
Started Aug 19 06:05:18 PM PDT 24
Finished Aug 19 06:05:55 PM PDT 24
Peak memory 200912 kb
Host smart-eadeb36d-52dc-43a0-bb90-29136afff0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895119644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.895119644
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.541653066
Short name T500
Test name
Test status
Simulation time 65385816456 ps
CPU time 30.72 seconds
Started Aug 19 06:05:25 PM PDT 24
Finished Aug 19 06:05:56 PM PDT 24
Peak memory 200912 kb
Host smart-cf1b9f5f-4e42-4ce2-8ee7-03ffdb0d340d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541653066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.541653066
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3334508302
Short name T953
Test name
Test status
Simulation time 162704377946 ps
CPU time 266.31 seconds
Started Aug 19 06:05:31 PM PDT 24
Finished Aug 19 06:09:58 PM PDT 24
Peak memory 200904 kb
Host smart-de6953e9-a7cd-4f57-b57a-3d92ae330f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334508302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3334508302
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.747788776
Short name T450
Test name
Test status
Simulation time 16808758327 ps
CPU time 8.75 seconds
Started Aug 19 06:05:20 PM PDT 24
Finished Aug 19 06:05:29 PM PDT 24
Peak memory 200544 kb
Host smart-f4de5c47-cfd3-4bc2-b38f-9a6077396128
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747788776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.747788776
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.174239795
Short name T860
Test name
Test status
Simulation time 81966946867 ps
CPU time 764.67 seconds
Started Aug 19 06:05:31 PM PDT 24
Finished Aug 19 06:18:16 PM PDT 24
Peak memory 200916 kb
Host smart-9b68d430-f069-43a5-a16a-a4db977d4970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174239795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.174239795
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2277830042
Short name T731
Test name
Test status
Simulation time 2696204812 ps
CPU time 4.98 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:24 PM PDT 24
Peak memory 197516 kb
Host smart-241c8dd4-05a1-45fa-a416-952b43e7971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277830042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2277830042
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2883486838
Short name T878
Test name
Test status
Simulation time 20332255190 ps
CPU time 8.34 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:27 PM PDT 24
Peak memory 200948 kb
Host smart-8d127c3e-822f-422a-963f-7031c9e7803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883486838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2883486838
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.809184943
Short name T888
Test name
Test status
Simulation time 21401676225 ps
CPU time 251.8 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:09:38 PM PDT 24
Peak memory 200924 kb
Host smart-7ac98d5f-bc8c-48dd-8b21-447706822dc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809184943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.809184943
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2032019837
Short name T844
Test name
Test status
Simulation time 2217554411 ps
CPU time 11.99 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:05:38 PM PDT 24
Peak memory 199012 kb
Host smart-813f9d10-49c8-45b9-8779-cf9e6d62bbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032019837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2032019837
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.951964095
Short name T366
Test name
Test status
Simulation time 50066456976 ps
CPU time 46.54 seconds
Started Aug 19 06:05:17 PM PDT 24
Finished Aug 19 06:06:03 PM PDT 24
Peak memory 200884 kb
Host smart-99197a0a-44e3-43f5-946d-5ff9573a4f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951964095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.951964095
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3275745331
Short name T268
Test name
Test status
Simulation time 37174236523 ps
CPU time 43.36 seconds
Started Aug 19 06:05:18 PM PDT 24
Finished Aug 19 06:06:01 PM PDT 24
Peak memory 197596 kb
Host smart-ebef8151-5a1f-47a5-b2ac-3d2ab8adfd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275745331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3275745331
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.666051813
Short name T561
Test name
Test status
Simulation time 6009328236 ps
CPU time 8.43 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:05:35 PM PDT 24
Peak memory 200824 kb
Host smart-39bd579a-9a8e-4753-b452-7bd1861d029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666051813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.666051813
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.25378897
Short name T892
Test name
Test status
Simulation time 76404575129 ps
CPU time 703.88 seconds
Started Aug 19 06:05:31 PM PDT 24
Finished Aug 19 06:17:15 PM PDT 24
Peak memory 200928 kb
Host smart-2281d607-67b7-41ea-b260-7e542c86bbe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.25378897
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.4263693832
Short name T995
Test name
Test status
Simulation time 2889862821 ps
CPU time 38.97 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:58 PM PDT 24
Peak memory 209448 kb
Host smart-eb2fd984-f46d-4caf-8c14-fe027314d094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263693832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.4263693832
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.557646833
Short name T433
Test name
Test status
Simulation time 873565270 ps
CPU time 2.78 seconds
Started Aug 19 06:05:18 PM PDT 24
Finished Aug 19 06:05:20 PM PDT 24
Peak memory 199888 kb
Host smart-c07e48f4-857f-4b16-afca-cd17f86ec1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557646833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.557646833
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3217331800
Short name T44
Test name
Test status
Simulation time 3803841944 ps
CPU time 6.03 seconds
Started Aug 19 06:05:19 PM PDT 24
Finished Aug 19 06:05:25 PM PDT 24
Peak memory 199496 kb
Host smart-9e4f8311-2fb3-44d1-9e4a-345e40079bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217331800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3217331800
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.4273830257
Short name T48
Test name
Test status
Simulation time 4803678616 ps
CPU time 23.8 seconds
Started Aug 19 06:08:27 PM PDT 24
Finished Aug 19 06:08:51 PM PDT 24
Peak memory 209220 kb
Host smart-b9f1da0a-ce60-45ef-8154-5e240f92824e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273830257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.4273830257
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3238991658
Short name T1176
Test name
Test status
Simulation time 1046424975 ps
CPU time 20.02 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:08:52 PM PDT 24
Peak memory 200968 kb
Host smart-c4cd2874-f514-46e1-93f8-418a2629aae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238991658 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3238991658
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2884731149
Short name T1023
Test name
Test status
Simulation time 34910419645 ps
CPU time 25.21 seconds
Started Aug 19 06:08:34 PM PDT 24
Finished Aug 19 06:08:59 PM PDT 24
Peak memory 200980 kb
Host smart-30b2878b-cc3e-45ab-8fa9-35f95ceb25b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884731149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2884731149
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.421654649
Short name T285
Test name
Test status
Simulation time 1847530215 ps
CPU time 40.93 seconds
Started Aug 19 06:08:33 PM PDT 24
Finished Aug 19 06:09:14 PM PDT 24
Peak memory 201200 kb
Host smart-e5639bf5-6d16-4387-a97d-4f4acd5f40e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421654649 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.421654649
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3375537288
Short name T301
Test name
Test status
Simulation time 24293824035 ps
CPU time 25.3 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:08:57 PM PDT 24
Peak memory 200756 kb
Host smart-dc9dc6be-828d-4740-be20-af8c22c8c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375537288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3375537288
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2547895553
Short name T862
Test name
Test status
Simulation time 4463261316 ps
CPU time 80.03 seconds
Started Aug 19 06:08:31 PM PDT 24
Finished Aug 19 06:09:51 PM PDT 24
Peak memory 217180 kb
Host smart-157c8f15-6690-4193-9a91-f5dddd4b5e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547895553 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2547895553
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1785081640
Short name T208
Test name
Test status
Simulation time 20038372430 ps
CPU time 9.48 seconds
Started Aug 19 06:08:29 PM PDT 24
Finished Aug 19 06:08:38 PM PDT 24
Peak memory 200872 kb
Host smart-f7173461-66b0-4b4c-9807-75a42137d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785081640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1785081640
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3094288420
Short name T572
Test name
Test status
Simulation time 3099979078 ps
CPU time 29.49 seconds
Started Aug 19 06:08:35 PM PDT 24
Finished Aug 19 06:09:05 PM PDT 24
Peak memory 216520 kb
Host smart-56a4c4db-b060-48fa-aa71-7c0eb83998fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094288420 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3094288420
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1299248494
Short name T854
Test name
Test status
Simulation time 17101660105 ps
CPU time 14.96 seconds
Started Aug 19 06:08:34 PM PDT 24
Finished Aug 19 06:08:49 PM PDT 24
Peak memory 200752 kb
Host smart-e7d34c3c-556c-4511-b393-88a048f5cbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299248494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1299248494
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1316616745
Short name T457
Test name
Test status
Simulation time 1636737496 ps
CPU time 26.29 seconds
Started Aug 19 06:08:31 PM PDT 24
Finished Aug 19 06:08:58 PM PDT 24
Peak memory 200952 kb
Host smart-506d3ce6-e5ec-456d-9b26-ce2a350cbc69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316616745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1316616745
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1865911998
Short name T952
Test name
Test status
Simulation time 260337616614 ps
CPU time 108.75 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:10:20 PM PDT 24
Peak memory 200988 kb
Host smart-86422e44-f3db-4e21-843d-4c68dfb9228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865911998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1865911998
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2313027955
Short name T475
Test name
Test status
Simulation time 2703234429 ps
CPU time 53.71 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:09:26 PM PDT 24
Peak memory 217584 kb
Host smart-0162011e-b996-4244-9649-644c8750174b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313027955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2313027955
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1507725187
Short name T231
Test name
Test status
Simulation time 113954158927 ps
CPU time 234.51 seconds
Started Aug 19 06:08:33 PM PDT 24
Finished Aug 19 06:12:28 PM PDT 24
Peak memory 200924 kb
Host smart-3c467ca8-4c35-472f-951d-38dcedfe459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507725187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1507725187
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.148478621
Short name T88
Test name
Test status
Simulation time 2879657376 ps
CPU time 38.55 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:09:11 PM PDT 24
Peak memory 209220 kb
Host smart-d94fbd51-a2ab-423a-949b-a78276e4e0a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148478621 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.148478621
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.516941629
Short name T577
Test name
Test status
Simulation time 13703319519 ps
CPU time 38.98 seconds
Started Aug 19 06:08:35 PM PDT 24
Finished Aug 19 06:09:14 PM PDT 24
Peak memory 200960 kb
Host smart-33f3e91e-78fa-43e4-8006-cac114b5e645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516941629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.516941629
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.615346679
Short name T580
Test name
Test status
Simulation time 3541553490 ps
CPU time 21.9 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:08:54 PM PDT 24
Peak memory 209564 kb
Host smart-24f03f81-f23f-4261-bd44-ebbd5a299135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615346679 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.615346679
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2036380232
Short name T25
Test name
Test status
Simulation time 16101864 ps
CPU time 0.58 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:28 PM PDT 24
Peak memory 196264 kb
Host smart-e3872800-b0c5-41b5-a909-8f387a940a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036380232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2036380232
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.559094891
Short name T502
Test name
Test status
Simulation time 34659919713 ps
CPU time 12.43 seconds
Started Aug 19 06:05:25 PM PDT 24
Finished Aug 19 06:05:38 PM PDT 24
Peak memory 200888 kb
Host smart-a5c2d2ab-be12-4b42-ad2b-c9e53a2e1ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559094891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.559094891
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2227083681
Short name T622
Test name
Test status
Simulation time 160063924927 ps
CPU time 362.41 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:11:30 PM PDT 24
Peak memory 200924 kb
Host smart-227fedd1-39b8-4255-826e-359306b2d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227083681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2227083681
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4003847192
Short name T464
Test name
Test status
Simulation time 29441583899 ps
CPU time 40.72 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:06:08 PM PDT 24
Peak memory 200436 kb
Host smart-9630fee5-b855-4f56-8b9c-7bedfafcdf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003847192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4003847192
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3381298669
Short name T591
Test name
Test status
Simulation time 61653200839 ps
CPU time 29.59 seconds
Started Aug 19 06:05:30 PM PDT 24
Finished Aug 19 06:05:59 PM PDT 24
Peak memory 200840 kb
Host smart-e8a8dbd4-123f-4373-8d1b-8fec12959454
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381298669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3381298669
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2287321022
Short name T1155
Test name
Test status
Simulation time 51656681947 ps
CPU time 230.09 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:09:17 PM PDT 24
Peak memory 200984 kb
Host smart-c1fb28cb-2f44-4d6b-b92b-43bb5f93697d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287321022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2287321022
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.315297575
Short name T1035
Test name
Test status
Simulation time 7007000644 ps
CPU time 6.05 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:35 PM PDT 24
Peak memory 200288 kb
Host smart-90019362-0251-49f0-8e39-2ff4fc8c16a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315297575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.315297575
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3204335443
Short name T1022
Test name
Test status
Simulation time 20603057146 ps
CPU time 15.87 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:43 PM PDT 24
Peak memory 201148 kb
Host smart-fd563554-1959-49a1-819b-fda2f15acdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204335443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3204335443
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1850013531
Short name T820
Test name
Test status
Simulation time 22524089699 ps
CPU time 280.49 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:10:09 PM PDT 24
Peak memory 200976 kb
Host smart-df641d94-bf06-4d61-84b5-87c858076c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850013531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1850013531
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1289508327
Short name T1028
Test name
Test status
Simulation time 6231115517 ps
CPU time 22.41 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:05:49 PM PDT 24
Peak memory 199312 kb
Host smart-2265ecfd-4c42-445c-b145-38b6d3b9cc06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289508327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1289508327
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3517356941
Short name T247
Test name
Test status
Simulation time 164000071174 ps
CPU time 171.05 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:08:17 PM PDT 24
Peak memory 200996 kb
Host smart-f06d08e8-3986-4746-8560-2f917ad2755e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517356941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3517356941
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1225703107
Short name T556
Test name
Test status
Simulation time 5556743612 ps
CPU time 1.91 seconds
Started Aug 19 06:05:28 PM PDT 24
Finished Aug 19 06:05:30 PM PDT 24
Peak memory 197464 kb
Host smart-5fb1868d-27fa-4c65-af3d-1dd6d4352df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225703107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1225703107
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1806998812
Short name T791
Test name
Test status
Simulation time 275167797 ps
CPU time 0.94 seconds
Started Aug 19 06:05:20 PM PDT 24
Finished Aug 19 06:05:21 PM PDT 24
Peak memory 199376 kb
Host smart-2e1036db-be53-4adb-8621-34b5f1316590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806998812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1806998812
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3219716135
Short name T271
Test name
Test status
Simulation time 50826913393 ps
CPU time 22.16 seconds
Started Aug 19 06:05:26 PM PDT 24
Finished Aug 19 06:05:48 PM PDT 24
Peak memory 200804 kb
Host smart-a0d87a85-e2f0-4dfd-8d15-6bc4522d6817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219716135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3219716135
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.709300774
Short name T946
Test name
Test status
Simulation time 12065240060 ps
CPU time 29.67 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:57 PM PDT 24
Peak memory 209840 kb
Host smart-fd947e97-408d-49b0-a0cf-350e8a673e19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709300774 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.709300774
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1076004117
Short name T1098
Test name
Test status
Simulation time 7361735093 ps
CPU time 13.17 seconds
Started Aug 19 06:05:27 PM PDT 24
Finished Aug 19 06:05:40 PM PDT 24
Peak memory 200900 kb
Host smart-e64d0e55-bd9e-478f-94d9-84604b3fefa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076004117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1076004117
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.854758173
Short name T783
Test name
Test status
Simulation time 57395494006 ps
CPU time 21.56 seconds
Started Aug 19 06:05:18 PM PDT 24
Finished Aug 19 06:05:39 PM PDT 24
Peak memory 201012 kb
Host smart-066d22cf-652c-4a28-8a50-aa49c9ca82d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854758173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.854758173
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.952647752
Short name T228
Test name
Test status
Simulation time 192629087554 ps
CPU time 62.49 seconds
Started Aug 19 06:08:31 PM PDT 24
Finished Aug 19 06:09:34 PM PDT 24
Peak memory 200940 kb
Host smart-8323acba-e24e-4a0e-8572-a4be12385a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952647752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.952647752
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2341256536
Short name T304
Test name
Test status
Simulation time 6201910572 ps
CPU time 22.06 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:08:54 PM PDT 24
Peak memory 217396 kb
Host smart-b7a7cffe-8540-4d7d-ad73-90a6e7626b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341256536 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2341256536
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3644900263
Short name T5
Test name
Test status
Simulation time 25781773742 ps
CPU time 10.67 seconds
Started Aug 19 06:08:35 PM PDT 24
Finished Aug 19 06:08:46 PM PDT 24
Peak memory 200776 kb
Host smart-fe495e65-822a-4cfc-a211-9ddea16c5403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644900263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3644900263
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3220786023
Short name T485
Test name
Test status
Simulation time 17694233161 ps
CPU time 61.63 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:09:33 PM PDT 24
Peak memory 216632 kb
Host smart-fe44b86a-25d1-4c77-a04f-3a47f4e47b3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220786023 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3220786023
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.972307491
Short name T113
Test name
Test status
Simulation time 66041394200 ps
CPU time 25.61 seconds
Started Aug 19 06:08:35 PM PDT 24
Finished Aug 19 06:09:00 PM PDT 24
Peak memory 200908 kb
Host smart-dbb52c4e-5421-4526-864f-451d25858b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972307491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.972307491
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1047630885
Short name T1050
Test name
Test status
Simulation time 3623475680 ps
CPU time 44.65 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:09:17 PM PDT 24
Peak memory 217420 kb
Host smart-f0e716d6-4508-4ece-ac4b-273ab285e2d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047630885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1047630885
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1752433661
Short name T560
Test name
Test status
Simulation time 34742188649 ps
CPU time 121.93 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:10:34 PM PDT 24
Peak memory 200892 kb
Host smart-60d1d095-5a39-4fdd-8413-38185964414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752433661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1752433661
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.61851614
Short name T106
Test name
Test status
Simulation time 9586163372 ps
CPU time 32.19 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:09:04 PM PDT 24
Peak memory 209256 kb
Host smart-2be107c5-2350-4a51-b15a-1ec140cadcd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61851614 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.61851614
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.846469929
Short name T182
Test name
Test status
Simulation time 12335203873 ps
CPU time 20.21 seconds
Started Aug 19 06:08:33 PM PDT 24
Finished Aug 19 06:08:53 PM PDT 24
Peak memory 200892 kb
Host smart-6da7c3bf-8d28-4926-ae06-a498c4021d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846469929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.846469929
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.931494322
Short name T743
Test name
Test status
Simulation time 3445984976 ps
CPU time 99.46 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:10:12 PM PDT 24
Peak memory 217432 kb
Host smart-e30ac818-932c-4534-ad34-a9e836111882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931494322 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.931494322
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3606116523
Short name T665
Test name
Test status
Simulation time 33396136002 ps
CPU time 24.77 seconds
Started Aug 19 06:08:35 PM PDT 24
Finished Aug 19 06:09:00 PM PDT 24
Peak memory 200968 kb
Host smart-0b35b2a1-93b7-4e8c-81b6-1dd50842b4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606116523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3606116523
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.277276116
Short name T998
Test name
Test status
Simulation time 3305900237 ps
CPU time 35.78 seconds
Started Aug 19 06:08:34 PM PDT 24
Finished Aug 19 06:09:10 PM PDT 24
Peak memory 209164 kb
Host smart-f6f37d34-f9f2-4ac4-819d-5f7f7ec157bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277276116 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.277276116
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2578331070
Short name T887
Test name
Test status
Simulation time 24269516542 ps
CPU time 13.78 seconds
Started Aug 19 06:08:31 PM PDT 24
Finished Aug 19 06:08:45 PM PDT 24
Peak memory 200912 kb
Host smart-408d0559-c579-47a6-8a26-3ebe055a5851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578331070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2578331070
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3001375286
Short name T598
Test name
Test status
Simulation time 4846764479 ps
CPU time 60.67 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:09:33 PM PDT 24
Peak memory 209244 kb
Host smart-fc26c9b0-c8dc-48cc-82fd-bc326876f9ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001375286 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3001375286
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3487987969
Short name T611
Test name
Test status
Simulation time 34094850261 ps
CPU time 30.3 seconds
Started Aug 19 06:08:32 PM PDT 24
Finished Aug 19 06:09:02 PM PDT 24
Peak memory 200968 kb
Host smart-df0dcbcc-ae87-4f8c-9bd3-39e317298a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487987969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3487987969
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3039916405
Short name T914
Test name
Test status
Simulation time 31761222114 ps
CPU time 47.46 seconds
Started Aug 19 06:08:30 PM PDT 24
Finished Aug 19 06:09:18 PM PDT 24
Peak memory 217560 kb
Host smart-7d18040c-1219-45e7-aff8-d002a30504a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039916405 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3039916405
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1343180759
Short name T134
Test name
Test status
Simulation time 13747849659 ps
CPU time 6.67 seconds
Started Aug 19 06:08:33 PM PDT 24
Finished Aug 19 06:08:40 PM PDT 24
Peak memory 200984 kb
Host smart-72c7f876-837a-4c9b-a454-5e8004910c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343180759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1343180759
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1741793329
Short name T249
Test name
Test status
Simulation time 21436489336 ps
CPU time 97.73 seconds
Started Aug 19 06:08:42 PM PDT 24
Finished Aug 19 06:10:20 PM PDT 24
Peak memory 212164 kb
Host smart-497711c4-8ecf-42f9-a7e3-7a0470717b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741793329 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1741793329
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4235330993
Short name T380
Test name
Test status
Simulation time 79323430049 ps
CPU time 22.4 seconds
Started Aug 19 06:08:41 PM PDT 24
Finished Aug 19 06:09:04 PM PDT 24
Peak memory 199780 kb
Host smart-4cddeac4-79b4-4ba1-a730-152e314d332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235330993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4235330993
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1414607509
Short name T964
Test name
Test status
Simulation time 10324199471 ps
CPU time 63.95 seconds
Started Aug 19 06:08:40 PM PDT 24
Finished Aug 19 06:09:44 PM PDT 24
Peak memory 210524 kb
Host smart-3259f332-2afd-4f99-84ac-80aea4927592
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414607509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1414607509
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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