Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	86030	1			T1	2		T2	7		T3	1
all_values[1]	86030	1			T1	2		T2	7		T3	1
all_values[2]	86030	1			T1	2		T2	7		T3	1
all_values[3]	86030	1			T1	2		T2	7		T3	1
all_values[4]	86030	1			T1	2		T2	7		T3	1
all_values[5]	86030	1			T1	2		T2	7		T3	1
all_values[6]	86030	1			T1	2		T2	7		T3	1
all_values[7]	86030	1			T1	2		T2	7		T3	1
all_values[8]	86030	1			T1	2		T2	7		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

398817

1

T1

18

T2

56

T3

4

auto[1]

375453

1

T2

7

T3

5

T4

156

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

698949

1

T1

13

T2

59

T3

7

auto[1]

75321

1

T1

5

T2

4

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	23398	1			T2	5		T11	3		T13	1
all_values[0]	auto[0]	auto[1]	19552	1			T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[0]	25563	1			T4	3		T11	10		T27	5
all_values[0]	auto[1]	auto[1]	17517	1			T4	23		T5	3		T6	5
all_values[1]	auto[0]	auto[0]	40214	1			T1	2		T2	7		T5	3
all_values[1]	auto[0]	auto[1]	1417	1			T16	1		T14	20		T89	1
all_values[1]	auto[1]	auto[0]	43041	1			T3	1		T4	15		T6	1
all_values[1]	auto[1]	auto[1]	1358	1			T4	11		T16	1		T19	38
all_values[2]	auto[0]	auto[0]	41139	1			T1	1		T2	7		T6	1
all_values[2]	auto[0]	auto[1]	2395	1			T1	1		T7	1		T11	8
all_values[2]	auto[1]	auto[0]	40335	1			T3	1		T4	26		T5	1
all_values[2]	auto[1]	auto[1]	2161	1			T5	2		T6	2		T13	1
all_values[3]	auto[0]	auto[0]	46234	1			T1	2		T4	24		T5	3
all_values[3]	auto[0]	auto[1]	251	1			T4	2		T14	3		T18	1
all_values[3]	auto[1]	auto[0]	39287	1			T2	7		T3	1		T6	1
all_values[3]	auto[1]	auto[1]	258	1			T16	5		T15	1		T19	1
all_values[4]	auto[0]	auto[0]	46400	1			T1	2		T2	7		T4	24
all_values[4]	auto[0]	auto[1]	331	1			T4	2		T16	5		T19	3
all_values[4]	auto[1]	auto[0]	38953	1			T3	1		T5	3		T6	1
all_values[4]	auto[1]	auto[1]	346	1			T16	2		T18	1		T19	3
all_values[5]	auto[0]	auto[0]	43900	1			T1	2		T2	7		T3	1
all_values[5]	auto[0]	auto[1]	147	1			T16	2		T35	1		T38	3
all_values[5]	auto[1]	auto[0]	41822	1			T4	26		T6	5		T8	1
all_values[5]	auto[1]	auto[1]	161	1			T16	1		T18	2		T34	1
all_values[6]	auto[0]	auto[0]	42992	1			T1	2		T2	7		T5	3
all_values[6]	auto[0]	auto[1]	161	1			T16	1		T34	1		T36	1
all_values[6]	auto[1]	auto[0]	42726	1			T3	1		T4	26		T6	1
all_values[6]	auto[1]	auto[1]	151	1			T16	1		T34	1		T35	2
all_values[7]	auto[0]	auto[0]	45523	1			T1	2		T2	7		T3	1
all_values[7]	auto[0]	auto[1]	289	1			T18	2		T19	8		T34	1
all_values[7]	auto[1]	auto[0]	39899	1			T4	24		T5	3		T11	25
all_values[7]	auto[1]	auto[1]	319	1			T4	2		T20	6		T101	8
all_values[8]	auto[0]	auto[0]	29597	1			T2	5		T4	6		T11	8
all_values[8]	auto[0]	auto[1]	14877	1			T1	2		T2	2		T3	1
all_values[8]	auto[1]	auto[0]	27926	1			T11	17		T13	1		T27	2
all_values[8]	auto[1]	auto[1]	13630	1			T6	5		T8	1		T11	3