Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2541

1

T1

1

T2

1

T3

1

auto[UartRx]

2541

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4435	1			T1	2		T2	2		T3	2
values[1]	42	1			T16	1		T18	2		T34	2
values[2]	50	1			T16	1		T26	2		T33	1
values[3]	57	1			T16	1		T18	1		T33	1
values[4]	49	1			T37	1		T39	2		T135	1
values[5]	61	1			T16	1		T35	1		T36	3
values[6]	56	1			T16	1		T26	1		T35	2
values[7]	61	1			T16	2		T26	1		T34	1
values[8]	70	1			T36	1		T38	1		T135	1
values[9]	74	1			T16	2		T35	1		T36	2
values[10]	80	1			T16	2		T26	1		T33	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2312	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	12	1			T18	1		T402	1		T403	1
auto[UartTx]	values[2]	19	1			T26	1		T80	1		T391	1
auto[UartTx]	values[3]	16	1			T16	1		T18	1		T33	1
auto[UartTx]	values[4]	16	1			T37	1		T311	1		T82	1
auto[UartTx]	values[5]	25	1			T39	1		T110	1		T404	1
auto[UartTx]	values[6]	25	1			T39	1		T405	1		T406	1
auto[UartTx]	values[7]	24	1			T16	2		T35	1		T135	1
auto[UartTx]	values[8]	26	1			T38	1		T110	1		T397	1
auto[UartTx]	values[9]	25	1			T36	1		T38	1		T39	1
auto[UartTx]	values[10]	32	1			T16	1		T36	1		T110	1
auto[UartRx]	values[0]	2123	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	30	1			T16	1		T18	1		T34	2
auto[UartRx]	values[2]	31	1			T16	1		T26	1		T33	1
auto[UartRx]	values[3]	41	1			T37	1		T39	1		T80	2
auto[UartRx]	values[4]	33	1			T39	2		T135	1		T110	1
auto[UartRx]	values[5]	36	1			T16	1		T35	1		T36	3
auto[UartRx]	values[6]	31	1			T16	1		T26	1		T35	2
auto[UartRx]	values[7]	37	1			T26	1		T34	1		T110	1
auto[UartRx]	values[8]	44	1			T36	1		T135	1		T80	1
auto[UartRx]	values[9]	49	1			T16	2		T35	1		T36	1
auto[UartRx]	values[10]	48	1			T16	1		T26	1		T33	1