Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1975	1			T3	10		T5	1		T8	3
auto[BaudRate115200]	1615	1			T1	1		T5	1		T7	1
auto[BaudRate230400]	1492	1			T4	1		T5	1		T8	3
auto[BaudRate128Kbps]	1541	1			T1	1		T6	1		T7	1
auto[BaudRate256Kbps]	1774	1			T2	1		T5	1		T6	2
auto[BaudRate1Mbps]	1453	1			T6	1		T8	6		T11	2
auto[BaudRate1p5Mbps]	1145	1			T5	2		T6	1		T8	6

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1216	1			T5	6		T12	2		T17	20
freqs[25]	933	1			T11	9		T42	2		T45	2
freqs[48]	496	1			T78	2		T304	2		T119	10
freqs[50]	600	1			T27	5		T18	5		T20	1
freqs[100]	951	1			T6	5		T7	2		T8	36

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	212	1			T5	1		T12	1		T17	20
auto[BaudRate9600]	freqs[25]	149	1			T11	1		T326	1		T122	1
auto[BaudRate9600]	freqs[48]	64	1			T304	1		T407	3		T209	1
auto[BaudRate9600]	freqs[50]	100	1			T27	1		T408	12		T272	2
auto[BaudRate9600]	freqs[100]	144	1			T8	3		T309	2		T134	1
auto[BaudRate115200]	freqs[24]	203	1			T5	1		T14	1		T409	9
auto[BaudRate115200]	freqs[25]	123	1			T11	1		T45	1		T22	1
auto[BaudRate115200]	freqs[48]	75	1			T119	3		T108	2		T292	1
auto[BaudRate115200]	freqs[50]	87	1			T408	15		T37	2		T354	1
auto[BaudRate115200]	freqs[100]	149	1			T7	1		T8	9		T33	2
auto[BaudRate230400]	freqs[24]	172	1			T5	1		T44	1		T409	12
auto[BaudRate230400]	freqs[25]	120	1			T11	2		T326	1		T122	2
auto[BaudRate230400]	freqs[48]	67	1			T119	2		T108	1		T292	1
auto[BaudRate230400]	freqs[50]	74	1			T27	1		T408	6		T37	2
auto[BaudRate230400]	freqs[100]	117	1			T8	3		T21	1		T309	2
auto[BaudRate128Kbps]	freqs[24]	183	1			T14	4		T409	15		T113	2
auto[BaudRate128Kbps]	freqs[25]	135	1			T11	1		T45	1		T94	1
auto[BaudRate128Kbps]	freqs[48]	69	1			T78	1		T108	1		T339	2
auto[BaudRate128Kbps]	freqs[50]	79	1			T27	1		T20	1		T408	3
auto[BaudRate128Kbps]	freqs[100]	124	1			T6	1		T7	1		T8	9
auto[BaudRate256Kbps]	freqs[24]	178	1			T5	1		T44	1		T409	6
auto[BaudRate256Kbps]	freqs[25]	142	1			T11	1		T42	2		T122	1
auto[BaudRate256Kbps]	freqs[48]	75	1			T304	1		T119	2		T292	1
auto[BaudRate256Kbps]	freqs[50]	69	1			T18	1		T408	6		T272	1
auto[BaudRate256Kbps]	freqs[100]	151	1			T6	2		T33	3		T309	3
auto[BaudRate1Mbps]	freqs[24]	168	1			T409	12		T113	2		T273	1
auto[BaudRate1Mbps]	freqs[25]	177	1			T11	2		T94	1		T122	1
auto[BaudRate1Mbps]	freqs[48]	69	1			T78	1		T119	2		T292	2
auto[BaudRate1Mbps]	freqs[50]	76	1			T18	2		T408	3		T354	1
auto[BaudRate1Mbps]	freqs[100]	130	1			T6	1		T8	6		T33	2
auto[BaudRate1p5Mbps]	freqs[25]	87	1			T11	1		T94	1		T302	2
auto[BaudRate1p5Mbps]	freqs[48]	77	1			T119	1		T292	1		T407	4
auto[BaudRate1p5Mbps]	freqs[50]	115	1			T27	2		T18	2		T408	12
auto[BaudRate1p5Mbps]	freqs[100]	136	1			T6	1		T8	6		T33	5

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded