Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_break_err_cg

Group : uart_env_pkg::uart_env_cov::rx_break_err_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00

Variables for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_break_level	4	0	4	100.00	100	1	1	0

Summary for Variable cp_break_level

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_break_level

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	319	1			T16	3		T18	2		T19	2
all_levels[1]	12	1			T108	1		T374	1		T109	1
all_levels[2]	22	1			T22	2		T393	1		T37	1
all_levels[3]	26	1			T20	1		T109	2		T384	1