Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	1	66	98.51
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	1	64	98.46	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	1	64	98.46

User Defined Bins for cp_lvl

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_levels[62]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	22728121	1			T2	15		T3	1		T4	590
all_levels[1]	152355	1			T11	5		T13	1		T16	4
all_levels[2]	2050	1			T11	1		T13	1		T14	1
all_levels[3]	938	1			T14	3		T43	11		T15	1
all_levels[4]	580	1			T5	1		T11	2		T14	2
all_levels[5]	445	1			T6	1		T13	1		T14	1
all_levels[6]	367	1			T13	1		T14	2		T48	2
all_levels[7]	286	1			T14	2		T92	1		T112	1
all_levels[8]	251	1			T48	1		T112	1		T98	1
all_levels[9]	190	1			T11	2		T113	1		T112	1
all_levels[10]	210	1			T48	2		T93	1		T114	3
all_levels[11]	145	1			T48	1		T102	2		T98	1
all_levels[12]	156	1			T48	1		T112	2		T115	1
all_levels[13]	118	1			T6	1		T18	1		T102	1
all_levels[14]	112	1			T13	2		T14	1		T89	1
all_levels[15]	114	1			T48	2		T114	1		T116	1
all_levels[16]	100	1			T102	1		T114	1		T117	2
all_levels[17]	66	1			T99	1		T118	1		T119	1
all_levels[18]	74	1			T120	2		T107	1		T121	1
all_levels[19]	70	1			T48	1		T102	1		T115	1
all_levels[20]	58	1			T15	1		T122	1		T123	1
all_levels[21]	68	1			T116	2		T124	1		T125	1
all_levels[22]	65	1			T126	2		T127	1		T128	2
all_levels[23]	50	1			T48	1		T115	1		T101	1
all_levels[24]	60	1			T48	1		T92	1		T36	1
all_levels[25]	47	1			T15	1		T115	1		T100	2
all_levels[26]	42	1			T112	1		T129	1		T130	1
all_levels[27]	47	1			T131	1		T93	1		T100	1
all_levels[28]	48	1			T131	1		T116	1		T132	1
all_levels[29]	32	1			T13	1		T129	1		T133	1
all_levels[30]	39	1			T18	1		T112	2		T134	1
all_levels[31]	36	1			T13	1		T101	1		T129	1
all_levels[32]	26	1			T116	1		T124	1		T104	1
all_levels[33]	31	1			T116	1		T99	1		T104	1
all_levels[34]	32	1			T100	1		T135	1		T136	1
all_levels[35]	24	1			T133	1		T125	1		T137	1
all_levels[36]	15	1			T102	1		T138	1		T139	2
all_levels[37]	15	1			T102	1		T140	1		T141	1
all_levels[38]	21	1			T105	1		T138	1		T142	1
all_levels[39]	12	1			T143	1		T144	1		T145	1
all_levels[40]	12	1			T146	1		T147	1		T139	1
all_levels[41]	25	1			T140	2		T148	1		T149	1
all_levels[42]	11	1			T14	1		T150	1		T105	1
all_levels[43]	12	1			T104	1		T121	1		T144	1
all_levels[44]	23	1			T100	1		T119	2		T151	1
all_levels[45]	14	1			T102	1		T100	1		T152	1
all_levels[46]	14	1			T14	1		T119	1		T153	1
all_levels[47]	14	1			T101	1		T106	2		T154	2
all_levels[48]	16	1			T6	1		T155	3		T156	1
all_levels[49]	12	1			T148	1		T142	2		T144	1
all_levels[50]	12	1			T127	1		T157	1		T158	1
all_levels[51]	4	1			T105	1		T159	1		T160	1
all_levels[52]	16	1			T93	1		T107	2		T161	1
all_levels[53]	13	1			T117	1		T119	2		T162	1
all_levels[54]	11	1			T123	1		T133	1		T105	1
all_levels[55]	7	1			T123	1		T105	1		T163	1
all_levels[56]	12	1			T144	1		T145	1		T164	1
all_levels[57]	14	1			T165	1		T164	1		T166	1
all_levels[58]	7	1			T90	1		T167	1		T168	2
all_levels[59]	3	1			T90	1		T121	1		T169	1
all_levels[60]	2	1			T170	1		T171	1		-	-
all_levels[61]	6	1			T115	1		T161	1		T139	1
all_levels[63]	5	1			T15	1		T172	1		T173	1
all_levels[64]	84	1			T14	2		T15	2		T131	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22884053

1

T2

15

T4

581

T5

19

auto[1]

3812

1

T3

1

T4

9

T6

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Element holes

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[62]]	*	--	--	2

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[59] , all_levels[60]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	22724750	1			T2	15		T4	581		T5	18
all_levels[0]	auto[1]	3371	1			T3	1		T4	9		T6	4
all_levels[1]	auto[0]	152287	1			T11	5		T13	1		T16	4
all_levels[1]	auto[1]	68	1			T174	2		T142	1		T155	1
all_levels[2]	auto[0]	2017	1			T11	1		T13	1		T14	1
all_levels[2]	auto[1]	33	1			T175	1		T106	2		T144	3
all_levels[3]	auto[0]	908	1			T14	1		T43	11		T15	1
all_levels[3]	auto[1]	30	1			T14	2		T176	1		T177	3
all_levels[4]	auto[0]	568	1			T5	1		T11	2		T14	2
all_levels[4]	auto[1]	12	1			T122	2		T178	1		T155	1
all_levels[5]	auto[0]	417	1			T6	1		T13	1		T14	1
all_levels[5]	auto[1]	28	1			T106	2		T179	1		T180	1
all_levels[6]	auto[0]	349	1			T13	1		T14	2		T48	2
all_levels[6]	auto[1]	18	1			T181	1		T182	1		T183	2
all_levels[7]	auto[0]	279	1			T14	2		T92	1		T112	1
all_levels[7]	auto[1]	7	1			T175	1		T184	2		T185	1
all_levels[8]	auto[0]	235	1			T48	1		T112	1		T98	1
all_levels[8]	auto[1]	16	1			T183	1		T186	3		T187	1
all_levels[9]	auto[0]	180	1			T11	2		T113	1		T112	1
all_levels[9]	auto[1]	10	1			T188	1		T189	2		T190	1
all_levels[10]	auto[0]	204	1			T48	2		T93	1		T114	3
all_levels[10]	auto[1]	6	1			T191	1		T192	1		T193	1
all_levels[11]	auto[0]	136	1			T48	1		T102	2		T98	1
all_levels[11]	auto[1]	9	1			T107	1		T194	2		T195	1
all_levels[12]	auto[0]	146	1			T48	1		T112	1		T115	1
all_levels[12]	auto[1]	10	1			T112	1		T196	1		T197	1
all_levels[13]	auto[0]	111	1			T6	1		T18	1		T102	1
all_levels[13]	auto[1]	7	1			T198	2		T199	1		T200	1
all_levels[14]	auto[0]	107	1			T13	2		T14	1		T89	1
all_levels[14]	auto[1]	5	1			T178	3		T201	1		T202	1
all_levels[15]	auto[0]	108	1			T48	2		T114	1		T116	1
all_levels[15]	auto[1]	6	1			T203	1		T204	1		T205	1
all_levels[16]	auto[0]	88	1			T102	1		T114	1		T117	2
all_levels[16]	auto[1]	12	1			T206	3		T168	1		T207	2
all_levels[17]	auto[0]	61	1			T99	1		T118	1		T119	1
all_levels[17]	auto[1]	5	1			T107	1		T164	1		T208	1
all_levels[18]	auto[0]	63	1			T120	1		T107	1		T121	1
all_levels[18]	auto[1]	11	1			T120	1		T142	1		T164	1
all_levels[19]	auto[0]	62	1			T48	1		T102	1		T115	1
all_levels[19]	auto[1]	8	1			T209	1		T210	1		T211	1
all_levels[20]	auto[0]	54	1			T15	1		T122	1		T123	1
all_levels[20]	auto[1]	4	1			T212	1		T213	1		T214	1
all_levels[21]	auto[0]	60	1			T116	2		T124	1		T125	1
all_levels[21]	auto[1]	8	1			T215	1		T216	4		T217	1
all_levels[22]	auto[0]	60	1			T126	2		T127	1		T128	2
all_levels[22]	auto[1]	5	1			T177	2		T218	1		T219	2
all_levels[23]	auto[0]	44	1			T48	1		T115	1		T101	1
all_levels[23]	auto[1]	6	1			T220	3		T212	1		T221	1
all_levels[24]	auto[0]	53	1			T48	1		T92	1		T36	1
all_levels[24]	auto[1]	7	1			T222	1		T223	1		T224	2
all_levels[25]	auto[0]	43	1			T15	1		T115	1		T100	2
all_levels[25]	auto[1]	4	1			T225	2		T226	1		T227	1
all_levels[26]	auto[0]	35	1			T112	1		T129	1		T130	1
all_levels[26]	auto[1]	7	1			T228	1		T229	5		T230	1
all_levels[27]	auto[0]	44	1			T131	1		T93	1		T100	1
all_levels[27]	auto[1]	3	1			T231	1		T232	1		T233	1
all_levels[28]	auto[0]	40	1			T131	1		T116	1		T132	1
all_levels[28]	auto[1]	8	1			T234	1		T235	6		T236	1
all_levels[29]	auto[0]	27	1			T13	1		T129	1		T133	1
all_levels[29]	auto[1]	5	1			T237	2		T238	1		T239	2
all_levels[30]	auto[0]	37	1			T18	1		T112	1		T134	1
all_levels[30]	auto[1]	2	1			T112	1		T240	1		-	-
all_levels[31]	auto[0]	33	1			T13	1		T101	1		T129	1
all_levels[31]	auto[1]	3	1			T191	1		T223	1		T241	1
all_levels[32]	auto[0]	24	1			T116	1		T124	1		T104	1
all_levels[32]	auto[1]	2	1			T242	1		T243	1		-	-
all_levels[33]	auto[0]	30	1			T116	1		T99	1		T104	1
all_levels[33]	auto[1]	1	1			T200	1		-	-		-	-
all_levels[34]	auto[0]	29	1			T100	1		T135	1		T136	1
all_levels[34]	auto[1]	3	1			T174	1		T244	1		T245	1
all_levels[35]	auto[0]	21	1			T133	1		T125	1		T137	1
all_levels[35]	auto[1]	3	1			T246	1		T219	1		T247	1
all_levels[36]	auto[0]	15	1			T102	1		T138	1		T139	2
all_levels[37]	auto[0]	14	1			T102	1		T140	1		T141	1
all_levels[37]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[38]	auto[0]	18	1			T105	1		T138	1		T142	1
all_levels[38]	auto[1]	3	1			T168	1		T249	2		-	-
all_levels[39]	auto[0]	12	1			T143	1		T144	1		T145	1
all_levels[40]	auto[0]	11	1			T146	1		T147	1		T139	1
all_levels[40]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[41]	auto[0]	20	1			T140	2		T148	1		T149	1
all_levels[41]	auto[1]	5	1			T237	1		T251	1		T245	3
all_levels[42]	auto[0]	9	1			T14	1		T150	1		T105	1
all_levels[42]	auto[1]	2	1			T252	2		-	-		-	-
all_levels[43]	auto[0]	10	1			T104	1		T121	1		T144	1
all_levels[43]	auto[1]	2	1			T253	1		T254	1		-	-
all_levels[44]	auto[0]	19	1			T100	1		T119	2		T151	1
all_levels[44]	auto[1]	4	1			T255	1		T159	1		T256	1
all_levels[45]	auto[0]	13	1			T102	1		T100	1		T152	1
all_levels[45]	auto[1]	1	1			T257	1		-	-		-	-
all_levels[46]	auto[0]	11	1			T14	1		T119	1		T153	1
all_levels[46]	auto[1]	3	1			T144	1		T204	2		-	-
all_levels[47]	auto[0]	11	1			T101	1		T106	1		T154	1
all_levels[47]	auto[1]	3	1			T106	1		T154	1		T160	1
all_levels[48]	auto[0]	13	1			T6	1		T155	1		T156	1
all_levels[48]	auto[1]	3	1			T155	2		T205	1		-	-
all_levels[49]	auto[0]	10	1			T148	1		T142	1		T144	1
all_levels[49]	auto[1]	2	1			T142	1		T258	1		-	-
all_levels[50]	auto[0]	8	1			T127	1		T157	1		T158	1
all_levels[50]	auto[1]	4	1			T259	3		T260	1		-	-
all_levels[51]	auto[0]	4	1			T105	1		T159	1		T160	1
all_levels[52]	auto[0]	12	1			T93	1		T107	1		T161	1
all_levels[52]	auto[1]	4	1			T107	1		T254	3		-	-
all_levels[53]	auto[0]	11	1			T117	1		T119	2		T162	1
all_levels[53]	auto[1]	2	1			T261	1		T221	1		-	-
all_levels[54]	auto[0]	10	1			T123	1		T133	1		T105	1
all_levels[54]	auto[1]	1	1			T222	1		-	-		-	-
all_levels[55]	auto[0]	7	1			T123	1		T105	1		T163	1
all_levels[56]	auto[0]	9	1			T144	1		T145	1		T164	1
all_levels[56]	auto[1]	3	1			T262	2		T263	1		-	-
all_levels[57]	auto[0]	8	1			T165	1		T164	1		T166	1
all_levels[57]	auto[1]	6	1			T264	4		T265	2		-	-
all_levels[58]	auto[0]	5	1			T90	1		T167	1		T168	1
all_levels[58]	auto[1]	2	1			T168	1		T266	1		-	-
all_levels[59]	auto[0]	3	1			T90	1		T121	1		T169	1
all_levels[60]	auto[0]	2	1			T170	1		T171	1		-	-
all_levels[61]	auto[0]	5	1			T115	1		T161	1		T139	1
all_levels[61]	auto[1]	1	1			T246	1		-	-		-	-
all_levels[63]	auto[0]	5	1			T15	1		T172	1		T173	1
all_levels[64]	auto[0]	68	1			T14	1		T15	2		T131	1
all_levels[64]	auto[1]	16	1			T14	1		T154	2		T267	1