Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_watermark_cg

Group : uart_env_pkg::uart_env_cov::rx_watermark_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_watermark_lvl	8	1	7	87.50	100	1	1	0

Summary for Variable cp_watermark_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_watermark_lvl

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_levels[7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	1276	1			T16	2		T47	1		T48	4
all_levels[1]	591	1			T19	38		T98	1		T99	2
all_levels[2]	327	1			T4	11		T100	4		T101	7
all_levels[3]	288	1			T102	10		T103	14		T104	16
all_levels[4]	179	1			T105	1		T106	7		T107	8
all_levels[5]	66	1			T14	20		T20	4		T35	6
all_levels[6]	40	1			T22	4		T108	4		T109	8