Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	86030	1			T1	2		T2	7		T3	1
all_pins[1]	86030	1			T1	2		T2	7		T3	1
all_pins[2]	86030	1			T1	2		T2	7		T3	1
all_pins[3]	86030	1			T1	2		T2	7		T3	1
all_pins[4]	86030	1			T1	2		T2	7		T3	1
all_pins[5]	86030	1			T1	2		T2	7		T3	1
all_pins[6]	86030	1			T1	2		T2	7		T3	1
all_pins[7]	86030	1			T1	2		T2	7		T3	1
all_pins[8]	86030	1			T1	2		T2	7		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	737575	1			T1	18		T2	63		T3	9
values[0x1]	36695	1			T4	38		T5	5		T6	12
transitions[0x0=>0x1]	29196	1			T4	27		T5	5		T6	8
transitions[0x1=>0x0]	29012	1			T4	26		T5	4		T6	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	68457	1			T1	2		T2	7		T3	1
all_pins[0]	values[0x1]	17573	1			T4	24		T5	3		T6	5
all_pins[0]	transitions[0x0=>0x1]	17048	1			T4	13		T5	3		T6	5
all_pins[0]	transitions[0x1=>0x0]	830	1			T16	1		T19	17		T47	1
all_pins[1]	values[0x0]	84675	1			T1	2		T2	7		T3	1
all_pins[1]	values[0x1]	1355	1			T4	11		T16	1		T19	38
all_pins[1]	transitions[0x0=>0x1]	1277	1			T4	11		T16	1		T19	38
all_pins[1]	transitions[0x1=>0x0]	2131	1			T4	1		T5	2		T6	2
all_pins[2]	values[0x0]	83821	1			T1	2		T2	7		T3	1
all_pins[2]	values[0x1]	2209	1			T4	1		T5	2		T6	2
all_pins[2]	transitions[0x0=>0x1]	2150	1			T4	1		T5	2		T6	2
all_pins[2]	transitions[0x1=>0x0]	199	1			T16	5		T15	1		T19	1
all_pins[3]	values[0x0]	85772	1			T1	2		T2	7		T3	1
all_pins[3]	values[0x1]	258	1			T16	5		T15	1		T19	1
all_pins[3]	transitions[0x0=>0x1]	220	1			T16	3		T15	1		T19	1
all_pins[3]	transitions[0x1=>0x0]	308	1			T18	1		T19	3		T20	6
all_pins[4]	values[0x0]	85684	1			T1	2		T2	7		T3	1
all_pins[4]	values[0x1]	346	1			T16	2		T18	1		T19	3
all_pins[4]	transitions[0x0=>0x1]	285	1			T16	1		T18	1		T19	2
all_pins[4]	transitions[0x1=>0x0]	135	1			T18	2		T19	1		T22	2
all_pins[5]	values[0x0]	85834	1			T1	2		T2	7		T3	1
all_pins[5]	values[0x1]	196	1			T16	1		T18	2		T19	2
all_pins[5]	transitions[0x0=>0x1]	161	1			T16	1		T18	2		T19	2
all_pins[5]	transitions[0x1=>0x0]	717	1			T11	1		T13	2		T16	1
all_pins[6]	values[0x0]	85278	1			T1	2		T2	7		T3	1
all_pins[6]	values[0x1]	752	1			T11	1		T13	2		T16	1
all_pins[6]	transitions[0x0=>0x1]	701	1			T11	1		T13	2		T16	1
all_pins[6]	transitions[0x1=>0x0]	268	1			T4	2		T20	6		T101	8
all_pins[7]	values[0x0]	85711	1			T1	2		T2	7		T3	1
all_pins[7]	values[0x1]	319	1			T4	2		T20	6		T101	8
all_pins[7]	transitions[0x0=>0x1]	188	1			T4	2		T20	6		T101	8
all_pins[7]	transitions[0x1=>0x0]	13556	1			T6	5		T8	1		T11	3
all_pins[8]	values[0x0]	72343	1			T1	2		T2	7		T3	1
all_pins[8]	values[0x1]	13687	1			T6	5		T8	1		T11	3
all_pins[8]	transitions[0x0=>0x1]	7166	1			T6	1		T11	2		T13	1
all_pins[8]	transitions[0x1=>0x0]	10868	1			T4	23		T5	2		T11	3