Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6274952	1			T3	1		T4	8		T5	18
all_levels[1]	1081144	1			T5	2		T11	9		T13	11
all_levels[2]	414911	1			T11	1		T13	3		T16	1
all_levels[3]	187788	1			T16	1		T26	2		T28	13
all_levels[4]	192470	1			T16	1		T28	10		T18	3
all_levels[5]	201335	1			T2	16		T16	2		T43	1
all_levels[6]	176942	1			T16	6		T43	4		T28	7
all_levels[7]	384600	1			T13	1		T25	7		T16	3
all_levels[8]	367151	1			T13	1		T25	1769		T27	2
all_levels[9]	161187	1			T11	2		T16	1		T43	3
all_levels[10]	159602	1			T11	12		T16	1		T28	7
all_levels[11]	159356	1			T13	2		T16	1		T28	14
all_levels[12]	193091	1			T11	1		T27	1		T16	3
all_levels[13]	153943	1			T16	1		T14	2		T28	8
all_levels[14]	207614	1			T16	1		T28	9		T18	3
all_levels[15]	156482	1			T4	2		T11	6		T16	1
all_levels[16]	193003	1			T4	580		T6	1		T11	1
all_levels[17]	326703	1			T16	1		T28	10		T18	2
all_levels[18]	144933	1			T27	2		T16	1		T14	2
all_levels[19]	509037	1			T11	3		T16	1		T28	8
all_levels[20]	207260	1			T11	2		T16	1		T43	2
all_levels[21]	145407	1			T11	2		T16	1		T43	1
all_levels[22]	136384	1			T16	1		T14	1		T28	7
all_levels[23]	158297	1			T16	1		T43	84		T28	12
all_levels[24]	128161	1			T27	2		T16	1		T14	4
all_levels[25]	246056	1			T13	1		T27	2		T16	1
all_levels[26]	282944	1			T16	3		T14	1		T28	15
all_levels[27]	153093	1			T13	2		T16	28083		T43	2
all_levels[28]	440634	1			T16	2		T15	1		T28	10
all_levels[29]	118269	1			T16	2		T28	8		T18	979
all_levels[30]	124447	1			T16	2		T14	2		T28	13
all_levels[31]	420255	1			T11	2		T16	408		T14	1
all_levels[32]	8680220	1			T6	4		T11	50		T13	4

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22884053

1

T2

15

T4

581

T5

19

auto[1]

3618

1

T2

1

T3

1

T4

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6272957	1			T5	17		T6	5		T11	10
all_levels[0]	auto[1]	1995	1			T3	1		T4	8		T5	1
all_levels[1]	auto[0]	1080875	1			T5	2		T11	9		T13	11
all_levels[1]	auto[1]	269	1			T41	1		T14	1		T94	1
all_levels[2]	auto[0]	414867	1			T11	1		T13	2		T16	1
all_levels[2]	auto[1]	44	1			T13	1		T151	2		T209	1
all_levels[3]	auto[0]	187715	1			T16	1		T26	2		T28	13
all_levels[3]	auto[1]	73	1			T103	14		T178	1		T410	8
all_levels[4]	auto[0]	192444	1			T16	1		T28	10		T18	3
all_levels[4]	auto[1]	26	1			T112	1		T36	1		T372	1
all_levels[5]	auto[0]	201316	1			T2	15		T16	2		T43	1
all_levels[5]	auto[1]	19	1			T2	1		T100	1		T106	2
all_levels[6]	auto[0]	176914	1			T16	6		T43	4		T28	7
all_levels[6]	auto[1]	28	1			T184	2		T411	1		T412	2
all_levels[7]	auto[0]	384489	1			T13	1		T25	2		T16	2
all_levels[7]	auto[1]	111	1			T25	5		T16	1		T14	1
all_levels[8]	auto[0]	367131	1			T13	1		T25	1769		T27	2
all_levels[8]	auto[1]	20	1			T122	2		T142	1		T155	2
all_levels[9]	auto[0]	161160	1			T11	2		T16	1		T43	2
all_levels[9]	auto[1]	27	1			T43	1		T369	1		T182	3
all_levels[10]	auto[0]	159575	1			T11	12		T16	1		T28	7
all_levels[10]	auto[1]	27	1			T107	1		T401	1		T323	1
all_levels[11]	auto[0]	159327	1			T13	2		T16	1		T28	14
all_levels[11]	auto[1]	29	1			T174	1		T161	1		T196	1
all_levels[12]	auto[0]	193064	1			T11	1		T27	1		T16	3
all_levels[12]	auto[1]	27	1			T14	2		T131	1		T98	1
all_levels[13]	auto[0]	153918	1			T16	1		T14	2		T28	8
all_levels[13]	auto[1]	25	1			T315	1		T413	1		T414	1
all_levels[14]	auto[0]	207598	1			T16	1		T28	9		T18	3
all_levels[14]	auto[1]	16	1			T113	1		T349	1		T360	1
all_levels[15]	auto[0]	156371	1			T4	1		T11	6		T16	1
all_levels[15]	auto[1]	111	1			T4	1		T20	5		T289	1
all_levels[16]	auto[0]	192980	1			T4	580		T6	1		T11	1
all_levels[16]	auto[1]	23	1			T101	1		T117	2		T175	1
all_levels[17]	auto[0]	326679	1			T16	1		T28	10		T18	2
all_levels[17]	auto[1]	24	1			T129	1		T106	2		T157	1
all_levels[18]	auto[0]	144906	1			T27	2		T16	1		T14	2
all_levels[18]	auto[1]	27	1			T89	1		T152	1		T316	1
all_levels[19]	auto[0]	509021	1			T11	3		T16	1		T28	8
all_levels[19]	auto[1]	16	1			T114	1		T415	1		T331	1
all_levels[20]	auto[0]	207239	1			T11	2		T16	1		T43	2
all_levels[20]	auto[1]	21	1			T339	1		T416	1		T417	1
all_levels[21]	auto[0]	145390	1			T11	2		T16	1		T43	1
all_levels[21]	auto[1]	17	1			T203	1		T243	1		T418	1
all_levels[22]	auto[0]	136363	1			T16	1		T14	1		T28	7
all_levels[22]	auto[1]	21	1			T419	1		T417	2		T420	2
all_levels[23]	auto[0]	158287	1			T16	1		T43	84		T28	12
all_levels[23]	auto[1]	10	1			T383	1		T354	1		T421	1
all_levels[24]	auto[0]	128143	1			T27	2		T16	1		T14	4
all_levels[24]	auto[1]	18	1			T175	1		T422	1		T170	1
all_levels[25]	auto[0]	246038	1			T13	1		T27	2		T16	1
all_levels[25]	auto[1]	18	1			T340	1		T379	1		T423	1
all_levels[26]	auto[0]	282902	1			T16	3		T14	1		T28	15
all_levels[26]	auto[1]	42	1			T188	1		T107	2		T142	3
all_levels[27]	auto[0]	153073	1			T13	2		T16	28083		T43	2
all_levels[27]	auto[1]	20	1			T153	5		T244	1		T424	2
all_levels[28]	auto[0]	440624	1			T16	2		T15	1		T28	10
all_levels[28]	auto[1]	10	1			T188	1		T146	1		T425	1
all_levels[29]	auto[0]	118254	1			T16	2		T28	8		T18	979
all_levels[29]	auto[1]	15	1			T188	1		T153	1		T144	1
all_levels[30]	auto[0]	124436	1			T16	2		T14	2		T28	13
all_levels[30]	auto[1]	11	1			T181	2		T194	2		T426	2
all_levels[31]	auto[0]	420248	1			T11	2		T16	408		T14	1
all_levels[31]	auto[1]	7	1			T215	2		T185	1		T218	1
all_levels[32]	auto[0]	8679749	1			T6	2		T11	50		T13	4
all_levels[32]	auto[1]	471	1			T6	2		T27	1		T14	2