Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	666	1			T16	7		T18	4		T34	4
all_values[1]	666	1			T16	7		T18	4		T34	4
all_values[2]	666	1			T16	7		T18	4		T34	4
all_values[3]	666	1			T16	7		T18	4		T34	4
all_values[4]	666	1			T16	7		T18	4		T34	4
all_values[5]	666	1			T16	7		T18	4		T34	4
all_values[6]	666	1			T16	7		T18	4		T34	4
all_values[7]	666	1			T16	7		T18	4		T34	4
all_values[8]	666	1			T16	7		T18	4		T34	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3321

1

T16

36

T18

24

T34

21

auto[1]

2673

1

T16

27

T18

12

T34

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1941

1

T16

26

T18

9

T34

13

auto[1]

4053

1

T16

37

T18

27

T34

23

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3536

1

T16

39

T18

23

T34

21

auto[1]

2458

1

T16

24

T18

13

T34

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	222	1			T16	1		T18	1		T34	1
all_values[0]	auto[0]	auto[1]	auto[1]	171	1			T16	1		T18	1		T34	1
all_values[0]	auto[1]	auto[0]	auto[1]	149	1			T18	2		T35	1		T36	5
all_values[0]	auto[1]	auto[1]	auto[1]	124	1			T16	5		T34	2		T38	2
all_values[1]	auto[0]	auto[0]	auto[0]	236	1			T16	5		T18	2		T34	1
all_values[1]	auto[0]	auto[1]	auto[0]	172	1			T18	2		T34	1		T35	3
all_values[1]	auto[1]	auto[0]	auto[1]	151	1			T16	2		T34	1		T36	3
all_values[1]	auto[1]	auto[1]	auto[1]	107	1			T34	1		T96	2		T110	1
all_values[2]	auto[0]	auto[0]	auto[0]	143	1			T16	4		T34	2		T35	4
all_values[2]	auto[0]	auto[0]	auto[1]	62	1			T18	2		T34	1		T36	4
all_values[2]	auto[0]	auto[1]	auto[0]	110	1			T16	3		T38	1		T95	3
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T18	1		T96	1		T110	2
all_values[2]	auto[1]	auto[0]	auto[1]	154	1			T18	1		T34	1		T36	3
all_values[2]	auto[1]	auto[1]	auto[1]	129	1			T38	1		T39	1		T80	1
all_values[3]	auto[0]	auto[0]	auto[0]	158	1			T16	1		T18	1		T34	2
all_values[3]	auto[0]	auto[0]	auto[1]	62	1			T18	1		T36	2		T39	2
all_values[3]	auto[0]	auto[1]	auto[0]	107	1			T34	1		T35	1		T38	1
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T16	1		T38	1		T39	2
all_values[3]	auto[1]	auto[0]	auto[1]	148	1			T16	2		T18	2		T34	1
all_values[3]	auto[1]	auto[1]	auto[1]	118	1			T16	3		T38	2		T39	1
all_values[4]	auto[0]	auto[0]	auto[0]	142	1			T18	1		T34	1		T36	4
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T16	4		T35	1		T96	1
all_values[4]	auto[0]	auto[1]	auto[0]	100	1			T35	1		T39	4		T95	1
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T34	1		T36	1		T38	2
all_values[4]	auto[1]	auto[0]	auto[1]	157	1			T16	2		T18	2		T34	1
all_values[4]	auto[1]	auto[1]	auto[1]	116	1			T16	1		T18	1		T34	1
all_values[5]	auto[0]	auto[0]	auto[0]	165	1			T16	2		T18	1		T34	1
all_values[5]	auto[0]	auto[0]	auto[1]	58	1			T16	1		T38	2		T39	1
all_values[5]	auto[0]	auto[1]	auto[0]	103	1			T16	1		T34	1		T36	4
all_values[5]	auto[0]	auto[1]	auto[1]	69	1			T18	2		T35	1		T39	2
all_values[5]	auto[1]	auto[0]	auto[1]	154	1			T16	2		T35	2		T36	1
all_values[5]	auto[1]	auto[1]	auto[1]	117	1			T16	1		T18	1		T34	2
all_values[6]	auto[0]	auto[0]	auto[0]	140	1			T16	2		T36	2		T39	2
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T36	1		T38	1		T39	1
all_values[6]	auto[0]	auto[1]	auto[0]	102	1			T16	1		T18	2		T34	1
all_values[6]	auto[0]	auto[1]	auto[1]	72	1			T35	2		T36	1		T95	3
all_values[6]	auto[1]	auto[0]	auto[1]	160	1			T16	2		T18	2		T34	3
all_values[6]	auto[1]	auto[1]	auto[1]	121	1			T16	2		T35	1		T36	2
all_values[7]	auto[0]	auto[0]	auto[0]	147	1			T16	2		T34	2		T35	1
all_values[7]	auto[0]	auto[0]	auto[1]	54	1			T18	2		T34	1		T80	1
all_values[7]	auto[0]	auto[1]	auto[0]	116	1			T16	5		T35	1		T38	1
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T36	1		T39	2		T96	1
all_values[7]	auto[1]	auto[0]	auto[1]	149	1			T18	2		T34	1		T35	2
all_values[7]	auto[1]	auto[1]	auto[1]	127	1			T36	2		T38	1		T95	1
all_values[8]	auto[0]	auto[0]	auto[1]	206	1			T16	4		T18	2		T34	1
all_values[8]	auto[0]	auto[1]	auto[1]	183	1			T16	1		T18	2		T34	2
all_values[8]	auto[1]	auto[0]	auto[1]	155	1			T35	1		T36	4		T38	2
all_values[8]	auto[1]	auto[1]	auto[1]	122	1			T16	2		T34	1		T39	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal