| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.11 | 99.10 | 97.65 | 100.00 | 98.38 | 100.00 | 99.55 |
| T1252 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.351894648 | Aug 21 06:55:13 AM UTC 24 | Aug 21 06:55:16 AM UTC 24 | 91113878 ps | ||
| T1253 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.4155598070 | Aug 21 06:55:13 AM UTC 24 | Aug 21 06:55:17 AM UTC 24 | 101870587 ps | ||
| T1254 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1281165447 | Aug 21 06:55:15 AM UTC 24 | Aug 21 06:55:17 AM UTC 24 | 33341436 ps | ||
| T1255 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.379445864 | Aug 21 06:55:15 AM UTC 24 | Aug 21 06:55:17 AM UTC 24 | 26198104 ps | ||
| T1256 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1015318670 | Aug 21 06:55:15 AM UTC 24 | Aug 21 06:55:17 AM UTC 24 | 22124045 ps | ||
| T1257 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3312531141 | Aug 21 06:55:15 AM UTC 24 | Aug 21 06:55:17 AM UTC 24 | 71295821 ps | ||
| T1258 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3495778424 | Aug 21 06:55:15 AM UTC 24 | Aug 21 06:55:17 AM UTC 24 | 51258990 ps | ||
| T1259 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2356355505 | Aug 21 06:55:15 AM UTC 24 | Aug 21 06:55:17 AM UTC 24 | 79436734 ps | ||
| T1260 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.3017113590 | Aug 21 06:55:15 AM UTC 24 | Aug 21 06:55:18 AM UTC 24 | 25794576 ps | ||
| T72 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.3179829850 | Aug 21 06:55:15 AM UTC 24 | Aug 21 06:55:18 AM UTC 24 | 353612496 ps | ||
| T1261 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.3240023973 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:19 AM UTC 24 | 34291776 ps | ||
| T1262 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.303039427 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:20 AM UTC 24 | 16879686 ps | ||
| T1263 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.1499402870 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:20 AM UTC 24 | 109816994 ps | ||
| T1264 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.1526245088 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:20 AM UTC 24 | 22934212 ps | ||
| T1265 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3516011938 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:20 AM UTC 24 | 57414545 ps | ||
| T1266 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.2534351010 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:20 AM UTC 24 | 22357000 ps | ||
| T1267 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2772857452 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:20 AM UTC 24 | 42577548 ps | ||
| T1268 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.4024933206 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:20 AM UTC 24 | 44052292 ps | ||
| T1269 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2643524671 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:20 AM UTC 24 | 94541750 ps | ||
| T1270 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2622626940 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:21 AM UTC 24 | 70468930 ps | ||
| T1271 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2924234862 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:21 AM UTC 24 | 396401617 ps | ||
| T1272 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.800630751 | Aug 21 06:55:18 AM UTC 24 | Aug 21 06:55:21 AM UTC 24 | 272432711 ps | ||
| T1273 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3946738788 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:22 AM UTC 24 | 186515609 ps | ||
| T1274 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2111570971 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:22 AM UTC 24 | 12686845 ps | ||
| T1275 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3950783613 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:22 AM UTC 24 | 20658732 ps | ||
| T1276 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.1733533805 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:22 AM UTC 24 | 16507958 ps | ||
| T1277 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3793726445 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:22 AM UTC 24 | 20725780 ps | ||
| T1278 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4104603798 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:22 AM UTC 24 | 120078165 ps | ||
| T1279 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1270340545 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:22 AM UTC 24 | 178198879 ps | ||
| T1280 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.617435683 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:22 AM UTC 24 | 23812561 ps | ||
| T1281 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.800019964 | Aug 21 06:55:20 AM UTC 24 | Aug 21 06:55:23 AM UTC 24 | 108068457 ps | ||
| T1282 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.3988029275 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 33086450 ps | ||
| T1283 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.592507304 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 31511874 ps | ||
| T1284 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.1736286950 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 20127844 ps | ||
| T1285 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.3193463675 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 27771676 ps | ||
| T1286 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.916629844 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 136867911 ps | ||
| T1287 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.1346084705 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 12937596 ps | ||
| T1288 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.360659943 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 15284114 ps | ||
| T1289 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2869167022 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 31297711 ps | ||
| T1290 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3503537475 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 30978297 ps | ||
| T1291 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2425508220 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 14141772 ps | ||
| T1292 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2146067949 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 37798260 ps | ||
| T1293 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.1298972179 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 24485325 ps | ||
| T1294 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.3128041202 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 12849156 ps | ||
| T1295 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1473823348 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 27684665 ps | ||
| T1296 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3552217172 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 18921307 ps | ||
| T1297 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.4233146533 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 44829968 ps | ||
| T1298 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1288697641 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 64899782 ps | ||
| T1299 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.523351517 | Aug 21 06:55:24 AM UTC 24 | Aug 21 06:55:26 AM UTC 24 | 198105168 ps | ||
| T1300 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3058788006 | Aug 21 06:55:26 AM UTC 24 | Aug 21 06:55:28 AM UTC 24 | 33566076 ps | ||
| T1301 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.2338958382 | Aug 21 06:55:26 AM UTC 24 | Aug 21 06:55:28 AM UTC 24 | 12517696 ps | ||
| T1302 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.914780182 | Aug 21 06:55:26 AM UTC 24 | Aug 21 06:55:28 AM UTC 24 | 14951260 ps | ||
| T1303 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3555815581 | Aug 21 06:55:26 AM UTC 24 | Aug 21 06:55:28 AM UTC 24 | 14855801 ps | ||
| T1304 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.797751350 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:32 AM UTC 24 | 26146455 ps | ||
| T1305 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2128941844 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:32 AM UTC 24 | 30100805 ps | ||
| T1306 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3443158712 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 13747397 ps | ||
| T1307 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3528966426 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 14481912 ps | ||
| T1308 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3880710836 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 47966454 ps | ||
| T1309 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3351336112 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 37703709 ps | ||
| T1310 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1476177620 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 42748568 ps | ||
| T1311 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.537513324 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 32805562 ps | ||
| T1312 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.1928244619 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 16150097 ps | ||
| T1313 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.3799985994 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 13549295 ps | ||
| T1314 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.1660569354 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 58115084 ps | ||
| T1315 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2782664080 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 35142793 ps | ||
| T1316 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.137729155 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 51212911 ps | ||
| T1317 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.3324258572 | Aug 21 06:55:31 AM UTC 24 | Aug 21 06:55:33 AM UTC 24 | 109060442 ps |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_loopback.1556713563 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6835289000 ps |
| CPU time | 21.4 seconds |
| Started | Aug 21 06:16:10 AM UTC 24 |
| Finished | Aug 21 06:16:33 AM UTC 24 |
| Peak memory | 208324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1556713563 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1556713563 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.4273983659 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3640961886 ps |
| CPU time | 110.97 seconds |
| Started | Aug 21 06:16:21 AM UTC 24 |
| Finished | Aug 21 06:18:15 AM UTC 24 |
| Peak memory | 225164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4273983659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4273983659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_stress_all.1811185918 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 597406062591 ps |
| CPU time | 214.23 seconds |
| Started | Aug 21 06:16:22 AM UTC 24 |
| Finished | Aug 21 06:20:00 AM UTC 24 |
| Peak memory | 219848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1811185918 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1811185918 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_stress_all.1197120599 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 128064229271 ps |
| CPU time | 186.24 seconds |
| Started | Aug 21 06:21:20 AM UTC 24 |
| Finished | Aug 21 06:24:30 AM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1197120599 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1197120599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.1098155112 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 113834029313 ps |
| CPU time | 255.22 seconds |
| Started | Aug 21 06:19:33 AM UTC 24 |
| Finished | Aug 21 06:23:52 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1098155112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1098155112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_fifo_reset.4179934145 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 119680944550 ps |
| CPU time | 79.14 seconds |
| Started | Aug 21 06:17:16 AM UTC 24 |
| Finished | Aug 21 06:18:37 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4179934145 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.4179934145 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_stress_all.2675229606 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 276000448329 ps |
| CPU time | 410.2 seconds |
| Started | Aug 21 06:18:42 AM UTC 24 |
| Finished | Aug 21 06:25:38 AM UTC 24 |
| Peak memory | 208968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2675229606 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2675229606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_stress_all.1991510020 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 538404646562 ps |
| CPU time | 624.29 seconds |
| Started | Aug 21 06:22:26 AM UTC 24 |
| Finished | Aug 21 06:32:58 AM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1991510020 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1991510020 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_stress_all.3871959798 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 72830287734 ps |
| CPU time | 58.74 seconds |
| Started | Aug 21 06:20:42 AM UTC 24 |
| Finished | Aug 21 06:21:42 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3871959798 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3871959798 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_intr.112590606 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 41318095056 ps |
| CPU time | 21.27 seconds |
| Started | Aug 21 06:21:40 AM UTC 24 |
| Finished | Aug 21 06:22:03 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=112590606 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.112590606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_noise_filter.2503156369 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 50077704917 ps |
| CPU time | 46.79 seconds |
| Started | Aug 21 06:16:01 AM UTC 24 |
| Finished | Aug 21 06:16:49 AM UTC 24 |
| Peak memory | 207892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2503156369 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2503156369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_fifo_full.3966880869 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 44308031570 ps |
| CPU time | 72.74 seconds |
| Started | Aug 21 06:26:02 AM UTC 24 |
| Finished | Aug 21 06:27:17 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3966880869 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3966880869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_sec_cm.2950567965 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 239401329 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 06:16:33 AM UTC 24 |
| Finished | Aug 21 06:16:36 AM UTC 24 |
| Peak memory | 240276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2950567965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2950567965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_stress_all.2801911378 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 120852496822 ps |
| CPU time | 133.5 seconds |
| Started | Aug 21 06:21:53 AM UTC 24 |
| Finished | Aug 21 06:24:09 AM UTC 24 |
| Peak memory | 217612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2801911378 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2801911378 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_stress_all.2846707317 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 328355205647 ps |
| CPU time | 292.22 seconds |
| Started | Aug 21 06:20:17 AM UTC 24 |
| Finished | Aug 21 06:25:13 AM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2846707317 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2846707317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_stress_all.3436708345 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 201179555255 ps |
| CPU time | 247.05 seconds |
| Started | Aug 21 06:25:08 AM UTC 24 |
| Finished | Aug 21 06:29:19 AM UTC 24 |
| Peak memory | 208124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3436708345 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3436708345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3795064594 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 21689828 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 06:54:53 AM UTC 24 |
| Finished | Aug 21 06:54:55 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3795064594 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3795064594 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2866903697 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 27169574503 ps |
| CPU time | 25.6 seconds |
| Started | Aug 21 06:25:21 AM UTC 24 |
| Finished | Aug 21 06:25:48 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2866903697 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2866903697 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.661460859 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 66722808952 ps |
| CPU time | 238.24 seconds |
| Started | Aug 21 06:18:19 AM UTC 24 |
| Finished | Aug 21 06:22:20 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=661460859 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.661460859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1875347392 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 17443778216 ps |
| CPU time | 33.86 seconds |
| Started | Aug 21 06:23:48 AM UTC 24 |
| Finished | Aug 21 06:24:23 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1875347392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1875347392 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_stress_all.2309031687 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 250963131248 ps |
| CPU time | 333.53 seconds |
| Started | Aug 21 06:26:54 AM UTC 24 |
| Finished | Aug 21 06:32:32 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2309031687 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2309031687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_noise_filter.617993161 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 56115801448 ps |
| CPU time | 87.43 seconds |
| Started | Aug 21 06:19:16 AM UTC 24 |
| Finished | Aug 21 06:20:45 AM UTC 24 |
| Peak memory | 217732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=617993161 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.617993161 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_stress_all.4265289222 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 151549741913 ps |
| CPU time | 414.3 seconds |
| Started | Aug 21 06:17:56 AM UTC 24 |
| Finished | Aug 21 06:24:55 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4265289222 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4265289222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_intr.3747286289 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11411635669 ps |
| CPU time | 12.75 seconds |
| Started | Aug 21 06:15:48 AM UTC 24 |
| Finished | Aug 21 06:16:02 AM UTC 24 |
| Peak memory | 207956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3747286289 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3747286289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_fifo_full.3791119103 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 39058917836 ps |
| CPU time | 22.01 seconds |
| Started | Aug 21 06:23:11 AM UTC 24 |
| Finished | Aug 21 06:23:34 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3791119103 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3791119103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_stress_all.1601464133 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 365694501902 ps |
| CPU time | 168.45 seconds |
| Started | Aug 21 06:28:50 AM UTC 24 |
| Finished | Aug 21 06:31:41 AM UTC 24 |
| Peak memory | 219764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1601464133 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1601464133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.1055645779 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 71213414 ps |
| CPU time | 1.87 seconds |
| Started | Aug 21 06:55:04 AM UTC 24 |
| Finished | Aug 21 06:55:06 AM UTC 24 |
| Peak memory | 201688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1055645779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1055645779 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.1536101857 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 193552928602 ps |
| CPU time | 503.61 seconds |
| Started | Aug 21 06:16:56 AM UTC 24 |
| Finished | Aug 21 06:25:25 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1536101857 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1536101857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.2420443916 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 131574135187 ps |
| CPU time | 185.77 seconds |
| Started | Aug 21 06:26:16 AM UTC 24 |
| Finished | Aug 21 06:29:24 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2420443916 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2420443916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_alert_test.1985396401 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 33699808 ps |
| CPU time | 0.75 seconds |
| Started | Aug 21 06:16:37 AM UTC 24 |
| Finished | Aug 21 06:16:38 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1985396401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1985396401 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_fifo_reset.3407461542 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 157661396029 ps |
| CPU time | 91.21 seconds |
| Started | Aug 21 06:19:00 AM UTC 24 |
| Finished | Aug 21 06:20:33 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3407461542 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3407461542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_intr.2700056606 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 54815684156 ps |
| CPU time | 41.9 seconds |
| Started | Aug 21 06:23:16 AM UTC 24 |
| Finished | Aug 21 06:24:00 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2700056606 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2700056606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.1429917098 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6073415636 ps |
| CPU time | 117.33 seconds |
| Started | Aug 21 06:21:52 AM UTC 24 |
| Finished | Aug 21 06:23:52 AM UTC 24 |
| Peak memory | 219984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1429917098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1429917098 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_fifo_reset.4152579115 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 46890335181 ps |
| CPU time | 41.04 seconds |
| Started | Aug 21 06:25:34 AM UTC 24 |
| Finished | Aug 21 06:26:16 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4152579115 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4152579115 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_stress_all.3994236810 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 403067065574 ps |
| CPU time | 121.83 seconds |
| Started | Aug 21 06:25:57 AM UTC 24 |
| Finished | Aug 21 06:28:01 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3994236810 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3994236810 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_stress_all.36992318 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 195476397472 ps |
| CPU time | 361.31 seconds |
| Started | Aug 21 06:23:06 AM UTC 24 |
| Finished | Aug 21 06:29:12 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36992318 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.36992318 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_fifo_reset.4223733996 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 231882311941 ps |
| CPU time | 168.67 seconds |
| Started | Aug 21 06:29:54 AM UTC 24 |
| Finished | Aug 21 06:32:45 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4223733996 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4223733996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.737899731 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 15578677443 ps |
| CPU time | 93.88 seconds |
| Started | Aug 21 06:22:25 AM UTC 24 |
| Finished | Aug 21 06:24:01 AM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=737899731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.737899731 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_fifo_reset.363327230 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 50603616738 ps |
| CPU time | 111.15 seconds |
| Started | Aug 21 06:21:30 AM UTC 24 |
| Finished | Aug 21 06:23:24 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=363327230 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.363327230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.2658658597 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2822637997 ps |
| CPU time | 46.27 seconds |
| Started | Aug 21 06:18:38 AM UTC 24 |
| Finished | Aug 21 06:19:26 AM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2658658597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2658658597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2140341222 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 56564482521 ps |
| CPU time | 26.27 seconds |
| Started | Aug 21 06:48:37 AM UTC 24 |
| Finished | Aug 21 06:49:05 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2140341222 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2140341222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/94.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_perf.2045314271 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 20411379932 ps |
| CPU time | 281.21 seconds |
| Started | Aug 21 06:20:37 AM UTC 24 |
| Finished | Aug 21 06:25:22 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2045314271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2045314271 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3170788981 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 267091010 ps |
| CPU time | 1.82 seconds |
| Started | Aug 21 06:54:41 AM UTC 24 |
| Finished | Aug 21 06:54:44 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3170788981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3170788981 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_noise_filter.2637497092 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 136069074205 ps |
| CPU time | 86.67 seconds |
| Started | Aug 21 06:22:17 AM UTC 24 |
| Finished | Aug 21 06:23:45 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2637497092 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2637497092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_fifo_full.3925982046 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 170137898316 ps |
| CPU time | 384.15 seconds |
| Started | Aug 21 06:15:36 AM UTC 24 |
| Finished | Aug 21 06:22:05 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3925982046 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3925982046 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_tx_rx.2806113690 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 151931587616 ps |
| CPU time | 275.1 seconds |
| Started | Aug 21 06:16:50 AM UTC 24 |
| Finished | Aug 21 06:21:28 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2806113690 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2806113690 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_noise_filter.3290079705 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 130399127176 ps |
| CPU time | 239.36 seconds |
| Started | Aug 21 06:23:16 AM UTC 24 |
| Finished | Aug 21 06:27:19 AM UTC 24 |
| Peak memory | 208232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3290079705 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3290079705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.227788519 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 58893128059 ps |
| CPU time | 72.05 seconds |
| Started | Aug 21 06:33:41 AM UTC 24 |
| Finished | Aug 21 06:34:54 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=227788519 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.227788519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.2154052672 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 49502501105 ps |
| CPU time | 41.45 seconds |
| Started | Aug 21 06:19:21 AM UTC 24 |
| Finished | Aug 21 06:20:04 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2154052672 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2154052672 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_fifo_full.2190160121 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 34139398552 ps |
| CPU time | 22.19 seconds |
| Started | Aug 21 06:16:52 AM UTC 24 |
| Finished | Aug 21 06:17:15 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2190160121 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2190160121 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_stress_all.426729500 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 219463573786 ps |
| CPU time | 102.38 seconds |
| Started | Aug 21 06:24:30 AM UTC 24 |
| Finished | Aug 21 06:26:15 AM UTC 24 |
| Peak memory | 208676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=426729500 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.426729500 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_intr.1389205869 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 53862062394 ps |
| CPU time | 52.72 seconds |
| Started | Aug 21 06:24:42 AM UTC 24 |
| Finished | Aug 21 06:25:36 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389205869 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1389205869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/139.uart_fifo_reset.634241871 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 35966266491 ps |
| CPU time | 37.69 seconds |
| Started | Aug 21 06:50:01 AM UTC 24 |
| Finished | Aug 21 06:50:40 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=634241871 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.634241871 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/139.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/87.uart_fifo_reset.3556526910 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 82348945427 ps |
| CPU time | 67.42 seconds |
| Started | Aug 21 06:48:13 AM UTC 24 |
| Finished | Aug 21 06:49:22 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3556526910 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3556526910 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/87.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.3830704547 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 88850247141 ps |
| CPU time | 163.24 seconds |
| Started | Aug 21 06:23:29 AM UTC 24 |
| Finished | Aug 21 06:26:15 AM UTC 24 |
| Peak memory | 208872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830704547 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3830704547 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_fifo_full.2020751568 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 64396217823 ps |
| CPU time | 39.26 seconds |
| Started | Aug 21 06:24:39 AM UTC 24 |
| Finished | Aug 21 06:25:19 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2020751568 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2020751568 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/198.uart_fifo_reset.4073907446 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 140575416607 ps |
| CPU time | 265.88 seconds |
| Started | Aug 21 06:51:46 AM UTC 24 |
| Finished | Aug 21 06:56:15 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4073907446 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4073907446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/198.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.2694283423 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 29088140303 ps |
| CPU time | 37.84 seconds |
| Started | Aug 21 06:18:11 AM UTC 24 |
| Finished | Aug 21 06:18:51 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2694283423 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2694283423 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_stress_all.88007035 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 335493930985 ps |
| CPU time | 865.32 seconds |
| Started | Aug 21 06:31:30 AM UTC 24 |
| Finished | Aug 21 06:46:06 AM UTC 24 |
| Peak memory | 212440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=88007035 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.88007035 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_fifo_reset.1847062831 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 59588280212 ps |
| CPU time | 99.52 seconds |
| Started | Aug 21 06:40:49 AM UTC 24 |
| Finished | Aug 21 06:42:31 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1847062831 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1847062831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_stress_all.3167482381 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 261647810733 ps |
| CPU time | 846.77 seconds |
| Started | Aug 21 06:23:26 AM UTC 24 |
| Finished | Aug 21 06:37:42 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3167482381 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3167482381 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_tx_rx.1242085519 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 53025024655 ps |
| CPU time | 38.32 seconds |
| Started | Aug 21 06:23:28 AM UTC 24 |
| Finished | Aug 21 06:24:07 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1242085519 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1242085519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/121.uart_fifo_reset.625103242 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 136742336124 ps |
| CPU time | 113.88 seconds |
| Started | Aug 21 06:49:24 AM UTC 24 |
| Finished | Aug 21 06:51:20 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=625103242 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.625103242 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/121.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_fifo_reset.1760337144 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 109383909610 ps |
| CPU time | 178.28 seconds |
| Started | Aug 21 06:25:17 AM UTC 24 |
| Finished | Aug 21 06:28:18 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1760337144 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1760337144 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/152.uart_fifo_reset.1975244289 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 69717313574 ps |
| CPU time | 36.91 seconds |
| Started | Aug 21 06:50:25 AM UTC 24 |
| Finished | Aug 21 06:51:03 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1975244289 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1975244289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/152.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/159.uart_fifo_reset.854812005 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 34128890357 ps |
| CPU time | 24.8 seconds |
| Started | Aug 21 06:50:33 AM UTC 24 |
| Finished | Aug 21 06:50:59 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=854812005 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.854812005 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/159.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.4151929210 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 27348804464 ps |
| CPU time | 43.93 seconds |
| Started | Aug 21 06:26:04 AM UTC 24 |
| Finished | Aug 21 06:26:50 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4151929210 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4151929210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_stress_all.3285426951 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 407351648659 ps |
| CPU time | 117.89 seconds |
| Started | Aug 21 06:26:20 AM UTC 24 |
| Finished | Aug 21 06:28:20 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3285426951 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3285426951 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/194.uart_fifo_reset.4181946627 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 34484844854 ps |
| CPU time | 35.27 seconds |
| Started | Aug 21 06:51:42 AM UTC 24 |
| Finished | Aug 21 06:52:19 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181946627 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.4181946627 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/194.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2169658607 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 106583749436 ps |
| CPU time | 45.28 seconds |
| Started | Aug 21 06:51:59 AM UTC 24 |
| Finished | Aug 21 06:52:46 AM UTC 24 |
| Peak memory | 208732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2169658607 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2169658607 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/209.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.3518178072 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 11782923510 ps |
| CPU time | 40.53 seconds |
| Started | Aug 21 06:34:58 AM UTC 24 |
| Finished | Aug 21 06:35:40 AM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3518178072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3518178072 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_stress_all.91296198 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 194897142714 ps |
| CPU time | 145.86 seconds |
| Started | Aug 21 06:44:28 AM UTC 24 |
| Finished | Aug 21 06:46:56 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91296198 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.91296198 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/88.uart_fifo_reset.2729360731 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 16112022474 ps |
| CPU time | 38.88 seconds |
| Started | Aug 21 06:48:17 AM UTC 24 |
| Finished | Aug 21 06:48:57 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2729360731 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2729360731 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/88.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_fifo_reset.198091788 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8630601698 ps |
| CPU time | 29.28 seconds |
| Started | Aug 21 06:15:40 AM UTC 24 |
| Finished | Aug 21 06:16:10 AM UTC 24 |
| Peak memory | 208424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=198091788 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.198091788 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2942855763 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2238681766 ps |
| CPU time | 46 seconds |
| Started | Aug 21 06:17:54 AM UTC 24 |
| Finished | Aug 21 06:18:41 AM UTC 24 |
| Peak memory | 209028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2942855763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2942855763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/103.uart_fifo_reset.282354342 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 57715289714 ps |
| CPU time | 84.06 seconds |
| Started | Aug 21 06:48:57 AM UTC 24 |
| Finished | Aug 21 06:50:23 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=282354342 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.282354342 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/103.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_fifo_full.1655018728 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 107597866467 ps |
| CPU time | 59.96 seconds |
| Started | Aug 21 06:23:28 AM UTC 24 |
| Finished | Aug 21 06:24:29 AM UTC 24 |
| Peak memory | 208968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1655018728 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1655018728 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/110.uart_fifo_reset.2310889700 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 32423737757 ps |
| CPU time | 18.03 seconds |
| Started | Aug 21 06:49:09 AM UTC 24 |
| Finished | Aug 21 06:49:28 AM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2310889700 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2310889700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/110.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/114.uart_fifo_reset.3923257479 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5886275272 ps |
| CPU time | 14.59 seconds |
| Started | Aug 21 06:49:14 AM UTC 24 |
| Finished | Aug 21 06:49:30 AM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3923257479 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3923257479 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/114.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/118.uart_fifo_reset.1389800013 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 77124813391 ps |
| CPU time | 106.66 seconds |
| Started | Aug 21 06:49:19 AM UTC 24 |
| Finished | Aug 21 06:51:07 AM UTC 24 |
| Peak memory | 208860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389800013 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1389800013 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/118.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/119.uart_fifo_reset.4169676415 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 58620334869 ps |
| CPU time | 61.15 seconds |
| Started | Aug 21 06:49:19 AM UTC 24 |
| Finished | Aug 21 06:50:21 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4169676415 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4169676415 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/119.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/128.uart_fifo_reset.2308360680 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 128037804407 ps |
| CPU time | 69.98 seconds |
| Started | Aug 21 06:49:34 AM UTC 24 |
| Finished | Aug 21 06:50:46 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2308360680 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2308360680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/128.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/137.uart_fifo_reset.1224160904 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 79075879389 ps |
| CPU time | 52.11 seconds |
| Started | Aug 21 06:49:50 AM UTC 24 |
| Finished | Aug 21 06:50:44 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1224160904 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1224160904 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/137.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/138.uart_fifo_reset.1909361179 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 96206272239 ps |
| CPU time | 83.05 seconds |
| Started | Aug 21 06:49:52 AM UTC 24 |
| Finished | Aug 21 06:51:17 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1909361179 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1909361179 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/138.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/144.uart_fifo_reset.3557042258 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 57916781751 ps |
| CPU time | 147.85 seconds |
| Started | Aug 21 06:50:17 AM UTC 24 |
| Finished | Aug 21 06:52:47 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557042258 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3557042258 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/144.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1776788202 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 165895854494 ps |
| CPU time | 23.26 seconds |
| Started | Aug 21 06:50:32 AM UTC 24 |
| Finished | Aug 21 06:50:56 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1776788202 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1776788202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/158.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/188.uart_fifo_reset.2323381667 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 48865051128 ps |
| CPU time | 22.86 seconds |
| Started | Aug 21 06:51:27 AM UTC 24 |
| Finished | Aug 21 06:51:51 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2323381667 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2323381667 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/188.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/213.uart_fifo_reset.3808356881 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 32579692840 ps |
| CPU time | 24.85 seconds |
| Started | Aug 21 06:52:08 AM UTC 24 |
| Finished | Aug 21 06:52:34 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3808356881 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3808356881 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/213.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/230.uart_fifo_reset.2916153585 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 69282289526 ps |
| CPU time | 43.75 seconds |
| Started | Aug 21 06:52:40 AM UTC 24 |
| Finished | Aug 21 06:53:25 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2916153585 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2916153585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/230.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/239.uart_fifo_reset.3864393708 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 25011819169 ps |
| CPU time | 19.69 seconds |
| Started | Aug 21 06:52:53 AM UTC 24 |
| Finished | Aug 21 06:53:14 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3864393708 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3864393708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/239.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_fifo_full.3149131614 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 339317809928 ps |
| CPU time | 50.12 seconds |
| Started | Aug 21 06:32:10 AM UTC 24 |
| Finished | Aug 21 06:33:02 AM UTC 24 |
| Peak memory | 208728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3149131614 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3149131614 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_fifo_reset.4232987600 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 141233180345 ps |
| CPU time | 283.11 seconds |
| Started | Aug 21 06:32:15 AM UTC 24 |
| Finished | Aug 21 06:37:02 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4232987600 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.4232987600 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3754440202 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 93591574560 ps |
| CPU time | 359.68 seconds |
| Started | Aug 21 06:54:34 AM UTC 24 |
| Finished | Aug 21 07:00:38 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3754440202 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3754440202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/295.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2151711741 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 36925833784 ps |
| CPU time | 76.49 seconds |
| Started | Aug 21 06:36:28 AM UTC 24 |
| Finished | Aug 21 06:37:47 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2151711741 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2151711741 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.2000536932 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 87686999 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 06:54:45 AM UTC 24 |
| Finished | Aug 21 06:54:47 AM UTC 24 |
| Peak memory | 200584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2000536932 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2000536932 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1113774599 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 1383283094 ps |
| CPU time | 3.43 seconds |
| Started | Aug 21 06:54:45 AM UTC 24 |
| Finished | Aug 21 06:54:49 AM UTC 24 |
| Peak memory | 202684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1113774599 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1113774599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.634949001 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 12756121 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 06:54:43 AM UTC 24 |
| Finished | Aug 21 06:54:45 AM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=634949001 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.634949001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3974359370 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 143533379 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 06:54:46 AM UTC 24 |
| Finished | Aug 21 06:54:48 AM UTC 24 |
| Peak memory | 201688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=3974359370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3974359370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.2940347235 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 19962634 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:54:45 AM UTC 24 |
| Finished | Aug 21 06:54:46 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2940347235 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2940347235 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3516779349 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 42530398 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:54:42 AM UTC 24 |
| Finished | Aug 21 06:54:44 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3516779349 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3516779349 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3616562684 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 69594556 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 06:54:45 AM UTC 24 |
| Finished | Aug 21 06:54:47 AM UTC 24 |
| Peak memory | 202556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36 16562684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.3616562684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.707662667 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 35398394 ps |
| CPU time | 2.52 seconds |
| Started | Aug 21 06:54:40 AM UTC 24 |
| Finished | Aug 21 06:54:44 AM UTC 24 |
| Peak memory | 202824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=707662667 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.707662667 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.3027524016 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 25086516 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 06:54:50 AM UTC 24 |
| Finished | Aug 21 06:54:52 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3027524016 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3027524016 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3680599004 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 125114881 ps |
| CPU time | 2 seconds |
| Started | Aug 21 06:54:49 AM UTC 24 |
| Finished | Aug 21 06:54:52 AM UTC 24 |
| Peak memory | 201828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3680599004 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3680599004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.372819078 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 32991013 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:54:48 AM UTC 24 |
| Finished | Aug 21 06:54:50 AM UTC 24 |
| Peak memory | 201640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=372819078 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.372819078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3398756129 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 59072170 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 06:54:50 AM UTC 24 |
| Finished | Aug 21 06:54:52 AM UTC 24 |
| Peak memory | 201564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=3398756129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3398756129 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3654048162 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 13134889 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 06:54:49 AM UTC 24 |
| Finished | Aug 21 06:54:51 AM UTC 24 |
| Peak memory | 201116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3654048162 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3654048162 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.1905046830 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 33536712 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 06:54:48 AM UTC 24 |
| Finished | Aug 21 06:54:50 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1905046830 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1905046830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.1635565391 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 16627461 ps |
| CPU time | 1 seconds |
| Started | Aug 21 06:54:50 AM UTC 24 |
| Finished | Aug 21 06:54:52 AM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16 35565391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.1635565391 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.238811733 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 58801982 ps |
| CPU time | 1.75 seconds |
| Started | Aug 21 06:54:46 AM UTC 24 |
| Finished | Aug 21 06:54:49 AM UTC 24 |
| Peak memory | 201648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=238811733 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.238811733 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.91808655 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 138401434 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 06:54:47 AM UTC 24 |
| Finished | Aug 21 06:54:49 AM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91808655 -a ssert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.91808655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2849004736 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 21516226 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:12 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=2849004736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2849004736 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1890857791 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 12279746 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:11 AM UTC 24 |
| Peak memory | 201516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1890857791 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1890857791 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.913394372 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 14375082 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:11 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=913394372 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.913394372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.1593461757 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 104702915 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:11 AM UTC 24 |
| Peak memory | 201564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15 93461757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.1593461757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.903637675 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 243798794 ps |
| CPU time | 2.08 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:12 AM UTC 24 |
| Peak memory | 202696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=903637675 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.903637675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.4253757356 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 138356079 ps |
| CPU time | 1.06 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:11 AM UTC 24 |
| Peak memory | 201244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4253757356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4253757356 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1743722373 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 55194652 ps |
| CPU time | 1.19 seconds |
| Started | Aug 21 06:55:11 AM UTC 24 |
| Finished | Aug 21 06:55:13 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=1743722373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1743722373 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1818366944 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 43810148 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:11 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1818366944 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1818366944 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.2912533116 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 11792844 ps |
| CPU time | 0.66 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:11 AM UTC 24 |
| Peak memory | 201304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2912533116 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2912533116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.339376267 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 37237250 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:12 AM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33 9376267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr _outstanding.339376267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.4087357655 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 242397489 ps |
| CPU time | 2.56 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:13 AM UTC 24 |
| Peak memory | 204648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4087357655 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4087357655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.2932958878 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 75148380 ps |
| CPU time | 1.43 seconds |
| Started | Aug 21 06:55:09 AM UTC 24 |
| Finished | Aug 21 06:55:12 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2932958878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2932958878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4101627488 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 172968166 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:15 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=4101627488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.4101627488 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1395619324 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 13001396 ps |
| CPU time | 0.64 seconds |
| Started | Aug 21 06:55:11 AM UTC 24 |
| Finished | Aug 21 06:55:13 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1395619324 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1395619324 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3311818783 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 13793019 ps |
| CPU time | 0.76 seconds |
| Started | Aug 21 06:55:11 AM UTC 24 |
| Finished | Aug 21 06:55:13 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3311818783 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3311818783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3704704208 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 52728486 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:15 AM UTC 24 |
| Peak memory | 201744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37 04704208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.3704704208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3009177487 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 231350787 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 06:55:11 AM UTC 24 |
| Finished | Aug 21 06:55:14 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009177487 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3009177487 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.481023008 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 972323455 ps |
| CPU time | 1.47 seconds |
| Started | Aug 21 06:55:11 AM UTC 24 |
| Finished | Aug 21 06:55:14 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=481023008 - assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.481023008 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1455072680 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 23018279 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:15 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=1455072680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1455072680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.448032420 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 48822555 ps |
| CPU time | 0.75 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:15 AM UTC 24 |
| Peak memory | 201688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448032420 -assert no postproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.448032420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1506652549 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 14439197 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:15 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1506652549 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1506652549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1501376293 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 100772132 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:15 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15 01376293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.1501376293 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.4155598070 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 101870587 ps |
| CPU time | 2.65 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:17 AM UTC 24 |
| Peak memory | 204684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4155598070 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.4155598070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3503036038 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 176201696 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:15 AM UTC 24 |
| Peak memory | 201652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3503036038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3503036038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2356355505 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 79436734 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 06:55:15 AM UTC 24 |
| Finished | Aug 21 06:55:17 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=2356355505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2356355505 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.379445864 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 26198104 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 06:55:15 AM UTC 24 |
| Finished | Aug 21 06:55:17 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=379445864 -assert no postproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.379445864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.1281165447 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 33341436 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 06:55:15 AM UTC 24 |
| Finished | Aug 21 06:55:17 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1281165447 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1281165447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1015318670 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 22124045 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 06:55:15 AM UTC 24 |
| Finished | Aug 21 06:55:17 AM UTC 24 |
| Peak memory | 203744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10 15318670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.1015318670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.351894648 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 91113878 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 06:55:13 AM UTC 24 |
| Finished | Aug 21 06:55:16 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=351894648 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.351894648 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3495778424 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 51258990 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 06:55:15 AM UTC 24 |
| Finished | Aug 21 06:55:17 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3495778424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3495778424 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3516011938 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 57414545 ps |
| CPU time | 1.04 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:20 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=3516011938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3516011938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.303039427 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 16879686 ps |
| CPU time | 0.93 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:20 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=303039427 -assert no postproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.303039427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3312531141 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 71295821 ps |
| CPU time | 0.78 seconds |
| Started | Aug 21 06:55:15 AM UTC 24 |
| Finished | Aug 21 06:55:17 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3312531141 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3312531141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.1526245088 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 22934212 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:20 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15 26245088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs r_outstanding.1526245088 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.3017113590 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 25794576 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 06:55:15 AM UTC 24 |
| Finished | Aug 21 06:55:18 AM UTC 24 |
| Peak memory | 201584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3017113590 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3017113590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.3179829850 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 353612496 ps |
| CPU time | 1.4 seconds |
| Started | Aug 21 06:55:15 AM UTC 24 |
| Finished | Aug 21 06:55:18 AM UTC 24 |
| Peak memory | 201652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3179829850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3179829850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2643524671 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 94541750 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:20 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=2643524671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2643524671 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.2534351010 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 22357000 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:20 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2534351010 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2534351010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.3240023973 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 34291776 ps |
| CPU time | 0.61 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:19 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3240023973 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3240023973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.4024933206 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 44052292 ps |
| CPU time | 0.91 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:20 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40 24933206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.4024933206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2622626940 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 70468930 ps |
| CPU time | 1.93 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:21 AM UTC 24 |
| Peak memory | 203632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2622626940 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2622626940 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2772857452 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 42577548 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:20 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2772857452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2772857452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3793726445 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 20725780 ps |
| CPU time | 1 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=3793726445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3793726445 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3946738788 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 186515609 ps |
| CPU time | 0.75 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3946738788 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3946738788 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.1499402870 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 109816994 ps |
| CPU time | 0.56 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:20 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1499402870 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1499402870 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2111570971 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 12686845 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 203680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21 11570971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.2111570971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.800630751 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 272432711 ps |
| CPU time | 2.31 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:21 AM UTC 24 |
| Peak memory | 202620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=800630751 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.800630751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2924234862 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 396401617 ps |
| CPU time | 1.99 seconds |
| Started | Aug 21 06:55:18 AM UTC 24 |
| Finished | Aug 21 06:55:21 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2924234862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2924234862 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.617435683 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 23812561 ps |
| CPU time | 0.98 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=617435683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.617435683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.1733533805 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 16507958 ps |
| CPU time | 0.89 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1733533805 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1733533805 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3950783613 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 20658732 ps |
| CPU time | 0.75 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950783613 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3950783613 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.4104603798 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 120078165 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 201760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41 04603798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.4104603798 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.800019964 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 108068457 ps |
| CPU time | 1.99 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:23 AM UTC 24 |
| Peak memory | 201584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=800019964 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.800019964 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1270340545 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 178198879 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 06:55:20 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 201652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1270340545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1270340545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3503537475 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 30978297 ps |
| CPU time | 0.95 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=3503537475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3503537475 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.1736286950 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 20127844 ps |
| CPU time | 0.76 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1736286950 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1736286950 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.3988029275 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 33086450 ps |
| CPU time | 0.57 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988029275 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3988029275 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1473823348 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 27684665 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14 73823348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.1473823348 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.523351517 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 198105168 ps |
| CPU time | 1.26 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=523351517 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.523351517 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.916629844 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 136867911 ps |
| CPU time | 0.92 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=916629844 - assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.916629844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.4156812515 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 18875457 ps |
| CPU time | 1.14 seconds |
| Started | Aug 21 06:54:54 AM UTC 24 |
| Finished | Aug 21 06:54:56 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4156812515 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.4156812515 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.634075866 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 258502560 ps |
| CPU time | 3.04 seconds |
| Started | Aug 21 06:54:53 AM UTC 24 |
| Finished | Aug 21 06:54:57 AM UTC 24 |
| Peak memory | 202836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=634075866 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.634075866 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.4259824555 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 45317516 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:54:53 AM UTC 24 |
| Finished | Aug 21 06:54:55 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4259824555 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4259824555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.7133197 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 57366828 ps |
| CPU time | 1.28 seconds |
| Started | Aug 21 06:54:54 AM UTC 24 |
| Finished | Aug 21 06:54:56 AM UTC 24 |
| Peak memory | 201684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=7133197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.7133197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.979432733 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 16805194 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:54:52 AM UTC 24 |
| Finished | Aug 21 06:54:53 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=979432733 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.979432733 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1126472536 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 71770318 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 06:54:54 AM UTC 24 |
| Finished | Aug 21 06:54:56 AM UTC 24 |
| Peak memory | 201700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11 26472536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.1126472536 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.277548691 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 618818718 ps |
| CPU time | 1.78 seconds |
| Started | Aug 21 06:54:51 AM UTC 24 |
| Finished | Aug 21 06:54:53 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=277548691 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.277548691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.956006759 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 445803943 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 06:54:51 AM UTC 24 |
| Finished | Aug 21 06:54:53 AM UTC 24 |
| Peak memory | 201652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=956006759 - assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.956006759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.3193463675 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 27771676 ps |
| CPU time | 0.72 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3193463675 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3193463675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.592507304 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 31511874 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=592507304 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.592507304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.360659943 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 15284114 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360659943 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.360659943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.3128041202 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 12849156 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3128041202 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3128041202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3552217172 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 18921307 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3552217172 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3552217172 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2146067949 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 37798260 ps |
| CPU time | 0.72 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2146067949 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2146067949 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2425508220 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 14141772 ps |
| CPU time | 0.69 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2425508220 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2425508220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1288697641 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 64899782 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1288697641 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1288697641 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.2869167022 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 31297711 ps |
| CPU time | 0.67 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2869167022 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2869167022 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.1346084705 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 12937596 ps |
| CPU time | 0.68 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1346084705 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1346084705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1385634591 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 79176311 ps |
| CPU time | 1 seconds |
| Started | Aug 21 06:54:57 AM UTC 24 |
| Finished | Aug 21 06:54:59 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1385634591 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1385634591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.1741165283 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 135966803 ps |
| CPU time | 2.02 seconds |
| Started | Aug 21 06:54:57 AM UTC 24 |
| Finished | Aug 21 06:55:00 AM UTC 24 |
| Peak memory | 202828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1741165283 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1741165283 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3300219393 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 43697451 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:54:56 AM UTC 24 |
| Finished | Aug 21 06:54:57 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3300219393 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3300219393 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3081804547 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 24943636 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 06:54:58 AM UTC 24 |
| Finished | Aug 21 06:55:00 AM UTC 24 |
| Peak memory | 201564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=3081804547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3081804547 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2731125199 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 32564119 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:54:56 AM UTC 24 |
| Finished | Aug 21 06:54:57 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2731125199 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2731125199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3255188243 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 53917971 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:54:54 AM UTC 24 |
| Finished | Aug 21 06:54:56 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3255188243 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3255188243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1056951031 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 16006084 ps |
| CPU time | 0.94 seconds |
| Started | Aug 21 06:54:57 AM UTC 24 |
| Finished | Aug 21 06:54:59 AM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10 56951031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.1056951031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2397955680 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 539893827 ps |
| CPU time | 3.24 seconds |
| Started | Aug 21 06:54:54 AM UTC 24 |
| Finished | Aug 21 06:54:59 AM UTC 24 |
| Peak memory | 204788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2397955680 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2397955680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2961168783 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 50387544 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 06:54:54 AM UTC 24 |
| Finished | Aug 21 06:54:57 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2961168783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2961168783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.4233146533 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 44829968 ps |
| CPU time | 0.64 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4233146533 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.4233146533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.1298972179 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 24485325 ps |
| CPU time | 0.61 seconds |
| Started | Aug 21 06:55:24 AM UTC 24 |
| Finished | Aug 21 06:55:26 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1298972179 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1298972179 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.914780182 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 14951260 ps |
| CPU time | 0.72 seconds |
| Started | Aug 21 06:55:26 AM UTC 24 |
| Finished | Aug 21 06:55:28 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=914780182 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.914780182 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.3058788006 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 33566076 ps |
| CPU time | 0.62 seconds |
| Started | Aug 21 06:55:26 AM UTC 24 |
| Finished | Aug 21 06:55:28 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3058788006 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3058788006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3555815581 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 14855801 ps |
| CPU time | 0.69 seconds |
| Started | Aug 21 06:55:26 AM UTC 24 |
| Finished | Aug 21 06:55:28 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3555815581 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3555815581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.2338958382 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 12517696 ps |
| CPU time | 0.6 seconds |
| Started | Aug 21 06:55:26 AM UTC 24 |
| Finished | Aug 21 06:55:28 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2338958382 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2338958382 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2128941844 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 30100805 ps |
| CPU time | 0.55 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:32 AM UTC 24 |
| Peak memory | 201528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128941844 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2128941844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.797751350 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 26146455 ps |
| CPU time | 0.58 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:32 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=797751350 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.797751350 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3528966426 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 14481912 ps |
| CPU time | 0.59 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3528966426 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3528966426 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3443158712 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 13747397 ps |
| CPU time | 0.69 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3443158712 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3443158712 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.3703052077 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 21342676 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 06:55:00 AM UTC 24 |
| Finished | Aug 21 06:55:02 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703052077 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3703052077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.1410545901 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 454169952 ps |
| CPU time | 2.87 seconds |
| Started | Aug 21 06:55:00 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 202892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1410545901 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1410545901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.4208404687 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 13257993 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 06:54:58 AM UTC 24 |
| Finished | Aug 21 06:55:00 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4208404687 -as sert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.4208404687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.257567603 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 548294854 ps |
| CPU time | 1.25 seconds |
| Started | Aug 21 06:55:00 AM UTC 24 |
| Finished | Aug 21 06:55:02 AM UTC 24 |
| Peak memory | 201624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=257567603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.257567603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.551917025 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 41635554 ps |
| CPU time | 0.92 seconds |
| Started | Aug 21 06:54:58 AM UTC 24 |
| Finished | Aug 21 06:55:00 AM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551917025 -assert no postproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.551917025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.1182250287 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 27485621 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:54:58 AM UTC 24 |
| Finished | Aug 21 06:55:00 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1182250287 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1182250287 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.944260292 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 50975023 ps |
| CPU time | 1.05 seconds |
| Started | Aug 21 06:55:00 AM UTC 24 |
| Finished | Aug 21 06:55:02 AM UTC 24 |
| Peak memory | 205728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94 4260292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_ outstanding.944260292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.1770716088 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 107607991 ps |
| CPU time | 1.24 seconds |
| Started | Aug 21 06:54:58 AM UTC 24 |
| Finished | Aug 21 06:55:00 AM UTC 24 |
| Peak memory | 201584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1770716088 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1770716088 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1249730981 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 50416332 ps |
| CPU time | 1.35 seconds |
| Started | Aug 21 06:54:58 AM UTC 24 |
| Finished | Aug 21 06:55:01 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1249730981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1249730981 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1476177620 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 42748568 ps |
| CPU time | 0.73 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1476177620 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1476177620 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3880710836 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 47966454 ps |
| CPU time | 0.69 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3880710836 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3880710836 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.537513324 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 32805562 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=537513324 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.537513324 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3351336112 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 37703709 ps |
| CPU time | 0.63 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3351336112 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3351336112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.3799985994 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 13549295 ps |
| CPU time | 0.71 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3799985994 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3799985994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.137729155 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 51212911 ps |
| CPU time | 0.74 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=137729155 -assert nopos tproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.137729155 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2782664080 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 35142793 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2782664080 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2782664080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.1928244619 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 16150097 ps |
| CPU time | 0.7 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1928244619 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1928244619 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.3324258572 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 109060442 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3324258572 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3324258572 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.1660569354 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 58115084 ps |
| CPU time | 0.69 seconds |
| Started | Aug 21 06:55:31 AM UTC 24 |
| Finished | Aug 21 06:55:33 AM UTC 24 |
| Peak memory | 201568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660569354 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1660569354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3232743190 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 88579519 ps |
| CPU time | 1.02 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 201564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=3232743190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3232743190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.75473996 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 20703498 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=75473996 -assert nop ostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.75473996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3393584392 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 15655538 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3393584392 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3393584392 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.2518821253 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 31244208 ps |
| CPU time | 1.08 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 205732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25 18821253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.2518821253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.2877233357 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 415158272 ps |
| CPU time | 2.64 seconds |
| Started | Aug 21 06:55:00 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 204852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2877233357 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2877233357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3537405498 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 118595156 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3537405498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3537405498 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2897772516 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 27059045 ps |
| CPU time | 1.2 seconds |
| Started | Aug 21 06:55:03 AM UTC 24 |
| Finished | Aug 21 06:55:06 AM UTC 24 |
| Peak memory | 201564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=2897772516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2897772516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1237246064 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 14915783 ps |
| CPU time | 0.86 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1237246064 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1237246064 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.1819200897 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 29322923 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1819200897 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1819200897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.955835696 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 20802879 ps |
| CPU time | 0.97 seconds |
| Started | Aug 21 06:55:03 AM UTC 24 |
| Finished | Aug 21 06:55:05 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=95 5835696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_ outstanding.955835696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3175026999 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 125053857 ps |
| CPU time | 1.65 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:05 AM UTC 24 |
| Peak memory | 201584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175026999 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3175026999 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.2343795425 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 263058297 ps |
| CPU time | 1.36 seconds |
| Started | Aug 21 06:55:02 AM UTC 24 |
| Finished | Aug 21 06:55:04 AM UTC 24 |
| Peak memory | 201688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2343795425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2343795425 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1614483420 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 38790690 ps |
| CPU time | 0.99 seconds |
| Started | Aug 21 06:55:05 AM UTC 24 |
| Finished | Aug 21 06:55:07 AM UTC 24 |
| Peak memory | 201624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=1614483420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1614483420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3663479703 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 39748334 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 06:55:05 AM UTC 24 |
| Finished | Aug 21 06:55:07 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3663479703 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3663479703 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.1785715688 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 29911386 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:55:05 AM UTC 24 |
| Finished | Aug 21 06:55:07 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1785715688 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1785715688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.764938549 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 15977710 ps |
| CPU time | 1.03 seconds |
| Started | Aug 21 06:55:05 AM UTC 24 |
| Finished | Aug 21 06:55:08 AM UTC 24 |
| Peak memory | 201632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=76 4938549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_ outstanding.764938549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.1614692038 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 33481475 ps |
| CPU time | 1.97 seconds |
| Started | Aug 21 06:55:03 AM UTC 24 |
| Finished | Aug 21 06:55:06 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1614692038 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1614692038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2339323679 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 34194604 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:55:06 AM UTC 24 |
| Finished | Aug 21 06:55:08 AM UTC 24 |
| Peak memory | 201564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=2339323679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2339323679 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.3379928451 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 23331993 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:55:06 AM UTC 24 |
| Finished | Aug 21 06:55:07 AM UTC 24 |
| Peak memory | 201696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3379928451 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3379928451 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.3140445451 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 14838335 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:55:06 AM UTC 24 |
| Finished | Aug 21 06:55:07 AM UTC 24 |
| Peak memory | 201628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3140445451 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3140445451 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.2523427345 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 140510047 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 06:55:06 AM UTC 24 |
| Finished | Aug 21 06:55:08 AM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25 23427345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.2523427345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.4082168104 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 331994098 ps |
| CPU time | 1.84 seconds |
| Started | Aug 21 06:55:06 AM UTC 24 |
| Finished | Aug 21 06:55:08 AM UTC 24 |
| Peak memory | 203632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4082168104 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.4082168104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3760912131 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 47154850 ps |
| CPU time | 1.34 seconds |
| Started | Aug 21 06:55:06 AM UTC 24 |
| Finished | Aug 21 06:55:08 AM UTC 24 |
| Peak memory | 201692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3760912131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3760912131 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2229961514 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 59215297 ps |
| CPU time | 1.3 seconds |
| Started | Aug 21 06:55:07 AM UTC 24 |
| Finished | Aug 21 06:55:10 AM UTC 24 |
| Peak memory | 201564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1 0000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/d v/tools/sim.tcl +ntb_random_seed=2229961514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2229961514 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2241271823 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 28240061 ps |
| CPU time | 0.9 seconds |
| Started | Aug 21 06:55:07 AM UTC 24 |
| Finished | Aug 21 06:55:09 AM UTC 24 |
| Peak memory | 201248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2241271823 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2241271823 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.3205831915 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 51548786 ps |
| CPU time | 0.76 seconds |
| Started | Aug 21 06:55:07 AM UTC 24 |
| Finished | Aug 21 06:55:09 AM UTC 24 |
| Peak memory | 200928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3205831915 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3205831915 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.3751105041 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 58648943 ps |
| CPU time | 1.09 seconds |
| Started | Aug 21 06:55:07 AM UTC 24 |
| Finished | Aug 21 06:55:09 AM UTC 24 |
| Peak memory | 201636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37 51105041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.3751105041 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.3007440258 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 84692578 ps |
| CPU time | 1.59 seconds |
| Started | Aug 21 06:55:06 AM UTC 24 |
| Finished | Aug 21 06:55:08 AM UTC 24 |
| Peak memory | 203632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007440258 -assert nopo stproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3007440258 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.1992394680 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 81876086 ps |
| CPU time | 1.85 seconds |
| Started | Aug 21 06:55:07 AM UTC 24 |
| Finished | Aug 21 06:55:10 AM UTC 24 |
| Peak memory | 200860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1992394680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1992394680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.526835295 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29173824841 ps |
| CPU time | 24.04 seconds |
| Started | Aug 21 06:15:39 AM UTC 24 |
| Finished | Aug 21 06:16:04 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=526835295 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.526835295 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.413239535 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 236035573493 ps |
| CPU time | 200.35 seconds |
| Started | Aug 21 06:16:14 AM UTC 24 |
| Finished | Aug 21 06:19:38 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=413239535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.413239535 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_perf.1574752376 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 14852031451 ps |
| CPU time | 269.86 seconds |
| Started | Aug 21 06:16:11 AM UTC 24 |
| Finished | Aug 21 06:20:46 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1574752376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1574752376 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_rx_oversample.3455772987 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3875585268 ps |
| CPU time | 17.15 seconds |
| Started | Aug 21 06:15:42 AM UTC 24 |
| Finished | Aug 21 06:16:00 AM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3455772987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3455772987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.1944683011 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 108694421059 ps |
| CPU time | 155.88 seconds |
| Started | Aug 21 06:16:05 AM UTC 24 |
| Finished | Aug 21 06:18:44 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1944683011 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1944683011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.525351515 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 49908315403 ps |
| CPU time | 109.55 seconds |
| Started | Aug 21 06:16:03 AM UTC 24 |
| Finished | Aug 21 06:17:55 AM UTC 24 |
| Peak memory | 207348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=525351515 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.525351515 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_smoke.2820196909 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 983302268 ps |
| CPU time | 2.72 seconds |
| Started | Aug 21 06:15:31 AM UTC 24 |
| Finished | Aug 21 06:15:35 AM UTC 24 |
| Peak memory | 208612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2820196909 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2820196909 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.1309126513 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1430829219 ps |
| CPU time | 10.96 seconds |
| Started | Aug 21 06:16:08 AM UTC 24 |
| Finished | Aug 21 06:16:20 AM UTC 24 |
| Peak memory | 207324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1309126513 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1309126513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/0.uart_tx_rx.634717213 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1474700246 ps |
| CPU time | 5.64 seconds |
| Started | Aug 21 06:15:34 AM UTC 24 |
| Finished | Aug 21 06:15:41 AM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=634717213 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.634717213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/0.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_alert_test.3156065971 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 31885422 ps |
| CPU time | 0.74 seconds |
| Started | Aug 21 06:18:04 AM UTC 24 |
| Finished | Aug 21 06:18:06 AM UTC 24 |
| Peak memory | 202476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3156065971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3156065971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_intr.2170034497 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 23883386119 ps |
| CPU time | 28.44 seconds |
| Started | Aug 21 06:17:23 AM UTC 24 |
| Finished | Aug 21 06:17:53 AM UTC 24 |
| Peak memory | 208164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2170034497 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2170034497 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.1231153207 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 140183283222 ps |
| CPU time | 85.94 seconds |
| Started | Aug 21 06:17:53 AM UTC 24 |
| Finished | Aug 21 06:19:20 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1231153207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1231153207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_loopback.4240883711 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5261192413 ps |
| CPU time | 18.3 seconds |
| Started | Aug 21 06:17:51 AM UTC 24 |
| Finished | Aug 21 06:18:10 AM UTC 24 |
| Peak memory | 207348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4240883711 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.4240883711 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_noise_filter.3947380844 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 45604607380 ps |
| CPU time | 116.5 seconds |
| Started | Aug 21 06:17:40 AM UTC 24 |
| Finished | Aug 21 06:19:39 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3947380844 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3947380844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_perf.2794214193 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3269581832 ps |
| CPU time | 236.96 seconds |
| Started | Aug 21 06:17:52 AM UTC 24 |
| Finished | Aug 21 06:21:52 AM UTC 24 |
| Peak memory | 208972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2794214193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2794214193 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_rx_oversample.1837873767 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6579501238 ps |
| CPU time | 20.55 seconds |
| Started | Aug 21 06:17:22 AM UTC 24 |
| Finished | Aug 21 06:17:44 AM UTC 24 |
| Peak memory | 207820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837873767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1837873767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.189852134 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 24224531242 ps |
| CPU time | 24.16 seconds |
| Started | Aug 21 06:17:44 AM UTC 24 |
| Finished | Aug 21 06:18:10 AM UTC 24 |
| Peak memory | 208860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=189852134 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.189852134 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.2429008660 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3044141982 ps |
| CPU time | 5.53 seconds |
| Started | Aug 21 06:17:43 AM UTC 24 |
| Finished | Aug 21 06:17:50 AM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2429008660 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2429008660 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_sec_cm.504462253 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 156483938 ps |
| CPU time | 1.13 seconds |
| Started | Aug 21 06:18:01 AM UTC 24 |
| Finished | Aug 21 06:18:03 AM UTC 24 |
| Peak memory | 237480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=504462253 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.504462253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_smoke.2847292803 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5811187353 ps |
| CPU time | 14.92 seconds |
| Started | Aug 21 06:16:39 AM UTC 24 |
| Finished | Aug 21 06:16:55 AM UTC 24 |
| Peak memory | 208600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2847292803 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2847292803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.774306179 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1063433374 ps |
| CPU time | 6.03 seconds |
| Started | Aug 21 06:17:44 AM UTC 24 |
| Finished | Aug 21 06:17:52 AM UTC 24 |
| Peak memory | 208552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774306179 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.774306179 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/1.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_alert_test.2557598545 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 20875975 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:23:27 AM UTC 24 |
| Finished | Aug 21 06:23:29 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2557598545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2557598545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2572789870 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 32112278230 ps |
| CPU time | 29.23 seconds |
| Started | Aug 21 06:23:12 AM UTC 24 |
| Finished | Aug 21 06:23:42 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2572789870 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2572789870 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3715485080 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 61699229403 ps |
| CPU time | 125.09 seconds |
| Started | Aug 21 06:23:13 AM UTC 24 |
| Finished | Aug 21 06:25:20 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3715485080 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3715485080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.162388263 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 74607135225 ps |
| CPU time | 151.79 seconds |
| Started | Aug 21 06:23:26 AM UTC 24 |
| Finished | Aug 21 06:26:00 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=162388263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.162388263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_loopback.4281037194 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 5088345792 ps |
| CPU time | 11.01 seconds |
| Started | Aug 21 06:23:24 AM UTC 24 |
| Finished | Aug 21 06:23:37 AM UTC 24 |
| Peak memory | 207552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4281037194 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.4281037194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_perf.3003344256 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 11876067086 ps |
| CPU time | 186.49 seconds |
| Started | Aug 21 06:23:26 AM UTC 24 |
| Finished | Aug 21 06:26:35 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3003344256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3003344256 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_rx_oversample.1204549920 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3601943688 ps |
| CPU time | 5.66 seconds |
| Started | Aug 21 06:23:14 AM UTC 24 |
| Finished | Aug 21 06:23:21 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1204549920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1204549920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.2107197368 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 16744350947 ps |
| CPU time | 19.45 seconds |
| Started | Aug 21 06:23:20 AM UTC 24 |
| Finished | Aug 21 06:23:41 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2107197368 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2107197368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.3435250141 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 6610319743 ps |
| CPU time | 5.31 seconds |
| Started | Aug 21 06:23:18 AM UTC 24 |
| Finished | Aug 21 06:23:25 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3435250141 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3435250141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_smoke.2526891401 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 507054078 ps |
| CPU time | 1.87 seconds |
| Started | Aug 21 06:23:08 AM UTC 24 |
| Finished | Aug 21 06:23:11 AM UTC 24 |
| Peak memory | 207696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526891401 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2526891401 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.1372893726 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5508846126 ps |
| CPU time | 47.17 seconds |
| Started | Aug 21 06:23:26 AM UTC 24 |
| Finished | Aug 21 06:24:14 AM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1372893726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1372893726 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.1684445842 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 980153980 ps |
| CPU time | 4.62 seconds |
| Started | Aug 21 06:23:21 AM UTC 24 |
| Finished | Aug 21 06:23:27 AM UTC 24 |
| Peak memory | 208612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1684445842 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1684445842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/10.uart_tx_rx.3498096189 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 16955998839 ps |
| CPU time | 15.72 seconds |
| Started | Aug 21 06:23:10 AM UTC 24 |
| Finished | Aug 21 06:23:27 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3498096189 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3498096189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/10.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/100.uart_fifo_reset.2412593225 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 7939794621 ps |
| CPU time | 30.97 seconds |
| Started | Aug 21 06:48:51 AM UTC 24 |
| Finished | Aug 21 06:49:23 AM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2412593225 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2412593225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/100.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/101.uart_fifo_reset.3590830083 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 34331298001 ps |
| CPU time | 85.78 seconds |
| Started | Aug 21 06:48:54 AM UTC 24 |
| Finished | Aug 21 06:50:22 AM UTC 24 |
| Peak memory | 208800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3590830083 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3590830083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/101.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/102.uart_fifo_reset.503974442 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 114344749227 ps |
| CPU time | 51.78 seconds |
| Started | Aug 21 06:48:54 AM UTC 24 |
| Finished | Aug 21 06:49:48 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=503974442 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.503974442 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/102.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/104.uart_fifo_reset.830338611 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 21124456353 ps |
| CPU time | 45.51 seconds |
| Started | Aug 21 06:48:59 AM UTC 24 |
| Finished | Aug 21 06:49:47 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=830338611 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.830338611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/104.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/105.uart_fifo_reset.2686512566 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 88643606332 ps |
| CPU time | 50.39 seconds |
| Started | Aug 21 06:49:00 AM UTC 24 |
| Finished | Aug 21 06:49:52 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2686512566 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2686512566 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/105.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/106.uart_fifo_reset.4101147660 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 77583603235 ps |
| CPU time | 83.54 seconds |
| Started | Aug 21 06:49:02 AM UTC 24 |
| Finished | Aug 21 06:50:27 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4101147660 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4101147660 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/106.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/107.uart_fifo_reset.3614196421 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 44576679253 ps |
| CPU time | 20.98 seconds |
| Started | Aug 21 06:49:03 AM UTC 24 |
| Finished | Aug 21 06:49:25 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3614196421 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3614196421 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/107.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/108.uart_fifo_reset.2303996753 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 39390318212 ps |
| CPU time | 114.55 seconds |
| Started | Aug 21 06:49:03 AM UTC 24 |
| Finished | Aug 21 06:50:59 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2303996753 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2303996753 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/108.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/109.uart_fifo_reset.2347093277 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 42407289607 ps |
| CPU time | 68.16 seconds |
| Started | Aug 21 06:49:06 AM UTC 24 |
| Finished | Aug 21 06:50:16 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347093277 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2347093277 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/109.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_alert_test.3093356592 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 12252057 ps |
| CPU time | 0.66 seconds |
| Started | Aug 21 06:23:52 AM UTC 24 |
| Finished | Aug 21 06:23:54 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3093356592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3093356592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_fifo_reset.883320325 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 29435663194 ps |
| CPU time | 94.35 seconds |
| Started | Aug 21 06:23:31 AM UTC 24 |
| Finished | Aug 21 06:25:08 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=883320325 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.883320325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_intr.3314703220 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 312479506192 ps |
| CPU time | 475.28 seconds |
| Started | Aug 21 06:23:35 AM UTC 24 |
| Finished | Aug 21 06:31:36 AM UTC 24 |
| Peak memory | 208552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3314703220 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3314703220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.2713753693 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 201005407397 ps |
| CPU time | 294.7 seconds |
| Started | Aug 21 06:23:46 AM UTC 24 |
| Finished | Aug 21 06:28:45 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2713753693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2713753693 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_loopback.3127545428 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 7129568476 ps |
| CPU time | 6.87 seconds |
| Started | Aug 21 06:23:46 AM UTC 24 |
| Finished | Aug 21 06:23:54 AM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3127545428 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3127545428 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_noise_filter.2830755124 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 183392902328 ps |
| CPU time | 79.89 seconds |
| Started | Aug 21 06:23:35 AM UTC 24 |
| Finished | Aug 21 06:24:57 AM UTC 24 |
| Peak memory | 209020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2830755124 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2830755124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_perf.1719996296 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 29062126878 ps |
| CPU time | 1483.21 seconds |
| Started | Aug 21 06:23:46 AM UTC 24 |
| Finished | Aug 21 06:48:45 AM UTC 24 |
| Peak memory | 212248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1719996296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1719996296 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_rx_oversample.1521259635 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 6979527373 ps |
| CPU time | 15.8 seconds |
| Started | Aug 21 06:23:31 AM UTC 24 |
| Finished | Aug 21 06:23:48 AM UTC 24 |
| Peak memory | 207304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1521259635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1521259635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.4276155633 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 70933014100 ps |
| CPU time | 54.97 seconds |
| Started | Aug 21 06:23:42 AM UTC 24 |
| Finished | Aug 21 06:24:38 AM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4276155633 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4276155633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.1684789602 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1792818329 ps |
| CPU time | 6.48 seconds |
| Started | Aug 21 06:23:37 AM UTC 24 |
| Finished | Aug 21 06:23:45 AM UTC 24 |
| Peak memory | 204968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1684789602 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1684789602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_smoke.463967945 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 888627027 ps |
| CPU time | 6.83 seconds |
| Started | Aug 21 06:23:27 AM UTC 24 |
| Finished | Aug 21 06:23:35 AM UTC 24 |
| Peak memory | 207664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=463967945 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.463967945 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_stress_all.249810141 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 263834820613 ps |
| CPU time | 123.58 seconds |
| Started | Aug 21 06:23:49 AM UTC 24 |
| Finished | Aug 21 06:25:55 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=249810141 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.249810141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.588957948 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 576181267 ps |
| CPU time | 2.76 seconds |
| Started | Aug 21 06:23:44 AM UTC 24 |
| Finished | Aug 21 06:23:47 AM UTC 24 |
| Peak memory | 208296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=588957948 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.588957948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/11.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/111.uart_fifo_reset.271998835 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 78099904278 ps |
| CPU time | 109.71 seconds |
| Started | Aug 21 06:49:09 AM UTC 24 |
| Finished | Aug 21 06:51:01 AM UTC 24 |
| Peak memory | 208980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=271998835 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.271998835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/111.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/112.uart_fifo_reset.3997248127 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 50775977816 ps |
| CPU time | 55.69 seconds |
| Started | Aug 21 06:49:09 AM UTC 24 |
| Finished | Aug 21 06:50:06 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3997248127 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3997248127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/112.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/113.uart_fifo_reset.4210197991 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 186735458634 ps |
| CPU time | 378.1 seconds |
| Started | Aug 21 06:49:12 AM UTC 24 |
| Finished | Aug 21 06:55:35 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4210197991 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4210197991 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/113.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/115.uart_fifo_reset.2008335222 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 93218778986 ps |
| CPU time | 194.05 seconds |
| Started | Aug 21 06:49:14 AM UTC 24 |
| Finished | Aug 21 06:52:32 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2008335222 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2008335222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/115.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/116.uart_fifo_reset.106837101 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 124942087040 ps |
| CPU time | 304.07 seconds |
| Started | Aug 21 06:49:15 AM UTC 24 |
| Finished | Aug 21 06:54:24 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=106837101 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.106837101 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/116.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/117.uart_fifo_reset.3101005966 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 20253000423 ps |
| CPU time | 15.42 seconds |
| Started | Aug 21 06:49:16 AM UTC 24 |
| Finished | Aug 21 06:49:33 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3101005966 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3101005966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/117.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_alert_test.2726622225 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 38164849 ps |
| CPU time | 0.78 seconds |
| Started | Aug 21 06:24:30 AM UTC 24 |
| Finished | Aug 21 06:24:32 AM UTC 24 |
| Peak memory | 204460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2726622225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2726622225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_fifo_full.3025815764 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 28753441884 ps |
| CPU time | 63.06 seconds |
| Started | Aug 21 06:23:54 AM UTC 24 |
| Finished | Aug 21 06:24:59 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3025815764 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3025815764 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1187855566 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 111581318888 ps |
| CPU time | 750.45 seconds |
| Started | Aug 21 06:23:54 AM UTC 24 |
| Finished | Aug 21 06:36:34 AM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1187855566 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1187855566 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1606221923 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 77893978562 ps |
| CPU time | 233.87 seconds |
| Started | Aug 21 06:23:56 AM UTC 24 |
| Finished | Aug 21 06:27:54 AM UTC 24 |
| Peak memory | 208548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1606221923 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1606221923 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_intr.3436741038 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 33743904221 ps |
| CPU time | 11.58 seconds |
| Started | Aug 21 06:24:01 AM UTC 24 |
| Finished | Aug 21 06:24:13 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3436741038 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3436741038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1122409006 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 100211108545 ps |
| CPU time | 771.17 seconds |
| Started | Aug 21 06:24:24 AM UTC 24 |
| Finished | Aug 21 06:37:24 AM UTC 24 |
| Peak memory | 212280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1122409006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1122409006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_loopback.2100100453 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2278396540 ps |
| CPU time | 8.76 seconds |
| Started | Aug 21 06:24:15 AM UTC 24 |
| Finished | Aug 21 06:24:25 AM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100100453 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2100100453 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_noise_filter.2475173162 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 35245178345 ps |
| CPU time | 80.57 seconds |
| Started | Aug 21 06:24:02 AM UTC 24 |
| Finished | Aug 21 06:25:24 AM UTC 24 |
| Peak memory | 208868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2475173162 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2475173162 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_perf.2674559760 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 12065469582 ps |
| CPU time | 610.58 seconds |
| Started | Aug 21 06:24:18 AM UTC 24 |
| Finished | Aug 21 06:34:36 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2674559760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2674559760 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_rx_oversample.2768340767 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6332031516 ps |
| CPU time | 80.16 seconds |
| Started | Aug 21 06:23:57 AM UTC 24 |
| Finished | Aug 21 06:25:19 AM UTC 24 |
| Peak memory | 207340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2768340767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2768340767 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.3043368536 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 25350332759 ps |
| CPU time | 46.19 seconds |
| Started | Aug 21 06:24:10 AM UTC 24 |
| Finished | Aug 21 06:24:57 AM UTC 24 |
| Peak memory | 208528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3043368536 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3043368536 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.1380639027 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 40433441218 ps |
| CPU time | 29.4 seconds |
| Started | Aug 21 06:24:09 AM UTC 24 |
| Finished | Aug 21 06:24:39 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1380639027 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1380639027 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_smoke.3683950998 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 895247100 ps |
| CPU time | 1.58 seconds |
| Started | Aug 21 06:23:53 AM UTC 24 |
| Finished | Aug 21 06:23:56 AM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3683950998 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3683950998 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.4079639480 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2918665672 ps |
| CPU time | 43.7 seconds |
| Started | Aug 21 06:24:25 AM UTC 24 |
| Finished | Aug 21 06:25:10 AM UTC 24 |
| Peak memory | 222100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4079639480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4079639480 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.1244484090 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 986265298 ps |
| CPU time | 2.79 seconds |
| Started | Aug 21 06:24:14 AM UTC 24 |
| Finished | Aug 21 06:24:18 AM UTC 24 |
| Peak memory | 207308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1244484090 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1244484090 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/12.uart_tx_rx.2162853710 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 48810396597 ps |
| CPU time | 44.11 seconds |
| Started | Aug 21 06:23:54 AM UTC 24 |
| Finished | Aug 21 06:24:40 AM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2162853710 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2162853710 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/12.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/120.uart_fifo_reset.778361084 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 10740881869 ps |
| CPU time | 35.13 seconds |
| Started | Aug 21 06:49:24 AM UTC 24 |
| Finished | Aug 21 06:50:00 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=778361084 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.778361084 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/120.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/122.uart_fifo_reset.3156277041 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 78496878907 ps |
| CPU time | 134.58 seconds |
| Started | Aug 21 06:49:25 AM UTC 24 |
| Finished | Aug 21 06:51:42 AM UTC 24 |
| Peak memory | 208432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3156277041 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3156277041 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/122.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/123.uart_fifo_reset.2896139910 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 149189823709 ps |
| CPU time | 52.07 seconds |
| Started | Aug 21 06:49:26 AM UTC 24 |
| Finished | Aug 21 06:50:20 AM UTC 24 |
| Peak memory | 208620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2896139910 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2896139910 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/123.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/124.uart_fifo_reset.2262501446 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 58446859683 ps |
| CPU time | 71.41 seconds |
| Started | Aug 21 06:49:29 AM UTC 24 |
| Finished | Aug 21 06:50:42 AM UTC 24 |
| Peak memory | 208600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2262501446 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2262501446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/124.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/125.uart_fifo_reset.2471533768 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 201817970839 ps |
| CPU time | 143.74 seconds |
| Started | Aug 21 06:49:30 AM UTC 24 |
| Finished | Aug 21 06:51:56 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471533768 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2471533768 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/125.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/126.uart_fifo_reset.4187053578 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 106719738813 ps |
| CPU time | 142.42 seconds |
| Started | Aug 21 06:49:30 AM UTC 24 |
| Finished | Aug 21 06:51:55 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4187053578 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4187053578 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/126.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/127.uart_fifo_reset.1660097284 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 38959796539 ps |
| CPU time | 16.9 seconds |
| Started | Aug 21 06:49:31 AM UTC 24 |
| Finished | Aug 21 06:49:49 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660097284 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1660097284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/127.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/129.uart_fifo_reset.425078487 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 47611660702 ps |
| CPU time | 25.27 seconds |
| Started | Aug 21 06:49:36 AM UTC 24 |
| Finished | Aug 21 06:50:03 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=425078487 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.425078487 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/129.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_alert_test.2653564555 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 136877202 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:25:09 AM UTC 24 |
| Finished | Aug 21 06:25:10 AM UTC 24 |
| Peak memory | 204004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2653564555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2653564555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2234800693 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 51964827428 ps |
| CPU time | 58.87 seconds |
| Started | Aug 21 06:24:39 AM UTC 24 |
| Finished | Aug 21 06:25:39 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2234800693 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2234800693 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_fifo_reset.3185766897 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 103048731992 ps |
| CPU time | 100.74 seconds |
| Started | Aug 21 06:24:41 AM UTC 24 |
| Finished | Aug 21 06:26:24 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3185766897 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3185766897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.2951261004 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 110319850811 ps |
| CPU time | 489.69 seconds |
| Started | Aug 21 06:25:05 AM UTC 24 |
| Finished | Aug 21 06:33:21 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2951261004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2951261004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_loopback.3246006133 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 7440317986 ps |
| CPU time | 16.6 seconds |
| Started | Aug 21 06:24:59 AM UTC 24 |
| Finished | Aug 21 06:25:17 AM UTC 24 |
| Peak memory | 208668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246006133 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3246006133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_noise_filter.2798651824 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 84091269719 ps |
| CPU time | 65.69 seconds |
| Started | Aug 21 06:24:54 AM UTC 24 |
| Finished | Aug 21 06:26:01 AM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2798651824 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2798651824 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_perf.3567448175 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 5568537390 ps |
| CPU time | 170.15 seconds |
| Started | Aug 21 06:25:03 AM UTC 24 |
| Finished | Aug 21 06:27:56 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3567448175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3567448175 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3321049548 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6422732345 ps |
| CPU time | 22.12 seconds |
| Started | Aug 21 06:24:41 AM UTC 24 |
| Finished | Aug 21 06:25:04 AM UTC 24 |
| Peak memory | 207892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3321049548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3321049548 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.2303669663 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 56736796743 ps |
| CPU time | 75.33 seconds |
| Started | Aug 21 06:24:58 AM UTC 24 |
| Finished | Aug 21 06:26:15 AM UTC 24 |
| Peak memory | 208860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2303669663 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2303669663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.3586706286 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 35143676083 ps |
| CPU time | 24.18 seconds |
| Started | Aug 21 06:24:56 AM UTC 24 |
| Finished | Aug 21 06:25:21 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3586706286 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3586706286 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_smoke.121333932 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 498803261 ps |
| CPU time | 3.06 seconds |
| Started | Aug 21 06:24:33 AM UTC 24 |
| Finished | Aug 21 06:24:38 AM UTC 24 |
| Peak memory | 207604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121333932 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.121333932 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.1697651579 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 11248285995 ps |
| CPU time | 37.95 seconds |
| Started | Aug 21 06:25:05 AM UTC 24 |
| Finished | Aug 21 06:25:45 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697651579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1697651579 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.3541736042 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1818201430 ps |
| CPU time | 3.02 seconds |
| Started | Aug 21 06:24:58 AM UTC 24 |
| Finished | Aug 21 06:25:02 AM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3541736042 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3541736042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/13.uart_tx_rx.1661766428 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 42176432887 ps |
| CPU time | 93.47 seconds |
| Started | Aug 21 06:24:35 AM UTC 24 |
| Finished | Aug 21 06:26:11 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1661766428 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1661766428 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/13.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/130.uart_fifo_reset.2554805208 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 130766277914 ps |
| CPU time | 67.59 seconds |
| Started | Aug 21 06:49:41 AM UTC 24 |
| Finished | Aug 21 06:50:51 AM UTC 24 |
| Peak memory | 208316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2554805208 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2554805208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/130.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/131.uart_fifo_reset.3149689396 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 54746382554 ps |
| CPU time | 130.17 seconds |
| Started | Aug 21 06:49:43 AM UTC 24 |
| Finished | Aug 21 06:51:55 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3149689396 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3149689396 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/131.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/132.uart_fifo_reset.275712948 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 209545158025 ps |
| CPU time | 327.15 seconds |
| Started | Aug 21 06:49:44 AM UTC 24 |
| Finished | Aug 21 06:55:15 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=275712948 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.275712948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/132.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/133.uart_fifo_reset.4262331924 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 34924513001 ps |
| CPU time | 29.84 seconds |
| Started | Aug 21 06:49:46 AM UTC 24 |
| Finished | Aug 21 06:50:17 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4262331924 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4262331924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/133.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/134.uart_fifo_reset.1987857978 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 42226500581 ps |
| CPU time | 18.45 seconds |
| Started | Aug 21 06:49:48 AM UTC 24 |
| Finished | Aug 21 06:50:07 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1987857978 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1987857978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/134.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/135.uart_fifo_reset.2279585082 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 18879234565 ps |
| CPU time | 41.63 seconds |
| Started | Aug 21 06:49:49 AM UTC 24 |
| Finished | Aug 21 06:50:32 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2279585082 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2279585082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/135.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/136.uart_fifo_reset.1781427773 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 123142676582 ps |
| CPU time | 285.72 seconds |
| Started | Aug 21 06:49:50 AM UTC 24 |
| Finished | Aug 21 06:54:39 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1781427773 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1781427773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/136.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_alert_test.2938974915 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 17411736 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 06:25:29 AM UTC 24 |
| Finished | Aug 21 06:25:31 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2938974915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2938974915 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_fifo_full.2040707441 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 165989725028 ps |
| CPU time | 281.26 seconds |
| Started | Aug 21 06:25:14 AM UTC 24 |
| Finished | Aug 21 06:29:59 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2040707441 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2040707441 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.3526853010 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 16619085621 ps |
| CPU time | 37.16 seconds |
| Started | Aug 21 06:25:16 AM UTC 24 |
| Finished | Aug 21 06:25:54 AM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3526853010 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3526853010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_intr.2564399597 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 19710107094 ps |
| CPU time | 9.58 seconds |
| Started | Aug 21 06:25:19 AM UTC 24 |
| Finished | Aug 21 06:25:30 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2564399597 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2564399597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.3620303761 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 116432953166 ps |
| CPU time | 224.61 seconds |
| Started | Aug 21 06:25:25 AM UTC 24 |
| Finished | Aug 21 06:29:13 AM UTC 24 |
| Peak memory | 208956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3620303761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3620303761 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_loopback.2174231548 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3213030399 ps |
| CPU time | 5.05 seconds |
| Started | Aug 21 06:25:23 AM UTC 24 |
| Finished | Aug 21 06:25:30 AM UTC 24 |
| Peak memory | 208552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2174231548 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2174231548 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_noise_filter.2363534882 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 310666235109 ps |
| CPU time | 76.8 seconds |
| Started | Aug 21 06:25:20 AM UTC 24 |
| Finished | Aug 21 06:26:39 AM UTC 24 |
| Peak memory | 217048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2363534882 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2363534882 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_perf.3037394338 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 11928323217 ps |
| CPU time | 357.65 seconds |
| Started | Aug 21 06:25:23 AM UTC 24 |
| Finished | Aug 21 06:31:26 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3037394338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3037394338 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_rx_oversample.4244175528 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1487354914 ps |
| CPU time | 6.19 seconds |
| Started | Aug 21 06:25:18 AM UTC 24 |
| Finished | Aug 21 06:25:25 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4244175528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4244175528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.2995762190 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 645778146 ps |
| CPU time | 1.41 seconds |
| Started | Aug 21 06:25:20 AM UTC 24 |
| Finished | Aug 21 06:25:23 AM UTC 24 |
| Peak memory | 204584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2995762190 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2995762190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_smoke.3919007464 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 868046143 ps |
| CPU time | 2.17 seconds |
| Started | Aug 21 06:25:12 AM UTC 24 |
| Finished | Aug 21 06:25:15 AM UTC 24 |
| Peak memory | 207588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3919007464 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3919007464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_stress_all.3979971780 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 359234165326 ps |
| CPU time | 502.19 seconds |
| Started | Aug 21 06:25:26 AM UTC 24 |
| Finished | Aug 21 06:33:54 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3979971780 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3979971780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.68250341 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5594919296 ps |
| CPU time | 28.62 seconds |
| Started | Aug 21 06:25:26 AM UTC 24 |
| Finished | Aug 21 06:25:56 AM UTC 24 |
| Peak memory | 217924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=68250341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.68250341 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.2721136371 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 651897994 ps |
| CPU time | 4.47 seconds |
| Started | Aug 21 06:25:22 AM UTC 24 |
| Finished | Aug 21 06:25:28 AM UTC 24 |
| Peak memory | 207168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2721136371 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2721136371 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/14.uart_tx_rx.924135427 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 89210434695 ps |
| CPU time | 58.93 seconds |
| Started | Aug 21 06:25:12 AM UTC 24 |
| Finished | Aug 21 06:26:12 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=924135427 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.924135427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/14.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/140.uart_fifo_reset.3594755637 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 80141285524 ps |
| CPU time | 68.47 seconds |
| Started | Aug 21 06:50:03 AM UTC 24 |
| Finished | Aug 21 06:51:13 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594755637 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3594755637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/140.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/141.uart_fifo_reset.483325387 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 7067755159 ps |
| CPU time | 24.75 seconds |
| Started | Aug 21 06:50:04 AM UTC 24 |
| Finished | Aug 21 06:50:30 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=483325387 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.483325387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/141.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/142.uart_fifo_reset.2558355514 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 148187026579 ps |
| CPU time | 101.73 seconds |
| Started | Aug 21 06:50:07 AM UTC 24 |
| Finished | Aug 21 06:51:51 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2558355514 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2558355514 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/142.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/143.uart_fifo_reset.583706727 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 141062475432 ps |
| CPU time | 110.01 seconds |
| Started | Aug 21 06:50:08 AM UTC 24 |
| Finished | Aug 21 06:52:01 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=583706727 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.583706727 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/143.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/145.uart_fifo_reset.960416946 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 26482895104 ps |
| CPU time | 19.69 seconds |
| Started | Aug 21 06:50:18 AM UTC 24 |
| Finished | Aug 21 06:50:38 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=960416946 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.960416946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/145.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1119382049 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 101685332282 ps |
| CPU time | 63.28 seconds |
| Started | Aug 21 06:50:21 AM UTC 24 |
| Finished | Aug 21 06:51:26 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1119382049 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1119382049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/146.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/147.uart_fifo_reset.1317741630 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 11203316009 ps |
| CPU time | 17.43 seconds |
| Started | Aug 21 06:50:22 AM UTC 24 |
| Finished | Aug 21 06:50:40 AM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1317741630 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1317741630 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/147.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/148.uart_fifo_reset.3772624934 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 64864070293 ps |
| CPU time | 25.5 seconds |
| Started | Aug 21 06:50:22 AM UTC 24 |
| Finished | Aug 21 06:50:49 AM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3772624934 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3772624934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/148.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/149.uart_fifo_reset.1624590992 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 167466547432 ps |
| CPU time | 113.99 seconds |
| Started | Aug 21 06:50:22 AM UTC 24 |
| Finished | Aug 21 06:52:18 AM UTC 24 |
| Peak memory | 208516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1624590992 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1624590992 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/149.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_alert_test.1455234305 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 13772175 ps |
| CPU time | 0.73 seconds |
| Started | Aug 21 06:25:59 AM UTC 24 |
| Finished | Aug 21 06:26:01 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1455234305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1455234305 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_fifo_full.3878685574 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 22843680143 ps |
| CPU time | 17.04 seconds |
| Started | Aug 21 06:25:32 AM UTC 24 |
| Finished | Aug 21 06:25:50 AM UTC 24 |
| Peak memory | 207920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3878685574 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3878685574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.4106809556 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 85707954098 ps |
| CPU time | 274.96 seconds |
| Started | Aug 21 06:25:34 AM UTC 24 |
| Finished | Aug 21 06:30:13 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4106809556 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.4106809556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_intr.3519123954 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 303411331093 ps |
| CPU time | 555.05 seconds |
| Started | Aug 21 06:25:38 AM UTC 24 |
| Finished | Aug 21 06:35:00 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3519123954 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3519123954 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.3807040058 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 80565505703 ps |
| CPU time | 301 seconds |
| Started | Aug 21 06:25:55 AM UTC 24 |
| Finished | Aug 21 06:31:00 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3807040058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3807040058 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_loopback.2525174298 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 7523660063 ps |
| CPU time | 16.72 seconds |
| Started | Aug 21 06:25:51 AM UTC 24 |
| Finished | Aug 21 06:26:09 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2525174298 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2525174298 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_noise_filter.3142433973 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 138468759605 ps |
| CPU time | 117.12 seconds |
| Started | Aug 21 06:25:40 AM UTC 24 |
| Finished | Aug 21 06:27:40 AM UTC 24 |
| Peak memory | 207636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3142433973 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3142433973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_perf.1992359650 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 10775029201 ps |
| CPU time | 723.68 seconds |
| Started | Aug 21 06:25:55 AM UTC 24 |
| Finished | Aug 21 06:38:07 AM UTC 24 |
| Peak memory | 212204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1992359650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1992359650 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_rx_oversample.1038250222 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6564269125 ps |
| CPU time | 69.37 seconds |
| Started | Aug 21 06:25:37 AM UTC 24 |
| Finished | Aug 21 06:26:48 AM UTC 24 |
| Peak memory | 208232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1038250222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1038250222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.472415831 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 43951676570 ps |
| CPU time | 39.05 seconds |
| Started | Aug 21 06:25:48 AM UTC 24 |
| Finished | Aug 21 06:26:28 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=472415831 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.472415831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.3133181581 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 6354767182 ps |
| CPU time | 11.94 seconds |
| Started | Aug 21 06:25:45 AM UTC 24 |
| Finished | Aug 21 06:25:59 AM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3133181581 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3133181581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_smoke.1168375476 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 449565286 ps |
| CPU time | 1.77 seconds |
| Started | Aug 21 06:25:31 AM UTC 24 |
| Finished | Aug 21 06:25:34 AM UTC 24 |
| Peak memory | 206428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1168375476 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1168375476 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.3571382918 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1907001297 ps |
| CPU time | 17.66 seconds |
| Started | Aug 21 06:25:56 AM UTC 24 |
| Finished | Aug 21 06:26:15 AM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3571382918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3571382918 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.3456957298 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1361031204 ps |
| CPU time | 4.3 seconds |
| Started | Aug 21 06:25:49 AM UTC 24 |
| Finished | Aug 21 06:25:54 AM UTC 24 |
| Peak memory | 207488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3456957298 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3456957298 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/15.uart_tx_rx.560519844 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 37151425745 ps |
| CPU time | 15.06 seconds |
| Started | Aug 21 06:25:31 AM UTC 24 |
| Finished | Aug 21 06:25:47 AM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=560519844 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.560519844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/15.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/150.uart_fifo_reset.4152582651 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 37251342961 ps |
| CPU time | 16.44 seconds |
| Started | Aug 21 06:50:23 AM UTC 24 |
| Finished | Aug 21 06:50:41 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4152582651 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4152582651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/150.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/151.uart_fifo_reset.62185209 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 69238109197 ps |
| CPU time | 79.34 seconds |
| Started | Aug 21 06:50:24 AM UTC 24 |
| Finished | Aug 21 06:51:45 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=62185209 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.62185209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/151.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/153.uart_fifo_reset.482158757 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 33064125525 ps |
| CPU time | 94.81 seconds |
| Started | Aug 21 06:50:26 AM UTC 24 |
| Finished | Aug 21 06:52:03 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=482158757 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.482158757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/153.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/154.uart_fifo_reset.794261196 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 6669755132 ps |
| CPU time | 12.92 seconds |
| Started | Aug 21 06:50:26 AM UTC 24 |
| Finished | Aug 21 06:50:40 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=794261196 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.794261196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/154.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/155.uart_fifo_reset.3171588361 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 223278267091 ps |
| CPU time | 46.28 seconds |
| Started | Aug 21 06:50:27 AM UTC 24 |
| Finished | Aug 21 06:51:15 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3171588361 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3171588361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/155.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3437420576 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 186041777803 ps |
| CPU time | 422.7 seconds |
| Started | Aug 21 06:50:28 AM UTC 24 |
| Finished | Aug 21 06:57:36 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3437420576 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3437420576 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/156.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/157.uart_fifo_reset.1605283690 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 126696756965 ps |
| CPU time | 59.14 seconds |
| Started | Aug 21 06:50:30 AM UTC 24 |
| Finished | Aug 21 06:51:31 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1605283690 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1605283690 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/157.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_alert_test.3826942357 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 66184008 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:26:24 AM UTC 24 |
| Finished | Aug 21 06:26:26 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3826942357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3826942357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_fifo_reset.2414183847 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 149250536463 ps |
| CPU time | 529.86 seconds |
| Started | Aug 21 06:26:09 AM UTC 24 |
| Finished | Aug 21 06:35:06 AM UTC 24 |
| Peak memory | 208756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2414183847 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2414183847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_intr.3271872542 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 35655260017 ps |
| CPU time | 60.53 seconds |
| Started | Aug 21 06:26:13 AM UTC 24 |
| Finished | Aug 21 06:27:15 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3271872542 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3271872542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.2571423976 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 140264247163 ps |
| CPU time | 1260.43 seconds |
| Started | Aug 21 06:26:19 AM UTC 24 |
| Finished | Aug 21 06:47:33 AM UTC 24 |
| Peak memory | 212208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2571423976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2571423976 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_loopback.4267169039 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1310516449 ps |
| CPU time | 2.66 seconds |
| Started | Aug 21 06:26:16 AM UTC 24 |
| Finished | Aug 21 06:26:20 AM UTC 24 |
| Peak memory | 205040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4267169039 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.4267169039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_noise_filter.3988434682 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 98604272741 ps |
| CPU time | 55.4 seconds |
| Started | Aug 21 06:26:14 AM UTC 24 |
| Finished | Aug 21 06:27:11 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988434682 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3988434682 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_perf.2920735682 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 18942879354 ps |
| CPU time | 778.29 seconds |
| Started | Aug 21 06:26:17 AM UTC 24 |
| Finished | Aug 21 06:39:24 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2920735682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2920735682 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_rx_oversample.622374201 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 4848732561 ps |
| CPU time | 14.95 seconds |
| Started | Aug 21 06:26:12 AM UTC 24 |
| Finished | Aug 21 06:26:28 AM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=622374201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.622374201 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.161589715 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2931106894 ps |
| CPU time | 2.27 seconds |
| Started | Aug 21 06:26:16 AM UTC 24 |
| Finished | Aug 21 06:26:19 AM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161589715 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.161589715 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_smoke.138116165 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 113615204 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 06:26:01 AM UTC 24 |
| Finished | Aug 21 06:26:03 AM UTC 24 |
| Peak memory | 206504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=138116165 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.138116165 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.3409427780 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4356886495 ps |
| CPU time | 118.41 seconds |
| Started | Aug 21 06:26:20 AM UTC 24 |
| Finished | Aug 21 06:28:21 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3409427780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3409427780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.1485505290 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 8116043236 ps |
| CPU time | 14.01 seconds |
| Started | Aug 21 06:26:16 AM UTC 24 |
| Finished | Aug 21 06:26:31 AM UTC 24 |
| Peak memory | 208456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1485505290 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1485505290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/16.uart_tx_rx.2696463243 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 137960917526 ps |
| CPU time | 48.99 seconds |
| Started | Aug 21 06:26:01 AM UTC 24 |
| Finished | Aug 21 06:26:52 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2696463243 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2696463243 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/16.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/160.uart_fifo_reset.3067157047 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 111803089039 ps |
| CPU time | 110.76 seconds |
| Started | Aug 21 06:50:34 AM UTC 24 |
| Finished | Aug 21 06:52:26 AM UTC 24 |
| Peak memory | 208416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3067157047 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3067157047 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/160.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/161.uart_fifo_reset.3378299817 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 119317559949 ps |
| CPU time | 353.82 seconds |
| Started | Aug 21 06:50:39 AM UTC 24 |
| Finished | Aug 21 06:56:37 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3378299817 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3378299817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/161.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/162.uart_fifo_reset.4056845835 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 26673340671 ps |
| CPU time | 57.65 seconds |
| Started | Aug 21 06:50:41 AM UTC 24 |
| Finished | Aug 21 06:51:40 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4056845835 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4056845835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/162.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/163.uart_fifo_reset.3642101831 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 19570944792 ps |
| CPU time | 15.57 seconds |
| Started | Aug 21 06:50:41 AM UTC 24 |
| Finished | Aug 21 06:50:58 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3642101831 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3642101831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/163.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/164.uart_fifo_reset.79061383 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 26928836834 ps |
| CPU time | 58.61 seconds |
| Started | Aug 21 06:50:41 AM UTC 24 |
| Finished | Aug 21 06:51:41 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79061383 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.79061383 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/164.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/165.uart_fifo_reset.3346999178 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 118159417278 ps |
| CPU time | 406.93 seconds |
| Started | Aug 21 06:50:41 AM UTC 24 |
| Finished | Aug 21 06:57:33 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3346999178 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3346999178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/165.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/166.uart_fifo_reset.2911667374 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 131745393896 ps |
| CPU time | 44.45 seconds |
| Started | Aug 21 06:50:43 AM UTC 24 |
| Finished | Aug 21 06:51:29 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2911667374 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2911667374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/166.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/167.uart_fifo_reset.3140076043 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 31438377722 ps |
| CPU time | 56.86 seconds |
| Started | Aug 21 06:50:44 AM UTC 24 |
| Finished | Aug 21 06:51:43 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3140076043 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3140076043 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/167.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1481026517 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 116950462655 ps |
| CPU time | 61.37 seconds |
| Started | Aug 21 06:50:45 AM UTC 24 |
| Finished | Aug 21 06:51:48 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1481026517 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1481026517 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/168.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/169.uart_fifo_reset.1262362665 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 95949823096 ps |
| CPU time | 138.73 seconds |
| Started | Aug 21 06:50:47 AM UTC 24 |
| Finished | Aug 21 06:53:09 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262362665 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1262362665 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/169.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_alert_test.2740314646 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 33569282 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:26:55 AM UTC 24 |
| Finished | Aug 21 06:26:56 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2740314646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2740314646 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_fifo_full.2220673829 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 30120961894 ps |
| CPU time | 88.56 seconds |
| Started | Aug 21 06:26:29 AM UTC 24 |
| Finished | Aug 21 06:27:59 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2220673829 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2220673829 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.3009919355 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 70007170824 ps |
| CPU time | 65.71 seconds |
| Started | Aug 21 06:26:29 AM UTC 24 |
| Finished | Aug 21 06:27:36 AM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009919355 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3009919355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_fifo_reset.4019747560 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 102184398518 ps |
| CPU time | 101.83 seconds |
| Started | Aug 21 06:26:32 AM UTC 24 |
| Finished | Aug 21 06:28:15 AM UTC 24 |
| Peak memory | 208488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4019747560 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.4019747560 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_intr.3276830433 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 18087907542 ps |
| CPU time | 13.62 seconds |
| Started | Aug 21 06:26:36 AM UTC 24 |
| Finished | Aug 21 06:26:51 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3276830433 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3276830433 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.3579003883 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 56410546508 ps |
| CPU time | 323.57 seconds |
| Started | Aug 21 06:26:51 AM UTC 24 |
| Finished | Aug 21 06:32:20 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3579003883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3579003883 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_loopback.2369615649 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2686647944 ps |
| CPU time | 6.81 seconds |
| Started | Aug 21 06:26:49 AM UTC 24 |
| Finished | Aug 21 06:26:57 AM UTC 24 |
| Peak memory | 205104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2369615649 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2369615649 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_noise_filter.4081840749 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 8017427526 ps |
| CPU time | 20.37 seconds |
| Started | Aug 21 06:26:38 AM UTC 24 |
| Finished | Aug 21 06:27:00 AM UTC 24 |
| Peak memory | 205244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4081840749 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.4081840749 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_perf.1877597691 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 5394905892 ps |
| CPU time | 277.24 seconds |
| Started | Aug 21 06:26:50 AM UTC 24 |
| Finished | Aug 21 06:31:31 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1877597691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1877597691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_rx_oversample.2846447160 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1798673810 ps |
| CPU time | 14.26 seconds |
| Started | Aug 21 06:26:32 AM UTC 24 |
| Finished | Aug 21 06:26:47 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2846447160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2846447160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.4012393802 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 23823208186 ps |
| CPU time | 40.13 seconds |
| Started | Aug 21 06:26:43 AM UTC 24 |
| Finished | Aug 21 06:27:25 AM UTC 24 |
| Peak memory | 208728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4012393802 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4012393802 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.4198437931 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 29910636641 ps |
| CPU time | 12.15 seconds |
| Started | Aug 21 06:26:40 AM UTC 24 |
| Finished | Aug 21 06:26:53 AM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4198437931 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4198437931 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_smoke.49080792 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 840541217 ps |
| CPU time | 5.4 seconds |
| Started | Aug 21 06:26:24 AM UTC 24 |
| Finished | Aug 21 06:26:31 AM UTC 24 |
| Peak memory | 207172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=49080792 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.49080792 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.4093907877 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4839302015 ps |
| CPU time | 109.92 seconds |
| Started | Aug 21 06:26:52 AM UTC 24 |
| Finished | Aug 21 06:28:44 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4093907877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.4093907877 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.3846227880 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 818189299 ps |
| CPU time | 4.59 seconds |
| Started | Aug 21 06:26:48 AM UTC 24 |
| Finished | Aug 21 06:26:54 AM UTC 24 |
| Peak memory | 208612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3846227880 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3846227880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/17.uart_tx_rx.2958424469 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 18347237504 ps |
| CPU time | 8.24 seconds |
| Started | Aug 21 06:26:27 AM UTC 24 |
| Finished | Aug 21 06:26:37 AM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2958424469 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2958424469 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/17.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/170.uart_fifo_reset.765801477 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 19925747773 ps |
| CPU time | 13.33 seconds |
| Started | Aug 21 06:50:49 AM UTC 24 |
| Finished | Aug 21 06:51:04 AM UTC 24 |
| Peak memory | 208520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=765801477 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.765801477 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/170.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1228140782 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 427594571629 ps |
| CPU time | 62.71 seconds |
| Started | Aug 21 06:50:52 AM UTC 24 |
| Finished | Aug 21 06:51:56 AM UTC 24 |
| Peak memory | 208616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1228140782 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1228140782 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/171.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2699786102 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 50629444879 ps |
| CPU time | 24.28 seconds |
| Started | Aug 21 06:50:54 AM UTC 24 |
| Finished | Aug 21 06:51:19 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2699786102 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2699786102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/172.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/173.uart_fifo_reset.355650410 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 48787104481 ps |
| CPU time | 60.77 seconds |
| Started | Aug 21 06:50:55 AM UTC 24 |
| Finished | Aug 21 06:51:57 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=355650410 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.355650410 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/173.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/174.uart_fifo_reset.1251343990 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 43401139615 ps |
| CPU time | 18.05 seconds |
| Started | Aug 21 06:50:57 AM UTC 24 |
| Finished | Aug 21 06:51:17 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1251343990 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1251343990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/174.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2996160019 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 171865126700 ps |
| CPU time | 159.48 seconds |
| Started | Aug 21 06:50:59 AM UTC 24 |
| Finished | Aug 21 06:53:41 AM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2996160019 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2996160019 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/175.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/176.uart_fifo_reset.844918922 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 103808870793 ps |
| CPU time | 343.92 seconds |
| Started | Aug 21 06:51:00 AM UTC 24 |
| Finished | Aug 21 06:56:49 AM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=844918922 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.844918922 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/176.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/177.uart_fifo_reset.824980450 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 38293743603 ps |
| CPU time | 55.27 seconds |
| Started | Aug 21 06:51:00 AM UTC 24 |
| Finished | Aug 21 06:51:57 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=824980450 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.824980450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/177.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/178.uart_fifo_reset.369682975 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 99216664153 ps |
| CPU time | 191.55 seconds |
| Started | Aug 21 06:51:02 AM UTC 24 |
| Finished | Aug 21 06:54:17 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=369682975 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.369682975 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/178.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/179.uart_fifo_reset.3563381404 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 256504874967 ps |
| CPU time | 69.94 seconds |
| Started | Aug 21 06:51:04 AM UTC 24 |
| Finished | Aug 21 06:52:16 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3563381404 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3563381404 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/179.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_alert_test.1683324269 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 14584729 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:27:42 AM UTC 24 |
| Finished | Aug 21 06:27:43 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683324269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1683324269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_fifo_full.265225812 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 298415912560 ps |
| CPU time | 332.08 seconds |
| Started | Aug 21 06:27:01 AM UTC 24 |
| Finished | Aug 21 06:32:37 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=265225812 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.265225812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.965442155 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 25109353041 ps |
| CPU time | 38.25 seconds |
| Started | Aug 21 06:27:01 AM UTC 24 |
| Finished | Aug 21 06:27:40 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=965442155 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.965442155 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3006550089 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 109993365047 ps |
| CPU time | 32.65 seconds |
| Started | Aug 21 06:27:07 AM UTC 24 |
| Finished | Aug 21 06:27:41 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3006550089 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3006550089 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_intr.1420761482 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 8814399859 ps |
| CPU time | 25.67 seconds |
| Started | Aug 21 06:27:11 AM UTC 24 |
| Finished | Aug 21 06:27:38 AM UTC 24 |
| Peak memory | 207436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1420761482 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1420761482 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.3536694934 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 111596271554 ps |
| CPU time | 369.09 seconds |
| Started | Aug 21 06:27:41 AM UTC 24 |
| Finished | Aug 21 06:33:55 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3536694934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3536694934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_loopback.307629669 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 8288512670 ps |
| CPU time | 15.11 seconds |
| Started | Aug 21 06:27:37 AM UTC 24 |
| Finished | Aug 21 06:27:54 AM UTC 24 |
| Peak memory | 207276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=307629669 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.307629669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_noise_filter.2384378403 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 451345978887 ps |
| CPU time | 120.35 seconds |
| Started | Aug 21 06:27:15 AM UTC 24 |
| Finished | Aug 21 06:29:18 AM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2384378403 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2384378403 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_perf.3397647217 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 20436420164 ps |
| CPU time | 499.38 seconds |
| Started | Aug 21 06:27:39 AM UTC 24 |
| Finished | Aug 21 06:36:04 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3397647217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3397647217 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1832668883 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 7387096343 ps |
| CPU time | 30.64 seconds |
| Started | Aug 21 06:27:09 AM UTC 24 |
| Finished | Aug 21 06:27:41 AM UTC 24 |
| Peak memory | 207508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1832668883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1832668883 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.2360642830 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 29864963783 ps |
| CPU time | 78.91 seconds |
| Started | Aug 21 06:27:20 AM UTC 24 |
| Finished | Aug 21 06:28:41 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2360642830 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2360642830 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.2893338812 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 39466587384 ps |
| CPU time | 44.3 seconds |
| Started | Aug 21 06:27:17 AM UTC 24 |
| Finished | Aug 21 06:28:03 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2893338812 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2893338812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_smoke.1675473018 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 707709078 ps |
| CPU time | 2.15 seconds |
| Started | Aug 21 06:26:57 AM UTC 24 |
| Finished | Aug 21 06:27:00 AM UTC 24 |
| Peak memory | 208516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1675473018 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1675473018 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_stress_all.4202988991 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 350183412484 ps |
| CPU time | 1166.71 seconds |
| Started | Aug 21 06:27:42 AM UTC 24 |
| Finished | Aug 21 06:47:22 AM UTC 24 |
| Peak memory | 212288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4202988991 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4202988991 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.2106363686 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1413528610 ps |
| CPU time | 11.81 seconds |
| Started | Aug 21 06:27:42 AM UTC 24 |
| Finished | Aug 21 06:27:55 AM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2106363686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2106363686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.3932472547 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 7459967679 ps |
| CPU time | 17.08 seconds |
| Started | Aug 21 06:27:25 AM UTC 24 |
| Finished | Aug 21 06:27:44 AM UTC 24 |
| Peak memory | 208088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3932472547 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3932472547 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/18.uart_tx_rx.4175718839 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 120238594116 ps |
| CPU time | 55.72 seconds |
| Started | Aug 21 06:26:58 AM UTC 24 |
| Finished | Aug 21 06:27:55 AM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4175718839 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4175718839 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/18.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/180.uart_fifo_reset.3181647973 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 49915015442 ps |
| CPU time | 30.25 seconds |
| Started | Aug 21 06:51:05 AM UTC 24 |
| Finished | Aug 21 06:51:37 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3181647973 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3181647973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/180.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1568436545 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 127640405252 ps |
| CPU time | 132.51 seconds |
| Started | Aug 21 06:51:08 AM UTC 24 |
| Finished | Aug 21 06:53:23 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1568436545 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1568436545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/181.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/182.uart_fifo_reset.591855659 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 117849690891 ps |
| CPU time | 92.9 seconds |
| Started | Aug 21 06:51:14 AM UTC 24 |
| Finished | Aug 21 06:52:49 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=591855659 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.591855659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/182.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/183.uart_fifo_reset.3589765556 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 44608464185 ps |
| CPU time | 38.24 seconds |
| Started | Aug 21 06:51:15 AM UTC 24 |
| Finished | Aug 21 06:51:55 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3589765556 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3589765556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/183.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/184.uart_fifo_reset.3963422110 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 7120028545 ps |
| CPU time | 23 seconds |
| Started | Aug 21 06:51:18 AM UTC 24 |
| Finished | Aug 21 06:51:42 AM UTC 24 |
| Peak memory | 208924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3963422110 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3963422110 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/184.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/185.uart_fifo_reset.3136786934 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 65338417741 ps |
| CPU time | 77.8 seconds |
| Started | Aug 21 06:51:18 AM UTC 24 |
| Finished | Aug 21 06:52:37 AM UTC 24 |
| Peak memory | 208728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3136786934 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3136786934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/185.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/186.uart_fifo_reset.69986437 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 113423474219 ps |
| CPU time | 128.8 seconds |
| Started | Aug 21 06:51:20 AM UTC 24 |
| Finished | Aug 21 06:53:31 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69986437 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.69986437 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/186.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/187.uart_fifo_reset.3364824203 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 109302659257 ps |
| CPU time | 63.81 seconds |
| Started | Aug 21 06:51:21 AM UTC 24 |
| Finished | Aug 21 06:52:26 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3364824203 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3364824203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/187.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/189.uart_fifo_reset.1032420900 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 5197667340 ps |
| CPU time | 27.15 seconds |
| Started | Aug 21 06:51:30 AM UTC 24 |
| Finished | Aug 21 06:51:58 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1032420900 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1032420900 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/189.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_alert_test.54725023 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 29514322 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:28:15 AM UTC 24 |
| Finished | Aug 21 06:28:17 AM UTC 24 |
| Peak memory | 204516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=54725023 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.54725023 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_fifo_full.3106523762 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 26418124777 ps |
| CPU time | 50.99 seconds |
| Started | Aug 21 06:27:45 AM UTC 24 |
| Finished | Aug 21 06:28:38 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3106523762 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3106523762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.627679403 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 43784970264 ps |
| CPU time | 136.01 seconds |
| Started | Aug 21 06:27:50 AM UTC 24 |
| Finished | Aug 21 06:30:08 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=627679403 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.627679403 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_fifo_reset.2289267005 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 21099022466 ps |
| CPU time | 41.37 seconds |
| Started | Aug 21 06:27:53 AM UTC 24 |
| Finished | Aug 21 06:28:36 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289267005 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2289267005 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_intr.1106511203 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 55001835120 ps |
| CPU time | 107.61 seconds |
| Started | Aug 21 06:27:54 AM UTC 24 |
| Finished | Aug 21 06:29:44 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1106511203 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1106511203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.1224650236 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 158073917449 ps |
| CPU time | 565.36 seconds |
| Started | Aug 21 06:28:04 AM UTC 24 |
| Finished | Aug 21 06:37:36 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1224650236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1224650236 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_loopback.1561101086 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3244317380 ps |
| CPU time | 3.23 seconds |
| Started | Aug 21 06:28:02 AM UTC 24 |
| Finished | Aug 21 06:28:06 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1561101086 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1561101086 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_noise_filter.3581589474 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 74119843748 ps |
| CPU time | 202.23 seconds |
| Started | Aug 21 06:27:55 AM UTC 24 |
| Finished | Aug 21 06:31:21 AM UTC 24 |
| Peak memory | 208548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3581589474 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3581589474 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_perf.832320145 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 9717156501 ps |
| CPU time | 313.05 seconds |
| Started | Aug 21 06:28:04 AM UTC 24 |
| Finished | Aug 21 06:33:21 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=832320145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.832320145 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_rx_oversample.2625952179 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 3043359980 ps |
| CPU time | 18.62 seconds |
| Started | Aug 21 06:27:54 AM UTC 24 |
| Finished | Aug 21 06:28:14 AM UTC 24 |
| Peak memory | 207300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2625952179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2625952179 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.2413594166 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 40390566456 ps |
| CPU time | 64.54 seconds |
| Started | Aug 21 06:27:57 AM UTC 24 |
| Finished | Aug 21 06:29:04 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2413594166 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2413594166 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.2637812831 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 28907232953 ps |
| CPU time | 6.08 seconds |
| Started | Aug 21 06:27:55 AM UTC 24 |
| Finished | Aug 21 06:28:03 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2637812831 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2637812831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_smoke.1396168398 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 486305891 ps |
| CPU time | 5.79 seconds |
| Started | Aug 21 06:27:43 AM UTC 24 |
| Finished | Aug 21 06:27:50 AM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1396168398 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1396168398 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_stress_all.2695676015 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 198065940797 ps |
| CPU time | 117.08 seconds |
| Started | Aug 21 06:28:08 AM UTC 24 |
| Finished | Aug 21 06:30:07 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2695676015 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2695676015 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.698522031 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3601856292 ps |
| CPU time | 53.62 seconds |
| Started | Aug 21 06:28:07 AM UTC 24 |
| Finished | Aug 21 06:29:02 AM UTC 24 |
| Peak memory | 217800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=698522031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.698522031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.802305426 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1030898888 ps |
| CPU time | 5.55 seconds |
| Started | Aug 21 06:28:00 AM UTC 24 |
| Finished | Aug 21 06:28:07 AM UTC 24 |
| Peak memory | 207632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=802305426 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.802305426 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/19.uart_tx_rx.2960436571 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 38353543407 ps |
| CPU time | 33.06 seconds |
| Started | Aug 21 06:27:44 AM UTC 24 |
| Finished | Aug 21 06:28:19 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2960436571 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2960436571 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/19.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/190.uart_fifo_reset.2979965780 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 148328829685 ps |
| CPU time | 113.18 seconds |
| Started | Aug 21 06:51:32 AM UTC 24 |
| Finished | Aug 21 06:53:28 AM UTC 24 |
| Peak memory | 208360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2979965780 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2979965780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/190.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2870618732 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 66569764415 ps |
| CPU time | 137.44 seconds |
| Started | Aug 21 06:51:32 AM UTC 24 |
| Finished | Aug 21 06:53:52 AM UTC 24 |
| Peak memory | 208212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2870618732 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2870618732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/191.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2268939048 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 185777635092 ps |
| CPU time | 52.97 seconds |
| Started | Aug 21 06:51:37 AM UTC 24 |
| Finished | Aug 21 06:52:32 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2268939048 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2268939048 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/192.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/193.uart_fifo_reset.4578202 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 91788812199 ps |
| CPU time | 55.95 seconds |
| Started | Aug 21 06:51:41 AM UTC 24 |
| Finished | Aug 21 06:52:39 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4578202 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.4578202 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/193.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/195.uart_fifo_reset.1436860397 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 179817782876 ps |
| CPU time | 55.66 seconds |
| Started | Aug 21 06:51:42 AM UTC 24 |
| Finished | Aug 21 06:52:40 AM UTC 24 |
| Peak memory | 208924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1436860397 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1436860397 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/195.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/196.uart_fifo_reset.1716369479 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 16543744545 ps |
| CPU time | 29.62 seconds |
| Started | Aug 21 06:51:43 AM UTC 24 |
| Finished | Aug 21 06:52:14 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1716369479 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1716369479 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/196.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3535730457 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 81377529623 ps |
| CPU time | 23.29 seconds |
| Started | Aug 21 06:51:44 AM UTC 24 |
| Finished | Aug 21 06:52:08 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3535730457 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3535730457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/197.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/199.uart_fifo_reset.806317053 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 123403228706 ps |
| CPU time | 232.35 seconds |
| Started | Aug 21 06:51:49 AM UTC 24 |
| Finished | Aug 21 06:55:44 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806317053 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.806317053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/199.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_alert_test.3405931288 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 31208463 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 06:18:47 AM UTC 24 |
| Finished | Aug 21 06:18:49 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3405931288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3405931288 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_fifo_full.4171387479 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 225821855137 ps |
| CPU time | 116.35 seconds |
| Started | Aug 21 06:18:11 AM UTC 24 |
| Finished | Aug 21 06:20:10 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4171387479 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.4171387479 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_fifo_reset.3847742526 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 379263867870 ps |
| CPU time | 75.19 seconds |
| Started | Aug 21 06:18:11 AM UTC 24 |
| Finished | Aug 21 06:19:28 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3847742526 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3847742526 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.330644928 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 126145707850 ps |
| CPU time | 1112.53 seconds |
| Started | Aug 21 06:18:38 AM UTC 24 |
| Finished | Aug 21 06:37:23 AM UTC 24 |
| Peak memory | 212288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=330644928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.330644928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_loopback.2906228812 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9613891884 ps |
| CPU time | 34.6 seconds |
| Started | Aug 21 06:18:23 AM UTC 24 |
| Finished | Aug 21 06:18:59 AM UTC 24 |
| Peak memory | 207304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2906228812 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2906228812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_noise_filter.3031075941 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 491403313 ps |
| CPU time | 1.33 seconds |
| Started | Aug 21 06:18:15 AM UTC 24 |
| Finished | Aug 21 06:18:18 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3031075941 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3031075941 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_perf.3299275272 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 27106700714 ps |
| CPU time | 1264.8 seconds |
| Started | Aug 21 06:18:34 AM UTC 24 |
| Finished | Aug 21 06:39:53 AM UTC 24 |
| Peak memory | 212388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3299275272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3299275272 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_rx_oversample.1938488527 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4025114339 ps |
| CPU time | 4.86 seconds |
| Started | Aug 21 06:18:11 AM UTC 24 |
| Finished | Aug 21 06:18:17 AM UTC 24 |
| Peak memory | 207900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1938488527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1938488527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.2987143755 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 42074809981 ps |
| CPU time | 100.47 seconds |
| Started | Aug 21 06:18:17 AM UTC 24 |
| Finished | Aug 21 06:19:59 AM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2987143755 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2987143755 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_sec_cm.808400657 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 205660229 ps |
| CPU time | 1.22 seconds |
| Started | Aug 21 06:18:44 AM UTC 24 |
| Finished | Aug 21 06:18:46 AM UTC 24 |
| Peak memory | 239548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=808400657 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.808400657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_smoke.2737536483 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 479957296 ps |
| CPU time | 1.8 seconds |
| Started | Aug 21 06:18:07 AM UTC 24 |
| Finished | Aug 21 06:18:10 AM UTC 24 |
| Peak memory | 207668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2737536483 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2737536483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.1835179350 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 796151990 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 06:18:19 AM UTC 24 |
| Finished | Aug 21 06:18:22 AM UTC 24 |
| Peak memory | 207460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1835179350 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1835179350 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/2.uart_tx_rx.1513355307 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 88087595181 ps |
| CPU time | 130.97 seconds |
| Started | Aug 21 06:18:11 AM UTC 24 |
| Finished | Aug 21 06:20:24 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1513355307 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1513355307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/2.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_alert_test.3520535248 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 14571861 ps |
| CPU time | 0.75 seconds |
| Started | Aug 21 06:28:50 AM UTC 24 |
| Finished | Aug 21 06:28:52 AM UTC 24 |
| Peak memory | 204432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3520535248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3520535248 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_fifo_full.449632294 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 46618174111 ps |
| CPU time | 223.87 seconds |
| Started | Aug 21 06:28:19 AM UTC 24 |
| Finished | Aug 21 06:32:06 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=449632294 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.449632294 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3747243188 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 173415178044 ps |
| CPU time | 76.76 seconds |
| Started | Aug 21 06:28:20 AM UTC 24 |
| Finished | Aug 21 06:29:39 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3747243188 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3747243188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_fifo_reset.146209476 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 168585798353 ps |
| CPU time | 390.4 seconds |
| Started | Aug 21 06:28:21 AM UTC 24 |
| Finished | Aug 21 06:34:57 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=146209476 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.146209476 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_intr.1507202019 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 21250544398 ps |
| CPU time | 10.98 seconds |
| Started | Aug 21 06:28:34 AM UTC 24 |
| Finished | Aug 21 06:28:46 AM UTC 24 |
| Peak memory | 208596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1507202019 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1507202019 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.1729077146 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 137678118713 ps |
| CPU time | 520.55 seconds |
| Started | Aug 21 06:28:45 AM UTC 24 |
| Finished | Aug 21 06:37:32 AM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1729077146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1729077146 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_loopback.2051316623 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 6331990740 ps |
| CPU time | 4.44 seconds |
| Started | Aug 21 06:28:44 AM UTC 24 |
| Finished | Aug 21 06:28:49 AM UTC 24 |
| Peak memory | 208488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2051316623 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2051316623 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_noise_filter.2003772131 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 123831583739 ps |
| CPU time | 87.42 seconds |
| Started | Aug 21 06:28:37 AM UTC 24 |
| Finished | Aug 21 06:30:06 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2003772131 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2003772131 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_perf.1062138286 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 9879771508 ps |
| CPU time | 90.17 seconds |
| Started | Aug 21 06:28:45 AM UTC 24 |
| Finished | Aug 21 06:30:17 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1062138286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1062138286 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1837497365 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3992114268 ps |
| CPU time | 10.2 seconds |
| Started | Aug 21 06:28:21 AM UTC 24 |
| Finished | Aug 21 06:28:33 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837497365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1837497365 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.1941654742 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 92810947621 ps |
| CPU time | 168.09 seconds |
| Started | Aug 21 06:28:42 AM UTC 24 |
| Finished | Aug 21 06:31:32 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1941654742 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1941654742 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.2089133468 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1710627259 ps |
| CPU time | 2.71 seconds |
| Started | Aug 21 06:28:39 AM UTC 24 |
| Finished | Aug 21 06:28:42 AM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2089133468 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2089133468 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_smoke.2535526062 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 6072771173 ps |
| CPU time | 25.76 seconds |
| Started | Aug 21 06:28:16 AM UTC 24 |
| Finished | Aug 21 06:28:43 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2535526062 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2535526062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.585752537 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 60434654497 ps |
| CPU time | 101.97 seconds |
| Started | Aug 21 06:28:46 AM UTC 24 |
| Finished | Aug 21 06:30:30 AM UTC 24 |
| Peak memory | 221900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=585752537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.585752537 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1554876927 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 751320899 ps |
| CPU time | 5.71 seconds |
| Started | Aug 21 06:28:43 AM UTC 24 |
| Finished | Aug 21 06:28:50 AM UTC 24 |
| Peak memory | 207488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1554876927 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1554876927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/20.uart_tx_rx.1159140375 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 38967000715 ps |
| CPU time | 93.24 seconds |
| Started | Aug 21 06:28:18 AM UTC 24 |
| Finished | Aug 21 06:29:53 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1159140375 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1159140375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/20.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/200.uart_fifo_reset.3128906935 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 19590066622 ps |
| CPU time | 14.12 seconds |
| Started | Aug 21 06:51:52 AM UTC 24 |
| Finished | Aug 21 06:52:07 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3128906935 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3128906935 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/200.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3682154776 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 113789252959 ps |
| CPU time | 317.18 seconds |
| Started | Aug 21 06:51:52 AM UTC 24 |
| Finished | Aug 21 06:57:13 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3682154776 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3682154776 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/201.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/202.uart_fifo_reset.1160091030 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 31947091771 ps |
| CPU time | 43.96 seconds |
| Started | Aug 21 06:51:56 AM UTC 24 |
| Finished | Aug 21 06:52:41 AM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1160091030 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1160091030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/202.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/203.uart_fifo_reset.1372653374 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 21934957541 ps |
| CPU time | 34.56 seconds |
| Started | Aug 21 06:51:56 AM UTC 24 |
| Finished | Aug 21 06:52:32 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1372653374 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1372653374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/203.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/204.uart_fifo_reset.3112683078 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 76126414233 ps |
| CPU time | 183.21 seconds |
| Started | Aug 21 06:51:56 AM UTC 24 |
| Finished | Aug 21 06:55:02 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3112683078 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3112683078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/204.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2700164989 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 131850125098 ps |
| CPU time | 66.1 seconds |
| Started | Aug 21 06:51:57 AM UTC 24 |
| Finished | Aug 21 06:53:05 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2700164989 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2700164989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/205.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/206.uart_fifo_reset.944780947 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 27858579090 ps |
| CPU time | 68.66 seconds |
| Started | Aug 21 06:51:57 AM UTC 24 |
| Finished | Aug 21 06:53:08 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=944780947 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.944780947 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/206.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/207.uart_fifo_reset.3052086999 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 13753159136 ps |
| CPU time | 22.63 seconds |
| Started | Aug 21 06:51:58 AM UTC 24 |
| Finished | Aug 21 06:52:22 AM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3052086999 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3052086999 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/207.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1395557406 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 40334716976 ps |
| CPU time | 29.98 seconds |
| Started | Aug 21 06:51:58 AM UTC 24 |
| Finished | Aug 21 06:52:30 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1395557406 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1395557406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/208.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_alert_test.822764544 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 15272181 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:29:49 AM UTC 24 |
| Finished | Aug 21 06:29:50 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822764544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.822764544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_fifo_full.2520155429 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 115757706475 ps |
| CPU time | 307.98 seconds |
| Started | Aug 21 06:28:58 AM UTC 24 |
| Finished | Aug 21 06:34:10 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2520155429 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2520155429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.2545492527 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 95550367875 ps |
| CPU time | 68.71 seconds |
| Started | Aug 21 06:29:03 AM UTC 24 |
| Finished | Aug 21 06:30:13 AM UTC 24 |
| Peak memory | 208336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2545492527 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2545492527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_fifo_reset.2305643352 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 94462777096 ps |
| CPU time | 20.4 seconds |
| Started | Aug 21 06:29:05 AM UTC 24 |
| Finished | Aug 21 06:29:26 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2305643352 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2305643352 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_intr.308521215 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 52257658934 ps |
| CPU time | 146.65 seconds |
| Started | Aug 21 06:29:14 AM UTC 24 |
| Finished | Aug 21 06:31:43 AM UTC 24 |
| Peak memory | 208924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=308521215 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.308521215 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.3702012935 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 51668830489 ps |
| CPU time | 338.65 seconds |
| Started | Aug 21 06:29:28 AM UTC 24 |
| Finished | Aug 21 06:35:12 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3702012935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3702012935 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_loopback.4198766862 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 9102422478 ps |
| CPU time | 19.55 seconds |
| Started | Aug 21 06:29:27 AM UTC 24 |
| Finished | Aug 21 06:29:48 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4198766862 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4198766862 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_noise_filter.3896192541 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 30472240642 ps |
| CPU time | 36.06 seconds |
| Started | Aug 21 06:29:14 AM UTC 24 |
| Finished | Aug 21 06:29:51 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3896192541 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3896192541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_perf.3950238014 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 8761477930 ps |
| CPU time | 512.19 seconds |
| Started | Aug 21 06:29:28 AM UTC 24 |
| Finished | Aug 21 06:38:07 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950238014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3950238014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_rx_oversample.2646249890 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 6637065549 ps |
| CPU time | 49.31 seconds |
| Started | Aug 21 06:29:13 AM UTC 24 |
| Finished | Aug 21 06:30:04 AM UTC 24 |
| Peak memory | 207376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2646249890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2646249890 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.4112635531 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 111167549230 ps |
| CPU time | 123.46 seconds |
| Started | Aug 21 06:29:20 AM UTC 24 |
| Finished | Aug 21 06:31:25 AM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4112635531 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4112635531 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.1036570430 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2547108046 ps |
| CPU time | 7.66 seconds |
| Started | Aug 21 06:29:19 AM UTC 24 |
| Finished | Aug 21 06:29:28 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1036570430 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1036570430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_smoke.505800806 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 246395889 ps |
| CPU time | 2.42 seconds |
| Started | Aug 21 06:28:52 AM UTC 24 |
| Finished | Aug 21 06:28:56 AM UTC 24 |
| Peak memory | 207312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=505800806 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.505800806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_stress_all.2787189257 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 83710654259 ps |
| CPU time | 710.62 seconds |
| Started | Aug 21 06:29:44 AM UTC 24 |
| Finished | Aug 21 06:41:44 AM UTC 24 |
| Peak memory | 221184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2787189257 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2787189257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3090095946 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 171324923 ps |
| CPU time | 7.58 seconds |
| Started | Aug 21 06:29:39 AM UTC 24 |
| Finished | Aug 21 06:29:48 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3090095946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3090095946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.3447134351 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1131424277 ps |
| CPU time | 1.66 seconds |
| Started | Aug 21 06:29:25 AM UTC 24 |
| Finished | Aug 21 06:29:28 AM UTC 24 |
| Peak memory | 206536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447134351 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3447134351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/21.uart_tx_rx.672918051 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 80533143479 ps |
| CPU time | 75.38 seconds |
| Started | Aug 21 06:28:56 AM UTC 24 |
| Finished | Aug 21 06:30:13 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=672918051 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.672918051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/21.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/210.uart_fifo_reset.939121257 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 26948669415 ps |
| CPU time | 22.96 seconds |
| Started | Aug 21 06:52:02 AM UTC 24 |
| Finished | Aug 21 06:52:26 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=939121257 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.939121257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/210.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/211.uart_fifo_reset.1841375448 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 85014308202 ps |
| CPU time | 89.09 seconds |
| Started | Aug 21 06:52:04 AM UTC 24 |
| Finished | Aug 21 06:53:35 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1841375448 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1841375448 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/211.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1307329281 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 67293537363 ps |
| CPU time | 27.87 seconds |
| Started | Aug 21 06:52:08 AM UTC 24 |
| Finished | Aug 21 06:52:37 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1307329281 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1307329281 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/212.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1365877680 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 126437986533 ps |
| CPU time | 130.19 seconds |
| Started | Aug 21 06:52:09 AM UTC 24 |
| Finished | Aug 21 06:54:21 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1365877680 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1365877680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/214.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3230630027 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 26532686820 ps |
| CPU time | 50.8 seconds |
| Started | Aug 21 06:52:14 AM UTC 24 |
| Finished | Aug 21 06:53:06 AM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3230630027 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3230630027 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/215.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/216.uart_fifo_reset.4162044872 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 182840978371 ps |
| CPU time | 283.67 seconds |
| Started | Aug 21 06:52:17 AM UTC 24 |
| Finished | Aug 21 06:57:04 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4162044872 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.4162044872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/216.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3787859093 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 16557951961 ps |
| CPU time | 31.58 seconds |
| Started | Aug 21 06:52:19 AM UTC 24 |
| Finished | Aug 21 06:52:52 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3787859093 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3787859093 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/217.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/218.uart_fifo_reset.2057012397 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 15140992204 ps |
| CPU time | 31.41 seconds |
| Started | Aug 21 06:52:20 AM UTC 24 |
| Finished | Aug 21 06:52:53 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2057012397 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2057012397 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/218.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/219.uart_fifo_reset.877767386 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 102804777724 ps |
| CPU time | 86.55 seconds |
| Started | Aug 21 06:52:23 AM UTC 24 |
| Finished | Aug 21 06:53:52 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=877767386 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.877767386 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/219.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_alert_test.1209666833 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 32349105 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 06:30:19 AM UTC 24 |
| Finished | Aug 21 06:30:20 AM UTC 24 |
| Peak memory | 202476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1209666833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1209666833 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_fifo_full.3907072893 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 65533381140 ps |
| CPU time | 36.44 seconds |
| Started | Aug 21 06:29:52 AM UTC 24 |
| Finished | Aug 21 06:30:30 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3907072893 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3907072893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.1725956310 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 132316749320 ps |
| CPU time | 57.1 seconds |
| Started | Aug 21 06:29:54 AM UTC 24 |
| Finished | Aug 21 06:30:53 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1725956310 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1725956310 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_intr.3262241457 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 36593132209 ps |
| CPU time | 62.53 seconds |
| Started | Aug 21 06:30:04 AM UTC 24 |
| Finished | Aug 21 06:31:08 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3262241457 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3262241457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.3032532256 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 77033866895 ps |
| CPU time | 519.31 seconds |
| Started | Aug 21 06:30:14 AM UTC 24 |
| Finished | Aug 21 06:38:59 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3032532256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3032532256 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_loopback.1937448760 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 10859925238 ps |
| CPU time | 38.41 seconds |
| Started | Aug 21 06:30:13 AM UTC 24 |
| Finished | Aug 21 06:30:53 AM UTC 24 |
| Peak memory | 207996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1937448760 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1937448760 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_noise_filter.4158453766 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 89309703302 ps |
| CPU time | 26.27 seconds |
| Started | Aug 21 06:30:07 AM UTC 24 |
| Finished | Aug 21 06:30:35 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4158453766 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.4158453766 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_perf.3135575139 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 20787603731 ps |
| CPU time | 170.82 seconds |
| Started | Aug 21 06:30:13 AM UTC 24 |
| Finished | Aug 21 06:33:07 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3135575139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3135575139 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_rx_oversample.2687630107 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 3402323611 ps |
| CPU time | 8.63 seconds |
| Started | Aug 21 06:30:00 AM UTC 24 |
| Finished | Aug 21 06:30:10 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2687630107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2687630107 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.2809047463 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 287577772589 ps |
| CPU time | 309.88 seconds |
| Started | Aug 21 06:30:09 AM UTC 24 |
| Finished | Aug 21 06:35:23 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809047463 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2809047463 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.111607951 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 5270134120 ps |
| CPU time | 2.97 seconds |
| Started | Aug 21 06:30:08 AM UTC 24 |
| Finished | Aug 21 06:30:12 AM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=111607951 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.111607951 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_smoke.1630729739 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 480288527 ps |
| CPU time | 3.21 seconds |
| Started | Aug 21 06:29:49 AM UTC 24 |
| Finished | Aug 21 06:29:53 AM UTC 24 |
| Peak memory | 207740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1630729739 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1630729739 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_stress_all.2343336812 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 390778229265 ps |
| CPU time | 805.85 seconds |
| Started | Aug 21 06:30:18 AM UTC 24 |
| Finished | Aug 21 06:43:52 AM UTC 24 |
| Peak memory | 222592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2343336812 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2343336812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.2530128125 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2996560183 ps |
| CPU time | 10.65 seconds |
| Started | Aug 21 06:30:15 AM UTC 24 |
| Finished | Aug 21 06:30:26 AM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2530128125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2530128125 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.111427947 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 7800654646 ps |
| CPU time | 12.26 seconds |
| Started | Aug 21 06:30:11 AM UTC 24 |
| Finished | Aug 21 06:30:25 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=111427947 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.111427947 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/22.uart_tx_rx.807159042 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 58578907128 ps |
| CPU time | 52.65 seconds |
| Started | Aug 21 06:29:52 AM UTC 24 |
| Finished | Aug 21 06:30:46 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=807159042 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.807159042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/22.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/220.uart_fifo_reset.3617047281 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 52453759762 ps |
| CPU time | 99.41 seconds |
| Started | Aug 21 06:52:26 AM UTC 24 |
| Finished | Aug 21 06:54:08 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3617047281 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3617047281 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/220.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/221.uart_fifo_reset.3342314448 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 12574077325 ps |
| CPU time | 16.2 seconds |
| Started | Aug 21 06:52:27 AM UTC 24 |
| Finished | Aug 21 06:52:45 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3342314448 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3342314448 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/221.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/222.uart_fifo_reset.324555439 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 89366144867 ps |
| CPU time | 190.55 seconds |
| Started | Aug 21 06:52:27 AM UTC 24 |
| Finished | Aug 21 06:55:41 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=324555439 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.324555439 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/222.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3252356038 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 6494433822 ps |
| CPU time | 23.44 seconds |
| Started | Aug 21 06:52:31 AM UTC 24 |
| Finished | Aug 21 06:52:55 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3252356038 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3252356038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/223.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2212734906 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 34326583023 ps |
| CPU time | 25.87 seconds |
| Started | Aug 21 06:52:33 AM UTC 24 |
| Finished | Aug 21 06:53:00 AM UTC 24 |
| Peak memory | 208820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212734906 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2212734906 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/224.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/225.uart_fifo_reset.580011221 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 46006256387 ps |
| CPU time | 73.75 seconds |
| Started | Aug 21 06:52:33 AM UTC 24 |
| Finished | Aug 21 06:53:48 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=580011221 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.580011221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/225.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/226.uart_fifo_reset.1319196096 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 26426761269 ps |
| CPU time | 33.23 seconds |
| Started | Aug 21 06:52:33 AM UTC 24 |
| Finished | Aug 21 06:53:07 AM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1319196096 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1319196096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/226.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/227.uart_fifo_reset.2177143642 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 11425900528 ps |
| CPU time | 41.18 seconds |
| Started | Aug 21 06:52:35 AM UTC 24 |
| Finished | Aug 21 06:53:18 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177143642 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2177143642 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/227.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/228.uart_fifo_reset.3918013066 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 267895199258 ps |
| CPU time | 137.98 seconds |
| Started | Aug 21 06:52:38 AM UTC 24 |
| Finished | Aug 21 06:54:58 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3918013066 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3918013066 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/228.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/229.uart_fifo_reset.1238665611 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 23915747552 ps |
| CPU time | 35.74 seconds |
| Started | Aug 21 06:52:38 AM UTC 24 |
| Finished | Aug 21 06:53:15 AM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1238665611 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1238665611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/229.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_alert_test.1593782817 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 30113387 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:30:54 AM UTC 24 |
| Finished | Aug 21 06:30:56 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1593782817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1593782817 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_fifo_full.2120891491 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 31917627905 ps |
| CPU time | 14.93 seconds |
| Started | Aug 21 06:30:27 AM UTC 24 |
| Finished | Aug 21 06:30:43 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2120891491 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2120891491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.3299619728 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 57892242173 ps |
| CPU time | 45.76 seconds |
| Started | Aug 21 06:30:27 AM UTC 24 |
| Finished | Aug 21 06:31:14 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3299619728 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3299619728 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_fifo_reset.75171615 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 119927609594 ps |
| CPU time | 50.66 seconds |
| Started | Aug 21 06:30:28 AM UTC 24 |
| Finished | Aug 21 06:31:20 AM UTC 24 |
| Peak memory | 208528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=75171615 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.75171615 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_intr.2837271185 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 34190354453 ps |
| CPU time | 89.16 seconds |
| Started | Aug 21 06:30:31 AM UTC 24 |
| Finished | Aug 21 06:32:02 AM UTC 24 |
| Peak memory | 208972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2837271185 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2837271185 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.764647987 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 115391354708 ps |
| CPU time | 822.74 seconds |
| Started | Aug 21 06:30:48 AM UTC 24 |
| Finished | Aug 21 06:44:40 AM UTC 24 |
| Peak memory | 212284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=764647987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.764647987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_loopback.3446101376 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1830350767 ps |
| CPU time | 7.64 seconds |
| Started | Aug 21 06:30:46 AM UTC 24 |
| Finished | Aug 21 06:30:54 AM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3446101376 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3446101376 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_noise_filter.2391848238 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 66463737675 ps |
| CPU time | 143.23 seconds |
| Started | Aug 21 06:30:35 AM UTC 24 |
| Finished | Aug 21 06:33:01 AM UTC 24 |
| Peak memory | 208012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2391848238 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2391848238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_perf.4174485360 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 19429763699 ps |
| CPU time | 251.54 seconds |
| Started | Aug 21 06:30:47 AM UTC 24 |
| Finished | Aug 21 06:35:02 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4174485360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4174485360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_rx_oversample.1823621624 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1725745790 ps |
| CPU time | 3.51 seconds |
| Started | Aug 21 06:30:30 AM UTC 24 |
| Finished | Aug 21 06:30:35 AM UTC 24 |
| Peak memory | 207372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1823621624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1823621624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.1236822112 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 85111221913 ps |
| CPU time | 53.04 seconds |
| Started | Aug 21 06:30:41 AM UTC 24 |
| Finished | Aug 21 06:31:35 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1236822112 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1236822112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.3365557944 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2590504480 ps |
| CPU time | 8.66 seconds |
| Started | Aug 21 06:30:35 AM UTC 24 |
| Finished | Aug 21 06:30:45 AM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3365557944 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3365557944 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_smoke.2784044305 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 979332903 ps |
| CPU time | 5.48 seconds |
| Started | Aug 21 06:30:21 AM UTC 24 |
| Finished | Aug 21 06:30:27 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2784044305 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2784044305 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_stress_all.2435922771 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 447887479118 ps |
| CPU time | 873.18 seconds |
| Started | Aug 21 06:30:53 AM UTC 24 |
| Finished | Aug 21 06:45:36 AM UTC 24 |
| Peak memory | 221252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2435922771 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2435922771 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.4044284544 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3508267688 ps |
| CPU time | 28.57 seconds |
| Started | Aug 21 06:30:52 AM UTC 24 |
| Finished | Aug 21 06:31:22 AM UTC 24 |
| Peak memory | 221824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4044284544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.4044284544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.2125221688 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1177016804 ps |
| CPU time | 2.2 seconds |
| Started | Aug 21 06:30:44 AM UTC 24 |
| Finished | Aug 21 06:30:47 AM UTC 24 |
| Peak memory | 208612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2125221688 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2125221688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/23.uart_tx_rx.4095588450 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 60451863184 ps |
| CPU time | 36.11 seconds |
| Started | Aug 21 06:30:26 AM UTC 24 |
| Finished | Aug 21 06:31:03 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4095588450 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.4095588450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/23.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/231.uart_fifo_reset.509049841 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 224399116309 ps |
| CPU time | 79.49 seconds |
| Started | Aug 21 06:52:40 AM UTC 24 |
| Finished | Aug 21 06:54:02 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=509049841 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.509049841 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/231.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/232.uart_fifo_reset.1155226197 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 29599618031 ps |
| CPU time | 62.08 seconds |
| Started | Aug 21 06:52:42 AM UTC 24 |
| Finished | Aug 21 06:53:46 AM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1155226197 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1155226197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/232.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3676517740 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 95682480132 ps |
| CPU time | 157.74 seconds |
| Started | Aug 21 06:52:42 AM UTC 24 |
| Finished | Aug 21 06:55:22 AM UTC 24 |
| Peak memory | 208352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3676517740 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3676517740 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/233.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/234.uart_fifo_reset.2245882233 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 5664462766 ps |
| CPU time | 10.66 seconds |
| Started | Aug 21 06:52:43 AM UTC 24 |
| Finished | Aug 21 06:52:55 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2245882233 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2245882233 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/234.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3952448540 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 29563483727 ps |
| CPU time | 55.58 seconds |
| Started | Aug 21 06:52:45 AM UTC 24 |
| Finished | Aug 21 06:53:42 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3952448540 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3952448540 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/235.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/236.uart_fifo_reset.2138141265 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 50851127522 ps |
| CPU time | 24.57 seconds |
| Started | Aug 21 06:52:47 AM UTC 24 |
| Finished | Aug 21 06:53:13 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2138141265 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2138141265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/236.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/237.uart_fifo_reset.3652052809 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 129174669686 ps |
| CPU time | 130.06 seconds |
| Started | Aug 21 06:52:48 AM UTC 24 |
| Finished | Aug 21 06:55:00 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3652052809 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3652052809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/237.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/238.uart_fifo_reset.1050766421 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 17346567514 ps |
| CPU time | 39.59 seconds |
| Started | Aug 21 06:52:51 AM UTC 24 |
| Finished | Aug 21 06:53:32 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1050766421 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1050766421 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/238.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_alert_test.2872409330 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 11000195 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:31:31 AM UTC 24 |
| Finished | Aug 21 06:31:34 AM UTC 24 |
| Peak memory | 202476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2872409330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2872409330 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_fifo_full.329021762 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 42690215378 ps |
| CPU time | 132.55 seconds |
| Started | Aug 21 06:30:59 AM UTC 24 |
| Finished | Aug 21 06:33:15 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=329021762 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.329021762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.443288597 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 321168476617 ps |
| CPU time | 43.3 seconds |
| Started | Aug 21 06:31:00 AM UTC 24 |
| Finished | Aug 21 06:31:45 AM UTC 24 |
| Peak memory | 208620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=443288597 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.443288597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_fifo_reset.1138748842 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 107483251788 ps |
| CPU time | 203.1 seconds |
| Started | Aug 21 06:31:03 AM UTC 24 |
| Finished | Aug 21 06:34:29 AM UTC 24 |
| Peak memory | 208648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1138748842 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1138748842 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_intr.2006340785 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 234137631757 ps |
| CPU time | 569.44 seconds |
| Started | Aug 21 06:31:09 AM UTC 24 |
| Finished | Aug 21 06:40:45 AM UTC 24 |
| Peak memory | 208872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2006340785 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2006340785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.373711782 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 91827035729 ps |
| CPU time | 231.31 seconds |
| Started | Aug 21 06:31:27 AM UTC 24 |
| Finished | Aug 21 06:35:22 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=373711782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.373711782 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_loopback.291552152 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1823594347 ps |
| CPU time | 2.24 seconds |
| Started | Aug 21 06:31:26 AM UTC 24 |
| Finished | Aug 21 06:31:30 AM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=291552152 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.291552152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_noise_filter.57582262 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 147081936769 ps |
| CPU time | 144.12 seconds |
| Started | Aug 21 06:31:15 AM UTC 24 |
| Finished | Aug 21 06:33:41 AM UTC 24 |
| Peak memory | 217668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=57582262 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.57582262 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_perf.4096732095 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 11206471114 ps |
| CPU time | 755.46 seconds |
| Started | Aug 21 06:31:27 AM UTC 24 |
| Finished | Aug 21 06:44:12 AM UTC 24 |
| Peak memory | 212284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4096732095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4096732095 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_rx_oversample.3020973117 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 5275697999 ps |
| CPU time | 49.34 seconds |
| Started | Aug 21 06:31:05 AM UTC 24 |
| Finished | Aug 21 06:31:55 AM UTC 24 |
| Peak memory | 207300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3020973117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3020973117 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.3439111926 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 33319124439 ps |
| CPU time | 59.49 seconds |
| Started | Aug 21 06:31:22 AM UTC 24 |
| Finished | Aug 21 06:32:23 AM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3439111926 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3439111926 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.3074495752 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 4293508141 ps |
| CPU time | 3.88 seconds |
| Started | Aug 21 06:31:21 AM UTC 24 |
| Finished | Aug 21 06:31:26 AM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3074495752 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3074495752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_smoke.3015420485 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 252314537 ps |
| CPU time | 1.93 seconds |
| Started | Aug 21 06:30:55 AM UTC 24 |
| Finished | Aug 21 06:30:58 AM UTC 24 |
| Peak memory | 207112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3015420485 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3015420485 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.4014789122 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1740065884 ps |
| CPU time | 30.32 seconds |
| Started | Aug 21 06:31:28 AM UTC 24 |
| Finished | Aug 21 06:32:00 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4014789122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4014789122 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2142180645 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3295193291 ps |
| CPU time | 3.34 seconds |
| Started | Aug 21 06:31:23 AM UTC 24 |
| Finished | Aug 21 06:31:27 AM UTC 24 |
| Peak memory | 208980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2142180645 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2142180645 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/24.uart_tx_rx.3159042536 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 57471284716 ps |
| CPU time | 161.33 seconds |
| Started | Aug 21 06:30:56 AM UTC 24 |
| Finished | Aug 21 06:33:40 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3159042536 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3159042536 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/24.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/240.uart_fifo_reset.949824866 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 116444957881 ps |
| CPU time | 101.64 seconds |
| Started | Aug 21 06:52:54 AM UTC 24 |
| Finished | Aug 21 06:54:37 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=949824866 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.949824866 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/240.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2851503397 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 93816783508 ps |
| CPU time | 62.65 seconds |
| Started | Aug 21 06:52:56 AM UTC 24 |
| Finished | Aug 21 06:54:00 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2851503397 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2851503397 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/241.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/242.uart_fifo_reset.84334335 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 20056023956 ps |
| CPU time | 61.8 seconds |
| Started | Aug 21 06:52:56 AM UTC 24 |
| Finished | Aug 21 06:53:59 AM UTC 24 |
| Peak memory | 208148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=84334335 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.84334335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/242.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/243.uart_fifo_reset.2801460292 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 54318698863 ps |
| CPU time | 26.37 seconds |
| Started | Aug 21 06:53:01 AM UTC 24 |
| Finished | Aug 21 06:53:29 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2801460292 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2801460292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/243.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/244.uart_fifo_reset.195231929 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 44801111051 ps |
| CPU time | 55.03 seconds |
| Started | Aug 21 06:53:04 AM UTC 24 |
| Finished | Aug 21 06:54:01 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=195231929 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.195231929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/244.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/245.uart_fifo_reset.194593809 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 29121974156 ps |
| CPU time | 85.06 seconds |
| Started | Aug 21 06:53:06 AM UTC 24 |
| Finished | Aug 21 06:54:33 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=194593809 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.194593809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/245.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2869101221 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 58946266934 ps |
| CPU time | 39.31 seconds |
| Started | Aug 21 06:53:07 AM UTC 24 |
| Finished | Aug 21 06:53:48 AM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2869101221 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2869101221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/246.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/247.uart_fifo_reset.2540896771 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 176271660147 ps |
| CPU time | 59.89 seconds |
| Started | Aug 21 06:53:08 AM UTC 24 |
| Finished | Aug 21 06:54:10 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2540896771 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2540896771 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/247.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3674164751 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 19480523357 ps |
| CPU time | 17.86 seconds |
| Started | Aug 21 06:53:08 AM UTC 24 |
| Finished | Aug 21 06:53:27 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3674164751 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3674164751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/248.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/249.uart_fifo_reset.3475235159 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 17911509886 ps |
| CPU time | 57.46 seconds |
| Started | Aug 21 06:53:09 AM UTC 24 |
| Finished | Aug 21 06:54:08 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3475235159 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3475235159 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/249.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_alert_test.2315404279 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 69882495 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:32:03 AM UTC 24 |
| Finished | Aug 21 06:32:05 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2315404279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2315404279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_fifo_full.2743743218 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 159982478436 ps |
| CPU time | 60.89 seconds |
| Started | Aug 21 06:31:35 AM UTC 24 |
| Finished | Aug 21 06:32:37 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2743743218 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2743743218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.1696876331 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 180906182604 ps |
| CPU time | 108.5 seconds |
| Started | Aug 21 06:31:36 AM UTC 24 |
| Finished | Aug 21 06:33:26 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1696876331 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1696876331 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_fifo_reset.2753756898 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 42497776501 ps |
| CPU time | 31.02 seconds |
| Started | Aug 21 06:31:37 AM UTC 24 |
| Finished | Aug 21 06:32:09 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2753756898 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2753756898 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_intr.3045706238 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 32548092655 ps |
| CPU time | 52.81 seconds |
| Started | Aug 21 06:31:42 AM UTC 24 |
| Finished | Aug 21 06:32:36 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3045706238 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3045706238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.2248832188 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 35857366499 ps |
| CPU time | 287.04 seconds |
| Started | Aug 21 06:31:57 AM UTC 24 |
| Finished | Aug 21 06:36:48 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2248832188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2248832188 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_loopback.3602435710 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3310714818 ps |
| CPU time | 7.07 seconds |
| Started | Aug 21 06:31:51 AM UTC 24 |
| Finished | Aug 21 06:32:00 AM UTC 24 |
| Peak memory | 207360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3602435710 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3602435710 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_noise_filter.332899406 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 51624986658 ps |
| CPU time | 29.85 seconds |
| Started | Aug 21 06:31:43 AM UTC 24 |
| Finished | Aug 21 06:32:14 AM UTC 24 |
| Peak memory | 207888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=332899406 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.332899406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_perf.298208481 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 12207169363 ps |
| CPU time | 543.96 seconds |
| Started | Aug 21 06:31:53 AM UTC 24 |
| Finished | Aug 21 06:41:03 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=298208481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.298208481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_rx_oversample.44317787 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1775161408 ps |
| CPU time | 11.09 seconds |
| Started | Aug 21 06:31:38 AM UTC 24 |
| Finished | Aug 21 06:31:50 AM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=44317787 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.44317787 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.3403058429 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 146540506073 ps |
| CPU time | 104.77 seconds |
| Started | Aug 21 06:31:46 AM UTC 24 |
| Finished | Aug 21 06:33:33 AM UTC 24 |
| Peak memory | 208556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3403058429 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3403058429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.915115583 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1982765377 ps |
| CPU time | 1.54 seconds |
| Started | Aug 21 06:31:44 AM UTC 24 |
| Finished | Aug 21 06:31:47 AM UTC 24 |
| Peak memory | 204584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=915115583 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.915115583 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_smoke.3602278530 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 568830879 ps |
| CPU time | 1.88 seconds |
| Started | Aug 21 06:31:34 AM UTC 24 |
| Finished | Aug 21 06:31:37 AM UTC 24 |
| Peak memory | 206584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3602278530 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3602278530 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_stress_all.3404252387 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 105532991523 ps |
| CPU time | 207.21 seconds |
| Started | Aug 21 06:32:02 AM UTC 24 |
| Finished | Aug 21 06:35:32 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3404252387 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3404252387 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.1695616141 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 8281550162 ps |
| CPU time | 46.44 seconds |
| Started | Aug 21 06:32:01 AM UTC 24 |
| Finished | Aug 21 06:32:49 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1695616141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1695616141 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.85213211 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 3968718556 ps |
| CPU time | 2.86 seconds |
| Started | Aug 21 06:31:47 AM UTC 24 |
| Finished | Aug 21 06:31:51 AM UTC 24 |
| Peak memory | 207904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=85213211 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.85213211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/25.uart_tx_rx.2662950406 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 32425426047 ps |
| CPU time | 7.62 seconds |
| Started | Aug 21 06:31:35 AM UTC 24 |
| Finished | Aug 21 06:31:44 AM UTC 24 |
| Peak memory | 208968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2662950406 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2662950406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/25.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/250.uart_fifo_reset.2665019372 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 9974318960 ps |
| CPU time | 16.76 seconds |
| Started | Aug 21 06:53:14 AM UTC 24 |
| Finished | Aug 21 06:53:31 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2665019372 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2665019372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/250.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3939945691 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 25527383259 ps |
| CPU time | 46.12 seconds |
| Started | Aug 21 06:53:15 AM UTC 24 |
| Finished | Aug 21 06:54:02 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3939945691 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3939945691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/251.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/252.uart_fifo_reset.3118876458 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 271416013864 ps |
| CPU time | 340.12 seconds |
| Started | Aug 21 06:53:15 AM UTC 24 |
| Finished | Aug 21 06:58:59 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3118876458 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3118876458 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/252.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/253.uart_fifo_reset.83704578 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 125766305350 ps |
| CPU time | 374.6 seconds |
| Started | Aug 21 06:53:16 AM UTC 24 |
| Finished | Aug 21 06:59:35 AM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=83704578 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.83704578 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/253.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/254.uart_fifo_reset.951763835 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 134085101536 ps |
| CPU time | 293.19 seconds |
| Started | Aug 21 06:53:18 AM UTC 24 |
| Finished | Aug 21 06:58:15 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=951763835 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.951763835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/254.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2034341361 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 38305713880 ps |
| CPU time | 70.88 seconds |
| Started | Aug 21 06:53:19 AM UTC 24 |
| Finished | Aug 21 06:54:31 AM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2034341361 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2034341361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/255.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1476156546 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 13841283031 ps |
| CPU time | 25.86 seconds |
| Started | Aug 21 06:53:24 AM UTC 24 |
| Finished | Aug 21 06:53:51 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1476156546 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1476156546 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/256.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3362977820 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 76064686159 ps |
| CPU time | 15.53 seconds |
| Started | Aug 21 06:53:26 AM UTC 24 |
| Finished | Aug 21 06:53:43 AM UTC 24 |
| Peak memory | 208504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362977820 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3362977820 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/257.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/258.uart_fifo_reset.774147558 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 12625435296 ps |
| CPU time | 29.32 seconds |
| Started | Aug 21 06:53:28 AM UTC 24 |
| Finished | Aug 21 06:53:59 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774147558 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.774147558 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/258.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3383779610 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 87286527158 ps |
| CPU time | 410.93 seconds |
| Started | Aug 21 06:53:28 AM UTC 24 |
| Finished | Aug 21 07:00:25 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3383779610 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3383779610 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/259.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_alert_test.3660655105 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 13565568 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:33:01 AM UTC 24 |
| Finished | Aug 21 06:33:04 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3660655105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3660655105 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2860522700 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 284886097152 ps |
| CPU time | 143.89 seconds |
| Started | Aug 21 06:32:10 AM UTC 24 |
| Finished | Aug 21 06:34:36 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2860522700 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2860522700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_intr.899544192 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 48266157398 ps |
| CPU time | 108.24 seconds |
| Started | Aug 21 06:32:23 AM UTC 24 |
| Finished | Aug 21 06:34:14 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=899544192 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.899544192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.1868992375 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 241862953962 ps |
| CPU time | 330 seconds |
| Started | Aug 21 06:32:46 AM UTC 24 |
| Finished | Aug 21 06:38:20 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1868992375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1868992375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_loopback.3885253528 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 10540210354 ps |
| CPU time | 24.33 seconds |
| Started | Aug 21 06:32:41 AM UTC 24 |
| Finished | Aug 21 06:33:06 AM UTC 24 |
| Peak memory | 208408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3885253528 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3885253528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_noise_filter.1456225464 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 98676456715 ps |
| CPU time | 31.61 seconds |
| Started | Aug 21 06:32:34 AM UTC 24 |
| Finished | Aug 21 06:33:06 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1456225464 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1456225464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_perf.3076076753 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 6073614165 ps |
| CPU time | 269.75 seconds |
| Started | Aug 21 06:32:45 AM UTC 24 |
| Finished | Aug 21 06:37:18 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3076076753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3076076753 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_rx_oversample.1984911626 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 5117539705 ps |
| CPU time | 55.56 seconds |
| Started | Aug 21 06:32:20 AM UTC 24 |
| Finished | Aug 21 06:33:17 AM UTC 24 |
| Peak memory | 208416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1984911626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1984911626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.2023555811 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 42738434039 ps |
| CPU time | 21.14 seconds |
| Started | Aug 21 06:32:38 AM UTC 24 |
| Finished | Aug 21 06:33:00 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2023555811 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2023555811 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.374527133 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 614042100 ps |
| CPU time | 1.39 seconds |
| Started | Aug 21 06:32:38 AM UTC 24 |
| Finished | Aug 21 06:32:40 AM UTC 24 |
| Peak memory | 204584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=374527133 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.374527133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_smoke.497424655 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 443589747 ps |
| CPU time | 2.12 seconds |
| Started | Aug 21 06:32:06 AM UTC 24 |
| Finished | Aug 21 06:32:09 AM UTC 24 |
| Peak memory | 207392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=497424655 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.497424655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_stress_all.1726651510 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 149189471031 ps |
| CPU time | 1567.42 seconds |
| Started | Aug 21 06:32:59 AM UTC 24 |
| Finished | Aug 21 06:59:24 AM UTC 24 |
| Peak memory | 212312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1726651510 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1726651510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.3292346813 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2377467958 ps |
| CPU time | 21.91 seconds |
| Started | Aug 21 06:32:49 AM UTC 24 |
| Finished | Aug 21 06:33:12 AM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3292346813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3292346813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2386890328 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2528903016 ps |
| CPU time | 4.07 seconds |
| Started | Aug 21 06:32:39 AM UTC 24 |
| Finished | Aug 21 06:32:44 AM UTC 24 |
| Peak memory | 207680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2386890328 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2386890328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/26.uart_tx_rx.1319095104 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 48237876634 ps |
| CPU time | 89.53 seconds |
| Started | Aug 21 06:32:07 AM UTC 24 |
| Finished | Aug 21 06:33:38 AM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1319095104 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1319095104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/26.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3954267216 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 50568604964 ps |
| CPU time | 113.75 seconds |
| Started | Aug 21 06:53:29 AM UTC 24 |
| Finished | Aug 21 06:55:25 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3954267216 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3954267216 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/260.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2274538653 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 54883285981 ps |
| CPU time | 42.63 seconds |
| Started | Aug 21 06:53:31 AM UTC 24 |
| Finished | Aug 21 06:54:15 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2274538653 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2274538653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/261.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2147569856 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 77405735337 ps |
| CPU time | 103.76 seconds |
| Started | Aug 21 06:53:32 AM UTC 24 |
| Finished | Aug 21 06:55:18 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2147569856 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2147569856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/262.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/263.uart_fifo_reset.4015494070 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 29095270633 ps |
| CPU time | 57.01 seconds |
| Started | Aug 21 06:53:33 AM UTC 24 |
| Finished | Aug 21 06:54:31 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4015494070 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.4015494070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/263.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/264.uart_fifo_reset.1440491859 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 69486706015 ps |
| CPU time | 177.07 seconds |
| Started | Aug 21 06:53:36 AM UTC 24 |
| Finished | Aug 21 06:56:35 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1440491859 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1440491859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/264.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/265.uart_fifo_reset.385386080 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 83219358480 ps |
| CPU time | 42.01 seconds |
| Started | Aug 21 06:53:43 AM UTC 24 |
| Finished | Aug 21 06:54:26 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=385386080 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.385386080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/265.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3679927213 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 73860959508 ps |
| CPU time | 165.08 seconds |
| Started | Aug 21 06:53:44 AM UTC 24 |
| Finished | Aug 21 06:56:31 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679927213 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3679927213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/266.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/267.uart_fifo_reset.958741054 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 20945188253 ps |
| CPU time | 48.95 seconds |
| Started | Aug 21 06:53:44 AM UTC 24 |
| Finished | Aug 21 06:54:34 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=958741054 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.958741054 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/267.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/268.uart_fifo_reset.166294023 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 13595387831 ps |
| CPU time | 50.9 seconds |
| Started | Aug 21 06:53:47 AM UTC 24 |
| Finished | Aug 21 06:54:39 AM UTC 24 |
| Peak memory | 208620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=166294023 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.166294023 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/268.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/269.uart_fifo_reset.2185246332 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 7850069268 ps |
| CPU time | 17.09 seconds |
| Started | Aug 21 06:53:49 AM UTC 24 |
| Finished | Aug 21 06:54:07 AM UTC 24 |
| Peak memory | 208748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2185246332 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2185246332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/269.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_alert_test.1203381110 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 14038110 ps |
| CPU time | 0.84 seconds |
| Started | Aug 21 06:33:34 AM UTC 24 |
| Finished | Aug 21 06:33:36 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1203381110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1203381110 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_fifo_full.1790538670 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 148968379813 ps |
| CPU time | 74.46 seconds |
| Started | Aug 21 06:33:04 AM UTC 24 |
| Finished | Aug 21 06:34:21 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1790538670 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1790538670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.2362089744 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 37331424696 ps |
| CPU time | 43.99 seconds |
| Started | Aug 21 06:33:08 AM UTC 24 |
| Finished | Aug 21 06:33:53 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2362089744 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2362089744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_fifo_reset.163117579 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 98136378615 ps |
| CPU time | 165.59 seconds |
| Started | Aug 21 06:33:08 AM UTC 24 |
| Finished | Aug 21 06:35:56 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=163117579 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.163117579 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_intr.844695124 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 49890315647 ps |
| CPU time | 17.84 seconds |
| Started | Aug 21 06:33:13 AM UTC 24 |
| Finished | Aug 21 06:33:32 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=844695124 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.844695124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.749183361 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 181823861021 ps |
| CPU time | 518.32 seconds |
| Started | Aug 21 06:33:25 AM UTC 24 |
| Finished | Aug 21 06:42:10 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=749183361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.749183361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_loopback.1763321057 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 9323265108 ps |
| CPU time | 21.7 seconds |
| Started | Aug 21 06:33:22 AM UTC 24 |
| Finished | Aug 21 06:33:45 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1763321057 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1763321057 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_noise_filter.3167187561 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 95238988629 ps |
| CPU time | 166.42 seconds |
| Started | Aug 21 06:33:16 AM UTC 24 |
| Finished | Aug 21 06:36:05 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3167187561 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3167187561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_perf.2338022406 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2344224232 ps |
| CPU time | 167.33 seconds |
| Started | Aug 21 06:33:22 AM UTC 24 |
| Finished | Aug 21 06:36:13 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2338022406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2338022406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_rx_oversample.3818172513 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 4538288230 ps |
| CPU time | 11.49 seconds |
| Started | Aug 21 06:33:09 AM UTC 24 |
| Finished | Aug 21 06:33:21 AM UTC 24 |
| Peak memory | 207460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3818172513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3818172513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.3760290799 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 106292866179 ps |
| CPU time | 188.07 seconds |
| Started | Aug 21 06:33:20 AM UTC 24 |
| Finished | Aug 21 06:36:31 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3760290799 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3760290799 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.3598062591 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 4947241896 ps |
| CPU time | 4.73 seconds |
| Started | Aug 21 06:33:18 AM UTC 24 |
| Finished | Aug 21 06:33:24 AM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3598062591 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3598062591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_smoke.3723684328 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 5351334684 ps |
| CPU time | 16.57 seconds |
| Started | Aug 21 06:33:01 AM UTC 24 |
| Finished | Aug 21 06:33:19 AM UTC 24 |
| Peak memory | 208400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3723684328 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3723684328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_stress_all.462133368 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 37985632155 ps |
| CPU time | 355.78 seconds |
| Started | Aug 21 06:33:32 AM UTC 24 |
| Finished | Aug 21 06:39:33 AM UTC 24 |
| Peak memory | 217744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=462133368 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.462133368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3463157449 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 14715292990 ps |
| CPU time | 77.19 seconds |
| Started | Aug 21 06:33:27 AM UTC 24 |
| Finished | Aug 21 06:34:46 AM UTC 24 |
| Peak memory | 219968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3463157449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3463157449 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.1141937556 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 7425357886 ps |
| CPU time | 13.44 seconds |
| Started | Aug 21 06:33:22 AM UTC 24 |
| Finished | Aug 21 06:33:37 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141937556 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1141937556 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/27.uart_tx_rx.4071239997 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 31279334754 ps |
| CPU time | 50.4 seconds |
| Started | Aug 21 06:33:02 AM UTC 24 |
| Finished | Aug 21 06:33:54 AM UTC 24 |
| Peak memory | 208252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4071239997 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4071239997 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/27.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/270.uart_fifo_reset.1820456956 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 117383936176 ps |
| CPU time | 212.6 seconds |
| Started | Aug 21 06:53:49 AM UTC 24 |
| Finished | Aug 21 06:57:25 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1820456956 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1820456956 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/270.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/271.uart_fifo_reset.4174123061 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 47647965726 ps |
| CPU time | 15.18 seconds |
| Started | Aug 21 06:53:52 AM UTC 24 |
| Finished | Aug 21 06:54:08 AM UTC 24 |
| Peak memory | 208888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4174123061 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.4174123061 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/271.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/272.uart_fifo_reset.1042240149 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 292701183021 ps |
| CPU time | 59.64 seconds |
| Started | Aug 21 06:53:52 AM UTC 24 |
| Finished | Aug 21 06:54:53 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042240149 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1042240149 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/272.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/273.uart_fifo_reset.930901104 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 117744245066 ps |
| CPU time | 46.7 seconds |
| Started | Aug 21 06:53:53 AM UTC 24 |
| Finished | Aug 21 06:54:41 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=930901104 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.930901104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/273.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/274.uart_fifo_reset.1065656775 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 94178743242 ps |
| CPU time | 94.18 seconds |
| Started | Aug 21 06:53:59 AM UTC 24 |
| Finished | Aug 21 06:55:36 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1065656775 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1065656775 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/274.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/275.uart_fifo_reset.1060003961 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 150310227177 ps |
| CPU time | 478.85 seconds |
| Started | Aug 21 06:54:00 AM UTC 24 |
| Finished | Aug 21 07:02:06 AM UTC 24 |
| Peak memory | 212212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1060003961 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1060003961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/275.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/276.uart_fifo_reset.1357784933 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 16099198973 ps |
| CPU time | 42.14 seconds |
| Started | Aug 21 06:54:00 AM UTC 24 |
| Finished | Aug 21 06:54:44 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1357784933 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1357784933 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/276.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/277.uart_fifo_reset.1397650302 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 35599101639 ps |
| CPU time | 80.98 seconds |
| Started | Aug 21 06:54:02 AM UTC 24 |
| Finished | Aug 21 06:55:24 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1397650302 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1397650302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/277.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2825593512 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 64670489975 ps |
| CPU time | 41.44 seconds |
| Started | Aug 21 06:54:03 AM UTC 24 |
| Finished | Aug 21 06:54:45 AM UTC 24 |
| Peak memory | 208388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2825593512 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2825593512 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/278.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2347105773 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 12063134824 ps |
| CPU time | 18.74 seconds |
| Started | Aug 21 06:54:03 AM UTC 24 |
| Finished | Aug 21 06:54:23 AM UTC 24 |
| Peak memory | 208412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347105773 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2347105773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/279.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_alert_test.1754868 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 13730068 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:34:22 AM UTC 24 |
| Finished | Aug 21 06:34:24 AM UTC 24 |
| Peak memory | 204524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1754868 -assert no postproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1754868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_fifo_full.1959478234 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 82333488673 ps |
| CPU time | 166.06 seconds |
| Started | Aug 21 06:33:39 AM UTC 24 |
| Finished | Aug 21 06:36:27 AM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1959478234 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1959478234 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_fifo_reset.3606980335 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 10022306280 ps |
| CPU time | 23.83 seconds |
| Started | Aug 21 06:33:42 AM UTC 24 |
| Finished | Aug 21 06:34:07 AM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3606980335 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3606980335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.1719800412 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 116089366535 ps |
| CPU time | 309.02 seconds |
| Started | Aug 21 06:34:12 AM UTC 24 |
| Finished | Aug 21 06:39:25 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1719800412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1719800412 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_loopback.198010995 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 4282812729 ps |
| CPU time | 9.95 seconds |
| Started | Aug 21 06:34:03 AM UTC 24 |
| Finished | Aug 21 06:34:14 AM UTC 24 |
| Peak memory | 208816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=198010995 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.198010995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_noise_filter.3880922302 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 83398842345 ps |
| CPU time | 58.03 seconds |
| Started | Aug 21 06:33:55 AM UTC 24 |
| Finished | Aug 21 06:34:55 AM UTC 24 |
| Peak memory | 207508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3880922302 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3880922302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_perf.2390565867 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 19299314790 ps |
| CPU time | 1328.25 seconds |
| Started | Aug 21 06:34:07 AM UTC 24 |
| Finished | Aug 21 06:56:31 AM UTC 24 |
| Peak memory | 212284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2390565867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2390565867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_rx_oversample.1781465275 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 5987280174 ps |
| CPU time | 50.51 seconds |
| Started | Aug 21 06:33:46 AM UTC 24 |
| Finished | Aug 21 06:34:38 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1781465275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1781465275 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.2881528501 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 130920452203 ps |
| CPU time | 78.2 seconds |
| Started | Aug 21 06:33:55 AM UTC 24 |
| Finished | Aug 21 06:35:15 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2881528501 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2881528501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.4240786987 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 501191316 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 06:33:55 AM UTC 24 |
| Finished | Aug 21 06:33:58 AM UTC 24 |
| Peak memory | 204584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4240786987 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4240786987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_smoke.4158400966 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 6067889801 ps |
| CPU time | 46.56 seconds |
| Started | Aug 21 06:33:38 AM UTC 24 |
| Finished | Aug 21 06:34:26 AM UTC 24 |
| Peak memory | 208600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4158400966 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.4158400966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_stress_all.2471117995 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 82834581515 ps |
| CPU time | 169.42 seconds |
| Started | Aug 21 06:34:16 AM UTC 24 |
| Finished | Aug 21 06:37:08 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471117995 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2471117995 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.1918063872 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 17356580511 ps |
| CPU time | 87.97 seconds |
| Started | Aug 21 06:34:15 AM UTC 24 |
| Finished | Aug 21 06:35:45 AM UTC 24 |
| Peak memory | 217600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1918063872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1918063872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.1946927049 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2696242378 ps |
| CPU time | 3.62 seconds |
| Started | Aug 21 06:33:58 AM UTC 24 |
| Finished | Aug 21 06:34:03 AM UTC 24 |
| Peak memory | 207552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1946927049 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1946927049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/28.uart_tx_rx.1430648029 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 165151076477 ps |
| CPU time | 60.26 seconds |
| Started | Aug 21 06:33:38 AM UTC 24 |
| Finished | Aug 21 06:34:39 AM UTC 24 |
| Peak memory | 208800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1430648029 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1430648029 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/28.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3123003352 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 31847901620 ps |
| CPU time | 34.43 seconds |
| Started | Aug 21 06:54:05 AM UTC 24 |
| Finished | Aug 21 06:54:41 AM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3123003352 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3123003352 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/280.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/281.uart_fifo_reset.4185435431 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 59750662990 ps |
| CPU time | 33.03 seconds |
| Started | Aug 21 06:54:08 AM UTC 24 |
| Finished | Aug 21 06:54:42 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4185435431 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4185435431 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/281.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/282.uart_fifo_reset.582649470 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 15551070167 ps |
| CPU time | 9.82 seconds |
| Started | Aug 21 06:54:09 AM UTC 24 |
| Finished | Aug 21 06:54:20 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=582649470 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.582649470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/282.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3550890664 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 10845812410 ps |
| CPU time | 22.07 seconds |
| Started | Aug 21 06:54:09 AM UTC 24 |
| Finished | Aug 21 06:54:33 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3550890664 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3550890664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/283.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/284.uart_fifo_reset.247572297 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 31985423893 ps |
| CPU time | 66.14 seconds |
| Started | Aug 21 06:54:09 AM UTC 24 |
| Finished | Aug 21 06:55:17 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=247572297 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.247572297 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/284.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/285.uart_fifo_reset.1294645529 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 99852375041 ps |
| CPU time | 109.07 seconds |
| Started | Aug 21 06:54:10 AM UTC 24 |
| Finished | Aug 21 06:56:02 AM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1294645529 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1294645529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/285.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3141649811 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 209169516979 ps |
| CPU time | 431.94 seconds |
| Started | Aug 21 06:54:16 AM UTC 24 |
| Finished | Aug 21 07:01:33 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3141649811 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3141649811 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/286.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3752495082 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 30054611998 ps |
| CPU time | 39.16 seconds |
| Started | Aug 21 06:54:17 AM UTC 24 |
| Finished | Aug 21 06:54:58 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3752495082 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3752495082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/287.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/288.uart_fifo_reset.4185274831 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 16044493923 ps |
| CPU time | 29.84 seconds |
| Started | Aug 21 06:54:21 AM UTC 24 |
| Finished | Aug 21 06:54:52 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4185274831 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.4185274831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/288.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/289.uart_fifo_reset.813677439 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 8484743439 ps |
| CPU time | 25.76 seconds |
| Started | Aug 21 06:54:22 AM UTC 24 |
| Finished | Aug 21 06:54:50 AM UTC 24 |
| Peak memory | 208964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=813677439 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.813677439 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/289.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_alert_test.187310806 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 40032885 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:35:01 AM UTC 24 |
| Finished | Aug 21 06:35:03 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=187310806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.187310806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_fifo_full.3318953479 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 121682169805 ps |
| CPU time | 284.35 seconds |
| Started | Aug 21 06:34:29 AM UTC 24 |
| Finished | Aug 21 06:39:17 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3318953479 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3318953479 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.1697427427 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 35307820050 ps |
| CPU time | 31.81 seconds |
| Started | Aug 21 06:34:34 AM UTC 24 |
| Finished | Aug 21 06:35:07 AM UTC 24 |
| Peak memory | 208516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697427427 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1697427427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_fifo_reset.2666913227 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 15395706516 ps |
| CPU time | 17.3 seconds |
| Started | Aug 21 06:34:36 AM UTC 24 |
| Finished | Aug 21 06:34:55 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2666913227 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2666913227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_intr.3584215759 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 12132706219 ps |
| CPU time | 4.98 seconds |
| Started | Aug 21 06:34:38 AM UTC 24 |
| Finished | Aug 21 06:34:45 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3584215759 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3584215759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.2881107227 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 59206770714 ps |
| CPU time | 233.4 seconds |
| Started | Aug 21 06:34:56 AM UTC 24 |
| Finished | Aug 21 06:38:53 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2881107227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2881107227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_loopback.1755913425 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1210885584 ps |
| CPU time | 3.84 seconds |
| Started | Aug 21 06:34:56 AM UTC 24 |
| Finished | Aug 21 06:35:01 AM UTC 24 |
| Peak memory | 207088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1755913425 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1755913425 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_noise_filter.2566954940 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 124277399207 ps |
| CPU time | 91.57 seconds |
| Started | Aug 21 06:34:40 AM UTC 24 |
| Finished | Aug 21 06:36:14 AM UTC 24 |
| Peak memory | 207528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2566954940 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2566954940 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_perf.3950920108 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 20680696862 ps |
| CPU time | 193.35 seconds |
| Started | Aug 21 06:34:56 AM UTC 24 |
| Finished | Aug 21 06:38:12 AM UTC 24 |
| Peak memory | 208860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950920108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3950920108 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_rx_oversample.3735209004 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 5617449522 ps |
| CPU time | 6.61 seconds |
| Started | Aug 21 06:34:37 AM UTC 24 |
| Finished | Aug 21 06:34:45 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3735209004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3735209004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.883012494 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 208305174245 ps |
| CPU time | 196.22 seconds |
| Started | Aug 21 06:34:47 AM UTC 24 |
| Finished | Aug 21 06:38:06 AM UTC 24 |
| Peak memory | 208596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=883012494 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.883012494 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.3294774604 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 57327372016 ps |
| CPU time | 60.12 seconds |
| Started | Aug 21 06:34:45 AM UTC 24 |
| Finished | Aug 21 06:35:47 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3294774604 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3294774604 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_smoke.3264995358 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 5465212771 ps |
| CPU time | 7.35 seconds |
| Started | Aug 21 06:34:25 AM UTC 24 |
| Finished | Aug 21 06:34:33 AM UTC 24 |
| Peak memory | 208344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3264995358 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3264995358 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_stress_all.4288838854 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 277729684370 ps |
| CPU time | 102.13 seconds |
| Started | Aug 21 06:35:00 AM UTC 24 |
| Finished | Aug 21 06:36:44 AM UTC 24 |
| Peak memory | 217664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4288838854 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.4288838854 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.4286528004 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 6431054144 ps |
| CPU time | 19.04 seconds |
| Started | Aug 21 06:34:48 AM UTC 24 |
| Finished | Aug 21 06:35:08 AM UTC 24 |
| Peak memory | 208600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286528004 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.4286528004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/29.uart_tx_rx.4141498360 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 25721206347 ps |
| CPU time | 33.15 seconds |
| Started | Aug 21 06:34:26 AM UTC 24 |
| Finished | Aug 21 06:35:00 AM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4141498360 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4141498360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/29.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2230285955 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 18883099798 ps |
| CPU time | 40.18 seconds |
| Started | Aug 21 06:54:23 AM UTC 24 |
| Finished | Aug 21 06:55:05 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2230285955 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2230285955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/290.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1230237175 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 63309639640 ps |
| CPU time | 106.68 seconds |
| Started | Aug 21 06:54:25 AM UTC 24 |
| Finished | Aug 21 06:56:14 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230237175 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1230237175 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/291.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/292.uart_fifo_reset.4120997161 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 60488980173 ps |
| CPU time | 29.07 seconds |
| Started | Aug 21 06:54:27 AM UTC 24 |
| Finished | Aug 21 06:54:57 AM UTC 24 |
| Peak memory | 208592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4120997161 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4120997161 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/292.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/293.uart_fifo_reset.225039812 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 124659218126 ps |
| CPU time | 98.23 seconds |
| Started | Aug 21 06:54:32 AM UTC 24 |
| Finished | Aug 21 06:56:12 AM UTC 24 |
| Peak memory | 208440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=225039812 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.225039812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/293.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/294.uart_fifo_reset.2231832193 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 264613100064 ps |
| CPU time | 107.25 seconds |
| Started | Aug 21 06:54:32 AM UTC 24 |
| Finished | Aug 21 06:56:21 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2231832193 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2231832193 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/294.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3464973865 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 71229813902 ps |
| CPU time | 85.14 seconds |
| Started | Aug 21 06:54:34 AM UTC 24 |
| Finished | Aug 21 06:56:01 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3464973865 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3464973865 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/296.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/297.uart_fifo_reset.963962129 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 194404891909 ps |
| CPU time | 300.87 seconds |
| Started | Aug 21 06:54:35 AM UTC 24 |
| Finished | Aug 21 06:59:40 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=963962129 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.963962129 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/297.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/298.uart_fifo_reset.2347043748 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 191958454874 ps |
| CPU time | 75.87 seconds |
| Started | Aug 21 06:54:38 AM UTC 24 |
| Finished | Aug 21 06:55:56 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347043748 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2347043748 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/298.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/299.uart_fifo_reset.1298922304 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 154123395162 ps |
| CPU time | 72.14 seconds |
| Started | Aug 21 06:54:40 AM UTC 24 |
| Finished | Aug 21 06:55:54 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1298922304 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1298922304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/299.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_alert_test.563759763 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 24262775 ps |
| CPU time | 0.78 seconds |
| Started | Aug 21 06:19:43 AM UTC 24 |
| Finished | Aug 21 06:19:46 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=563759763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.563759763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_fifo_full.280832230 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 73225635597 ps |
| CPU time | 51.82 seconds |
| Started | Aug 21 06:18:55 AM UTC 24 |
| Finished | Aug 21 06:19:49 AM UTC 24 |
| Peak memory | 208984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=280832230 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.280832230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.2915448392 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 73046162673 ps |
| CPU time | 84.8 seconds |
| Started | Aug 21 06:18:57 AM UTC 24 |
| Finished | Aug 21 06:20:24 AM UTC 24 |
| Peak memory | 208676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2915448392 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2915448392 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_intr.1071339769 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 40844002960 ps |
| CPU time | 10.18 seconds |
| Started | Aug 21 06:19:15 AM UTC 24 |
| Finished | Aug 21 06:19:26 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1071339769 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1071339769 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_loopback.4195090652 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 11489230211 ps |
| CPU time | 13.96 seconds |
| Started | Aug 21 06:19:27 AM UTC 24 |
| Finished | Aug 21 06:19:42 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4195090652 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4195090652 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_perf.93342725 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 18982257394 ps |
| CPU time | 96.17 seconds |
| Started | Aug 21 06:19:29 AM UTC 24 |
| Finished | Aug 21 06:21:07 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=93342725 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.93342725 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_rx_oversample.1604105618 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2199757891 ps |
| CPU time | 13.8 seconds |
| Started | Aug 21 06:19:04 AM UTC 24 |
| Finished | Aug 21 06:19:19 AM UTC 24 |
| Peak memory | 207228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1604105618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1604105618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.646980498 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4384841643 ps |
| CPU time | 15.61 seconds |
| Started | Aug 21 06:19:19 AM UTC 24 |
| Finished | Aug 21 06:19:36 AM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646980498 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.646980498 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_sec_cm.4001735976 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 35348058 ps |
| CPU time | 1.12 seconds |
| Started | Aug 21 06:19:40 AM UTC 24 |
| Finished | Aug 21 06:19:42 AM UTC 24 |
| Peak memory | 239604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4001735976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.4001735976 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_smoke.1038176110 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 873043322 ps |
| CPU time | 2.97 seconds |
| Started | Aug 21 06:18:50 AM UTC 24 |
| Finished | Aug 21 06:18:54 AM UTC 24 |
| Peak memory | 208312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1038176110 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1038176110 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.3282003546 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1562965776 ps |
| CPU time | 21.24 seconds |
| Started | Aug 21 06:19:36 AM UTC 24 |
| Finished | Aug 21 06:19:59 AM UTC 24 |
| Peak memory | 217500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3282003546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3282003546 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.529248965 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1393800624 ps |
| CPU time | 3.9 seconds |
| Started | Aug 21 06:19:27 AM UTC 24 |
| Finished | Aug 21 06:19:32 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=529248965 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.529248965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/3.uart_tx_rx.1256796090 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 46209370713 ps |
| CPU time | 119.09 seconds |
| Started | Aug 21 06:18:51 AM UTC 24 |
| Finished | Aug 21 06:20:53 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1256796090 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1256796090 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/3.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_alert_test.1920066281 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 45126913 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:35:32 AM UTC 24 |
| Finished | Aug 21 06:35:34 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1920066281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1920066281 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_fifo_full.890880368 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 21190787611 ps |
| CPU time | 27.35 seconds |
| Started | Aug 21 06:35:03 AM UTC 24 |
| Finished | Aug 21 06:35:32 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=890880368 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.890880368 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.1676167302 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 14646501205 ps |
| CPU time | 21.25 seconds |
| Started | Aug 21 06:35:04 AM UTC 24 |
| Finished | Aug 21 06:35:27 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1676167302 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1676167302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_fifo_reset.3236426053 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 69233701787 ps |
| CPU time | 100.65 seconds |
| Started | Aug 21 06:35:06 AM UTC 24 |
| Finished | Aug 21 06:36:49 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3236426053 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3236426053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_intr.1187606214 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 13965591235 ps |
| CPU time | 16.55 seconds |
| Started | Aug 21 06:35:09 AM UTC 24 |
| Finished | Aug 21 06:35:26 AM UTC 24 |
| Peak memory | 207164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1187606214 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1187606214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.1299423545 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 433265151655 ps |
| CPU time | 375.07 seconds |
| Started | Aug 21 06:35:28 AM UTC 24 |
| Finished | Aug 21 06:41:48 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1299423545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1299423545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_loopback.3574805894 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 9619952308 ps |
| CPU time | 30.37 seconds |
| Started | Aug 21 06:35:25 AM UTC 24 |
| Finished | Aug 21 06:35:57 AM UTC 24 |
| Peak memory | 208320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3574805894 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3574805894 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_noise_filter.191330468 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 160012111243 ps |
| CPU time | 76.7 seconds |
| Started | Aug 21 06:35:13 AM UTC 24 |
| Finished | Aug 21 06:36:31 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=191330468 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.191330468 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_perf.1136455211 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 9971082256 ps |
| CPU time | 156.54 seconds |
| Started | Aug 21 06:35:27 AM UTC 24 |
| Finished | Aug 21 06:38:06 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1136455211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1136455211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_rx_oversample.3412408629 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 7039113200 ps |
| CPU time | 54.74 seconds |
| Started | Aug 21 06:35:09 AM UTC 24 |
| Finished | Aug 21 06:36:05 AM UTC 24 |
| Peak memory | 208040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3412408629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3412408629 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.143640779 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 195581156331 ps |
| CPU time | 78.56 seconds |
| Started | Aug 21 06:35:23 AM UTC 24 |
| Finished | Aug 21 06:36:43 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=143640779 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.143640779 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.1431061222 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3250701744 ps |
| CPU time | 7.39 seconds |
| Started | Aug 21 06:35:16 AM UTC 24 |
| Finished | Aug 21 06:35:24 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1431061222 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1431061222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_smoke.1853527714 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 278066465 ps |
| CPU time | 1.5 seconds |
| Started | Aug 21 06:35:01 AM UTC 24 |
| Finished | Aug 21 06:35:04 AM UTC 24 |
| Peak memory | 207016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1853527714 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1853527714 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_stress_all.3353086036 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 41518436153 ps |
| CPU time | 285.89 seconds |
| Started | Aug 21 06:35:32 AM UTC 24 |
| Finished | Aug 21 06:40:22 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3353086036 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3353086036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.1801914775 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 553811983 ps |
| CPU time | 8.79 seconds |
| Started | Aug 21 06:35:28 AM UTC 24 |
| Finished | Aug 21 06:35:38 AM UTC 24 |
| Peak memory | 208956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1801914775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1801914775 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3732833508 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 6505130263 ps |
| CPU time | 19.27 seconds |
| Started | Aug 21 06:35:24 AM UTC 24 |
| Finished | Aug 21 06:35:44 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3732833508 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3732833508 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/30.uart_tx_rx.3681119643 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 84865446439 ps |
| CPU time | 214.95 seconds |
| Started | Aug 21 06:35:02 AM UTC 24 |
| Finished | Aug 21 06:38:40 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3681119643 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3681119643 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/30.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_alert_test.2854148595 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 43918049 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:36:14 AM UTC 24 |
| Finished | Aug 21 06:36:16 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854148595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2854148595 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_fifo_full.1701063001 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 108334260304 ps |
| CPU time | 161.03 seconds |
| Started | Aug 21 06:35:41 AM UTC 24 |
| Finished | Aug 21 06:38:24 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1701063001 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1701063001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.2221255943 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 37239878320 ps |
| CPU time | 28.24 seconds |
| Started | Aug 21 06:35:42 AM UTC 24 |
| Finished | Aug 21 06:36:11 AM UTC 24 |
| Peak memory | 208480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2221255943 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2221255943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_fifo_reset.3423546902 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 100158275151 ps |
| CPU time | 56.38 seconds |
| Started | Aug 21 06:35:45 AM UTC 24 |
| Finished | Aug 21 06:36:43 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3423546902 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3423546902 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_intr.504656218 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 55088448194 ps |
| CPU time | 113.44 seconds |
| Started | Aug 21 06:35:48 AM UTC 24 |
| Finished | Aug 21 06:37:43 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=504656218 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.504656218 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3709213316 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 136609116238 ps |
| CPU time | 205.93 seconds |
| Started | Aug 21 06:36:12 AM UTC 24 |
| Finished | Aug 21 06:39:42 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3709213316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3709213316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_loopback.3212034517 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 4834681132 ps |
| CPU time | 5.79 seconds |
| Started | Aug 21 06:36:06 AM UTC 24 |
| Finished | Aug 21 06:36:13 AM UTC 24 |
| Peak memory | 208100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3212034517 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3212034517 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_noise_filter.3984135561 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 106056244095 ps |
| CPU time | 144.21 seconds |
| Started | Aug 21 06:35:57 AM UTC 24 |
| Finished | Aug 21 06:38:24 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3984135561 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3984135561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_perf.1659773298 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 16172297596 ps |
| CPU time | 646.65 seconds |
| Started | Aug 21 06:36:12 AM UTC 24 |
| Finished | Aug 21 06:47:07 AM UTC 24 |
| Peak memory | 212308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1659773298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1659773298 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_rx_oversample.592985028 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 6155087891 ps |
| CPU time | 56.83 seconds |
| Started | Aug 21 06:35:46 AM UTC 24 |
| Finished | Aug 21 06:36:44 AM UTC 24 |
| Peak memory | 208164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=592985028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.592985028 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.885078929 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 36833552806 ps |
| CPU time | 59.63 seconds |
| Started | Aug 21 06:36:05 AM UTC 24 |
| Finished | Aug 21 06:37:06 AM UTC 24 |
| Peak memory | 208500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=885078929 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.885078929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.3434698014 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 35790302527 ps |
| CPU time | 14.72 seconds |
| Started | Aug 21 06:35:57 AM UTC 24 |
| Finished | Aug 21 06:36:13 AM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3434698014 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3434698014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_smoke.3841594406 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 490773746 ps |
| CPU time | 4.46 seconds |
| Started | Aug 21 06:35:35 AM UTC 24 |
| Finished | Aug 21 06:35:41 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3841594406 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3841594406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_stress_all.2173142468 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 149173291583 ps |
| CPU time | 605.79 seconds |
| Started | Aug 21 06:36:14 AM UTC 24 |
| Finished | Aug 21 06:46:27 AM UTC 24 |
| Peak memory | 219176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2173142468 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2173142468 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.3489228292 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 14704588409 ps |
| CPU time | 44.8 seconds |
| Started | Aug 21 06:36:12 AM UTC 24 |
| Finished | Aug 21 06:36:59 AM UTC 24 |
| Peak memory | 219704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3489228292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3489228292 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.1244625223 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 762540860 ps |
| CPU time | 5.13 seconds |
| Started | Aug 21 06:36:05 AM UTC 24 |
| Finished | Aug 21 06:36:11 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1244625223 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1244625223 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/31.uart_tx_rx.3951738488 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 307454432969 ps |
| CPU time | 56.19 seconds |
| Started | Aug 21 06:35:38 AM UTC 24 |
| Finished | Aug 21 06:36:36 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3951738488 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3951738488 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/31.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_alert_test.2395926962 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 14379750 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 06:36:50 AM UTC 24 |
| Finished | Aug 21 06:36:52 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2395926962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2395926962 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_fifo_full.1601537867 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 68021124138 ps |
| CPU time | 35.16 seconds |
| Started | Aug 21 06:36:15 AM UTC 24 |
| Finished | Aug 21 06:36:52 AM UTC 24 |
| Peak memory | 208928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1601537867 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1601537867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.4261837131 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 38827432796 ps |
| CPU time | 50.08 seconds |
| Started | Aug 21 06:36:17 AM UTC 24 |
| Finished | Aug 21 06:37:08 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4261837131 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4261837131 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_intr.4233807190 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 438892127964 ps |
| CPU time | 164.22 seconds |
| Started | Aug 21 06:36:32 AM UTC 24 |
| Finished | Aug 21 06:39:19 AM UTC 24 |
| Peak memory | 207248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4233807190 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4233807190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.79486055 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 142673382302 ps |
| CPU time | 421.43 seconds |
| Started | Aug 21 06:36:45 AM UTC 24 |
| Finished | Aug 21 06:43:52 AM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79486055 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.79486055 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_loopback.230644897 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 12191392797 ps |
| CPU time | 44.51 seconds |
| Started | Aug 21 06:36:44 AM UTC 24 |
| Finished | Aug 21 06:37:30 AM UTC 24 |
| Peak memory | 208824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=230644897 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.230644897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_noise_filter.44175105 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 89314794362 ps |
| CPU time | 53.98 seconds |
| Started | Aug 21 06:36:34 AM UTC 24 |
| Finished | Aug 21 06:37:30 AM UTC 24 |
| Peak memory | 217476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=44175105 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.44175105 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_perf.3232214383 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 19901247106 ps |
| CPU time | 255.73 seconds |
| Started | Aug 21 06:36:45 AM UTC 24 |
| Finished | Aug 21 06:41:04 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3232214383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3232214383 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_rx_oversample.1896219066 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2561447770 ps |
| CPU time | 6.8 seconds |
| Started | Aug 21 06:36:32 AM UTC 24 |
| Finished | Aug 21 06:36:40 AM UTC 24 |
| Peak memory | 207300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1896219066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1896219066 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.2680264279 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 48792400994 ps |
| CPU time | 136 seconds |
| Started | Aug 21 06:36:40 AM UTC 24 |
| Finished | Aug 21 06:38:59 AM UTC 24 |
| Peak memory | 208812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2680264279 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2680264279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.176274586 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 3606183861 ps |
| CPU time | 6.46 seconds |
| Started | Aug 21 06:36:37 AM UTC 24 |
| Finished | Aug 21 06:36:45 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=176274586 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.176274586 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_smoke.4240999562 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 5890822935 ps |
| CPU time | 39.08 seconds |
| Started | Aug 21 06:36:14 AM UTC 24 |
| Finished | Aug 21 06:36:55 AM UTC 24 |
| Peak memory | 208428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4240999562 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.4240999562 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_stress_all.2243118127 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 169448168605 ps |
| CPU time | 236.82 seconds |
| Started | Aug 21 06:36:49 AM UTC 24 |
| Finished | Aug 21 06:40:49 AM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2243118127 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2243118127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.3636024763 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 9212679435 ps |
| CPU time | 40.63 seconds |
| Started | Aug 21 06:36:46 AM UTC 24 |
| Finished | Aug 21 06:37:28 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3636024763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3636024763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.4286401895 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2164988988 ps |
| CPU time | 4.09 seconds |
| Started | Aug 21 06:36:44 AM UTC 24 |
| Finished | Aug 21 06:36:49 AM UTC 24 |
| Peak memory | 207384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286401895 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4286401895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/32.uart_tx_rx.278254763 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 73685131977 ps |
| CPU time | 76.52 seconds |
| Started | Aug 21 06:36:15 AM UTC 24 |
| Finished | Aug 21 06:37:33 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=278254763 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.278254763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/32.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_alert_test.1595726955 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 17146912 ps |
| CPU time | 0.85 seconds |
| Started | Aug 21 06:37:25 AM UTC 24 |
| Finished | Aug 21 06:37:27 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1595726955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1595726955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_fifo_full.1042257867 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 148719042211 ps |
| CPU time | 346.72 seconds |
| Started | Aug 21 06:36:53 AM UTC 24 |
| Finished | Aug 21 06:42:45 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042257867 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1042257867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.106920287 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 19000994251 ps |
| CPU time | 35.72 seconds |
| Started | Aug 21 06:36:55 AM UTC 24 |
| Finished | Aug 21 06:37:32 AM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=106920287 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.106920287 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_fifo_reset.2693546208 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 36377208566 ps |
| CPU time | 29.47 seconds |
| Started | Aug 21 06:37:00 AM UTC 24 |
| Finished | Aug 21 06:37:31 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2693546208 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2693546208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_intr.2731440524 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 46659536448 ps |
| CPU time | 69.34 seconds |
| Started | Aug 21 06:37:07 AM UTC 24 |
| Finished | Aug 21 06:38:18 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2731440524 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2731440524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2812707005 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 93952284886 ps |
| CPU time | 410.82 seconds |
| Started | Aug 21 06:37:23 AM UTC 24 |
| Finished | Aug 21 06:44:19 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2812707005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2812707005 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_loopback.1576560538 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 12216727073 ps |
| CPU time | 10.62 seconds |
| Started | Aug 21 06:37:21 AM UTC 24 |
| Finished | Aug 21 06:37:33 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1576560538 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1576560538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_noise_filter.4175722572 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 32199282810 ps |
| CPU time | 23.94 seconds |
| Started | Aug 21 06:37:09 AM UTC 24 |
| Finished | Aug 21 06:37:34 AM UTC 24 |
| Peak memory | 207908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4175722572 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4175722572 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_perf.3702051858 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 15733836320 ps |
| CPU time | 239.52 seconds |
| Started | Aug 21 06:37:21 AM UTC 24 |
| Finished | Aug 21 06:41:24 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3702051858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3702051858 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_rx_oversample.2222022902 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3955454970 ps |
| CPU time | 5.05 seconds |
| Started | Aug 21 06:37:02 AM UTC 24 |
| Finished | Aug 21 06:37:09 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2222022902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2222022902 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.2116330517 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 53882109883 ps |
| CPU time | 94.58 seconds |
| Started | Aug 21 06:37:10 AM UTC 24 |
| Finished | Aug 21 06:38:46 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2116330517 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2116330517 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.922343608 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 3487997611 ps |
| CPU time | 11.06 seconds |
| Started | Aug 21 06:37:10 AM UTC 24 |
| Finished | Aug 21 06:37:22 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=922343608 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.922343608 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_smoke.3336994189 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 5730118019 ps |
| CPU time | 28.94 seconds |
| Started | Aug 21 06:36:50 AM UTC 24 |
| Finished | Aug 21 06:37:20 AM UTC 24 |
| Peak memory | 207864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3336994189 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3336994189 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_stress_all.2422421686 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 186220252479 ps |
| CPU time | 372.77 seconds |
| Started | Aug 21 06:37:24 AM UTC 24 |
| Finished | Aug 21 06:43:42 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422421686 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2422421686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.245528622 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 10444772342 ps |
| CPU time | 30.02 seconds |
| Started | Aug 21 06:37:23 AM UTC 24 |
| Finished | Aug 21 06:37:55 AM UTC 24 |
| Peak memory | 219848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=245528622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.245528622 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.2538175647 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1186783416 ps |
| CPU time | 2.09 seconds |
| Started | Aug 21 06:37:19 AM UTC 24 |
| Finished | Aug 21 06:37:22 AM UTC 24 |
| Peak memory | 207012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538175647 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2538175647 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/33.uart_tx_rx.2704244049 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 112812495194 ps |
| CPU time | 26.98 seconds |
| Started | Aug 21 06:36:52 AM UTC 24 |
| Finished | Aug 21 06:37:20 AM UTC 24 |
| Peak memory | 207160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2704244049 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2704244049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/33.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_alert_test.755466436 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 35179728 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:37:42 AM UTC 24 |
| Finished | Aug 21 06:37:45 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=755466436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.755466436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_fifo_full.1104279787 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 48272476592 ps |
| CPU time | 37.09 seconds |
| Started | Aug 21 06:37:28 AM UTC 24 |
| Finished | Aug 21 06:38:07 AM UTC 24 |
| Peak memory | 208800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1104279787 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1104279787 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.4292661637 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 62532945746 ps |
| CPU time | 134.52 seconds |
| Started | Aug 21 06:37:30 AM UTC 24 |
| Finished | Aug 21 06:39:47 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292661637 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.4292661637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_fifo_reset.3594797053 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 72663707733 ps |
| CPU time | 38.45 seconds |
| Started | Aug 21 06:37:30 AM UTC 24 |
| Finished | Aug 21 06:38:10 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594797053 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3594797053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_intr.333371602 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 35993590910 ps |
| CPU time | 32.83 seconds |
| Started | Aug 21 06:37:32 AM UTC 24 |
| Finished | Aug 21 06:38:06 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=333371602 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.333371602 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.1248057658 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 346054348107 ps |
| CPU time | 155.36 seconds |
| Started | Aug 21 06:37:41 AM UTC 24 |
| Finished | Aug 21 06:40:19 AM UTC 24 |
| Peak memory | 208620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1248057658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1248057658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_loopback.1855345961 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4267977110 ps |
| CPU time | 4.74 seconds |
| Started | Aug 21 06:37:35 AM UTC 24 |
| Finished | Aug 21 06:37:41 AM UTC 24 |
| Peak memory | 205168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1855345961 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1855345961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_noise_filter.3997664566 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 116134187984 ps |
| CPU time | 249.3 seconds |
| Started | Aug 21 06:37:33 AM UTC 24 |
| Finished | Aug 21 06:41:46 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3997664566 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3997664566 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_perf.2107901894 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 17366039192 ps |
| CPU time | 249.52 seconds |
| Started | Aug 21 06:37:37 AM UTC 24 |
| Finished | Aug 21 06:41:50 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2107901894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2107901894 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_rx_oversample.3126745622 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4702882005 ps |
| CPU time | 8.44 seconds |
| Started | Aug 21 06:37:32 AM UTC 24 |
| Finished | Aug 21 06:37:41 AM UTC 24 |
| Peak memory | 207496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3126745622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3126745622 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.904848958 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 105436899489 ps |
| CPU time | 52.25 seconds |
| Started | Aug 21 06:37:34 AM UTC 24 |
| Finished | Aug 21 06:38:28 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=904848958 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.904848958 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.2135521679 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 38507789709 ps |
| CPU time | 51.86 seconds |
| Started | Aug 21 06:37:33 AM UTC 24 |
| Finished | Aug 21 06:38:26 AM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2135521679 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2135521679 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_smoke.4180286951 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 499237845 ps |
| CPU time | 1.93 seconds |
| Started | Aug 21 06:37:27 AM UTC 24 |
| Finished | Aug 21 06:37:30 AM UTC 24 |
| Peak memory | 207904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4180286951 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4180286951 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_stress_all.3596686307 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 86632137620 ps |
| CPU time | 128.33 seconds |
| Started | Aug 21 06:37:42 AM UTC 24 |
| Finished | Aug 21 06:39:54 AM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3596686307 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3596686307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.3832558549 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 321315331 ps |
| CPU time | 4.19 seconds |
| Started | Aug 21 06:37:41 AM UTC 24 |
| Finished | Aug 21 06:37:46 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3832558549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3832558549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.3044852207 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 755189488 ps |
| CPU time | 4.85 seconds |
| Started | Aug 21 06:37:34 AM UTC 24 |
| Finished | Aug 21 06:37:40 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3044852207 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3044852207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/34.uart_tx_rx.3905335822 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 24925631095 ps |
| CPU time | 19.07 seconds |
| Started | Aug 21 06:37:28 AM UTC 24 |
| Finished | Aug 21 06:37:49 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3905335822 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3905335822 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/34.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_alert_test.3655470636 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 13718147 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:38:12 AM UTC 24 |
| Finished | Aug 21 06:38:13 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3655470636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3655470636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_fifo_full.269740034 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 34777676229 ps |
| CPU time | 93.03 seconds |
| Started | Aug 21 06:37:48 AM UTC 24 |
| Finished | Aug 21 06:39:23 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=269740034 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.269740034 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.3217688327 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 30737454692 ps |
| CPU time | 35.83 seconds |
| Started | Aug 21 06:37:48 AM UTC 24 |
| Finished | Aug 21 06:38:25 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3217688327 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3217688327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_fifo_reset.4269105953 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 61883156215 ps |
| CPU time | 108.79 seconds |
| Started | Aug 21 06:37:50 AM UTC 24 |
| Finished | Aug 21 06:39:41 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4269105953 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4269105953 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_intr.873928081 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 14842847575 ps |
| CPU time | 12.55 seconds |
| Started | Aug 21 06:37:55 AM UTC 24 |
| Finished | Aug 21 06:38:09 AM UTC 24 |
| Peak memory | 207284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=873928081 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.873928081 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.227260228 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 50910914659 ps |
| CPU time | 192.02 seconds |
| Started | Aug 21 06:38:09 AM UTC 24 |
| Finished | Aug 21 06:41:24 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=227260228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.227260228 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_loopback.1913970207 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 7461142805 ps |
| CPU time | 4.01 seconds |
| Started | Aug 21 06:38:09 AM UTC 24 |
| Finished | Aug 21 06:38:14 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1913970207 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1913970207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_noise_filter.1554224434 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 89389212724 ps |
| CPU time | 226.6 seconds |
| Started | Aug 21 06:38:07 AM UTC 24 |
| Finished | Aug 21 06:41:57 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1554224434 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1554224434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_perf.4004781812 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 21023931734 ps |
| CPU time | 1065.42 seconds |
| Started | Aug 21 06:38:09 AM UTC 24 |
| Finished | Aug 21 06:56:07 AM UTC 24 |
| Peak memory | 212212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4004781812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.4004781812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_rx_oversample.2043650775 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 5348458703 ps |
| CPU time | 16.24 seconds |
| Started | Aug 21 06:37:51 AM UTC 24 |
| Finished | Aug 21 06:38:08 AM UTC 24 |
| Peak memory | 207972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2043650775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2043650775 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.312854350 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 74745493197 ps |
| CPU time | 120.04 seconds |
| Started | Aug 21 06:38:07 AM UTC 24 |
| Finished | Aug 21 06:40:09 AM UTC 24 |
| Peak memory | 208864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=312854350 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.312854350 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.1536684702 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2750490223 ps |
| CPU time | 3.07 seconds |
| Started | Aug 21 06:38:07 AM UTC 24 |
| Finished | Aug 21 06:38:11 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1536684702 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1536684702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_smoke.3055717808 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 267151343 ps |
| CPU time | 2 seconds |
| Started | Aug 21 06:37:44 AM UTC 24 |
| Finished | Aug 21 06:37:48 AM UTC 24 |
| Peak memory | 206584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3055717808 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3055717808 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_stress_all.2926071510 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 430056791111 ps |
| CPU time | 668.48 seconds |
| Started | Aug 21 06:38:12 AM UTC 24 |
| Finished | Aug 21 06:49:29 AM UTC 24 |
| Peak memory | 222728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2926071510 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2926071510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.924771351 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 4982057280 ps |
| CPU time | 49.41 seconds |
| Started | Aug 21 06:38:09 AM UTC 24 |
| Finished | Aug 21 06:39:00 AM UTC 24 |
| Peak memory | 219800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=924771351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.924771351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.2050151711 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3115949884 ps |
| CPU time | 2.23 seconds |
| Started | Aug 21 06:38:09 AM UTC 24 |
| Finished | Aug 21 06:38:12 AM UTC 24 |
| Peak memory | 207856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2050151711 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2050151711 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/35.uart_tx_rx.2609963840 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 65096359896 ps |
| CPU time | 38.57 seconds |
| Started | Aug 21 06:37:45 AM UTC 24 |
| Finished | Aug 21 06:38:26 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2609963840 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2609963840 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/35.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_alert_test.886704802 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 18063818 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:38:31 AM UTC 24 |
| Finished | Aug 21 06:38:33 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=886704802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.886704802 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_fifo_full.2159053662 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 139309809440 ps |
| CPU time | 271.6 seconds |
| Started | Aug 21 06:38:14 AM UTC 24 |
| Finished | Aug 21 06:42:49 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2159053662 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2159053662 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.3924162765 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 247506550029 ps |
| CPU time | 126.6 seconds |
| Started | Aug 21 06:38:16 AM UTC 24 |
| Finished | Aug 21 06:40:25 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924162765 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3924162765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_fifo_reset.3914639345 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 22250958912 ps |
| CPU time | 14.26 seconds |
| Started | Aug 21 06:38:17 AM UTC 24 |
| Finished | Aug 21 06:38:32 AM UTC 24 |
| Peak memory | 208348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3914639345 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3914639345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_intr.3897423357 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 7100850511 ps |
| CPU time | 5.88 seconds |
| Started | Aug 21 06:38:21 AM UTC 24 |
| Finished | Aug 21 06:38:28 AM UTC 24 |
| Peak memory | 207292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3897423357 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3897423357 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.2619649983 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 102137381009 ps |
| CPU time | 306.58 seconds |
| Started | Aug 21 06:38:29 AM UTC 24 |
| Finished | Aug 21 06:43:39 AM UTC 24 |
| Peak memory | 208956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2619649983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2619649983 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_loopback.4098076943 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 11025115240 ps |
| CPU time | 39.27 seconds |
| Started | Aug 21 06:38:27 AM UTC 24 |
| Finished | Aug 21 06:39:07 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4098076943 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.4098076943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_noise_filter.53143052 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 26327859397 ps |
| CPU time | 22.67 seconds |
| Started | Aug 21 06:38:22 AM UTC 24 |
| Finished | Aug 21 06:38:46 AM UTC 24 |
| Peak memory | 205248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=53143052 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.53143052 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_perf.3144233 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 10689554102 ps |
| CPU time | 154.47 seconds |
| Started | Aug 21 06:38:27 AM UTC 24 |
| Finished | Aug 21 06:41:04 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3144233 -assert nopostproc +U VM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc h/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3144233 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_rx_oversample.3823816116 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 5504751450 ps |
| CPU time | 14.93 seconds |
| Started | Aug 21 06:38:19 AM UTC 24 |
| Finished | Aug 21 06:38:35 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3823816116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3823816116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.3022688471 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 99054996158 ps |
| CPU time | 187.92 seconds |
| Started | Aug 21 06:38:25 AM UTC 24 |
| Finished | Aug 21 06:41:36 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3022688471 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3022688471 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1052447762 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3774588333 ps |
| CPU time | 4.23 seconds |
| Started | Aug 21 06:38:24 AM UTC 24 |
| Finished | Aug 21 06:38:30 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1052447762 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1052447762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_smoke.3192037482 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 813307725 ps |
| CPU time | 1.83 seconds |
| Started | Aug 21 06:38:14 AM UTC 24 |
| Finished | Aug 21 06:38:17 AM UTC 24 |
| Peak memory | 207696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3192037482 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3192037482 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_stress_all.251988850 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 96600277967 ps |
| CPU time | 364.51 seconds |
| Started | Aug 21 06:38:31 AM UTC 24 |
| Finished | Aug 21 06:44:40 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=251988850 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.251988850 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.2992518740 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 7231479493 ps |
| CPU time | 35.89 seconds |
| Started | Aug 21 06:38:29 AM UTC 24 |
| Finished | Aug 21 06:39:06 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2992518740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2992518740 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.2354481366 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 818388132 ps |
| CPU time | 4 seconds |
| Started | Aug 21 06:38:25 AM UTC 24 |
| Finished | Aug 21 06:38:30 AM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354481366 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2354481366 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/36.uart_tx_rx.2048892206 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 135898833165 ps |
| CPU time | 186.06 seconds |
| Started | Aug 21 06:38:14 AM UTC 24 |
| Finished | Aug 21 06:41:23 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2048892206 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2048892206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/36.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_alert_test.3136159759 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 22144554 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:39:13 AM UTC 24 |
| Finished | Aug 21 06:39:15 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3136159759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3136159759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_fifo_full.1594477970 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 175388177261 ps |
| CPU time | 125.09 seconds |
| Started | Aug 21 06:38:36 AM UTC 24 |
| Finished | Aug 21 06:40:43 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1594477970 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1594477970 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.3665878247 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 133369798350 ps |
| CPU time | 72.14 seconds |
| Started | Aug 21 06:38:36 AM UTC 24 |
| Finished | Aug 21 06:39:50 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3665878247 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3665878247 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_fifo_reset.3357669724 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 9982942454 ps |
| CPU time | 19.91 seconds |
| Started | Aug 21 06:38:41 AM UTC 24 |
| Finished | Aug 21 06:39:02 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3357669724 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3357669724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_intr.2948903573 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 27791327853 ps |
| CPU time | 30.49 seconds |
| Started | Aug 21 06:38:47 AM UTC 24 |
| Finished | Aug 21 06:39:19 AM UTC 24 |
| Peak memory | 207244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2948903573 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2948903573 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1519418908 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 120832323933 ps |
| CPU time | 352.73 seconds |
| Started | Aug 21 06:39:07 AM UTC 24 |
| Finished | Aug 21 06:45:04 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519418908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1519418908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_loopback.3432492637 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 374667376 ps |
| CPU time | 2.28 seconds |
| Started | Aug 21 06:39:03 AM UTC 24 |
| Finished | Aug 21 06:39:06 AM UTC 24 |
| Peak memory | 205040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3432492637 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3432492637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_noise_filter.1757066650 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 122951665187 ps |
| CPU time | 139.49 seconds |
| Started | Aug 21 06:38:53 AM UTC 24 |
| Finished | Aug 21 06:41:15 AM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1757066650 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1757066650 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_perf.267744598 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 8234103465 ps |
| CPU time | 109.06 seconds |
| Started | Aug 21 06:39:06 AM UTC 24 |
| Finished | Aug 21 06:40:57 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=267744598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.267744598 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_rx_oversample.3552311380 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4516099225 ps |
| CPU time | 24.19 seconds |
| Started | Aug 21 06:38:47 AM UTC 24 |
| Finished | Aug 21 06:39:13 AM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3552311380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3552311380 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.3313552427 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 78017848797 ps |
| CPU time | 234.96 seconds |
| Started | Aug 21 06:39:00 AM UTC 24 |
| Finished | Aug 21 06:42:58 AM UTC 24 |
| Peak memory | 208680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3313552427 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3313552427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.1402814812 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 29718722260 ps |
| CPU time | 34.17 seconds |
| Started | Aug 21 06:39:00 AM UTC 24 |
| Finished | Aug 21 06:39:35 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1402814812 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1402814812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_smoke.3914274236 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 98380534 ps |
| CPU time | 1.42 seconds |
| Started | Aug 21 06:38:33 AM UTC 24 |
| Finished | Aug 21 06:38:35 AM UTC 24 |
| Peak memory | 206568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3914274236 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3914274236 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_stress_all.3090464155 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 427617736331 ps |
| CPU time | 156.16 seconds |
| Started | Aug 21 06:39:08 AM UTC 24 |
| Finished | Aug 21 06:41:46 AM UTC 24 |
| Peak memory | 217608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3090464155 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3090464155 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.2181812248 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2232377890 ps |
| CPU time | 33.75 seconds |
| Started | Aug 21 06:39:07 AM UTC 24 |
| Finished | Aug 21 06:39:42 AM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2181812248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2181812248 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.1478482792 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1045534637 ps |
| CPU time | 2.01 seconds |
| Started | Aug 21 06:39:02 AM UTC 24 |
| Finished | Aug 21 06:39:05 AM UTC 24 |
| Peak memory | 206568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1478482792 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1478482792 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/37.uart_tx_rx.2228617220 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 115531675842 ps |
| CPU time | 215.51 seconds |
| Started | Aug 21 06:38:33 AM UTC 24 |
| Finished | Aug 21 06:42:11 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2228617220 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2228617220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/37.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_alert_test.3059215488 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 11342354 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:39:50 AM UTC 24 |
| Finished | Aug 21 06:39:52 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3059215488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3059215488 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_fifo_full.2066961217 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 120769434745 ps |
| CPU time | 243.95 seconds |
| Started | Aug 21 06:39:19 AM UTC 24 |
| Finished | Aug 21 06:43:27 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2066961217 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2066961217 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.2116483102 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 87802957835 ps |
| CPU time | 176.8 seconds |
| Started | Aug 21 06:39:20 AM UTC 24 |
| Finished | Aug 21 06:42:20 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2116483102 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2116483102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3322335416 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 114859966509 ps |
| CPU time | 134.54 seconds |
| Started | Aug 21 06:39:23 AM UTC 24 |
| Finished | Aug 21 06:41:40 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3322335416 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3322335416 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_intr.3795367954 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 162830936477 ps |
| CPU time | 270.87 seconds |
| Started | Aug 21 06:39:26 AM UTC 24 |
| Finished | Aug 21 06:44:00 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3795367954 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3795367954 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.872060354 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 58497495232 ps |
| CPU time | 559.43 seconds |
| Started | Aug 21 06:39:45 AM UTC 24 |
| Finished | Aug 21 06:49:12 AM UTC 24 |
| Peak memory | 212284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=872060354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.872060354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_loopback.3564539851 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 127128554 ps |
| CPU time | 1.1 seconds |
| Started | Aug 21 06:39:43 AM UTC 24 |
| Finished | Aug 21 06:39:45 AM UTC 24 |
| Peak memory | 206564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3564539851 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3564539851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_noise_filter.131430882 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 91582475444 ps |
| CPU time | 51.77 seconds |
| Started | Aug 21 06:39:30 AM UTC 24 |
| Finished | Aug 21 06:40:23 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=131430882 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.131430882 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_perf.1230176878 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 35885331662 ps |
| CPU time | 339.73 seconds |
| Started | Aug 21 06:39:43 AM UTC 24 |
| Finished | Aug 21 06:45:28 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230176878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1230176878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_rx_oversample.2119552338 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5442886577 ps |
| CPU time | 43.18 seconds |
| Started | Aug 21 06:39:26 AM UTC 24 |
| Finished | Aug 21 06:40:10 AM UTC 24 |
| Peak memory | 207236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119552338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2119552338 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.4159116421 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 133462644229 ps |
| CPU time | 350.62 seconds |
| Started | Aug 21 06:39:36 AM UTC 24 |
| Finished | Aug 21 06:45:31 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4159116421 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4159116421 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1360210554 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 31001527264 ps |
| CPU time | 22.72 seconds |
| Started | Aug 21 06:39:34 AM UTC 24 |
| Finished | Aug 21 06:39:58 AM UTC 24 |
| Peak memory | 207220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1360210554 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1360210554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_smoke.3578854211 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5806480319 ps |
| CPU time | 10.79 seconds |
| Started | Aug 21 06:39:16 AM UTC 24 |
| Finished | Aug 21 06:39:28 AM UTC 24 |
| Peak memory | 208296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578854211 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3578854211 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_stress_all.217626462 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 206456280526 ps |
| CPU time | 1100.22 seconds |
| Started | Aug 21 06:39:48 AM UTC 24 |
| Finished | Aug 21 06:58:21 AM UTC 24 |
| Peak memory | 212424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=217626462 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.217626462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.1482682229 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3185779219 ps |
| CPU time | 97.18 seconds |
| Started | Aug 21 06:39:46 AM UTC 24 |
| Finished | Aug 21 06:41:26 AM UTC 24 |
| Peak memory | 217812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1482682229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1482682229 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.943546325 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 2100292680 ps |
| CPU time | 2.63 seconds |
| Started | Aug 21 06:39:41 AM UTC 24 |
| Finished | Aug 21 06:39:45 AM UTC 24 |
| Peak memory | 207400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=943546325 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.943546325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/38.uart_tx_rx.289691004 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 158081176540 ps |
| CPU time | 63.4 seconds |
| Started | Aug 21 06:39:18 AM UTC 24 |
| Finished | Aug 21 06:40:23 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=289691004 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.289691004 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/38.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_alert_test.2845204544 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 11689323 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:40:43 AM UTC 24 |
| Finished | Aug 21 06:40:45 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2845204544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2845204544 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_fifo_full.3469341982 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 46027257396 ps |
| CPU time | 46.27 seconds |
| Started | Aug 21 06:39:55 AM UTC 24 |
| Finished | Aug 21 06:40:42 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3469341982 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3469341982 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.113639239 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 40964071429 ps |
| CPU time | 107.99 seconds |
| Started | Aug 21 06:39:59 AM UTC 24 |
| Finished | Aug 21 06:41:49 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113639239 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.113639239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_fifo_reset.1435655510 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 17015959759 ps |
| CPU time | 36 seconds |
| Started | Aug 21 06:40:00 AM UTC 24 |
| Finished | Aug 21 06:40:37 AM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1435655510 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1435655510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_intr.933756751 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 392037938221 ps |
| CPU time | 71.43 seconds |
| Started | Aug 21 06:40:11 AM UTC 24 |
| Finished | Aug 21 06:41:24 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=933756751 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.933756751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.3388894502 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 102661134608 ps |
| CPU time | 759.02 seconds |
| Started | Aug 21 06:40:29 AM UTC 24 |
| Finished | Aug 21 06:53:17 AM UTC 24 |
| Peak memory | 212400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3388894502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3388894502 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_loopback.2780249044 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4640013860 ps |
| CPU time | 17.92 seconds |
| Started | Aug 21 06:40:25 AM UTC 24 |
| Finished | Aug 21 06:40:45 AM UTC 24 |
| Peak memory | 207604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2780249044 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2780249044 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_noise_filter.1276640433 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 21985665109 ps |
| CPU time | 52.63 seconds |
| Started | Aug 21 06:40:20 AM UTC 24 |
| Finished | Aug 21 06:41:14 AM UTC 24 |
| Peak memory | 207436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1276640433 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1276640433 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_perf.3735311634 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 25789338229 ps |
| CPU time | 236.14 seconds |
| Started | Aug 21 06:40:25 AM UTC 24 |
| Finished | Aug 21 06:44:25 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3735311634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3735311634 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_rx_oversample.3625574458 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3066812593 ps |
| CPU time | 13.54 seconds |
| Started | Aug 21 06:40:10 AM UTC 24 |
| Finished | Aug 21 06:40:25 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3625574458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3625574458 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.1747516971 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 59563943106 ps |
| CPU time | 123.42 seconds |
| Started | Aug 21 06:40:24 AM UTC 24 |
| Finished | Aug 21 06:42:30 AM UTC 24 |
| Peak memory | 208632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1747516971 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1747516971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.3041963564 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 5892314677 ps |
| CPU time | 5.06 seconds |
| Started | Aug 21 06:40:23 AM UTC 24 |
| Finished | Aug 21 06:40:29 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3041963564 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3041963564 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_smoke.1170137846 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 646857525 ps |
| CPU time | 4.38 seconds |
| Started | Aug 21 06:39:54 AM UTC 24 |
| Finished | Aug 21 06:39:59 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170137846 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1170137846 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_stress_all.3838750698 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 357928414946 ps |
| CPU time | 194.5 seconds |
| Started | Aug 21 06:40:39 AM UTC 24 |
| Finished | Aug 21 06:43:56 AM UTC 24 |
| Peak memory | 217616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3838750698 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3838750698 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.149918183 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2836150450 ps |
| CPU time | 73.02 seconds |
| Started | Aug 21 06:40:31 AM UTC 24 |
| Finished | Aug 21 06:41:46 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=149918183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.149918183 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.726212154 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1755336690 ps |
| CPU time | 3.82 seconds |
| Started | Aug 21 06:40:24 AM UTC 24 |
| Finished | Aug 21 06:40:29 AM UTC 24 |
| Peak memory | 208008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=726212154 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.726212154 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/39.uart_tx_rx.1180916610 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 43724533036 ps |
| CPU time | 98.27 seconds |
| Started | Aug 21 06:39:54 AM UTC 24 |
| Finished | Aug 21 06:41:34 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1180916610 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1180916610 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/39.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_alert_test.3948157909 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 12533053 ps |
| CPU time | 0.78 seconds |
| Started | Aug 21 06:20:20 AM UTC 24 |
| Finished | Aug 21 06:20:21 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3948157909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3948157909 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_fifo_full.1854674002 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 69397010513 ps |
| CPU time | 24.67 seconds |
| Started | Aug 21 06:19:50 AM UTC 24 |
| Finished | Aug 21 06:20:16 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1854674002 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1854674002 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.308502277 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 30998582574 ps |
| CPU time | 76.6 seconds |
| Started | Aug 21 06:19:51 AM UTC 24 |
| Finished | Aug 21 06:21:09 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=308502277 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.308502277 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2329196010 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 70644327086 ps |
| CPU time | 40.71 seconds |
| Started | Aug 21 06:19:55 AM UTC 24 |
| Finished | Aug 21 06:20:37 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2329196010 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2329196010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_intr.3750760453 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12230105625 ps |
| CPU time | 17.23 seconds |
| Started | Aug 21 06:20:00 AM UTC 24 |
| Finished | Aug 21 06:20:19 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3750760453 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3750760453 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.289813157 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 127114998958 ps |
| CPU time | 301.67 seconds |
| Started | Aug 21 06:20:10 AM UTC 24 |
| Finished | Aug 21 06:25:16 AM UTC 24 |
| Peak memory | 208964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=289813157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.289813157 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_loopback.2163204524 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 7946426323 ps |
| CPU time | 21.75 seconds |
| Started | Aug 21 06:20:08 AM UTC 24 |
| Finished | Aug 21 06:20:31 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2163204524 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2163204524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_noise_filter.3178175953 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 26479184770 ps |
| CPU time | 18.45 seconds |
| Started | Aug 21 06:20:00 AM UTC 24 |
| Finished | Aug 21 06:20:20 AM UTC 24 |
| Peak memory | 208760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3178175953 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3178175953 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_perf.1871110733 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 25854243500 ps |
| CPU time | 137.04 seconds |
| Started | Aug 21 06:20:09 AM UTC 24 |
| Finished | Aug 21 06:22:29 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1871110733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1871110733 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_rx_oversample.212234027 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 7573577964 ps |
| CPU time | 34.72 seconds |
| Started | Aug 21 06:19:57 AM UTC 24 |
| Finished | Aug 21 06:20:33 AM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=212234027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.212234027 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.3224416757 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 38375380723 ps |
| CPU time | 104.69 seconds |
| Started | Aug 21 06:20:01 AM UTC 24 |
| Finished | Aug 21 06:21:48 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224416757 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3224416757 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.617369454 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5374739743 ps |
| CPU time | 18.99 seconds |
| Started | Aug 21 06:20:01 AM UTC 24 |
| Finished | Aug 21 06:20:22 AM UTC 24 |
| Peak memory | 207080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=617369454 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.617369454 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_sec_cm.2177371239 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 103189976 ps |
| CPU time | 1.11 seconds |
| Started | Aug 21 06:20:17 AM UTC 24 |
| Finished | Aug 21 06:20:19 AM UTC 24 |
| Peak memory | 240276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177371239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2177371239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_smoke.2654073480 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5473116329 ps |
| CPU time | 11.11 seconds |
| Started | Aug 21 06:19:44 AM UTC 24 |
| Finished | Aug 21 06:19:56 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2654073480 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2654073480 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.1069486237 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2320611760 ps |
| CPU time | 35.97 seconds |
| Started | Aug 21 06:20:10 AM UTC 24 |
| Finished | Aug 21 06:20:48 AM UTC 24 |
| Peak memory | 219708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1069486237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1069486237 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.137975041 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1019742799 ps |
| CPU time | 3.65 seconds |
| Started | Aug 21 06:20:04 AM UTC 24 |
| Finished | Aug 21 06:20:09 AM UTC 24 |
| Peak memory | 207492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=137975041 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.137975041 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/4.uart_tx_rx.179422988 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 53408191675 ps |
| CPU time | 63.74 seconds |
| Started | Aug 21 06:19:47 AM UTC 24 |
| Finished | Aug 21 06:20:52 AM UTC 24 |
| Peak memory | 208860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=179422988 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.179422988 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/4.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_alert_test.3464261889 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 24127392 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:41:24 AM UTC 24 |
| Finished | Aug 21 06:41:26 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3464261889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3464261889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_fifo_full.3466892059 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 111131439853 ps |
| CPU time | 137.27 seconds |
| Started | Aug 21 06:40:45 AM UTC 24 |
| Finished | Aug 21 06:43:05 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466892059 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3466892059 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.4167594326 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 92318000909 ps |
| CPU time | 24.35 seconds |
| Started | Aug 21 06:40:46 AM UTC 24 |
| Finished | Aug 21 06:41:12 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4167594326 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.4167594326 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_intr.2547708973 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5716114595 ps |
| CPU time | 11.34 seconds |
| Started | Aug 21 06:41:04 AM UTC 24 |
| Finished | Aug 21 06:41:17 AM UTC 24 |
| Peak memory | 207164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2547708973 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2547708973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3425566871 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 96070381473 ps |
| CPU time | 812.72 seconds |
| Started | Aug 21 06:41:18 AM UTC 24 |
| Finished | Aug 21 06:55:00 AM UTC 24 |
| Peak memory | 212344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3425566871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3425566871 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_loopback.93194206 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 8973184139 ps |
| CPU time | 10.05 seconds |
| Started | Aug 21 06:41:15 AM UTC 24 |
| Finished | Aug 21 06:41:26 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=93194206 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.93194206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_noise_filter.726933347 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 141099680080 ps |
| CPU time | 139.26 seconds |
| Started | Aug 21 06:41:04 AM UTC 24 |
| Finished | Aug 21 06:43:26 AM UTC 24 |
| Peak memory | 217600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=726933347 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.726933347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_perf.452591483 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 20712030836 ps |
| CPU time | 341.44 seconds |
| Started | Aug 21 06:41:16 AM UTC 24 |
| Finished | Aug 21 06:47:02 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=452591483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.452591483 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_rx_oversample.1292618091 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 5583880340 ps |
| CPU time | 54.42 seconds |
| Started | Aug 21 06:40:58 AM UTC 24 |
| Finished | Aug 21 06:41:54 AM UTC 24 |
| Peak memory | 207340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1292618091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1292618091 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.2130020534 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 69010687870 ps |
| CPU time | 85.93 seconds |
| Started | Aug 21 06:41:06 AM UTC 24 |
| Finished | Aug 21 06:42:33 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2130020534 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2130020534 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.3591297643 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 45683022440 ps |
| CPU time | 21.45 seconds |
| Started | Aug 21 06:41:04 AM UTC 24 |
| Finished | Aug 21 06:41:27 AM UTC 24 |
| Peak memory | 205032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3591297643 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3591297643 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_smoke.3041012682 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 6028437337 ps |
| CPU time | 18.93 seconds |
| Started | Aug 21 06:40:44 AM UTC 24 |
| Finished | Aug 21 06:41:04 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3041012682 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3041012682 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_stress_all.3623858033 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 105411773958 ps |
| CPU time | 108.39 seconds |
| Started | Aug 21 06:41:23 AM UTC 24 |
| Finished | Aug 21 06:43:14 AM UTC 24 |
| Peak memory | 208800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623858033 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3623858033 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1123813976 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 8481220290 ps |
| CPU time | 37.56 seconds |
| Started | Aug 21 06:41:20 AM UTC 24 |
| Finished | Aug 21 06:41:59 AM UTC 24 |
| Peak memory | 224692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1123813976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1123813976 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.1593663381 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 844515442 ps |
| CPU time | 5.48 seconds |
| Started | Aug 21 06:41:13 AM UTC 24 |
| Finished | Aug 21 06:41:19 AM UTC 24 |
| Peak memory | 207232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1593663381 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1593663381 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/40.uart_tx_rx.2484624569 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 232053178858 ps |
| CPU time | 187.06 seconds |
| Started | Aug 21 06:40:45 AM UTC 24 |
| Finished | Aug 21 06:43:55 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2484624569 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2484624569 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/40.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_alert_test.43150592 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 12834233 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:41:46 AM UTC 24 |
| Finished | Aug 21 06:41:48 AM UTC 24 |
| Peak memory | 204516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=43150592 -assert n opostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.43150592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_fifo_full.475914925 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 45242603379 ps |
| CPU time | 67.81 seconds |
| Started | Aug 21 06:41:25 AM UTC 24 |
| Finished | Aug 21 06:42:35 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=475914925 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.475914925 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.2767989111 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 19782108043 ps |
| CPU time | 17.39 seconds |
| Started | Aug 21 06:41:26 AM UTC 24 |
| Finished | Aug 21 06:41:45 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2767989111 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2767989111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_fifo_reset.2150912857 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 118205976611 ps |
| CPU time | 58.84 seconds |
| Started | Aug 21 06:41:27 AM UTC 24 |
| Finished | Aug 21 06:42:27 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2150912857 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2150912857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_intr.851063031 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 124530705169 ps |
| CPU time | 32.03 seconds |
| Started | Aug 21 06:41:28 AM UTC 24 |
| Finished | Aug 21 06:42:01 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=851063031 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.851063031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.3401403171 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 81990988565 ps |
| CPU time | 331.11 seconds |
| Started | Aug 21 06:41:46 AM UTC 24 |
| Finished | Aug 21 06:47:22 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401403171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3401403171 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_loopback.2149214406 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 3584031337 ps |
| CPU time | 12.11 seconds |
| Started | Aug 21 06:41:42 AM UTC 24 |
| Finished | Aug 21 06:41:55 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2149214406 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2149214406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_noise_filter.2604812018 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 217132146596 ps |
| CPU time | 166.01 seconds |
| Started | Aug 21 06:41:30 AM UTC 24 |
| Finished | Aug 21 06:44:18 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2604812018 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2604812018 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_perf.4170727795 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 19030099112 ps |
| CPU time | 270.62 seconds |
| Started | Aug 21 06:41:44 AM UTC 24 |
| Finished | Aug 21 06:46:19 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4170727795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4170727795 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_rx_oversample.1894760143 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4943348369 ps |
| CPU time | 13.58 seconds |
| Started | Aug 21 06:41:27 AM UTC 24 |
| Finished | Aug 21 06:41:41 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1894760143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1894760143 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3332356914 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 51327638167 ps |
| CPU time | 138.29 seconds |
| Started | Aug 21 06:41:37 AM UTC 24 |
| Finished | Aug 21 06:43:57 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3332356914 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3332356914 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.3139769793 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3850558863 ps |
| CPU time | 13.82 seconds |
| Started | Aug 21 06:41:35 AM UTC 24 |
| Finished | Aug 21 06:41:50 AM UTC 24 |
| Peak memory | 205236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3139769793 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3139769793 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_smoke.1223598328 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 911367930 ps |
| CPU time | 2.54 seconds |
| Started | Aug 21 06:41:25 AM UTC 24 |
| Finished | Aug 21 06:41:29 AM UTC 24 |
| Peak memory | 207188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1223598328 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1223598328 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_stress_all.2897489578 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 120910122950 ps |
| CPU time | 1180.69 seconds |
| Started | Aug 21 06:41:46 AM UTC 24 |
| Finished | Aug 21 07:01:41 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2897489578 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2897489578 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.3261083959 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 6502902237 ps |
| CPU time | 42.34 seconds |
| Started | Aug 21 06:41:46 AM UTC 24 |
| Finished | Aug 21 06:42:30 AM UTC 24 |
| Peak memory | 225116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3261083959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3261083959 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.407239806 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1909869190 ps |
| CPU time | 3.54 seconds |
| Started | Aug 21 06:41:41 AM UTC 24 |
| Finished | Aug 21 06:41:45 AM UTC 24 |
| Peak memory | 208332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=407239806 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.407239806 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/41.uart_tx_rx.2297641715 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 165295939854 ps |
| CPU time | 144.94 seconds |
| Started | Aug 21 06:41:25 AM UTC 24 |
| Finished | Aug 21 06:43:53 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2297641715 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2297641715 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/41.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_alert_test.5232777 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 11404677 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:42:07 AM UTC 24 |
| Finished | Aug 21 06:42:08 AM UTC 24 |
| Peak memory | 204524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=5232777 -assert no postproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.5232777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_fifo_full.3499526322 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 93798934322 ps |
| CPU time | 151.06 seconds |
| Started | Aug 21 06:41:49 AM UTC 24 |
| Finished | Aug 21 06:44:22 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3499526322 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3499526322 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.790977637 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 71130001967 ps |
| CPU time | 57.12 seconds |
| Started | Aug 21 06:41:50 AM UTC 24 |
| Finished | Aug 21 06:42:48 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=790977637 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.790977637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_fifo_reset.480113343 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 19047087180 ps |
| CPU time | 39.62 seconds |
| Started | Aug 21 06:41:51 AM UTC 24 |
| Finished | Aug 21 06:42:32 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=480113343 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.480113343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_intr.2542689926 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 28585190184 ps |
| CPU time | 8.26 seconds |
| Started | Aug 21 06:41:55 AM UTC 24 |
| Finished | Aug 21 06:42:04 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2542689926 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2542689926 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.3453794617 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 74700591424 ps |
| CPU time | 339.59 seconds |
| Started | Aug 21 06:42:02 AM UTC 24 |
| Finished | Aug 21 06:47:47 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3453794617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3453794617 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_loopback.3710663480 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5140768428 ps |
| CPU time | 4.75 seconds |
| Started | Aug 21 06:42:00 AM UTC 24 |
| Finished | Aug 21 06:42:06 AM UTC 24 |
| Peak memory | 207152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3710663480 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3710663480 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_noise_filter.1438786754 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 65293356520 ps |
| CPU time | 72.2 seconds |
| Started | Aug 21 06:41:55 AM UTC 24 |
| Finished | Aug 21 06:43:09 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1438786754 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1438786754 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_perf.2944165180 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 13043575438 ps |
| CPU time | 74.15 seconds |
| Started | Aug 21 06:42:01 AM UTC 24 |
| Finished | Aug 21 06:43:17 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2944165180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2944165180 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_rx_oversample.3188651516 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 6837511793 ps |
| CPU time | 6.12 seconds |
| Started | Aug 21 06:41:51 AM UTC 24 |
| Finished | Aug 21 06:41:58 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3188651516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3188651516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.1266353775 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 155435246967 ps |
| CPU time | 340.23 seconds |
| Started | Aug 21 06:41:58 AM UTC 24 |
| Finished | Aug 21 06:47:43 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1266353775 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1266353775 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.1309125505 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 2920346580 ps |
| CPU time | 4.08 seconds |
| Started | Aug 21 06:41:56 AM UTC 24 |
| Finished | Aug 21 06:42:01 AM UTC 24 |
| Peak memory | 207092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1309125505 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1309125505 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_smoke.1261168971 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 847023593 ps |
| CPU time | 5.38 seconds |
| Started | Aug 21 06:41:47 AM UTC 24 |
| Finished | Aug 21 06:41:54 AM UTC 24 |
| Peak memory | 207972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1261168971 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1261168971 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_stress_all.1285299210 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 549605582626 ps |
| CPU time | 650.68 seconds |
| Started | Aug 21 06:42:06 AM UTC 24 |
| Finished | Aug 21 06:53:03 AM UTC 24 |
| Peak memory | 224844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1285299210 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1285299210 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.2593603026 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 12062362253 ps |
| CPU time | 57.51 seconds |
| Started | Aug 21 06:42:04 AM UTC 24 |
| Finished | Aug 21 06:43:04 AM UTC 24 |
| Peak memory | 219752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2593603026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2593603026 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.138016437 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1638671094 ps |
| CPU time | 3.78 seconds |
| Started | Aug 21 06:41:59 AM UTC 24 |
| Finished | Aug 21 06:42:04 AM UTC 24 |
| Peak memory | 208868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=138016437 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.138016437 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/42.uart_tx_rx.3476429868 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 91302651142 ps |
| CPU time | 279.93 seconds |
| Started | Aug 21 06:41:49 AM UTC 24 |
| Finished | Aug 21 06:46:32 AM UTC 24 |
| Peak memory | 208640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3476429868 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3476429868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/42.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_alert_test.549042305 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 11018092 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 06:42:49 AM UTC 24 |
| Finished | Aug 21 06:42:51 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=549042305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.549042305 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_fifo_full.2149350615 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 125640722797 ps |
| CPU time | 95.04 seconds |
| Started | Aug 21 06:42:12 AM UTC 24 |
| Finished | Aug 21 06:43:49 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2149350615 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2149350615 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.134081122 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 264671606810 ps |
| CPU time | 75.93 seconds |
| Started | Aug 21 06:42:13 AM UTC 24 |
| Finished | Aug 21 06:43:31 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=134081122 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.134081122 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_fifo_reset.2918850594 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 43174364061 ps |
| CPU time | 22.01 seconds |
| Started | Aug 21 06:42:21 AM UTC 24 |
| Finished | Aug 21 06:42:44 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2918850594 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2918850594 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_intr.3315865270 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 48830979486 ps |
| CPU time | 116.2 seconds |
| Started | Aug 21 06:42:31 AM UTC 24 |
| Finished | Aug 21 06:44:30 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3315865270 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3315865270 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.168949140 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 50380516626 ps |
| CPU time | 100.41 seconds |
| Started | Aug 21 06:42:42 AM UTC 24 |
| Finished | Aug 21 06:44:24 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=168949140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.168949140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_loopback.4053330846 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 7820150458 ps |
| CPU time | 18.31 seconds |
| Started | Aug 21 06:42:36 AM UTC 24 |
| Finished | Aug 21 06:42:55 AM UTC 24 |
| Peak memory | 208500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4053330846 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4053330846 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_noise_filter.411130208 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 14559571319 ps |
| CPU time | 22.48 seconds |
| Started | Aug 21 06:42:31 AM UTC 24 |
| Finished | Aug 21 06:42:55 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=411130208 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.411130208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_perf.73412096 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 20365954245 ps |
| CPU time | 291.06 seconds |
| Started | Aug 21 06:42:36 AM UTC 24 |
| Finished | Aug 21 06:47:31 AM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=73412096 -assert nopostproc + UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat ch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.73412096 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_rx_oversample.3347774786 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3775335627 ps |
| CPU time | 5.1 seconds |
| Started | Aug 21 06:42:28 AM UTC 24 |
| Finished | Aug 21 06:42:34 AM UTC 24 |
| Peak memory | 207492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3347774786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3347774786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.3080202589 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 53547805362 ps |
| CPU time | 67.63 seconds |
| Started | Aug 21 06:42:32 AM UTC 24 |
| Finished | Aug 21 06:43:42 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3080202589 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3080202589 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.211367735 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3642221951 ps |
| CPU time | 8.2 seconds |
| Started | Aug 21 06:42:31 AM UTC 24 |
| Finished | Aug 21 06:42:41 AM UTC 24 |
| Peak memory | 205040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=211367735 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.211367735 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_smoke.2917014827 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 285709127 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 06:42:09 AM UTC 24 |
| Finished | Aug 21 06:42:12 AM UTC 24 |
| Peak memory | 207492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2917014827 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2917014827 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_stress_all.3756563404 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 94244426927 ps |
| CPU time | 554.56 seconds |
| Started | Aug 21 06:42:46 AM UTC 24 |
| Finished | Aug 21 06:52:07 AM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3756563404 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3756563404 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.1319153302 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 877165094 ps |
| CPU time | 6.54 seconds |
| Started | Aug 21 06:42:45 AM UTC 24 |
| Finished | Aug 21 06:42:53 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1319153302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1319153302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.1429810697 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7221087778 ps |
| CPU time | 20.38 seconds |
| Started | Aug 21 06:42:34 AM UTC 24 |
| Finished | Aug 21 06:42:56 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1429810697 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1429810697 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/43.uart_tx_rx.3394816853 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 42459889932 ps |
| CPU time | 73.88 seconds |
| Started | Aug 21 06:42:11 AM UTC 24 |
| Finished | Aug 21 06:43:26 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3394816853 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3394816853 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/43.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_alert_test.3767224624 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 38274455 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:43:22 AM UTC 24 |
| Finished | Aug 21 06:43:24 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767224624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3767224624 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_fifo_full.2525428778 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 43588022170 ps |
| CPU time | 32.28 seconds |
| Started | Aug 21 06:42:53 AM UTC 24 |
| Finished | Aug 21 06:43:27 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2525428778 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2525428778 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.3903294512 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 12864842486 ps |
| CPU time | 43.57 seconds |
| Started | Aug 21 06:42:56 AM UTC 24 |
| Finished | Aug 21 06:43:41 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3903294512 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3903294512 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_fifo_reset.3050319594 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 24332344735 ps |
| CPU time | 29.33 seconds |
| Started | Aug 21 06:42:56 AM UTC 24 |
| Finished | Aug 21 06:43:27 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3050319594 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3050319594 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_intr.2245912011 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 34530468817 ps |
| CPU time | 60.58 seconds |
| Started | Aug 21 06:42:57 AM UTC 24 |
| Finished | Aug 21 06:44:00 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2245912011 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2245912011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.519231194 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 225494575858 ps |
| CPU time | 488.38 seconds |
| Started | Aug 21 06:43:17 AM UTC 24 |
| Finished | Aug 21 06:51:32 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=519231194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.519231194 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_loopback.2363899717 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 6701289157 ps |
| CPU time | 7.05 seconds |
| Started | Aug 21 06:43:13 AM UTC 24 |
| Finished | Aug 21 06:43:21 AM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2363899717 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2363899717 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_noise_filter.2261509524 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 87775482924 ps |
| CPU time | 112.04 seconds |
| Started | Aug 21 06:42:58 AM UTC 24 |
| Finished | Aug 21 06:44:53 AM UTC 24 |
| Peak memory | 208880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2261509524 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2261509524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_perf.1984966454 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 9746955905 ps |
| CPU time | 325.51 seconds |
| Started | Aug 21 06:43:14 AM UTC 24 |
| Finished | Aug 21 06:48:44 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1984966454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1984966454 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_rx_oversample.2214471382 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 4236515190 ps |
| CPU time | 42.04 seconds |
| Started | Aug 21 06:42:56 AM UTC 24 |
| Finished | Aug 21 06:43:40 AM UTC 24 |
| Peak memory | 207300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2214471382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2214471382 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.124836317 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 28383784597 ps |
| CPU time | 55.02 seconds |
| Started | Aug 21 06:43:06 AM UTC 24 |
| Finished | Aug 21 06:44:02 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=124836317 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.124836317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.2501686656 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 1992992070 ps |
| CPU time | 6.72 seconds |
| Started | Aug 21 06:43:05 AM UTC 24 |
| Finished | Aug 21 06:43:12 AM UTC 24 |
| Peak memory | 205044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2501686656 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2501686656 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_smoke.2607615655 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 712773228 ps |
| CPU time | 4.83 seconds |
| Started | Aug 21 06:42:50 AM UTC 24 |
| Finished | Aug 21 06:42:56 AM UTC 24 |
| Peak memory | 208048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2607615655 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2607615655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_stress_all.987571936 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 208455883613 ps |
| CPU time | 1112.16 seconds |
| Started | Aug 21 06:43:18 AM UTC 24 |
| Finished | Aug 21 07:02:03 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=987571936 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.987571936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.923744521 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 686952534 ps |
| CPU time | 5.52 seconds |
| Started | Aug 21 06:43:18 AM UTC 24 |
| Finished | Aug 21 06:43:25 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923744521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.923744521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.4241485100 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 829400991 ps |
| CPU time | 4.9 seconds |
| Started | Aug 21 06:43:10 AM UTC 24 |
| Finished | Aug 21 06:43:16 AM UTC 24 |
| Peak memory | 208296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241485100 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4241485100 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/44.uart_tx_rx.3666239146 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 14154341349 ps |
| CPU time | 24.72 seconds |
| Started | Aug 21 06:42:51 AM UTC 24 |
| Finished | Aug 21 06:43:17 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3666239146 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3666239146 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/44.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_alert_test.344700609 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 42051046 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:43:46 AM UTC 24 |
| Finished | Aug 21 06:43:48 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344700609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.344700609 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_fifo_full.569848627 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 59597210439 ps |
| CPU time | 28.48 seconds |
| Started | Aug 21 06:43:27 AM UTC 24 |
| Finished | Aug 21 06:43:57 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=569848627 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.569848627 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.2360866759 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 304951721385 ps |
| CPU time | 105.81 seconds |
| Started | Aug 21 06:43:28 AM UTC 24 |
| Finished | Aug 21 06:45:15 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2360866759 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2360866759 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_fifo_reset.2676589664 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 24253371121 ps |
| CPU time | 57.62 seconds |
| Started | Aug 21 06:43:28 AM UTC 24 |
| Finished | Aug 21 06:44:27 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2676589664 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2676589664 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_intr.3404132606 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 171716934803 ps |
| CPU time | 417.26 seconds |
| Started | Aug 21 06:43:28 AM UTC 24 |
| Finished | Aug 21 06:50:30 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3404132606 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3404132606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.3338349419 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 73301908649 ps |
| CPU time | 397.17 seconds |
| Started | Aug 21 06:43:43 AM UTC 24 |
| Finished | Aug 21 06:50:26 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3338349419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3338349419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_loopback.1731149113 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 3023119114 ps |
| CPU time | 5.69 seconds |
| Started | Aug 21 06:43:42 AM UTC 24 |
| Finished | Aug 21 06:43:49 AM UTC 24 |
| Peak memory | 208028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1731149113 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1731149113 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_noise_filter.4253131764 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 107610497857 ps |
| CPU time | 18.81 seconds |
| Started | Aug 21 06:43:32 AM UTC 24 |
| Finished | Aug 21 06:43:52 AM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4253131764 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4253131764 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_perf.647091908 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 16650745646 ps |
| CPU time | 217.72 seconds |
| Started | Aug 21 06:43:43 AM UTC 24 |
| Finished | Aug 21 06:47:24 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=647091908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.647091908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_rx_oversample.3828457521 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3182559367 ps |
| CPU time | 14.84 seconds |
| Started | Aug 21 06:43:28 AM UTC 24 |
| Finished | Aug 21 06:43:44 AM UTC 24 |
| Peak memory | 208012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3828457521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3828457521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.904377481 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 192162949966 ps |
| CPU time | 151.26 seconds |
| Started | Aug 21 06:43:41 AM UTC 24 |
| Finished | Aug 21 06:46:15 AM UTC 24 |
| Peak memory | 208728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=904377481 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.904377481 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.3787144775 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 477003720 ps |
| CPU time | 2.79 seconds |
| Started | Aug 21 06:43:40 AM UTC 24 |
| Finished | Aug 21 06:43:44 AM UTC 24 |
| Peak memory | 205044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3787144775 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3787144775 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_smoke.3532845756 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 5559781980 ps |
| CPU time | 18.93 seconds |
| Started | Aug 21 06:43:25 AM UTC 24 |
| Finished | Aug 21 06:43:46 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3532845756 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3532845756 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_stress_all.4168630723 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 83224140099 ps |
| CPU time | 691.21 seconds |
| Started | Aug 21 06:43:44 AM UTC 24 |
| Finished | Aug 21 06:55:24 AM UTC 24 |
| Peak memory | 212356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168630723 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4168630723 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.188096173 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 22816181858 ps |
| CPU time | 29.94 seconds |
| Started | Aug 21 06:43:44 AM UTC 24 |
| Finished | Aug 21 06:44:16 AM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=188096173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.188096173 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.3267821947 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2479241034 ps |
| CPU time | 4.77 seconds |
| Started | Aug 21 06:43:42 AM UTC 24 |
| Finished | Aug 21 06:43:48 AM UTC 24 |
| Peak memory | 207344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3267821947 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3267821947 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/45.uart_tx_rx.4263754156 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 8875349919 ps |
| CPU time | 14.04 seconds |
| Started | Aug 21 06:43:25 AM UTC 24 |
| Finished | Aug 21 06:43:41 AM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4263754156 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.4263754156 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/45.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_alert_test.2381207943 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 25810435 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:44:03 AM UTC 24 |
| Finished | Aug 21 06:44:04 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2381207943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2381207943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_fifo_full.4085851871 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 45207781018 ps |
| CPU time | 33.93 seconds |
| Started | Aug 21 06:43:50 AM UTC 24 |
| Finished | Aug 21 06:44:25 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085851871 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4085851871 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.3969519733 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 47957217342 ps |
| CPU time | 21.81 seconds |
| Started | Aug 21 06:43:50 AM UTC 24 |
| Finished | Aug 21 06:44:13 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3969519733 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3969519733 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_fifo_reset.399112079 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 147401858293 ps |
| CPU time | 60.32 seconds |
| Started | Aug 21 06:43:53 AM UTC 24 |
| Finished | Aug 21 06:44:55 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=399112079 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.399112079 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_intr.695031994 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 20262446295 ps |
| CPU time | 16.5 seconds |
| Started | Aug 21 06:43:53 AM UTC 24 |
| Finished | Aug 21 06:44:11 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=695031994 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.695031994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.472925111 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 129145421549 ps |
| CPU time | 1009.16 seconds |
| Started | Aug 21 06:44:00 AM UTC 24 |
| Finished | Aug 21 07:01:01 AM UTC 24 |
| Peak memory | 212412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=472925111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.472925111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_loopback.3197210298 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 6741645009 ps |
| CPU time | 14.19 seconds |
| Started | Aug 21 06:43:58 AM UTC 24 |
| Finished | Aug 21 06:44:14 AM UTC 24 |
| Peak memory | 208664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3197210298 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3197210298 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_noise_filter.1208527740 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 281273298382 ps |
| CPU time | 156.73 seconds |
| Started | Aug 21 06:43:54 AM UTC 24 |
| Finished | Aug 21 06:46:33 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208527740 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1208527740 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_perf.4156673657 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 19889374447 ps |
| CPU time | 1029.34 seconds |
| Started | Aug 21 06:43:58 AM UTC 24 |
| Finished | Aug 21 07:01:19 AM UTC 24 |
| Peak memory | 212308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4156673657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4156673657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_rx_oversample.2259879425 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 4350711189 ps |
| CPU time | 40.35 seconds |
| Started | Aug 21 06:43:53 AM UTC 24 |
| Finished | Aug 21 06:44:35 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2259879425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2259879425 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.2233696127 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 37366427727 ps |
| CPU time | 27.02 seconds |
| Started | Aug 21 06:43:56 AM UTC 24 |
| Finished | Aug 21 06:44:24 AM UTC 24 |
| Peak memory | 208792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2233696127 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2233696127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.2037364671 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4460941744 ps |
| CPU time | 9.64 seconds |
| Started | Aug 21 06:43:54 AM UTC 24 |
| Finished | Aug 21 06:44:05 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2037364671 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2037364671 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_smoke.2232576655 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 451684500 ps |
| CPU time | 3.24 seconds |
| Started | Aug 21 06:43:49 AM UTC 24 |
| Finished | Aug 21 06:43:53 AM UTC 24 |
| Peak memory | 208320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2232576655 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2232576655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_stress_all.875584227 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 165162188979 ps |
| CPU time | 406.85 seconds |
| Started | Aug 21 06:44:02 AM UTC 24 |
| Finished | Aug 21 06:50:53 AM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=875584227 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.875584227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.2822001928 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 7279587643 ps |
| CPU time | 53.21 seconds |
| Started | Aug 21 06:44:01 AM UTC 24 |
| Finished | Aug 21 06:44:56 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2822001928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2822001928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.1487249197 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 540531239 ps |
| CPU time | 2.72 seconds |
| Started | Aug 21 06:43:57 AM UTC 24 |
| Finished | Aug 21 06:44:01 AM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1487249197 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1487249197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/46.uart_tx_rx.3722860245 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 257837003008 ps |
| CPU time | 50.19 seconds |
| Started | Aug 21 06:43:49 AM UTC 24 |
| Finished | Aug 21 06:44:40 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3722860245 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3722860245 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/46.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_alert_test.2542712742 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 42439988 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 06:44:29 AM UTC 24 |
| Finished | Aug 21 06:44:31 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2542712742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2542712742 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_fifo_full.1831980484 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 125773726514 ps |
| CPU time | 224.3 seconds |
| Started | Aug 21 06:44:11 AM UTC 24 |
| Finished | Aug 21 06:47:58 AM UTC 24 |
| Peak memory | 208800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1831980484 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1831980484 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.1334625125 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 135105991254 ps |
| CPU time | 50.05 seconds |
| Started | Aug 21 06:44:13 AM UTC 24 |
| Finished | Aug 21 06:45:04 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1334625125 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1334625125 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1395677011 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 32734481739 ps |
| CPU time | 29.07 seconds |
| Started | Aug 21 06:44:14 AM UTC 24 |
| Finished | Aug 21 06:44:44 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1395677011 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1395677011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_intr.2772986772 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 51843625172 ps |
| CPU time | 71.88 seconds |
| Started | Aug 21 06:44:16 AM UTC 24 |
| Finished | Aug 21 06:45:30 AM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2772986772 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2772986772 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.3686790238 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 154127600069 ps |
| CPU time | 1392.61 seconds |
| Started | Aug 21 06:44:26 AM UTC 24 |
| Finished | Aug 21 07:07:54 AM UTC 24 |
| Peak memory | 212212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3686790238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3686790238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_loopback.2791595924 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 7128786598 ps |
| CPU time | 19.55 seconds |
| Started | Aug 21 06:44:26 AM UTC 24 |
| Finished | Aug 21 06:44:46 AM UTC 24 |
| Peak memory | 207516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2791595924 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2791595924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_noise_filter.337131847 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 17705654638 ps |
| CPU time | 26.12 seconds |
| Started | Aug 21 06:44:19 AM UTC 24 |
| Finished | Aug 21 06:44:47 AM UTC 24 |
| Peak memory | 207288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=337131847 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.337131847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_perf.707596584 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 24290602966 ps |
| CPU time | 693.05 seconds |
| Started | Aug 21 06:44:26 AM UTC 24 |
| Finished | Aug 21 06:56:07 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=707596584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.707596584 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_rx_oversample.1011332014 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 5476739844 ps |
| CPU time | 13.09 seconds |
| Started | Aug 21 06:44:14 AM UTC 24 |
| Finished | Aug 21 06:44:28 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1011332014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1011332014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.2683293751 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 74040733543 ps |
| CPU time | 197.53 seconds |
| Started | Aug 21 06:44:22 AM UTC 24 |
| Finished | Aug 21 06:47:43 AM UTC 24 |
| Peak memory | 208628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2683293751 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2683293751 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.1842176647 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 6061967886 ps |
| CPU time | 4.87 seconds |
| Started | Aug 21 06:44:20 AM UTC 24 |
| Finished | Aug 21 06:44:26 AM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1842176647 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1842176647 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_smoke.1828424482 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 5811939343 ps |
| CPU time | 32.24 seconds |
| Started | Aug 21 06:44:06 AM UTC 24 |
| Finished | Aug 21 06:44:39 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1828424482 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1828424482 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.3862234134 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 5429943039 ps |
| CPU time | 96.94 seconds |
| Started | Aug 21 06:44:27 AM UTC 24 |
| Finished | Aug 21 06:46:06 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3862234134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3862234134 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.103562352 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 592377801 ps |
| CPU time | 3.27 seconds |
| Started | Aug 21 06:44:26 AM UTC 24 |
| Finished | Aug 21 06:44:30 AM UTC 24 |
| Peak memory | 207564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=103562352 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey _1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.103562352 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/47.uart_tx_rx.2780827659 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 42669580070 ps |
| CPU time | 112.15 seconds |
| Started | Aug 21 06:44:06 AM UTC 24 |
| Finished | Aug 21 06:46:00 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2780827659 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2780827659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/47.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_alert_test.2631725889 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 29475980 ps |
| CPU time | 0.83 seconds |
| Started | Aug 21 06:44:55 AM UTC 24 |
| Finished | Aug 21 06:44:57 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2631725889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2631725889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_fifo_full.260648233 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 139968067907 ps |
| CPU time | 153.59 seconds |
| Started | Aug 21 06:44:32 AM UTC 24 |
| Finished | Aug 21 06:47:08 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=260648233 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.260648233 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.765463168 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 44194541865 ps |
| CPU time | 82.04 seconds |
| Started | Aug 21 06:44:35 AM UTC 24 |
| Finished | Aug 21 06:45:59 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=765463168 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.765463168 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_fifo_reset.319471412 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 42740438983 ps |
| CPU time | 41.45 seconds |
| Started | Aug 21 06:44:35 AM UTC 24 |
| Finished | Aug 21 06:45:18 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=319471412 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.319471412 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_intr.3366955449 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 21799312712 ps |
| CPU time | 36.08 seconds |
| Started | Aug 21 06:44:41 AM UTC 24 |
| Finished | Aug 21 06:45:19 AM UTC 24 |
| Peak memory | 207356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3366955449 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3366955449 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.3559047541 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 325159246515 ps |
| CPU time | 333.25 seconds |
| Started | Aug 21 06:44:48 AM UTC 24 |
| Finished | Aug 21 06:50:26 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3559047541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3559047541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_loopback.1544211263 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 12314835375 ps |
| CPU time | 4.94 seconds |
| Started | Aug 21 06:44:47 AM UTC 24 |
| Finished | Aug 21 06:44:53 AM UTC 24 |
| Peak memory | 207468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1544211263 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1544211263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_noise_filter.3873368009 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 117811152225 ps |
| CPU time | 106.48 seconds |
| Started | Aug 21 06:44:41 AM UTC 24 |
| Finished | Aug 21 06:46:30 AM UTC 24 |
| Peak memory | 207636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3873368009 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3873368009 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_perf.981186176 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 7338253824 ps |
| CPU time | 467.94 seconds |
| Started | Aug 21 06:44:48 AM UTC 24 |
| Finished | Aug 21 06:52:42 AM UTC 24 |
| Peak memory | 208924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=981186176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.981186176 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_rx_oversample.3120840444 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 3973779485 ps |
| CPU time | 4.59 seconds |
| Started | Aug 21 06:44:40 AM UTC 24 |
| Finished | Aug 21 06:44:46 AM UTC 24 |
| Peak memory | 207324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3120840444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3120840444 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.1790493428 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 26230880745 ps |
| CPU time | 46.38 seconds |
| Started | Aug 21 06:44:46 AM UTC 24 |
| Finished | Aug 21 06:45:33 AM UTC 24 |
| Peak memory | 208556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1790493428 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1790493428 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.842403868 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 4678876078 ps |
| CPU time | 4.5 seconds |
| Started | Aug 21 06:44:42 AM UTC 24 |
| Finished | Aug 21 06:44:47 AM UTC 24 |
| Peak memory | 207156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=842403868 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.842403868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_smoke.3115333486 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 473056105 ps |
| CPU time | 3.53 seconds |
| Started | Aug 21 06:44:30 AM UTC 24 |
| Finished | Aug 21 06:44:35 AM UTC 24 |
| Peak memory | 208032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3115333486 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3115333486 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_stress_all.3167634241 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 475664729272 ps |
| CPU time | 1070.11 seconds |
| Started | Aug 21 06:44:54 AM UTC 24 |
| Finished | Aug 21 07:02:56 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3167634241 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3167634241 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.1035496062 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 4320427792 ps |
| CPU time | 62.61 seconds |
| Started | Aug 21 06:44:53 AM UTC 24 |
| Finished | Aug 21 06:45:57 AM UTC 24 |
| Peak memory | 220028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1035496062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1035496062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.3629138192 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 8152396820 ps |
| CPU time | 14.21 seconds |
| Started | Aug 21 06:44:47 AM UTC 24 |
| Finished | Aug 21 06:45:02 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3629138192 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3629138192 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/48.uart_tx_rx.817929426 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 118163982118 ps |
| CPU time | 56.53 seconds |
| Started | Aug 21 06:44:31 AM UTC 24 |
| Finished | Aug 21 06:45:29 AM UTC 24 |
| Peak memory | 208928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=817929426 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.817929426 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/48.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_alert_test.2943723586 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 40427980 ps |
| CPU time | 0.82 seconds |
| Started | Aug 21 06:45:33 AM UTC 24 |
| Finished | Aug 21 06:45:35 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2943723586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2943723586 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_fifo_full.3850882637 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 51520278266 ps |
| CPU time | 13.83 seconds |
| Started | Aug 21 06:45:02 AM UTC 24 |
| Finished | Aug 21 06:45:17 AM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3850882637 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3850882637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.3547890618 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 21776980273 ps |
| CPU time | 22.12 seconds |
| Started | Aug 21 06:45:03 AM UTC 24 |
| Finished | Aug 21 06:45:27 AM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3547890618 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3547890618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_fifo_reset.1473051722 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 151665214074 ps |
| CPU time | 79.37 seconds |
| Started | Aug 21 06:45:04 AM UTC 24 |
| Finished | Aug 21 06:46:26 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1473051722 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1473051722 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_intr.1832233674 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 50244445995 ps |
| CPU time | 107.97 seconds |
| Started | Aug 21 06:45:17 AM UTC 24 |
| Finished | Aug 21 06:47:07 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1832233674 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1832233674 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.1200523371 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 140858843375 ps |
| CPU time | 183.07 seconds |
| Started | Aug 21 06:45:31 AM UTC 24 |
| Finished | Aug 21 06:48:37 AM UTC 24 |
| Peak memory | 208692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1200523371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1200523371 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_loopback.2425673128 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 245760968 ps |
| CPU time | 1.45 seconds |
| Started | Aug 21 06:45:28 AM UTC 24 |
| Finished | Aug 21 06:45:31 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2425673128 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2425673128 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_noise_filter.4084531236 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 34833201638 ps |
| CPU time | 67.78 seconds |
| Started | Aug 21 06:45:18 AM UTC 24 |
| Finished | Aug 21 06:46:27 AM UTC 24 |
| Peak memory | 209120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4084531236 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.4084531236 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_perf.2671164323 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 22692638306 ps |
| CPU time | 1248.33 seconds |
| Started | Aug 21 06:45:30 AM UTC 24 |
| Finished | Aug 21 07:06:33 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2671164323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2671164323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_rx_oversample.3737491840 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 5689024233 ps |
| CPU time | 44.65 seconds |
| Started | Aug 21 06:45:06 AM UTC 24 |
| Finished | Aug 21 06:45:52 AM UTC 24 |
| Peak memory | 207240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3737491840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3737491840 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.41035920 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 37088877354 ps |
| CPU time | 13.43 seconds |
| Started | Aug 21 06:45:20 AM UTC 24 |
| Finished | Aug 21 06:45:35 AM UTC 24 |
| Peak memory | 207888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41035920 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.41035920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.1037353056 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 39777316346 ps |
| CPU time | 54.16 seconds |
| Started | Aug 21 06:45:19 AM UTC 24 |
| Finished | Aug 21 06:46:15 AM UTC 24 |
| Peak memory | 205108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1037353056 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1037353056 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_smoke.919324472 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 510135792 ps |
| CPU time | 3.49 seconds |
| Started | Aug 21 06:44:57 AM UTC 24 |
| Finished | Aug 21 06:45:02 AM UTC 24 |
| Peak memory | 207428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=919324472 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.919324472 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_stress_all.2379023707 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 139961279484 ps |
| CPU time | 454.4 seconds |
| Started | Aug 21 06:45:32 AM UTC 24 |
| Finished | Aug 21 06:53:12 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2379023707 -ass ert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2379023707 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.3998590938 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 16502511176 ps |
| CPU time | 79.12 seconds |
| Started | Aug 21 06:45:31 AM UTC 24 |
| Finished | Aug 21 06:46:53 AM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3998590938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3998590938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.3099489809 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 582045901 ps |
| CPU time | 3.5 seconds |
| Started | Aug 21 06:45:28 AM UTC 24 |
| Finished | Aug 21 06:45:33 AM UTC 24 |
| Peak memory | 207544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3099489809 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3099489809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/49.uart_tx_rx.3096504968 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 70942766950 ps |
| CPU time | 95.91 seconds |
| Started | Aug 21 06:44:57 AM UTC 24 |
| Finished | Aug 21 06:46:35 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3096504968 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3096504968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/49.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_alert_test.2077496458 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 43719902 ps |
| CPU time | 0.78 seconds |
| Started | Aug 21 06:20:43 AM UTC 24 |
| Finished | Aug 21 06:20:44 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2077496458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2077496458 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_fifo_full.2211169491 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 288308573731 ps |
| CPU time | 48.73 seconds |
| Started | Aug 21 06:20:22 AM UTC 24 |
| Finished | Aug 21 06:21:12 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2211169491 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2211169491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.774322669 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 215262655505 ps |
| CPU time | 57.65 seconds |
| Started | Aug 21 06:20:23 AM UTC 24 |
| Finished | Aug 21 06:21:22 AM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774322669 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.774322669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_fifo_reset.2101213803 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 9938088736 ps |
| CPU time | 17.34 seconds |
| Started | Aug 21 06:20:23 AM UTC 24 |
| Finished | Aug 21 06:20:41 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2101213803 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2101213803 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_intr.2789274131 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 147099687839 ps |
| CPU time | 264.25 seconds |
| Started | Aug 21 06:20:25 AM UTC 24 |
| Finished | Aug 21 06:24:53 AM UTC 24 |
| Peak memory | 207148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2789274131 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2789274131 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.3797616576 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 147722353032 ps |
| CPU time | 1228.63 seconds |
| Started | Aug 21 06:20:40 AM UTC 24 |
| Finished | Aug 21 06:41:22 AM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3797616576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3797616576 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_loopback.2768009969 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1769222532 ps |
| CPU time | 3.6 seconds |
| Started | Aug 21 06:20:36 AM UTC 24 |
| Finished | Aug 21 06:20:41 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2768009969 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2768009969 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_noise_filter.211469383 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 49470960335 ps |
| CPU time | 165.28 seconds |
| Started | Aug 21 06:20:27 AM UTC 24 |
| Finished | Aug 21 06:23:15 AM UTC 24 |
| Peak memory | 207496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=211469383 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.211469383 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2900473908 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 5474858473 ps |
| CPU time | 9.06 seconds |
| Started | Aug 21 06:20:25 AM UTC 24 |
| Finished | Aug 21 06:20:35 AM UTC 24 |
| Peak memory | 207236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2900473908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2900473908 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.3693912988 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 25075531475 ps |
| CPU time | 67.79 seconds |
| Started | Aug 21 06:20:33 AM UTC 24 |
| Finished | Aug 21 06:21:43 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693912988 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3693912988 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.2654776533 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 52301443277 ps |
| CPU time | 33.21 seconds |
| Started | Aug 21 06:20:32 AM UTC 24 |
| Finished | Aug 21 06:21:07 AM UTC 24 |
| Peak memory | 205036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2654776533 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2654776533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_smoke.1265277103 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 5786367069 ps |
| CPU time | 5.31 seconds |
| Started | Aug 21 06:20:20 AM UTC 24 |
| Finished | Aug 21 06:20:26 AM UTC 24 |
| Peak memory | 208572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1265277103 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1265277103 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.4018198206 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3649104018 ps |
| CPU time | 93.77 seconds |
| Started | Aug 21 06:20:42 AM UTC 24 |
| Finished | Aug 21 06:22:17 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4018198206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.4018198206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.4192353800 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 706154017 ps |
| CPU time | 3.51 seconds |
| Started | Aug 21 06:20:34 AM UTC 24 |
| Finished | Aug 21 06:20:39 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4192353800 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.4192353800 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/5.uart_tx_rx.2740008232 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 8456076353 ps |
| CPU time | 30.49 seconds |
| Started | Aug 21 06:20:21 AM UTC 24 |
| Finished | Aug 21 06:20:53 AM UTC 24 |
| Peak memory | 207084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2740008232 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2740008232 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/5.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/50.uart_fifo_reset.3376486611 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 12257486939 ps |
| CPU time | 44.08 seconds |
| Started | Aug 21 06:45:35 AM UTC 24 |
| Finished | Aug 21 06:46:20 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3376486611 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3376486611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/50.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.3119538518 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 12727989660 ps |
| CPU time | 79.35 seconds |
| Started | Aug 21 06:45:36 AM UTC 24 |
| Finished | Aug 21 06:46:57 AM UTC 24 |
| Peak memory | 219840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3119538518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3119538518 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/51.uart_fifo_reset.1224694891 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 17109522474 ps |
| CPU time | 40.11 seconds |
| Started | Aug 21 06:45:36 AM UTC 24 |
| Finished | Aug 21 06:46:17 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1224694891 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1224694891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/51.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.688153673 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 3049063310 ps |
| CPU time | 40.34 seconds |
| Started | Aug 21 06:45:37 AM UTC 24 |
| Finished | Aug 21 06:46:18 AM UTC 24 |
| Peak memory | 217724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=688153673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.688153673 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/52.uart_fifo_reset.2548456228 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 51520431792 ps |
| CPU time | 72.13 seconds |
| Started | Aug 21 06:45:53 AM UTC 24 |
| Finished | Aug 21 06:47:07 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2548456228 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2548456228 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/52.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.218428933 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 10460445633 ps |
| CPU time | 17.86 seconds |
| Started | Aug 21 06:45:58 AM UTC 24 |
| Finished | Aug 21 06:46:17 AM UTC 24 |
| Peak memory | 223868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=218428933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.218428933 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2056951305 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 27020926614 ps |
| CPU time | 53.57 seconds |
| Started | Aug 21 06:46:00 AM UTC 24 |
| Finished | Aug 21 06:46:55 AM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056951305 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2056951305 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/53.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.291753814 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 5422868781 ps |
| CPU time | 65.11 seconds |
| Started | Aug 21 06:46:01 AM UTC 24 |
| Finished | Aug 21 06:47:08 AM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=291753814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.291753814 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/54.uart_fifo_reset.578598891 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 58568071053 ps |
| CPU time | 40.96 seconds |
| Started | Aug 21 06:46:06 AM UTC 24 |
| Finished | Aug 21 06:46:49 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=578598891 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.578598891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/54.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.152655235 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 867325605 ps |
| CPU time | 36.84 seconds |
| Started | Aug 21 06:46:06 AM UTC 24 |
| Finished | Aug 21 06:46:45 AM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=152655235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.152655235 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/55.uart_fifo_reset.806945356 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 84282605600 ps |
| CPU time | 48.09 seconds |
| Started | Aug 21 06:46:15 AM UTC 24 |
| Finished | Aug 21 06:47:05 AM UTC 24 |
| Peak memory | 208928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806945356 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.806945356 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/55.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.1469087353 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 7468830119 ps |
| CPU time | 33.82 seconds |
| Started | Aug 21 06:46:15 AM UTC 24 |
| Finished | Aug 21 06:46:51 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1469087353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1469087353 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/56.uart_fifo_reset.1828073901 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 95423545571 ps |
| CPU time | 263.48 seconds |
| Started | Aug 21 06:46:17 AM UTC 24 |
| Finished | Aug 21 06:50:45 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1828073901 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1828073901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/56.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.4139474485 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2564976136 ps |
| CPU time | 39.95 seconds |
| Started | Aug 21 06:46:19 AM UTC 24 |
| Finished | Aug 21 06:47:00 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4139474485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4139474485 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/57.uart_fifo_reset.3017721470 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 157450625116 ps |
| CPU time | 47.47 seconds |
| Started | Aug 21 06:46:20 AM UTC 24 |
| Finished | Aug 21 06:47:09 AM UTC 24 |
| Peak memory | 208668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3017721470 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3017721470 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/57.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.3761356611 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 17404802946 ps |
| CPU time | 25.71 seconds |
| Started | Aug 21 06:46:20 AM UTC 24 |
| Finished | Aug 21 06:46:47 AM UTC 24 |
| Peak memory | 220032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3761356611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3761356611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/58.uart_fifo_reset.2437336406 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 33508523863 ps |
| CPU time | 25.45 seconds |
| Started | Aug 21 06:46:21 AM UTC 24 |
| Finished | Aug 21 06:46:48 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2437336406 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2437336406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/58.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.2878871148 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 6067286781 ps |
| CPU time | 32.89 seconds |
| Started | Aug 21 06:46:27 AM UTC 24 |
| Finished | Aug 21 06:47:01 AM UTC 24 |
| Peak memory | 223912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2878871148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2878871148 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/59.uart_fifo_reset.594163043 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 26851417378 ps |
| CPU time | 29.36 seconds |
| Started | Aug 21 06:46:28 AM UTC 24 |
| Finished | Aug 21 06:46:59 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=594163043 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.594163043 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/59.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.1488912807 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 3529269061 ps |
| CPU time | 40.99 seconds |
| Started | Aug 21 06:46:28 AM UTC 24 |
| Finished | Aug 21 06:47:10 AM UTC 24 |
| Peak memory | 224268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1488912807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1488912807 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_alert_test.1195096516 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 42856573 ps |
| CPU time | 0.81 seconds |
| Started | Aug 21 06:21:23 AM UTC 24 |
| Finished | Aug 21 06:21:25 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1195096516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1195096516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_fifo_full.2271049661 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 20281729467 ps |
| CPU time | 19.12 seconds |
| Started | Aug 21 06:20:47 AM UTC 24 |
| Finished | Aug 21 06:21:07 AM UTC 24 |
| Peak memory | 208900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2271049661 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2271049661 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.806904446 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 40147899626 ps |
| CPU time | 49.25 seconds |
| Started | Aug 21 06:20:49 AM UTC 24 |
| Finished | Aug 21 06:21:40 AM UTC 24 |
| Peak memory | 208396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806904446 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.806904446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_fifo_reset.3349360025 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 64702264156 ps |
| CPU time | 114.77 seconds |
| Started | Aug 21 06:20:53 AM UTC 24 |
| Finished | Aug 21 06:22:50 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3349360025 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3349360025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_intr.2618500533 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 34443770848 ps |
| CPU time | 28.47 seconds |
| Started | Aug 21 06:20:53 AM UTC 24 |
| Finished | Aug 21 06:21:23 AM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2618500533 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2618500533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.2701920321 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 60944402075 ps |
| CPU time | 571.78 seconds |
| Started | Aug 21 06:21:13 AM UTC 24 |
| Finished | Aug 21 06:30:51 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2701920321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2701920321 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_loopback.3871317611 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 9975573879 ps |
| CPU time | 26.63 seconds |
| Started | Aug 21 06:21:12 AM UTC 24 |
| Finished | Aug 21 06:21:40 AM UTC 24 |
| Peak memory | 208876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3871317611 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3871317611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_noise_filter.731648040 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 44301459393 ps |
| CPU time | 43.2 seconds |
| Started | Aug 21 06:21:07 AM UTC 24 |
| Finished | Aug 21 06:21:52 AM UTC 24 |
| Peak memory | 207400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=731648040 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear lgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.731648040 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_perf.1584308152 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 9747519509 ps |
| CPU time | 103.32 seconds |
| Started | Aug 21 06:21:13 AM UTC 24 |
| Finished | Aug 21 06:22:58 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1584308152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1584308152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_rx_oversample.417184823 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2892867786 ps |
| CPU time | 29.4 seconds |
| Started | Aug 21 06:20:53 AM UTC 24 |
| Finished | Aug 21 06:21:24 AM UTC 24 |
| Peak memory | 207296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=417184823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.417184823 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.806483714 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 29051491300 ps |
| CPU time | 66.53 seconds |
| Started | Aug 21 06:21:08 AM UTC 24 |
| Finished | Aug 21 06:22:16 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806483714 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.806483714 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.2439685650 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 522724034 ps |
| CPU time | 2.52 seconds |
| Started | Aug 21 06:21:08 AM UTC 24 |
| Finished | Aug 21 06:21:12 AM UTC 24 |
| Peak memory | 205048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439685650 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2439685650 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_smoke.702037513 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5892184569 ps |
| CPU time | 43.43 seconds |
| Started | Aug 21 06:20:45 AM UTC 24 |
| Finished | Aug 21 06:21:30 AM UTC 24 |
| Peak memory | 208664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=702037513 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.702037513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.2281732887 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 23438576860 ps |
| CPU time | 59.94 seconds |
| Started | Aug 21 06:21:14 AM UTC 24 |
| Finished | Aug 21 06:22:15 AM UTC 24 |
| Peak memory | 217796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2281732887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2281732887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.2099837577 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 453573390 ps |
| CPU time | 2.84 seconds |
| Started | Aug 21 06:21:09 AM UTC 24 |
| Finished | Aug 21 06:21:13 AM UTC 24 |
| Peak memory | 207268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2099837577 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2099837577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/6.uart_tx_rx.3163913686 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 83521873183 ps |
| CPU time | 184.89 seconds |
| Started | Aug 21 06:20:46 AM UTC 24 |
| Finished | Aug 21 06:23:54 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3163913686 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3163913686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/6.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/60.uart_fifo_reset.1625544603 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 106253081633 ps |
| CPU time | 148.09 seconds |
| Started | Aug 21 06:46:31 AM UTC 24 |
| Finished | Aug 21 06:49:01 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1625544603 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1625544603 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/60.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.2430577311 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 7055719043 ps |
| CPU time | 97.53 seconds |
| Started | Aug 21 06:46:33 AM UTC 24 |
| Finished | Aug 21 06:48:13 AM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2430577311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2430577311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/61.uart_fifo_reset.3326424419 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 114299713952 ps |
| CPU time | 119.96 seconds |
| Started | Aug 21 06:46:34 AM UTC 24 |
| Finished | Aug 21 06:48:37 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3326424419 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3326424419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/61.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.1789649165 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 3151163928 ps |
| CPU time | 13.38 seconds |
| Started | Aug 21 06:46:36 AM UTC 24 |
| Finished | Aug 21 06:46:51 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1789649165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1789649165 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/62.uart_fifo_reset.3989984897 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 66762156402 ps |
| CPU time | 45.6 seconds |
| Started | Aug 21 06:46:45 AM UTC 24 |
| Finished | Aug 21 06:47:33 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3989984897 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3989984897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/62.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.2854848274 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 39120025743 ps |
| CPU time | 58.2 seconds |
| Started | Aug 21 06:46:48 AM UTC 24 |
| Finished | Aug 21 06:47:47 AM UTC 24 |
| Peak memory | 219852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854848274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2854848274 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/63.uart_fifo_reset.2303984957 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 82994819188 ps |
| CPU time | 123.12 seconds |
| Started | Aug 21 06:46:49 AM UTC 24 |
| Finished | Aug 21 06:48:54 AM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2303984957 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2303984957 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/63.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.475682420 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 68531617745 ps |
| CPU time | 72.21 seconds |
| Started | Aug 21 06:46:50 AM UTC 24 |
| Finished | Aug 21 06:48:04 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=475682420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.475682420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/64.uart_fifo_reset.358215851 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 82230920643 ps |
| CPU time | 109.85 seconds |
| Started | Aug 21 06:46:52 AM UTC 24 |
| Finished | Aug 21 06:48:44 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358215851 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.358215851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/64.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.4008726909 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 18361181577 ps |
| CPU time | 44.58 seconds |
| Started | Aug 21 06:46:52 AM UTC 24 |
| Finished | Aug 21 06:47:38 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4008726909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4008726909 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/65.uart_fifo_reset.4001623132 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 11969431734 ps |
| CPU time | 26.71 seconds |
| Started | Aug 21 06:46:53 AM UTC 24 |
| Finished | Aug 21 06:47:21 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4001623132 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4001623132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/65.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.2986877927 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2558399060 ps |
| CPU time | 19.37 seconds |
| Started | Aug 21 06:46:56 AM UTC 24 |
| Finished | Aug 21 06:47:17 AM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2986877927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2986877927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/66.uart_fifo_reset.121817786 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 119886849669 ps |
| CPU time | 212.16 seconds |
| Started | Aug 21 06:46:57 AM UTC 24 |
| Finished | Aug 21 06:50:32 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121817786 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.121817786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/66.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.525255568 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 18543505933 ps |
| CPU time | 52.12 seconds |
| Started | Aug 21 06:46:58 AM UTC 24 |
| Finished | Aug 21 06:47:52 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=525255568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.525255568 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/67.uart_fifo_reset.358028216 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 95947474848 ps |
| CPU time | 199.26 seconds |
| Started | Aug 21 06:46:59 AM UTC 24 |
| Finished | Aug 21 06:50:21 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358028216 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.358028216 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/67.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.3027052196 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 5940276712 ps |
| CPU time | 73.51 seconds |
| Started | Aug 21 06:47:00 AM UTC 24 |
| Finished | Aug 21 06:48:16 AM UTC 24 |
| Peak memory | 219860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3027052196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3027052196 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/68.uart_fifo_reset.3938271738 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 62828716496 ps |
| CPU time | 75.83 seconds |
| Started | Aug 21 06:47:02 AM UTC 24 |
| Finished | Aug 21 06:48:20 AM UTC 24 |
| Peak memory | 208736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3938271738 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3938271738 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/68.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.1148564783 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 7275054289 ps |
| CPU time | 47.56 seconds |
| Started | Aug 21 06:47:03 AM UTC 24 |
| Finished | Aug 21 06:47:52 AM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1148564783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1148564783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/69.uart_fifo_reset.1230329164 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 50852598202 ps |
| CPU time | 86.24 seconds |
| Started | Aug 21 06:47:06 AM UTC 24 |
| Finished | Aug 21 06:48:34 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230329164 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1230329164 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/69.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.2630790667 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5543308271 ps |
| CPU time | 31.89 seconds |
| Started | Aug 21 06:47:08 AM UTC 24 |
| Finished | Aug 21 06:47:41 AM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2630790667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2630790667 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_alert_test.788038652 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 24376240 ps |
| CPU time | 0.8 seconds |
| Started | Aug 21 06:21:53 AM UTC 24 |
| Finished | Aug 21 06:21:55 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=788038652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.788038652 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_fifo_full.1833268721 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 134986985212 ps |
| CPU time | 105.2 seconds |
| Started | Aug 21 06:21:26 AM UTC 24 |
| Finished | Aug 21 06:23:13 AM UTC 24 |
| Peak memory | 208796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1833268721 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1833268721 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1283289269 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 54409323340 ps |
| CPU time | 93.53 seconds |
| Started | Aug 21 06:21:29 AM UTC 24 |
| Finished | Aug 21 06:23:05 AM UTC 24 |
| Peak memory | 208696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1283289269 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1283289269 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.3554730901 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 95132510945 ps |
| CPU time | 808.9 seconds |
| Started | Aug 21 06:21:49 AM UTC 24 |
| Finished | Aug 21 06:35:27 AM UTC 24 |
| Peak memory | 212208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3554730901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3554730901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_loopback.4227905670 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 7981278806 ps |
| CPU time | 8.64 seconds |
| Started | Aug 21 06:21:45 AM UTC 24 |
| Finished | Aug 21 06:21:55 AM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4227905670 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.4227905670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_noise_filter.3441419933 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 392630014669 ps |
| CPU time | 67.51 seconds |
| Started | Aug 21 06:21:41 AM UTC 24 |
| Finished | Aug 21 06:22:50 AM UTC 24 |
| Peak memory | 217772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3441419933 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3441419933 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_perf.2826672212 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 17576372828 ps |
| CPU time | 224.21 seconds |
| Started | Aug 21 06:21:46 AM UTC 24 |
| Finished | Aug 21 06:25:33 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2826672212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2826672212 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_rx_oversample.4187740529 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1826436965 ps |
| CPU time | 3.92 seconds |
| Started | Aug 21 06:21:35 AM UTC 24 |
| Finished | Aug 21 06:21:41 AM UTC 24 |
| Peak memory | 207364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4187740529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.4187740529 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.3818925713 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 77027130373 ps |
| CPU time | 72.7 seconds |
| Started | Aug 21 06:21:43 AM UTC 24 |
| Finished | Aug 21 06:22:57 AM UTC 24 |
| Peak memory | 208840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3818925713 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3818925713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.218128341 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4703546076 ps |
| CPU time | 8.91 seconds |
| Started | Aug 21 06:21:42 AM UTC 24 |
| Finished | Aug 21 06:21:52 AM UTC 24 |
| Peak memory | 205300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=218128341 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra tch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.218128341 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_smoke.44325879 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 5439505944 ps |
| CPU time | 18.13 seconds |
| Started | Aug 21 06:21:24 AM UTC 24 |
| Finished | Aug 21 06:21:44 AM UTC 24 |
| Peak memory | 208980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=44325879 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_ 0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.44325879 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.4169586593 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 7098739913 ps |
| CPU time | 35.91 seconds |
| Started | Aug 21 06:21:44 AM UTC 24 |
| Finished | Aug 21 06:22:21 AM UTC 24 |
| Peak memory | 208588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4169586593 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4169586593 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/7.uart_tx_rx.3252272939 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 37022742677 ps |
| CPU time | 54.12 seconds |
| Started | Aug 21 06:21:25 AM UTC 24 |
| Finished | Aug 21 06:22:21 AM UTC 24 |
| Peak memory | 208656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3252272939 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3252272939 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/7.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/70.uart_fifo_reset.2142591590 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 44570620923 ps |
| CPU time | 100.85 seconds |
| Started | Aug 21 06:47:08 AM UTC 24 |
| Finished | Aug 21 06:48:51 AM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2142591590 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2142591590 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/70.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.2221794081 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 6155083621 ps |
| CPU time | 27.85 seconds |
| Started | Aug 21 06:47:09 AM UTC 24 |
| Finished | Aug 21 06:47:38 AM UTC 24 |
| Peak memory | 219564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2221794081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2221794081 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/71.uart_fifo_reset.1219452010 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 241020999929 ps |
| CPU time | 42.9 seconds |
| Started | Aug 21 06:47:09 AM UTC 24 |
| Finished | Aug 21 06:47:53 AM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1219452010 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1219452010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/71.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.3224717786 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1956353291 ps |
| CPU time | 31.9 seconds |
| Started | Aug 21 06:47:09 AM UTC 24 |
| Finished | Aug 21 06:47:42 AM UTC 24 |
| Peak memory | 217940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224717786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3224717786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/72.uart_fifo_reset.2100973383 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 110524900175 ps |
| CPU time | 219.54 seconds |
| Started | Aug 21 06:47:10 AM UTC 24 |
| Finished | Aug 21 06:50:53 AM UTC 24 |
| Peak memory | 208804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100973383 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2100973383 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/72.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.1242948206 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2223928698 ps |
| CPU time | 27.9 seconds |
| Started | Aug 21 06:47:11 AM UTC 24 |
| Finished | Aug 21 06:47:40 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1242948206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1242948206 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/73.uart_fifo_reset.1539500376 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 114280390627 ps |
| CPU time | 48.66 seconds |
| Started | Aug 21 06:47:17 AM UTC 24 |
| Finished | Aug 21 06:48:07 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1539500376 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1539500376 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/73.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.3830337169 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 4129377356 ps |
| CPU time | 24.04 seconds |
| Started | Aug 21 06:47:21 AM UTC 24 |
| Finished | Aug 21 06:47:47 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830337169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3830337169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/74.uart_fifo_reset.407268225 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 48704671540 ps |
| CPU time | 31.01 seconds |
| Started | Aug 21 06:47:22 AM UTC 24 |
| Finished | Aug 21 06:47:55 AM UTC 24 |
| Peak memory | 208956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=407268225 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.407268225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/74.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.2483861547 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3805874648 ps |
| CPU time | 31.12 seconds |
| Started | Aug 21 06:47:22 AM UTC 24 |
| Finished | Aug 21 06:47:55 AM UTC 24 |
| Peak memory | 217636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2483861547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2483861547 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/75.uart_fifo_reset.3932319125 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 20608220254 ps |
| CPU time | 55.36 seconds |
| Started | Aug 21 06:47:25 AM UTC 24 |
| Finished | Aug 21 06:48:21 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3932319125 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3932319125 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/75.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2296230867 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 4677717496 ps |
| CPU time | 53.6 seconds |
| Started | Aug 21 06:47:32 AM UTC 24 |
| Finished | Aug 21 06:48:27 AM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2296230867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2296230867 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/76.uart_fifo_reset.3672128857 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 82499758000 ps |
| CPU time | 146.96 seconds |
| Started | Aug 21 06:47:34 AM UTC 24 |
| Finished | Aug 21 06:50:03 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3672128857 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3672128857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/76.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.3998797070 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 2678262983 ps |
| CPU time | 37.11 seconds |
| Started | Aug 21 06:47:35 AM UTC 24 |
| Finished | Aug 21 06:48:14 AM UTC 24 |
| Peak memory | 217700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3998797070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3998797070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/77.uart_fifo_reset.2862087298 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 75235736251 ps |
| CPU time | 93.4 seconds |
| Started | Aug 21 06:47:39 AM UTC 24 |
| Finished | Aug 21 06:49:14 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2862087298 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2862087298 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/77.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.4231128564 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3158558444 ps |
| CPU time | 11.61 seconds |
| Started | Aug 21 06:47:39 AM UTC 24 |
| Finished | Aug 21 06:47:52 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4231128564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.4231128564 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/78.uart_fifo_reset.2508158469 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 28327019265 ps |
| CPU time | 63.58 seconds |
| Started | Aug 21 06:47:41 AM UTC 24 |
| Finished | Aug 21 06:48:46 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2508158469 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2508158469 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/78.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.3738827213 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 5955138282 ps |
| CPU time | 42.21 seconds |
| Started | Aug 21 06:47:42 AM UTC 24 |
| Finished | Aug 21 06:48:26 AM UTC 24 |
| Peak memory | 217916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3738827213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3738827213 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/79.uart_fifo_reset.2157697643 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 19971372029 ps |
| CPU time | 31.46 seconds |
| Started | Aug 21 06:47:43 AM UTC 24 |
| Finished | Aug 21 06:48:16 AM UTC 24 |
| Peak memory | 208704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2157697643 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2157697643 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/79.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.2746739409 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 6534191307 ps |
| CPU time | 117.29 seconds |
| Started | Aug 21 06:47:43 AM UTC 24 |
| Finished | Aug 21 06:49:43 AM UTC 24 |
| Peak memory | 217592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2746739409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2746739409 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_alert_test.4236515040 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 12684539 ps |
| CPU time | 0.79 seconds |
| Started | Aug 21 06:22:26 AM UTC 24 |
| Finished | Aug 21 06:22:28 AM UTC 24 |
| Peak memory | 204216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4236515040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4236515040 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_fifo_full.3649895400 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 48596681304 ps |
| CPU time | 30.05 seconds |
| Started | Aug 21 06:21:59 AM UTC 24 |
| Finished | Aug 21 06:22:31 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3649895400 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3649895400 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.3660813786 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 19730023586 ps |
| CPU time | 54.19 seconds |
| Started | Aug 21 06:22:03 AM UTC 24 |
| Finished | Aug 21 06:22:59 AM UTC 24 |
| Peak memory | 208808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3660813786 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3660813786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_fifo_reset.244637829 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 6504444759 ps |
| CPU time | 17.79 seconds |
| Started | Aug 21 06:22:07 AM UTC 24 |
| Finished | Aug 21 06:22:25 AM UTC 24 |
| Peak memory | 208956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=244637829 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.244637829 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_intr.4207262893 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 23128278264 ps |
| CPU time | 12.64 seconds |
| Started | Aug 21 06:22:16 AM UTC 24 |
| Finished | Aug 21 06:22:29 AM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4207262893 -asse rt nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4207262893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.513687181 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 148316330450 ps |
| CPU time | 890.59 seconds |
| Started | Aug 21 06:22:25 AM UTC 24 |
| Finished | Aug 21 06:37:26 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=513687181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.513687181 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_loopback.3242453065 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 133330972 ps |
| CPU time | 1.37 seconds |
| Started | Aug 21 06:22:22 AM UTC 24 |
| Finished | Aug 21 06:22:25 AM UTC 24 |
| Peak memory | 206092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3242453065 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3242453065 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_perf.3640811592 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 6903288981 ps |
| CPU time | 65.37 seconds |
| Started | Aug 21 06:22:23 AM UTC 24 |
| Finished | Aug 21 06:23:30 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3640811592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3640811592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_rx_oversample.3403682861 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 6393751448 ps |
| CPU time | 73.26 seconds |
| Started | Aug 21 06:22:11 AM UTC 24 |
| Finished | Aug 21 06:23:26 AM UTC 24 |
| Peak memory | 207492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3403682861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3403682861 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.2143030533 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 159302867716 ps |
| CPU time | 257.86 seconds |
| Started | Aug 21 06:22:21 AM UTC 24 |
| Finished | Aug 21 06:26:43 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2143030533 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2143030533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.4180683943 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4634114193 ps |
| CPU time | 3.01 seconds |
| Started | Aug 21 06:22:18 AM UTC 24 |
| Finished | Aug 21 06:22:22 AM UTC 24 |
| Peak memory | 205112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4180683943 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.4180683943 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_smoke.4022899647 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 500987752 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 06:21:55 AM UTC 24 |
| Finished | Aug 21 06:21:58 AM UTC 24 |
| Peak memory | 207920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4022899647 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4022899647 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.1339236744 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 888603242 ps |
| CPU time | 2.55 seconds |
| Started | Aug 21 06:22:22 AM UTC 24 |
| Finished | Aug 21 06:22:26 AM UTC 24 |
| Peak memory | 206596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1339236744 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1339236744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/8.uart_tx_rx.162831721 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 48562906824 ps |
| CPU time | 86.97 seconds |
| Started | Aug 21 06:21:56 AM UTC 24 |
| Finished | Aug 21 06:23:25 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=162831721 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.162831721 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/8.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/80.uart_fifo_reset.45674078 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 24887285140 ps |
| CPU time | 21.62 seconds |
| Started | Aug 21 06:47:44 AM UTC 24 |
| Finished | Aug 21 06:48:07 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=45674078 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.45674078 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/80.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2198168445 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 3962155684 ps |
| CPU time | 32.12 seconds |
| Started | Aug 21 06:47:47 AM UTC 24 |
| Finished | Aug 21 06:48:21 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2198168445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2198168445 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/81.uart_fifo_reset.4263643127 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 81429573388 ps |
| CPU time | 57.81 seconds |
| Started | Aug 21 06:47:47 AM UTC 24 |
| Finished | Aug 21 06:48:47 AM UTC 24 |
| Peak memory | 208652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4263643127 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4263643127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/81.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.3884474928 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2198845837 ps |
| CPU time | 55.67 seconds |
| Started | Aug 21 06:47:48 AM UTC 24 |
| Finished | Aug 21 06:48:46 AM UTC 24 |
| Peak memory | 217980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3884474928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3884474928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/82.uart_fifo_reset.4280933124 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 115320312843 ps |
| CPU time | 56.31 seconds |
| Started | Aug 21 06:47:53 AM UTC 24 |
| Finished | Aug 21 06:48:50 AM UTC 24 |
| Peak memory | 208744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4280933124 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4280933124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/82.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.2265129102 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 5426387867 ps |
| CPU time | 66.36 seconds |
| Started | Aug 21 06:47:53 AM UTC 24 |
| Finished | Aug 21 06:49:01 AM UTC 24 |
| Peak memory | 219904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2265129102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2265129102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/83.uart_fifo_reset.3684435257 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 101245230837 ps |
| CPU time | 285.6 seconds |
| Started | Aug 21 06:47:53 AM UTC 24 |
| Finished | Aug 21 06:52:42 AM UTC 24 |
| Peak memory | 208972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3684435257 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3684435257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/83.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.2033052834 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 1632246612 ps |
| CPU time | 23.91 seconds |
| Started | Aug 21 06:47:54 AM UTC 24 |
| Finished | Aug 21 06:48:19 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2033052834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2033052834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/84.uart_fifo_reset.827516738 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 168754955837 ps |
| CPU time | 111.45 seconds |
| Started | Aug 21 06:47:56 AM UTC 24 |
| Finished | Aug 21 06:49:49 AM UTC 24 |
| Peak memory | 208644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=827516738 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.827516738 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/84.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.1122565478 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 11338058657 ps |
| CPU time | 36.77 seconds |
| Started | Aug 21 06:47:56 AM UTC 24 |
| Finished | Aug 21 06:48:34 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1122565478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1122565478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/85.uart_fifo_reset.3191174011 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 192543978137 ps |
| CPU time | 146.4 seconds |
| Started | Aug 21 06:47:59 AM UTC 24 |
| Finished | Aug 21 06:50:28 AM UTC 24 |
| Peak memory | 208932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3191174011 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3191174011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/85.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.2672379684 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 4972288668 ps |
| CPU time | 18.46 seconds |
| Started | Aug 21 06:48:04 AM UTC 24 |
| Finished | Aug 21 06:48:24 AM UTC 24 |
| Peak memory | 217656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2672379684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2672379684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3769927207 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5713344847 ps |
| CPU time | 21.89 seconds |
| Started | Aug 21 06:48:08 AM UTC 24 |
| Finished | Aug 21 06:48:31 AM UTC 24 |
| Peak memory | 208716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3769927207 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3769927207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/86.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.1309885695 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 4112824128 ps |
| CPU time | 91.11 seconds |
| Started | Aug 21 06:48:08 AM UTC 24 |
| Finished | Aug 21 06:49:41 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1309885695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1309885695 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.1708886260 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2863673007 ps |
| CPU time | 42.35 seconds |
| Started | Aug 21 06:48:14 AM UTC 24 |
| Finished | Aug 21 06:48:58 AM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1708886260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1708886260 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.2913463068 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 7793735889 ps |
| CPU time | 50.63 seconds |
| Started | Aug 21 06:48:17 AM UTC 24 |
| Finished | Aug 21 06:49:09 AM UTC 24 |
| Peak memory | 208892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2913463068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2913463068 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/89.uart_fifo_reset.1593936926 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 61719285159 ps |
| CPU time | 40.81 seconds |
| Started | Aug 21 06:48:20 AM UTC 24 |
| Finished | Aug 21 06:49:02 AM UTC 24 |
| Peak memory | 208784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1593936926 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1593936926 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/89.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.1803829878 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 21388917058 ps |
| CPU time | 22.14 seconds |
| Started | Aug 21 06:48:21 AM UTC 24 |
| Finished | Aug 21 06:48:44 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1803829878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1803829878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_alert_test.4092799691 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 120320378 ps |
| CPU time | 0.78 seconds |
| Started | Aug 21 06:23:07 AM UTC 24 |
| Finished | Aug 21 06:23:09 AM UTC 24 |
| Peak memory | 204520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4092799691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4092799691 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_fifo_full.1222895608 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 14557559186 ps |
| CPU time | 37.59 seconds |
| Started | Aug 21 06:22:31 AM UTC 24 |
| Finished | Aug 21 06:23:10 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1222895608 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg rey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1222895608 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_fifo_full/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.1097049964 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 115182025466 ps |
| CPU time | 45.83 seconds |
| Started | Aug 21 06:22:31 AM UTC 24 |
| Finished | Aug 21 06:23:18 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097049964 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e arlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1097049964 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_fifo_overflow/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_fifo_reset.2040816083 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 59624073415 ps |
| CPU time | 51.65 seconds |
| Started | Aug 21 06:22:32 AM UTC 24 |
| Finished | Aug 21 06:23:25 AM UTC 24 |
| Peak memory | 208732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2040816083 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2040816083 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_intr.659633178 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 60895174277 ps |
| CPU time | 109.45 seconds |
| Started | Aug 21 06:22:50 AM UTC 24 |
| Finished | Aug 21 06:24:41 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=659633178 -asser t nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.659633178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_intr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.1185810637 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 57494559570 ps |
| CPU time | 37.7 seconds |
| Started | Aug 21 06:23:05 AM UTC 24 |
| Finished | Aug 21 06:23:45 AM UTC 24 |
| Peak memory | 208712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1185810637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1185810637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_loopback.3744157255 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4406742327 ps |
| CPU time | 13.02 seconds |
| Started | Aug 21 06:23:01 AM UTC 24 |
| Finished | Aug 21 06:23:15 AM UTC 24 |
| Peak memory | 208672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3744157255 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3744157255 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_loopback/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_noise_filter.2442754708 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 11212643615 ps |
| CPU time | 11.55 seconds |
| Started | Aug 21 06:22:51 AM UTC 24 |
| Finished | Aug 21 06:23:04 AM UTC 24 |
| Peak memory | 207500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2442754708 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2442754708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_noise_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_perf.1210085116 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 20516303344 ps |
| CPU time | 190.83 seconds |
| Started | Aug 21 06:23:04 AM UTC 24 |
| Finished | Aug 21 06:26:18 AM UTC 24 |
| Peak memory | 208728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1210085116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1210085116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_perf/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2399683329 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3907954619 ps |
| CPU time | 41.3 seconds |
| Started | Aug 21 06:22:43 AM UTC 24 |
| Finished | Aug 21 06:23:26 AM UTC 24 |
| Peak memory | 208220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2399683329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2399683329 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_rx_oversample/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.748446562 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 23884524750 ps |
| CPU time | 19.17 seconds |
| Started | Aug 21 06:22:59 AM UTC 24 |
| Finished | Aug 21 06:23:20 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=748446562 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea rlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.748446562 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_rx_parity_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.2560275285 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1790051547 ps |
| CPU time | 5.32 seconds |
| Started | Aug 21 06:22:58 AM UTC 24 |
| Finished | Aug 21 06:23:04 AM UTC 24 |
| Peak memory | 205048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560275285 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr atch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2560275285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_rx_start_bit_filter/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_smoke.2902680419 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5907339764 ps |
| CPU time | 34.84 seconds |
| Started | Aug 21 06:22:29 AM UTC 24 |
| Finished | Aug 21 06:23:06 AM UTC 24 |
| Peak memory | 208740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2902680419 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_ 1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2902680419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.1667671267 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3819107562 ps |
| CPU time | 22.98 seconds |
| Started | Aug 21 06:23:05 AM UTC 24 |
| Finished | Aug 21 06:23:30 AM UTC 24 |
| Peak memory | 217796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1667671267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1667671267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.3763829020 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 982377395 ps |
| CPU time | 3.22 seconds |
| Started | Aug 21 06:23:00 AM UTC 24 |
| Finished | Aug 21 06:23:05 AM UTC 24 |
| Peak memory | 207464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3763829020 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre y_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3763829020 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_tx_ovrd/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/9.uart_tx_rx.460964208 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 65282568362 ps |
| CPU time | 85.19 seconds |
| Started | Aug 21 06:22:29 AM UTC 24 |
| Finished | Aug 21 06:23:57 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=460964208 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1 _0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.460964208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/9.uart_tx_rx/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/90.uart_fifo_reset.4142808039 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 26020322283 ps |
| CPU time | 24.74 seconds |
| Started | Aug 21 06:48:22 AM UTC 24 |
| Finished | Aug 21 06:48:48 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4142808039 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4142808039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/90.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.2427100420 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3309841606 ps |
| CPU time | 24.16 seconds |
| Started | Aug 21 06:48:22 AM UTC 24 |
| Finished | Aug 21 06:48:47 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2427100420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2427100420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/91.uart_fifo_reset.1240878254 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 22805428763 ps |
| CPU time | 32.42 seconds |
| Started | Aug 21 06:48:25 AM UTC 24 |
| Finished | Aug 21 06:48:59 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1240878254 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1240878254 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/91.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.1977908789 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3096366090 ps |
| CPU time | 53.64 seconds |
| Started | Aug 21 06:48:27 AM UTC 24 |
| Finished | Aug 21 06:49:22 AM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1977908789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1977908789 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3012810138 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 79310942608 ps |
| CPU time | 110.62 seconds |
| Started | Aug 21 06:48:28 AM UTC 24 |
| Finished | Aug 21 06:50:21 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012810138 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3012810138 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/92.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.892262780 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 8118797213 ps |
| CPU time | 34.79 seconds |
| Started | Aug 21 06:48:32 AM UTC 24 |
| Finished | Aug 21 06:49:08 AM UTC 24 |
| Peak memory | 217796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=892262780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.892262780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/93.uart_fifo_reset.1821467514 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 116407814223 ps |
| CPU time | 65.13 seconds |
| Started | Aug 21 06:48:34 AM UTC 24 |
| Finished | Aug 21 06:49:41 AM UTC 24 |
| Peak memory | 208904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1821467514 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1821467514 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/93.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.1656453490 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 3802638946 ps |
| CPU time | 37.09 seconds |
| Started | Aug 21 06:48:35 AM UTC 24 |
| Finished | Aug 21 06:49:14 AM UTC 24 |
| Peak memory | 219772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1656453490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1656453490 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.4136382843 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 1029043659 ps |
| CPU time | 13.93 seconds |
| Started | Aug 21 06:48:38 AM UTC 24 |
| Finished | Aug 21 06:48:54 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4136382843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4136382843 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/95.uart_fifo_reset.3010185683 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 14068742606 ps |
| CPU time | 29.92 seconds |
| Started | Aug 21 06:48:45 AM UTC 24 |
| Finished | Aug 21 06:49:16 AM UTC 24 |
| Peak memory | 208912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3010185683 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3010185683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/95.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.420229835 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 21109097692 ps |
| CPU time | 49.64 seconds |
| Started | Aug 21 06:48:45 AM UTC 24 |
| Finished | Aug 21 06:49:36 AM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=420229835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.420229835 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/96.uart_fifo_reset.2064462831 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 98652783729 ps |
| CPU time | 314.92 seconds |
| Started | Aug 21 06:48:45 AM UTC 24 |
| Finished | Aug 21 06:54:04 AM UTC 24 |
| Peak memory | 208720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2064462831 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2064462831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/96.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.2640061445 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 920874503 ps |
| CPU time | 42.45 seconds |
| Started | Aug 21 06:48:46 AM UTC 24 |
| Finished | Aug 21 06:49:30 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640061445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2640061445 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/97.uart_fifo_reset.1230366756 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 30530751453 ps |
| CPU time | 25.17 seconds |
| Started | Aug 21 06:48:47 AM UTC 24 |
| Finished | Aug 21 06:49:13 AM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230366756 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1230366756 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/97.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.568039565 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 7153979103 ps |
| CPU time | 29.52 seconds |
| Started | Aug 21 06:48:47 AM UTC 24 |
| Finished | Aug 21 06:49:18 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=568039565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.568039565 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/98.uart_fifo_reset.1612205635 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 63303135215 ps |
| CPU time | 28.47 seconds |
| Started | Aug 21 06:48:48 AM UTC 24 |
| Finished | Aug 21 06:49:18 AM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1612205635 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl grey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1612205635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/98.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.3319105967 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 1696382420 ps |
| CPU time | 18.55 seconds |
| Started | Aug 21 06:48:48 AM UTC 24 |
| Finished | Aug 21 06:49:08 AM UTC 24 |
| Peak memory | 217532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3319105967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3319105967 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/99.uart_fifo_reset.65051808 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 37756734545 ps |
| CPU time | 92.94 seconds |
| Started | Aug 21 06:48:49 AM UTC 24 |
| Finished | Aug 21 06:50:24 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=65051808 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgr ey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.65051808 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/99.uart_fifo_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.3092419593 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 12968435334 ps |
| CPU time | 52.21 seconds |
| Started | Aug 21 06:48:51 AM UTC 24 |
| Finished | Aug 21 06:49:45 AM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=1000000 0000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowri sc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3092419593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3092419593 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest |
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