Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	90480	1			T1	2		T4	1		T5	33
all_values[1]	90480	1			T1	2		T4	1		T5	33
all_values[2]	90480	1			T1	2		T4	1		T5	33
all_values[3]	90480	1			T1	2		T4	1		T5	33
all_values[4]	90480	1			T1	2		T4	1		T5	33
all_values[5]	90480	1			T1	2		T4	1		T5	33
all_values[6]	90480	1			T1	2		T4	1		T5	33
all_values[7]	90480	1			T1	2		T4	1		T5	33
all_values[8]	90480	1			T1	2		T4	1		T5	33

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

406108

1

T1

18

T4

4

T5

137

auto[1]

408212

1

T4

5

T5

160

T6

92

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

741972

1

T1

13

T4

7

T5

260

auto[1]

72348

1

T1

5

T4

2

T5

37

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29773	1			T5	5		T6	7		T47	1
all_values[0]	auto[0]	auto[1]	19028	1			T1	2		T4	1		T5	19
all_values[0]	auto[1]	auto[0]	25214	1			T5	9		T6	8		T7	7
all_values[0]	auto[1]	auto[1]	16465	1			T6	1		T7	4		T12	1
all_values[1]	auto[0]	auto[0]	40755	1			T1	2		T5	12		T6	14
all_values[1]	auto[0]	auto[1]	1322	1			T21	2		T104	16		T20	1
all_values[1]	auto[1]	auto[0]	46883	1			T4	1		T5	21		T6	10
all_values[1]	auto[1]	auto[1]	1520	1			T19	1		T22	7		T20	4
all_values[2]	auto[0]	auto[0]	41906	1			T1	1		T4	1		T5	16
all_values[2]	auto[0]	auto[1]	2274	1			T1	1		T5	1		T6	8
all_values[2]	auto[1]	auto[0]	44199	1			T5	13		T6	1		T7	13
all_values[2]	auto[1]	auto[1]	2101	1			T5	3		T7	5		T30	1
all_values[3]	auto[0]	auto[0]	45588	1			T1	2		T4	1		T5	10
all_values[3]	auto[0]	auto[1]	294	1			T19	1		T20	8		T33	5
all_values[3]	auto[1]	auto[0]	44322	1			T5	23		T6	15		T7	7
all_values[3]	auto[1]	auto[1]	276	1			T19	2		T16	2		T20	2
all_values[4]	auto[0]	auto[0]	43092	1			T1	2		T5	8		T6	14
all_values[4]	auto[0]	auto[1]	399	1			T20	1		T18	6		T33	3
all_values[4]	auto[1]	auto[0]	46560	1			T4	1		T5	25		T6	10
all_values[4]	auto[1]	auto[1]	429	1			T21	13		T20	5		T18	5
all_values[5]	auto[0]	auto[0]	45525	1			T1	2		T4	1		T5	23
all_values[5]	auto[0]	auto[1]	167	1			T19	1		T20	5		T33	2
all_values[5]	auto[1]	auto[0]	44603	1			T5	10		T6	11		T7	12
all_values[5]	auto[1]	auto[1]	185	1			T19	3		T20	3		T33	2
all_values[6]	auto[0]	auto[0]	45531	1			T1	2		T5	17		T6	9
all_values[6]	auto[0]	auto[1]	163	1			T19	3		T20	3		T53	2
all_values[6]	auto[1]	auto[0]	44627	1			T4	1		T5	16		T6	15
all_values[6]	auto[1]	auto[1]	159	1			T20	4		T33	4		T53	1
all_values[7]	auto[0]	auto[0]	43391	1			T1	2		T5	10		T6	20
all_values[7]	auto[0]	auto[1]	313	1			T19	1		T20	2		T18	1
all_values[7]	auto[1]	auto[0]	46476	1			T4	1		T5	23		T6	4
all_values[7]	auto[1]	auto[1]	300	1			T19	3		T21	4		T22	3
all_values[8]	auto[0]	auto[0]	31547	1			T5	5		T6	7		T7	7
all_values[8]	auto[0]	auto[1]	15040	1			T1	2		T5	11		T9	2
all_values[8]	auto[1]	auto[0]	31980	1			T5	14		T6	14		T21	7
all_values[8]	auto[1]	auto[1]	11913	1			T4	1		T5	3		T6	3