Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2572

1

T1

1

T2

1

T3

11

auto[UartRx]

2572

1

T1

1

T2

1

T3

11

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4511	1			T1	2		T2	2		T3	22
values[1]	44	1			T33	1		T35	1		T39	1
values[2]	47	1			T19	1		T36	1		T291	1
values[3]	51	1			T19	1		T20	1		T33	2
values[4]	51	1			T33	2		T35	1		T36	1
values[5]	61	1			T19	1		T37	1		T38	2
values[6]	55	1			T20	1		T38	3		T88	1
values[7]	64	1			T29	1		T20	1		T33	1
values[8]	58	1			T20	1		T36	1		T38	1
values[9]	67	1			T29	1		T20	1		T33	2
values[10]	77	1			T29	1		T33	3		T34	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2358	1			T1	1		T2	1		T3	11
auto[UartTx]	values[1]	13	1			T35	1		T88	1		T398	1
auto[UartTx]	values[2]	13	1			T291	1		T89	1		T399	1
auto[UartTx]	values[3]	21	1			T19	1		T293	1		T400	1
auto[UartTx]	values[4]	19	1			T33	2		T36	1		T114	1
auto[UartTx]	values[5]	20	1			T19	1		T37	1		T88	1
auto[UartTx]	values[6]	18	1			T38	1		T93	1		T94	1
auto[UartTx]	values[7]	22	1			T293	2		T291	2		T329	1
auto[UartTx]	values[8]	21	1			T20	1		T39	1		T401	1
auto[UartTx]	values[9]	25	1			T36	1		T37	1		T38	1
auto[UartTx]	values[10]	24	1			T33	2		T34	1		T36	2
auto[UartRx]	values[0]	2153	1			T1	1		T2	1		T3	11
auto[UartRx]	values[1]	31	1			T33	1		T39	1		T400	1
auto[UartRx]	values[2]	34	1			T19	1		T36	1		T400	1
auto[UartRx]	values[3]	30	1			T20	1		T33	2		T39	1
auto[UartRx]	values[4]	32	1			T35	1		T37	1		T38	1
auto[UartRx]	values[5]	41	1			T38	2		T291	1		T401	1
auto[UartRx]	values[6]	37	1			T20	1		T38	2		T88	1
auto[UartRx]	values[7]	42	1			T29	1		T20	1		T33	1
auto[UartRx]	values[8]	37	1			T36	1		T38	1		T39	1
auto[UartRx]	values[9]	42	1			T29	1		T20	1		T33	2
auto[UartRx]	values[10]	53	1			T29	1		T33	1		T35	1