Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1934	1			T5	1		T6	2		T12	8
auto[BaudRate115200]	1550	1			T4	3		T5	1		T6	5
auto[BaudRate230400]	1582	1			T4	6		T5	1		T6	2
auto[BaudRate128Kbps]	1614	1			T5	2		T6	1		T14	1
auto[BaudRate256Kbps]	1714	1			T1	1		T4	3		T5	1
auto[BaudRate1Mbps]	1488	1			T1	1		T4	3		T5	3
auto[BaudRate1p5Mbps]	1070	1			T5	1		T9	1		T11	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1130	1			T13	2		T15	50		T130	8
freqs[25]	1006	1			T4	15		T7	10		T103	9
freqs[48]	560	1			T20	16		T318	2		T339	2
freqs[50]	483	1			T9	2		T44	2		T99	3
freqs[100]	1156	1			T11	2		T23	2		T341	2

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	184	1			T15	17		T130	1		T298	1
auto[BaudRate9600]	freqs[25]	149	1			T103	2		T133	1		T308	1
auto[BaudRate9600]	freqs[48]	58	1			T318	1		T339	1		T367	2
auto[BaudRate9600]	freqs[50]	64	1			T99	1		T52	1		T368	1
auto[BaudRate9600]	freqs[100]	212	1			T402	18		T315	1		T403	3
auto[BaudRate115200]	freqs[24]	172	1			T15	3		T25	2		T298	3
auto[BaudRate115200]	freqs[25]	125	1			T4	3		T7	3		T103	1
auto[BaudRate115200]	freqs[48]	89	1			T20	5		T124	3		T328	1
auto[BaudRate115200]	freqs[50]	85	1			T9	1		T99	1		T52	4
auto[BaudRate115200]	freqs[100]	140	1			T11	1		T380	1		T35	2
auto[BaudRate230400]	freqs[24]	169	1			T15	6		T130	2		T25	1
auto[BaudRate230400]	freqs[25]	160	1			T4	6		T7	4		T133	2
auto[BaudRate230400]	freqs[48]	68	1			T20	2		T330	1		T301	1
auto[BaudRate230400]	freqs[50]	50	1			T52	2		T323	1		T400	1
auto[BaudRate230400]	freqs[100]	133	1			T380	1		T35	3		T134	2
auto[BaudRate128Kbps]	freqs[24]	208	1			T15	12		T130	3		T298	3
auto[BaudRate128Kbps]	freqs[25]	143	1			T103	3		T342	1		T308	1
auto[BaudRate128Kbps]	freqs[48]	84	1			T20	1		T318	1		T124	2
auto[BaudRate128Kbps]	freqs[50]	67	1			T44	2		T52	4		T313	2
auto[BaudRate128Kbps]	freqs[100]	147	1			T23	1		T35	1		T134	1
auto[BaudRate256Kbps]	freqs[24]	180	1			T15	6		T130	1		T298	2
auto[BaudRate256Kbps]	freqs[25]	152	1			T4	3		T7	1		T133	2
auto[BaudRate256Kbps]	freqs[48]	83	1			T20	1		T124	2		T328	1
auto[BaudRate256Kbps]	freqs[50]	65	1			T52	2		T368	1		T323	1
auto[BaudRate256Kbps]	freqs[100]	176	1			T23	1		T35	1		T134	1
auto[BaudRate1Mbps]	freqs[24]	134	1			T13	2		T15	6		T130	1
auto[BaudRate1Mbps]	freqs[25]	178	1			T4	3		T7	2		T103	2
auto[BaudRate1Mbps]	freqs[48]	88	1			T20	4		T339	1		T124	1
auto[BaudRate1Mbps]	freqs[50]	83	1			T52	2		T323	3		T400	2
auto[BaudRate1Mbps]	freqs[100]	168	1			T341	1		T35	3		T134	1
auto[BaudRate1p5Mbps]	freqs[25]	99	1			T103	1		T342	1		T308	1
auto[BaudRate1p5Mbps]	freqs[48]	90	1			T20	3		T124	1		T330	1
auto[BaudRate1p5Mbps]	freqs[50]	69	1			T9	1		T99	1		T52	4
auto[BaudRate1p5Mbps]	freqs[100]	180	1			T11	1		T341	1		T35	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded