Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	26938358	1			T4	3		T5	73		T6	254
all_levels[1]	150033	1			T6	26		T7	26		T16	1
all_levels[2]	1942	1			T6	8		T7	4		T45	2
all_levels[3]	866	1			T6	10		T47	4		T99	2
all_levels[4]	589	1			T6	4		T7	1		T47	3
all_levels[5]	498	1			T5	1		T6	3		T30	1
all_levels[6]	341	1			T6	1		T47	1		T22	1
all_levels[7]	324	1			T5	1		T6	1		T104	2
all_levels[8]	241	1			T6	3		T16	1		T47	1
all_levels[9]	222	1			T104	1		T95	1		T122	1
all_levels[10]	170	1			T6	1		T104	1		T123	1
all_levels[11]	147	1			T6	2		T95	1		T100	1
all_levels[12]	146	1			T30	1		T47	1		T104	1
all_levels[13]	107	1			T6	1		T30	1		T124	1
all_levels[14]	95	1			T6	1		T100	2		T125	1
all_levels[15]	88	1			T16	1		T126	1		T127	1
all_levels[16]	89	1			T125	1		T124	1		T128	2
all_levels[17]	112	1			T47	1		T95	1		T17	1
all_levels[18]	94	1			T16	2		T30	1		T98	1
all_levels[19]	80	1			T103	1		T124	1		T129	1
all_levels[20]	76	1			T104	1		T100	1		T103	1
all_levels[21]	63	1			T95	1		T100	1		T127	2
all_levels[22]	51	1			T100	1		T130	1		T107	1
all_levels[23]	64	1			T100	1		T131	1		T132	1
all_levels[24]	50	1			T95	1		T96	4		T103	2
all_levels[25]	35	1			T128	1		T37	1		T127	1
all_levels[26]	34	1			T104	1		T107	1		T112	1
all_levels[27]	42	1			T133	2		T131	1		T118	1
all_levels[28]	50	1			T107	1		T128	1		T134	1
all_levels[29]	36	1			T22	1		T104	1		T135	2
all_levels[30]	28	1			T107	1		T128	1		T136	2
all_levels[31]	29	1			T5	1		T132	1		T137	1
all_levels[32]	17	1			T138	1		T139	1		T140	1
all_levels[33]	20	1			T126	1		T112	1		T138	2
all_levels[34]	23	1			T16	1		T141	1		T138	1
all_levels[35]	21	1			T142	1		T143	1		T144	1
all_levels[36]	31	1			T104	1		T107	1		T145	2
all_levels[37]	36	1			T128	1		T135	3		T132	1
all_levels[38]	19	1			T114	1		T146	1		T147	1
all_levels[39]	28	1			T22	1		T95	1		T125	1
all_levels[40]	12	1			T148	1		T146	1		T149	1
all_levels[41]	16	1			T123	1		T131	1		T129	1
all_levels[42]	17	1			T36	2		T150	1		T151	1
all_levels[43]	8	1			T152	1		T153	2		T154	3
all_levels[44]	6	1			T139	1		T155	1		T156	1
all_levels[45]	3	1			T157	1		T158	1		T159	1
all_levels[46]	10	1			T143	1		T160	1		T161	1
all_levels[47]	18	1			T162	1		T163	1		T164	1
all_levels[48]	11	1			T112	1		T165	1		T166	1
all_levels[49]	8	1			T16	1		T151	1		T167	1
all_levels[50]	6	1			T168	1		T169	1		T170	1
all_levels[51]	14	1			T30	1		T123	1		T126	1
all_levels[52]	11	1			T171	4		T146	1		T157	1
all_levels[53]	5	1			T172	1		T173	1		T174	2
all_levels[54]	10	1			T150	1		T175	1		T176	1
all_levels[55]	9	1			T16	2		T177	1		T148	1
all_levels[56]	6	1			T178	1		T163	2		T169	1
all_levels[57]	9	1			T98	1		T162	1		T179	3
all_levels[58]	4	1			T180	1		T181	1		T182	1
all_levels[59]	3	1			T183	2		T184	1		-	-
all_levels[60]	5	1			T180	1		T137	1		T152	1
all_levels[61]	3	1			T30	1		T129	1		T180	1
all_levels[62]	4	1			T185	1		T186	2		T154	1
all_levels[63]	8	1			T187	1		T188	1		T189	1
all_levels[64]	99	1			T16	1		T17	1		T123	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27091623

1

T5

76

T6

315

T7

379

auto[1]

3977

1

T4

3

T12

1

T15

10

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[44] , all_levels[45]]	[auto[1]]	--	--	2
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	26934871	1			T5	73		T6	254		T7	348
all_levels[0]	auto[1]	3487	1			T4	3		T12	1		T15	10
all_levels[1]	auto[0]	149940	1			T6	26		T7	26		T16	1
all_levels[1]	auto[1]	93	1			T190	1		T191	1		T135	2
all_levels[2]	auto[0]	1918	1			T6	8		T7	4		T45	2
all_levels[2]	auto[1]	24	1			T126	1		T192	2		T193	1
all_levels[3]	auto[0]	845	1			T6	10		T47	4		T99	2
all_levels[3]	auto[1]	21	1			T194	1		T195	2		T196	2
all_levels[4]	auto[0]	572	1			T6	4		T7	1		T47	3
all_levels[4]	auto[1]	17	1			T192	1		T197	1		T198	1
all_levels[5]	auto[0]	480	1			T5	1		T6	3		T30	1
all_levels[5]	auto[1]	18	1			T128	1		T194	1		T136	1
all_levels[6]	auto[0]	325	1			T6	1		T47	1		T22	1
all_levels[6]	auto[1]	16	1			T131	1		T199	1		T200	1
all_levels[7]	auto[0]	299	1			T5	1		T6	1		T104	2
all_levels[7]	auto[1]	25	1			T110	1		T201	1		T179	1
all_levels[8]	auto[0]	221	1			T6	3		T16	1		T47	1
all_levels[8]	auto[1]	20	1			T195	1		T202	3		T199	1
all_levels[9]	auto[0]	207	1			T104	1		T95	1		T122	1
all_levels[9]	auto[1]	15	1			T203	1		T204	1		T205	1
all_levels[10]	auto[0]	161	1			T6	1		T104	1		T123	1
all_levels[10]	auto[1]	9	1			T206	4		T207	1		T208	2
all_levels[11]	auto[0]	137	1			T6	2		T95	1		T100	1
all_levels[11]	auto[1]	10	1			T209	3		T210	1		T211	2
all_levels[12]	auto[0]	138	1			T30	1		T47	1		T104	1
all_levels[12]	auto[1]	8	1			T171	1		T212	1		T213	1
all_levels[13]	auto[0]	98	1			T6	1		T30	1		T124	1
all_levels[13]	auto[1]	9	1			T214	1		T215	1		T216	1
all_levels[14]	auto[0]	92	1			T6	1		T100	2		T125	1
all_levels[14]	auto[1]	3	1			T217	1		T218	2		-	-
all_levels[15]	auto[0]	85	1			T16	1		T126	1		T127	1
all_levels[15]	auto[1]	3	1			T219	2		T220	1		-	-
all_levels[16]	auto[0]	85	1			T125	1		T124	1		T128	1
all_levels[16]	auto[1]	4	1			T128	1		T221	1		T222	1
all_levels[17]	auto[0]	96	1			T47	1		T95	1		T17	1
all_levels[17]	auto[1]	16	1			T192	2		T212	1		T198	1
all_levels[18]	auto[0]	85	1			T16	1		T30	1		T98	1
all_levels[18]	auto[1]	9	1			T16	1		T183	1		T223	1
all_levels[19]	auto[0]	68	1			T103	1		T124	1		T129	1
all_levels[19]	auto[1]	12	1			T161	1		T209	1		T224	1
all_levels[20]	auto[0]	67	1			T104	1		T100	1		T103	1
all_levels[20]	auto[1]	9	1			T225	1		T226	1		T227	1
all_levels[21]	auto[0]	54	1			T95	1		T100	1		T127	2
all_levels[21]	auto[1]	9	1			T202	2		T213	1		T228	1
all_levels[22]	auto[0]	50	1			T100	1		T130	1		T107	1
all_levels[22]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[23]	auto[0]	54	1			T100	1		T131	1		T132	1
all_levels[23]	auto[1]	10	1			T230	1		T231	1		T213	1
all_levels[24]	auto[0]	41	1			T95	1		T96	1		T103	2
all_levels[24]	auto[1]	9	1			T96	3		T232	3		T233	2
all_levels[25]	auto[0]	32	1			T128	1		T37	1		T127	1
all_levels[25]	auto[1]	3	1			T234	3		-	-		-	-
all_levels[26]	auto[0]	32	1			T104	1		T107	1		T112	1
all_levels[26]	auto[1]	2	1			T235	2		-	-		-	-
all_levels[27]	auto[0]	36	1			T133	1		T131	1		T118	1
all_levels[27]	auto[1]	6	1			T133	1		T236	1		T159	1
all_levels[28]	auto[0]	41	1			T107	1		T128	1		T134	1
all_levels[28]	auto[1]	9	1			T237	1		T238	3		T165	1
all_levels[29]	auto[0]	29	1			T22	1		T104	1		T135	1
all_levels[29]	auto[1]	7	1			T135	1		T203	4		T186	1
all_levels[30]	auto[0]	26	1			T107	1		T128	1		T136	1
all_levels[30]	auto[1]	2	1			T136	1		T203	1		-	-
all_levels[31]	auto[0]	21	1			T5	1		T132	1		T137	1
all_levels[31]	auto[1]	8	1			T239	1		T240	1		T241	3
all_levels[32]	auto[0]	16	1			T138	1		T139	1		T140	1
all_levels[32]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[33]	auto[0]	18	1			T126	1		T112	1		T138	1
all_levels[33]	auto[1]	2	1			T138	1		T243	1		-	-
all_levels[34]	auto[0]	19	1			T16	1		T141	1		T138	1
all_levels[34]	auto[1]	4	1			T244	4		-	-		-	-
all_levels[35]	auto[0]	20	1			T142	1		T143	1		T144	1
all_levels[35]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[36]	auto[0]	28	1			T104	1		T107	1		T145	2
all_levels[36]	auto[1]	3	1			T246	1		T247	1		T248	1
all_levels[37]	auto[0]	26	1			T128	1		T135	1		T132	1
all_levels[37]	auto[1]	10	1			T135	2		T249	1		T250	2
all_levels[38]	auto[0]	16	1			T114	1		T146	1		T147	1
all_levels[38]	auto[1]	3	1			T159	2		T208	1		-	-
all_levels[39]	auto[0]	24	1			T22	1		T95	1		T125	1
all_levels[39]	auto[1]	4	1			T251	3		T252	1		-	-
all_levels[40]	auto[0]	12	1			T148	1		T146	1		T149	1
all_levels[41]	auto[0]	14	1			T123	1		T131	1		T129	1
all_levels[41]	auto[1]	2	1			T92	1		T253	1		-	-
all_levels[42]	auto[0]	15	1			T36	1		T150	1		T151	1
all_levels[42]	auto[1]	2	1			T36	1		T254	1		-	-
all_levels[43]	auto[0]	6	1			T152	1		T153	2		T154	1
all_levels[43]	auto[1]	2	1			T154	2		-	-		-	-
all_levels[44]	auto[0]	6	1			T139	1		T155	1		T156	1
all_levels[45]	auto[0]	3	1			T157	1		T158	1		T159	1
all_levels[46]	auto[0]	9	1			T143	1		T160	1		T161	1
all_levels[46]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[47]	auto[0]	13	1			T162	1		T163	1		T164	1
all_levels[47]	auto[1]	5	1			T255	2		T256	2		T257	1
all_levels[48]	auto[0]	8	1			T112	1		T165	1		T166	1
all_levels[48]	auto[1]	3	1			T258	3		-	-		-	-
all_levels[49]	auto[0]	7	1			T16	1		T151	1		T167	1
all_levels[49]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[50]	auto[0]	5	1			T168	1		T169	1		T170	1
all_levels[50]	auto[1]	1	1			T259	1		-	-		-	-
all_levels[51]	auto[0]	10	1			T30	1		T123	1		T126	1
all_levels[51]	auto[1]	4	1			T260	2		T261	2		-	-
all_levels[52]	auto[0]	8	1			T171	1		T146	1		T157	1
all_levels[52]	auto[1]	3	1			T171	3		-	-		-	-
all_levels[53]	auto[0]	4	1			T172	1		T173	1		T174	1
all_levels[53]	auto[1]	1	1			T174	1		-	-		-	-
all_levels[54]	auto[0]	9	1			T150	1		T175	1		T176	1
all_levels[54]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[55]	auto[0]	8	1			T16	1		T177	1		T148	1
all_levels[55]	auto[1]	1	1			T16	1		-	-		-	-
all_levels[56]	auto[0]	6	1			T178	1		T163	2		T169	1
all_levels[57]	auto[0]	5	1			T98	1		T162	1		T179	1
all_levels[57]	auto[1]	4	1			T179	2		T262	1		T263	1
all_levels[58]	auto[0]	4	1			T180	1		T181	1		T182	1
all_levels[59]	auto[0]	2	1			T183	1		T184	1		-	-
all_levels[59]	auto[1]	1	1			T183	1		-	-		-	-
all_levels[60]	auto[0]	5	1			T180	1		T137	1		T152	1
all_levels[61]	auto[0]	3	1			T30	1		T129	1		T180	1
all_levels[62]	auto[0]	3	1			T185	1		T186	1		T154	1
all_levels[62]	auto[1]	1	1			T186	1		-	-		-	-
all_levels[63]	auto[0]	8	1			T187	1		T188	1		T189	1
all_levels[64]	auto[0]	77	1			T16	1		T17	1		T123	1
all_levels[64]	auto[1]	22	1			T114	3		T161	2		T264	1