Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	90480	1			T1	2		T4	1		T5	33
all_pins[1]	90480	1			T1	2		T4	1		T5	33
all_pins[2]	90480	1			T1	2		T4	1		T5	33
all_pins[3]	90480	1			T1	2		T4	1		T5	33
all_pins[4]	90480	1			T1	2		T4	1		T5	33
all_pins[5]	90480	1			T1	2		T4	1		T5	33
all_pins[6]	90480	1			T1	2		T4	1		T5	33
all_pins[7]	90480	1			T1	2		T4	1		T5	33
all_pins[8]	90480	1			T1	2		T4	1		T5	33

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	780075	1			T1	18		T4	8		T5	285
values[0x1]	34245	1			T4	1		T5	12		T6	6
transitions[0x0=>0x1]	28173	1			T5	11		T6	6		T7	15
transitions[0x1=>0x0]	27972	1			T4	1		T5	12		T6	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	73959	1			T1	2		T4	1		T5	33
all_pins[0]	values[0x1]	16521	1			T6	1		T7	4		T12	1
all_pins[0]	transitions[0x0=>0x1]	16069	1			T6	1		T7	4		T12	1
all_pins[0]	transitions[0x1=>0x0]	1066	1			T22	6		T20	2		T95	4
all_pins[1]	values[0x0]	88962	1			T1	2		T4	1		T5	33
all_pins[1]	values[0x1]	1518	1			T19	1		T22	7		T20	4
all_pins[1]	transitions[0x0=>0x1]	1428	1			T19	1		T22	7		T20	4
all_pins[1]	transitions[0x1=>0x0]	2065	1			T5	3		T7	5		T21	2
all_pins[2]	values[0x0]	88325	1			T1	2		T4	1		T5	30
all_pins[2]	values[0x1]	2155	1			T5	3		T7	5		T21	2
all_pins[2]	transitions[0x0=>0x1]	2082	1			T5	3		T7	5		T21	2
all_pins[2]	transitions[0x1=>0x0]	203	1			T19	2		T16	2		T20	2
all_pins[3]	values[0x0]	90204	1			T1	2		T4	1		T5	33
all_pins[3]	values[0x1]	276	1			T19	2		T16	2		T20	2
all_pins[3]	transitions[0x0=>0x1]	221	1			T19	2		T16	2		T20	2
all_pins[3]	transitions[0x1=>0x0]	374	1			T21	13		T20	5		T18	5
all_pins[4]	values[0x0]	90051	1			T1	2		T4	1		T5	33
all_pins[4]	values[0x1]	429	1			T21	13		T20	5		T18	5
all_pins[4]	transitions[0x0=>0x1]	356	1			T21	12		T20	3		T18	4
all_pins[4]	transitions[0x1=>0x0]	165	1			T19	3		T20	1		T18	1
all_pins[5]	values[0x0]	90242	1			T1	2		T4	1		T5	33
all_pins[5]	values[0x1]	238	1			T19	3		T21	1		T20	3
all_pins[5]	transitions[0x0=>0x1]	189	1			T19	3		T21	1		T20	1
all_pins[5]	transitions[0x1=>0x0]	776	1			T5	6		T6	2		T16	2
all_pins[6]	values[0x0]	89655	1			T1	2		T4	1		T5	27
all_pins[6]	values[0x1]	825	1			T5	6		T6	2		T16	2
all_pins[6]	transitions[0x0=>0x1]	763	1			T5	6		T6	2		T16	2
all_pins[6]	transitions[0x1=>0x0]	238	1			T19	3		T21	4		T22	2
all_pins[7]	values[0x0]	90180	1			T1	2		T4	1		T5	33
all_pins[7]	values[0x1]	300	1			T19	3		T21	4		T22	3
all_pins[7]	transitions[0x0=>0x1]	154	1			T19	2		T22	3		T20	6
all_pins[7]	transitions[0x1=>0x0]	11837	1			T4	1		T5	3		T6	3
all_pins[8]	values[0x0]	78497	1			T1	2		T5	30		T6	21
all_pins[8]	values[0x1]	11983	1			T4	1		T5	3		T6	3
all_pins[8]	transitions[0x0=>0x1]	6911	1			T5	2		T6	3		T7	6
all_pins[8]	transitions[0x1=>0x0]	11248	1			T6	1		T19	4		T21	5