Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5941267	1			T5	6		T6	32		T7	172
all_levels[1]	1672668	1			T5	29		T6	100		T7	1
all_levels[2]	305273	1			T5	3		T6	9		T7	18
all_levels[3]	187119	1			T5	1		T6	6		T16	1
all_levels[4]	223193	1			T6	7		T104	1		T95	2
all_levels[5]	274194	1			T5	2		T6	7		T19	4
all_levels[6]	183572	1			T6	9		T16	5		T47	1
all_levels[7]	252805	1			T6	7		T45	3		T104	4
all_levels[8]	240678	1			T5	1		T6	32		T7	1
all_levels[9]	382154	1			T5	8		T6	6		T122	84
all_levels[10]	172716	1			T6	14		T30	1		T47	4
all_levels[11]	569645	1			T6	11		T47	9		T95	8
all_levels[12]	321069	1			T6	37		T47	5		T98	1
all_levels[13]	205361	1			T6	7		T7	48		T30	5
all_levels[14]	186282	1			T5	3		T7	43		T98	1
all_levels[15]	151199	1			T21	5		T16	1		T99	133
all_levels[16]	291956	1			T21	186		T30	4		T99	1
all_levels[17]	170293	1			T295	3		T150	2		T283	9
all_levels[18]	161312	1			T95	1		T122	2		T33	1
all_levels[19]	160080	1			T7	2		T104	1		T98	1
all_levels[20]	226555	1			T7	1		T47	2		T104	1
all_levels[21]	175680	1			T33	3		T283	6		T306	1042
all_levels[22]	142516	1			T6	6		T16	2		T95	5
all_levels[23]	215135	1			T16	3		T47	2		T95	2
all_levels[24]	139498	1			T6	2		T7	42		T30	12
all_levels[25]	236079	1			T95	4		T100	2		T122	5
all_levels[26]	224578	1			T95	1		T17	17		T122	5
all_levels[27]	155912	1			T104	2		T95	2		T124	2
all_levels[28]	133500	1			T7	3		T95	25		T98	1
all_levels[29]	210808	1			T6	5		T7	1		T104	2
all_levels[30]	153618	1			T6	10		T22	2		T122	4
all_levels[31]	434901	1			T6	6		T95	2		T98	3
all_levels[32]	12593761	1			T5	24		T6	2		T7	47

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27091623

1

T5

76

T6

315

T7

379

auto[1]

3754

1

T5

1

T12

1

T21

18

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5939151	1			T5	6		T6	32		T7	172
all_levels[0]	auto[1]	2116	1			T12	1		T21	14		T16	3
all_levels[1]	auto[0]	1672441	1			T5	28		T6	100		T7	1
all_levels[1]	auto[1]	227	1			T5	1		T16	3		T95	1
all_levels[2]	auto[0]	305232	1			T5	3		T6	9		T7	18
all_levels[2]	auto[1]	41	1			T30	1		T314	2		T407	1
all_levels[3]	auto[0]	187002	1			T5	1		T6	6		T16	1
all_levels[3]	auto[1]	117	1			T25	26		T105	4		T106	18
all_levels[4]	auto[0]	223159	1			T6	7		T104	1		T95	2
all_levels[4]	auto[1]	34	1			T190	1		T131	1		T136	1
all_levels[5]	auto[0]	274179	1			T5	2		T6	7		T19	4
all_levels[5]	auto[1]	15	1			T408	1		T409	1		T410	2
all_levels[6]	auto[0]	183541	1			T6	9		T16	3		T47	1
all_levels[6]	auto[1]	31	1			T16	2		T128	1		T290	1
all_levels[7]	auto[0]	252687	1			T6	7		T45	3		T104	3
all_levels[7]	auto[1]	118	1			T104	1		T105	20		T116	1
all_levels[8]	auto[0]	240660	1			T5	1		T6	32		T7	1
all_levels[8]	auto[1]	18	1			T128	2		T171	2		T411	1
all_levels[9]	auto[0]	382129	1			T5	8		T6	6		T122	84
all_levels[9]	auto[1]	25	1			T267	1		T191	1		T296	1
all_levels[10]	auto[0]	172697	1			T6	14		T30	1		T47	4
all_levels[10]	auto[1]	19	1			T112	1		T135	1		T296	1
all_levels[11]	auto[0]	569612	1			T6	11		T47	9		T95	8
all_levels[11]	auto[1]	33	1			T266	1		T299	1		T135	1
all_levels[12]	auto[0]	321037	1			T6	37		T47	5		T98	1
all_levels[12]	auto[1]	32	1			T126	1		T270	1		T194	2
all_levels[13]	auto[0]	205336	1			T6	7		T7	48		T30	5
all_levels[13]	auto[1]	25	1			T314	1		T193	2		T412	1
all_levels[14]	auto[0]	186253	1			T5	3		T7	43		T98	1
all_levels[14]	auto[1]	29	1			T308	1		T373	1		T378	1
all_levels[15]	auto[0]	151087	1			T21	1		T16	1		T99	133
all_levels[15]	auto[1]	112	1			T21	4		T18	3		T108	7
all_levels[16]	auto[0]	291930	1			T21	186		T30	4		T99	1
all_levels[16]	auto[1]	26	1			T272	1		T413	1		T414	1
all_levels[17]	auto[0]	170270	1			T295	3		T150	2		T283	9
all_levels[17]	auto[1]	23	1			T321	1		T415	2		T183	1
all_levels[18]	auto[0]	161287	1			T95	1		T122	2		T33	1
all_levels[18]	auto[1]	25	1			T296	2		T161	1		T201	1
all_levels[19]	auto[0]	160068	1			T7	2		T104	1		T98	1
all_levels[19]	auto[1]	12	1			T280	1		T205	1		T416	2
all_levels[20]	auto[0]	226524	1			T7	1		T47	2		T104	1
all_levels[20]	auto[1]	31	1			T280	1		T337	1		T336	1
all_levels[21]	auto[0]	175677	1			T33	3		T283	6		T306	1042
all_levels[21]	auto[1]	3	1			T417	1		T206	1		T251	1
all_levels[22]	auto[0]	142500	1			T6	6		T16	2		T95	5
all_levels[22]	auto[1]	16	1			T296	2		T336	1		T418	1
all_levels[23]	auto[0]	215121	1			T16	2		T47	2		T95	2
all_levels[23]	auto[1]	14	1			T16	1		T397	1		T419	1
all_levels[24]	auto[0]	139478	1			T6	2		T7	42		T30	12
all_levels[24]	auto[1]	20	1			T47	1		T277	1		T287	1
all_levels[25]	auto[0]	236064	1			T95	4		T100	2		T122	5
all_levels[25]	auto[1]	15	1			T128	1		T305	1		T171	1
all_levels[26]	auto[0]	224541	1			T95	1		T17	16		T122	5
all_levels[26]	auto[1]	37	1			T17	1		T112	1		T117	1
all_levels[27]	auto[0]	155896	1			T104	2		T95	2		T124	2
all_levels[27]	auto[1]	16	1			T352	1		T138	1		T171	3
all_levels[28]	auto[0]	133486	1			T7	3		T95	25		T98	1
all_levels[28]	auto[1]	14	1			T180	1		T274	1		T146	1
all_levels[29]	auto[0]	210791	1			T6	5		T7	1		T104	2
all_levels[29]	auto[1]	17	1			T194	1		T136	1		T389	1
all_levels[30]	auto[0]	153598	1			T6	10		T22	2		T122	3
all_levels[30]	auto[1]	20	1			T122	1		T302	1		T420	1
all_levels[31]	auto[0]	434881	1			T6	6		T95	2		T98	3
all_levels[31]	auto[1]	20	1			T298	1		T350	1		T192	1
all_levels[32]	auto[0]	12593308	1			T5	24		T6	2		T7	47
all_levels[32]	auto[1]	453	1			T16	1		T96	4		T280	4