Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	734	1			T19	4		T20	14		T33	7
all_values[1]	734	1			T19	4		T20	14		T33	7
all_values[2]	734	1			T19	4		T20	14		T33	7
all_values[3]	734	1			T19	4		T20	14		T33	7
all_values[4]	734	1			T19	4		T20	14		T33	7
all_values[5]	734	1			T19	4		T20	14		T33	7
all_values[6]	734	1			T19	4		T20	14		T33	7
all_values[7]	734	1			T19	4		T20	14		T33	7
all_values[8]	734	1			T19	4		T20	14		T33	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3649

1

T19

20

T20

63

T33

35

auto[1]

2957

1

T19

16

T20

63

T33

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2165

1

T19

11

T20

36

T33

15

auto[1]

4441

1

T19

25

T20

90

T33

48

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3886

1

T19

23

T20

64

T33

34

auto[1]

2720

1

T19

13

T20

62

T33

29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	251	1			T19	1		T20	2		T33	1
all_values[0]	auto[0]	auto[1]	auto[1]	183	1			T19	2		T20	6		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	166	1			T19	1		T20	5		T33	3
all_values[0]	auto[1]	auto[1]	auto[1]	134	1			T20	1		T33	2		T39	1
all_values[1]	auto[0]	auto[0]	auto[0]	247	1			T19	1		T20	2		T33	4
all_values[1]	auto[0]	auto[1]	auto[0]	197	1			T19	2		T20	7		T33	1
all_values[1]	auto[1]	auto[0]	auto[1]	163	1			T20	1		T33	1		T53	1
all_values[1]	auto[1]	auto[1]	auto[1]	127	1			T19	1		T20	4		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	170	1			T19	2		T20	5		T33	2
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T33	1		T114	2		T115	4
all_values[2]	auto[0]	auto[1]	auto[0]	125	1			T19	2		T20	3		T53	1
all_values[2]	auto[0]	auto[1]	auto[1]	63	1			T33	2		T53	1		T36	1
all_values[2]	auto[1]	auto[0]	auto[1]	158	1			T20	3		T33	1		T116	1
all_values[2]	auto[1]	auto[1]	auto[1]	148	1			T20	3		T33	1		T53	1
all_values[3]	auto[0]	auto[0]	auto[0]	169	1			T20	1		T33	2		T36	4
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T20	4		T33	3		T116	1
all_values[3]	auto[0]	auto[1]	auto[0]	111	1			T53	1		T39	4		T101	1
all_values[3]	auto[0]	auto[1]	auto[1]	55	1			T19	1		T53	1		T39	2
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T19	2		T20	6		T33	2
all_values[3]	auto[1]	auto[1]	auto[1]	131	1			T19	1		T20	3		T53	1
all_values[4]	auto[0]	auto[0]	auto[0]	164	1			T19	4		T20	2		T33	1
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T20	1		T33	2		T39	1
all_values[4]	auto[0]	auto[1]	auto[0]	117	1			T20	4		T116	2		T39	2
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T20	2		T53	1		T101	2
all_values[4]	auto[1]	auto[0]	auto[1]	165	1			T20	2		T33	1		T53	1
all_values[4]	auto[1]	auto[1]	auto[1]	141	1			T20	3		T33	3		T53	1
all_values[5]	auto[0]	auto[0]	auto[0]	151	1			T20	6		T36	2		T39	1
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T19	1		T20	2		T33	1
all_values[5]	auto[0]	auto[1]	auto[0]	121	1			T33	1		T116	2		T101	1
all_values[5]	auto[0]	auto[1]	auto[1]	73	1			T19	1		T39	4		T117	2
all_values[5]	auto[1]	auto[0]	auto[1]	173	1			T20	1		T33	2		T53	2
all_values[5]	auto[1]	auto[1]	auto[1]	147	1			T19	2		T20	5		T33	3
all_values[6]	auto[0]	auto[0]	auto[0]	156	1			T20	2		T36	4		T116	2
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T19	2		T20	1		T53	1
all_values[6]	auto[0]	auto[1]	auto[0]	134	1			T20	2		T33	1		T53	1
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T20	1		T33	2		T118	2
all_values[6]	auto[1]	auto[0]	auto[1]	162	1			T19	2		T20	3		T33	1
all_values[6]	auto[1]	auto[1]	auto[1]	139	1			T20	5		T33	3		T53	1
all_values[7]	auto[0]	auto[0]	auto[0]	167	1			T20	2		T33	3		T36	1
all_values[7]	auto[0]	auto[0]	auto[1]	68	1			T36	1		T116	1		T114	3
all_values[7]	auto[0]	auto[1]	auto[0]	136	1			T53	2		T36	1		T39	3
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T19	2		T20	1		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	153	1			T19	1		T20	4		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	136	1			T19	1		T20	7		T33	2
all_values[8]	auto[0]	auto[0]	auto[1]	253	1			T19	2		T20	4		T33	2
all_values[8]	auto[0]	auto[1]	auto[1]	186	1			T20	4		T33	3		T53	1
all_values[8]	auto[1]	auto[0]	auto[1]	170	1			T19	1		T20	4		T33	1
all_values[8]	auto[1]	auto[1]	auto[1]	125	1			T19	1		T20	2		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal