Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	89888	1			T1	2		T2	2		T3	60
all_values[1]	89888	1			T1	2		T2	2		T3	60
all_values[2]	89888	1			T1	2		T2	2		T3	60
all_values[3]	89888	1			T1	2		T2	2		T3	60
all_values[4]	89888	1			T1	2		T2	2		T3	60
all_values[5]	89888	1			T1	2		T2	2		T3	60
all_values[6]	89888	1			T1	2		T2	2		T3	60
all_values[7]	89888	1			T1	2		T2	2		T3	60
all_values[8]	89888	1			T1	2		T2	2		T3	60

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

403645

1

T1

18

T2

18

T3

374

auto[1]

405347

1

T3

166

T4

114

T8

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

734930

1

T1

13

T2

13

T3

456

auto[1]

74062

1

T1

5

T2

5

T3

84

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	24540	1			T11	12		T19	4		T257	7
all_values[0]	auto[0]	auto[1]	19041	1			T1	2		T2	2		T3	19
all_values[0]	auto[1]	auto[0]	28601	1			T11	2		T12	1		T16	2
all_values[0]	auto[1]	auto[1]	17706	1			T3	41		T15	2		T11	68
all_values[1]	auto[0]	auto[0]	44343	1			T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	1354	1			T3	2		T11	31		T18	2
all_values[1]	auto[1]	auto[0]	42987	1			T3	56		T4	15		T8	1
all_values[1]	auto[1]	auto[1]	1204	1			T4	4		T11	4		T12	1
all_values[2]	auto[0]	auto[0]	43371	1			T1	1		T2	1		T3	57
all_values[2]	auto[0]	auto[1]	2254	1			T1	1		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	42157	1			T3	1		T4	19		T8	1
all_values[2]	auto[1]	auto[1]	2106	1			T15	1		T11	5		T19	1
all_values[3]	auto[0]	auto[0]	43086	1			T1	2		T2	2		T3	57
all_values[3]	auto[0]	auto[1]	246	1			T4	2		T11	4		T12	1
all_values[3]	auto[1]	auto[0]	46286	1			T3	3		T8	1		T9	1
all_values[3]	auto[1]	auto[1]	270	1			T11	3		T27	2		T18	8
all_values[4]	auto[0]	auto[0]	45181	1			T1	2		T2	2		T3	57
all_values[4]	auto[0]	auto[1]	401	1			T4	11		T11	2		T18	12
all_values[4]	auto[1]	auto[0]	43972	1			T3	3		T15	2		T11	93
all_values[4]	auto[1]	auto[1]	334	1			T11	13		T18	4		T34	3
all_values[5]	auto[0]	auto[0]	44137	1			T1	2		T2	2		T3	58
all_values[5]	auto[0]	auto[1]	161	1			T11	1		T18	6		T25	1
all_values[5]	auto[1]	auto[0]	45423	1			T3	2		T4	19		T15	2
all_values[5]	auto[1]	auto[1]	167	1			T11	3		T18	7		T25	2
all_values[6]	auto[0]	auto[0]	44666	1			T1	2		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	155	1			T11	4		T18	2		T25	1
all_values[6]	auto[1]	auto[0]	44917	1			T3	56		T4	19		T8	1
all_values[6]	auto[1]	auto[1]	150	1			T11	2		T18	5		T25	2
all_values[7]	auto[0]	auto[0]	44713	1			T1	2		T2	2		T3	59
all_values[7]	auto[0]	auto[1]	321	1			T11	4		T20	2		T18	3
all_values[7]	auto[1]	auto[0]	44515	1			T3	1		T4	19		T8	1
all_values[7]	auto[1]	auto[1]	339	1			T11	10		T20	2		T18	4
all_values[8]	auto[0]	auto[0]	30627	1			T3	40		T16	1		T257	11
all_values[8]	auto[0]	auto[1]	15048	1			T1	2		T2	2		T3	17
all_values[8]	auto[1]	auto[0]	31408	1			T11	30		T12	1		T19	4
all_values[8]	auto[1]	auto[1]	12805	1			T3	3		T4	19		T15	2