Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1879	1			T3	1		T8	6		T13	1
auto[BaudRate115200]	1497	1			T1	1		T2	1		T7	1
auto[BaudRate230400]	1505	1			T3	3		T4	1		T7	1
auto[BaudRate128Kbps]	1533	1			T1	1		T3	1		T8	3
auto[BaudRate256Kbps]	1721	1			T3	1		T8	6		T9	6
auto[BaudRate1Mbps]	1490	1			T2	1		T3	1		T8	3
auto[BaudRate1p5Mbps]	1116	1			T8	3		T15	1		T12	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1191	1			T2	2		T74	2		T24	7
freqs[25]	1126	1			T3	7		T19	6		T21	2
freqs[48]	437	1			T12	6		T17	9		T111	14
freqs[50]	579	1			T29	2		T27	5		T98	8
freqs[100]	961	1			T14	2		T384	6		T41	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	201	1			T24	1		T46	1		T96	3
auto[BaudRate9600]	freqs[25]	198	1			T3	1		T19	1		T21	1
auto[BaudRate9600]	freqs[48]	124	1			T17	9		T111	1		T118	1
auto[BaudRate9600]	freqs[50]	89	1			T98	1		T269	1		T341	2
auto[BaudRate9600]	freqs[100]	154	1			T384	3		T293	3		T33	2
auto[BaudRate115200]	freqs[24]	171	1			T2	1		T24	1		T96	1
auto[BaudRate115200]	freqs[25]	185	1			T19	2		T25	5		T294	3
auto[BaudRate115200]	freqs[48]	45	1			T111	1		T116	1		T50	1
auto[BaudRate115200]	freqs[50]	68	1			T29	1		T27	1		T93	1
auto[BaudRate115200]	freqs[100]	135	1			T14	1		T41	1		T22	1
auto[BaudRate230400]	freqs[24]	160	1			T24	3		T46	3		T96	1
auto[BaudRate230400]	freqs[25]	180	1			T3	3		T44	1		T25	2
auto[BaudRate230400]	freqs[48]	57	1			T111	3		T116	3		T118	2
auto[BaudRate230400]	freqs[50]	90	1			T27	1		T98	2		T269	3
auto[BaudRate230400]	freqs[100]	139	1			T33	1		T100	3		T285	1
auto[BaudRate128Kbps]	freqs[24]	183	1			T24	2		T46	1		T96	1
auto[BaudRate128Kbps]	freqs[25]	152	1			T3	1		T21	1		T44	1
auto[BaudRate128Kbps]	freqs[48]	56	1			T111	1		T116	2		T118	1
auto[BaudRate128Kbps]	freqs[50]	67	1			T27	1		T98	3		T93	2
auto[BaudRate128Kbps]	freqs[100]	121	1			T14	1		T293	1		T33	2
auto[BaudRate256Kbps]	freqs[24]	203	1			T46	1		T96	1		T119	2
auto[BaudRate256Kbps]	freqs[25]	179	1			T3	1		T19	1		T44	2
auto[BaudRate256Kbps]	freqs[48]	46	1			T111	3		T131	3		T342	1
auto[BaudRate256Kbps]	freqs[50]	82	1			T29	1		T27	1		T93	3
auto[BaudRate256Kbps]	freqs[100]	134	1			T41	1		T33	1		T38	4
auto[BaudRate1Mbps]	freqs[24]	185	1			T2	1		T74	1		T46	1
auto[BaudRate1Mbps]	freqs[25]	160	1			T3	1		T19	1		T45	3
auto[BaudRate1Mbps]	freqs[48]	57	1			T12	4		T111	3		T50	1
auto[BaudRate1Mbps]	freqs[50]	94	1			T98	2		T269	1		T93	9
auto[BaudRate1Mbps]	freqs[100]	145	1			T384	3		T293	1		T33	2
auto[BaudRate1p5Mbps]	freqs[25]	72	1			T19	1		T25	2		T37	2
auto[BaudRate1p5Mbps]	freqs[48]	52	1			T12	2		T111	2		T50	3
auto[BaudRate1p5Mbps]	freqs[50]	89	1			T27	1		T269	2		T93	5
auto[BaudRate1p5Mbps]	freqs[100]	133	1			T293	1		T33	2		T100	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded