Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	26756954	1			T3	49		T4	11		T8	3
all_levels[1]	162766	1			T3	15		T12	1		T20	2
all_levels[2]	1955	1			T3	14		T48	2		T44	1
all_levels[3]	832	1			T3	9		T20	1		T44	1
all_levels[4]	559	1			T3	3		T12	3		T110	1
all_levels[5]	439	1			T3	3		T15	2		T96	5
all_levels[6]	395	1			T3	1		T27	1		T96	1
all_levels[7]	303	1			T3	1		T16	1		T96	2
all_levels[8]	235	1			T3	1		T111	2		T112	1
all_levels[9]	218	1			T46	2		T110	1		T95	1
all_levels[10]	197	1			T20	1		T46	1		T95	1
all_levels[11]	172	1			T12	1		T19	1		T20	1
all_levels[12]	123	1			T3	1		T48	1		T113	2
all_levels[13]	119	1			T48	3		T110	1		T114	1
all_levels[14]	116	1			T19	1		T45	1		T113	1
all_levels[15]	109	1			T19	1		T16	1		T115	1
all_levels[16]	98	1			T116	1		T97	1		T117	1
all_levels[17]	96	1			T20	1		T118	1		T93	1
all_levels[18]	87	1			T119	1		T97	1		T100	1
all_levels[19]	72	1			T110	1		T119	1		T120	1
all_levels[20]	71	1			T116	1		T121	1		T122	1
all_levels[21]	60	1			T20	1		T94	1		T123	1
all_levels[22]	60	1			T119	1		T124	1		T125	1
all_levels[23]	56	1			T110	1		T96	2		T119	1
all_levels[24]	59	1			T35	1		T100	1		T125	1
all_levels[25]	59	1			T95	1		T98	1		T50	1
all_levels[26]	70	1			T95	1		T126	1		T114	1
all_levels[27]	34	1			T126	1		T127	1		T117	1
all_levels[28]	38	1			T114	1		T121	1		T128	1
all_levels[29]	35	1			T128	1		T129	1		T130	1
all_levels[30]	39	1			T114	1		T131	1		T100	1
all_levels[31]	33	1			T118	1		T128	1		T123	1
all_levels[32]	25	1			T132	1		T133	1		T134	1
all_levels[33]	24	1			T124	1		T135	1		T122	1
all_levels[34]	22	1			T20	1		T114	1		T93	1
all_levels[35]	29	1			T95	1		T136	1		T133	1
all_levels[36]	22	1			T131	1		T124	1		T137	1
all_levels[37]	22	1			T93	1		T125	3		T138	1
all_levels[38]	24	1			T15	1		T12	2		T50	1
all_levels[39]	13	1			T133	1		T139	1		T140	1
all_levels[40]	22	1			T20	1		T132	1		T141	1
all_levels[41]	19	1			T142	1		T123	1		T143	1
all_levels[42]	23	1			T12	4		T144	1		T145	1
all_levels[43]	17	1			T146	1		T147	1		T148	1
all_levels[44]	13	1			T122	1		T149	1		T143	1
all_levels[45]	9	1			T150	1		T151	1		T152	1
all_levels[46]	12	1			T149	1		T153	1		T154	1
all_levels[47]	13	1			T133	1		T149	1		T146	1
all_levels[48]	11	1			T142	1		T155	1		T153	1
all_levels[49]	9	1			T36	1		T143	1		T156	1
all_levels[50]	10	1			T95	1		T157	2		T158	1
all_levels[51]	9	1			T39	1		T159	1		T147	1
all_levels[52]	3	1			T136	1		T160	1		T161	1
all_levels[53]	10	1			T137	1		T132	1		T162	2
all_levels[54]	13	1			T144	1		T143	1		T163	1
all_levels[55]	12	1			T155	1		T152	1		T164	2
all_levels[56]	8	1			T97	1		T165	1		T164	1
all_levels[57]	9	1			T115	1		T157	1		T166	2
all_levels[58]	4	1			T167	1		T150	1		T147	1
all_levels[59]	5	1			T168	1		T169	1		T170	3
all_levels[60]	9	1			T171	1		T147	1		T172	1
all_levels[61]	3	1			T147	1		T173	1		T174	1
all_levels[62]	4	1			T175	3		T176	1		-	-
all_levels[63]	9	1			T117	1		T165	1		T123	1
all_levels[64]	75	1			T27	1		T177	1		T35	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26923197

1

T3

97

T15

20

T11

655

auto[1]

3774

1

T4

11

T8

3

T9

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[27]]	[auto[1]]	0	1	1
[all_levels[34]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51] , all_levels[52] , all_levels[53]]	[auto[1]]	--	--	4
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	26753635	1			T3	49		T15	17		T11	655
all_levels[0]	auto[1]	3319	1			T4	11		T8	3		T9	1
all_levels[1]	auto[0]	162702	1			T3	15		T12	1		T20	2
all_levels[1]	auto[1]	64	1			T178	1		T179	2		T180	1
all_levels[2]	auto[0]	1919	1			T3	14		T48	2		T44	1
all_levels[2]	auto[1]	36	1			T136	1		T180	1		T181	1
all_levels[3]	auto[0]	804	1			T3	9		T20	1		T44	1
all_levels[3]	auto[1]	28	1			T113	3		T136	1		T182	1
all_levels[4]	auto[0]	537	1			T3	3		T12	2		T110	1
all_levels[4]	auto[1]	22	1			T12	1		T183	1		T184	1
all_levels[5]	auto[0]	423	1			T3	3		T15	2		T96	5
all_levels[5]	auto[1]	16	1			T125	3		T135	1		T185	1
all_levels[6]	auto[0]	379	1			T3	1		T27	1		T96	1
all_levels[6]	auto[1]	16	1			T98	1		T114	2		T186	1
all_levels[7]	auto[0]	290	1			T3	1		T16	1		T96	2
all_levels[7]	auto[1]	13	1			T113	2		T134	1		T174	1
all_levels[8]	auto[0]	221	1			T3	1		T111	2		T112	1
all_levels[8]	auto[1]	14	1			T187	1		T188	1		T189	2
all_levels[9]	auto[0]	201	1			T46	2		T110	1		T95	1
all_levels[9]	auto[1]	17	1			T125	1		T190	2		T152	1
all_levels[10]	auto[0]	184	1			T20	1		T46	1		T95	1
all_levels[10]	auto[1]	13	1			T191	2		T192	1		T193	1
all_levels[11]	auto[0]	162	1			T12	1		T19	1		T20	1
all_levels[11]	auto[1]	10	1			T179	1		T134	1		T194	1
all_levels[12]	auto[0]	114	1			T3	1		T48	1		T113	2
all_levels[12]	auto[1]	9	1			T195	1		T196	2		T197	1
all_levels[13]	auto[0]	114	1			T48	3		T110	1		T114	1
all_levels[13]	auto[1]	5	1			T198	1		T199	1		T200	3
all_levels[14]	auto[0]	107	1			T19	1		T45	1		T113	1
all_levels[14]	auto[1]	9	1			T201	2		T202	1		T203	1
all_levels[15]	auto[0]	91	1			T19	1		T16	1		T115	1
all_levels[15]	auto[1]	18	1			T113	1		T125	4		T204	2
all_levels[16]	auto[0]	86	1			T116	1		T97	1		T117	1
all_levels[16]	auto[1]	12	1			T205	3		T206	1		T198	1
all_levels[17]	auto[0]	89	1			T20	1		T118	1		T93	1
all_levels[17]	auto[1]	7	1			T178	1		T207	1		T208	1
all_levels[18]	auto[0]	79	1			T119	1		T97	1		T100	1
all_levels[18]	auto[1]	8	1			T209	1		T210	1		T211	1
all_levels[19]	auto[0]	63	1			T110	1		T119	1		T120	1
all_levels[19]	auto[1]	9	1			T125	1		T212	4		T213	2
all_levels[20]	auto[0]	60	1			T116	1		T121	1		T122	1
all_levels[20]	auto[1]	11	1			T214	2		T152	1		T192	2
all_levels[21]	auto[0]	51	1			T20	1		T94	1		T123	1
all_levels[21]	auto[1]	9	1			T215	1		T216	2		T217	1
all_levels[22]	auto[0]	47	1			T119	1		T124	1		T125	1
all_levels[22]	auto[1]	13	1			T218	2		T205	2		T195	1
all_levels[23]	auto[0]	50	1			T110	1		T96	2		T119	1
all_levels[23]	auto[1]	6	1			T166	1		T219	1		T220	2
all_levels[24]	auto[0]	57	1			T35	1		T100	1		T125	1
all_levels[24]	auto[1]	2	1			T221	1		T222	1		-	-
all_levels[25]	auto[0]	53	1			T95	1		T98	1		T50	1
all_levels[25]	auto[1]	6	1			T125	1		T223	1		T221	1
all_levels[26]	auto[0]	64	1			T95	1		T126	1		T114	1
all_levels[26]	auto[1]	6	1			T224	1		T225	1		T226	1
all_levels[27]	auto[0]	34	1			T126	1		T127	1		T117	1
all_levels[28]	auto[0]	34	1			T114	1		T121	1		T128	1
all_levels[28]	auto[1]	4	1			T227	2		T228	1		T229	1
all_levels[29]	auto[0]	29	1			T128	1		T129	1		T130	1
all_levels[29]	auto[1]	6	1			T230	1		T174	1		T197	1
all_levels[30]	auto[0]	37	1			T114	1		T131	1		T100	1
all_levels[30]	auto[1]	2	1			T231	1		T232	1		-	-
all_levels[31]	auto[0]	32	1			T118	1		T128	1		T123	1
all_levels[31]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[32]	auto[0]	23	1			T132	1		T133	1		T134	1
all_levels[32]	auto[1]	2	1			T229	2		-	-		-	-
all_levels[33]	auto[0]	23	1			T124	1		T135	1		T122	1
all_levels[33]	auto[1]	1	1			T174	1		-	-		-	-
all_levels[34]	auto[0]	22	1			T20	1		T114	1		T93	1
all_levels[35]	auto[0]	22	1			T95	1		T136	1		T133	1
all_levels[35]	auto[1]	7	1			T130	1		T201	1		T231	2
all_levels[36]	auto[0]	21	1			T131	1		T124	1		T137	1
all_levels[36]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[37]	auto[0]	18	1			T93	1		T125	1		T138	1
all_levels[37]	auto[1]	4	1			T125	2		T235	1		T236	1
all_levels[38]	auto[0]	20	1			T15	1		T12	1		T50	1
all_levels[38]	auto[1]	4	1			T12	1		T237	2		T176	1
all_levels[39]	auto[0]	13	1			T133	1		T139	1		T140	1
all_levels[40]	auto[0]	19	1			T20	1		T132	1		T141	1
all_levels[40]	auto[1]	3	1			T238	2		T239	1		-	-
all_levels[41]	auto[0]	18	1			T142	1		T123	1		T143	1
all_levels[41]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[42]	auto[0]	17	1			T12	1		T144	1		T145	1
all_levels[42]	auto[1]	6	1			T12	3		T241	1		T242	2
all_levels[43]	auto[0]	16	1			T146	1		T147	1		T148	1
all_levels[43]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[44]	auto[0]	12	1			T122	1		T149	1		T143	1
all_levels[44]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[45]	auto[0]	9	1			T150	1		T151	1		T152	1
all_levels[46]	auto[0]	9	1			T149	1		T153	1		T154	1
all_levels[46]	auto[1]	3	1			T245	2		T200	1		-	-
all_levels[47]	auto[0]	13	1			T133	1		T149	1		T146	1
all_levels[48]	auto[0]	9	1			T142	1		T155	1		T153	1
all_levels[48]	auto[1]	2	1			T246	2		-	-		-	-
all_levels[49]	auto[0]	8	1			T36	1		T143	1		T156	1
all_levels[49]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[50]	auto[0]	10	1			T95	1		T157	2		T158	1
all_levels[51]	auto[0]	9	1			T39	1		T159	1		T147	1
all_levels[52]	auto[0]	3	1			T136	1		T160	1		T161	1
all_levels[53]	auto[0]	10	1			T137	1		T132	1		T162	2
all_levels[54]	auto[0]	11	1			T144	1		T143	1		T163	1
all_levels[54]	auto[1]	2	1			T248	2		-	-		-	-
all_levels[55]	auto[0]	9	1			T155	1		T152	1		T164	1
all_levels[55]	auto[1]	3	1			T164	1		T249	1		T250	1
all_levels[56]	auto[0]	6	1			T97	1		T165	1		T164	1
all_levels[56]	auto[1]	2	1			T251	1		T252	1		-	-
all_levels[57]	auto[0]	7	1			T115	1		T157	1		T166	1
all_levels[57]	auto[1]	2	1			T166	1		T253	1		-	-
all_levels[58]	auto[0]	4	1			T167	1		T150	1		T147	1
all_levels[59]	auto[0]	3	1			T168	1		T169	1		T170	1
all_levels[59]	auto[1]	2	1			T170	2		-	-		-	-
all_levels[60]	auto[0]	6	1			T171	1		T147	1		T172	1
all_levels[60]	auto[1]	3	1			T156	2		T244	1		-	-
all_levels[61]	auto[0]	3	1			T147	1		T173	1		T174	1
all_levels[62]	auto[0]	2	1			T175	1		T176	1		-	-
all_levels[62]	auto[1]	2	1			T175	2		-	-		-	-
all_levels[63]	auto[0]	7	1			T117	1		T165	1		T123	1
all_levels[63]	auto[1]	2	1			T254	2		-	-		-	-
all_levels[64]	auto[0]	67	1			T27	1		T177	1		T35	1
all_levels[64]	auto[1]	8	1			T245	1		T255	1		T256	2