Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	89888	1			T1	2		T2	2		T3	60
all_pins[1]	89888	1			T1	2		T2	2		T3	60
all_pins[2]	89888	1			T1	2		T2	2		T3	60
all_pins[3]	89888	1			T1	2		T2	2		T3	60
all_pins[4]	89888	1			T1	2		T2	2		T3	60
all_pins[5]	89888	1			T1	2		T2	2		T3	60
all_pins[6]	89888	1			T1	2		T2	2		T3	60
all_pins[7]	89888	1			T1	2		T2	2		T3	60
all_pins[8]	89888	1			T1	2		T2	2		T3	60

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	773089	1			T1	18		T2	18		T3	496
values[0x1]	35903	1			T3	44		T4	25		T15	5
transitions[0x0=>0x1]	28584	1			T3	43		T4	24		T15	4
transitions[0x1=>0x0]	28388	1			T3	43		T4	25		T15	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	72134	1			T1	2		T2	2		T3	19
all_pins[0]	values[0x1]	17754	1			T3	41		T15	2		T11	68
all_pins[0]	transitions[0x0=>0x1]	17349	1			T3	41		T15	2		T11	65
all_pins[0]	transitions[0x1=>0x0]	796	1			T4	4		T11	1		T12	1
all_pins[1]	values[0x0]	88687	1			T1	2		T2	2		T3	60
all_pins[1]	values[0x1]	1201	1			T4	4		T11	4		T12	1
all_pins[1]	transitions[0x0=>0x1]	1115	1			T4	4		T11	2		T12	1
all_pins[1]	transitions[0x1=>0x0]	2047	1			T15	1		T11	3		T19	1
all_pins[2]	values[0x0]	87755	1			T1	2		T2	2		T3	60
all_pins[2]	values[0x1]	2133	1			T15	1		T11	5		T19	1
all_pins[2]	transitions[0x0=>0x1]	2067	1			T15	1		T11	5		T19	1
all_pins[2]	transitions[0x1=>0x0]	204	1			T11	3		T27	2		T18	6
all_pins[3]	values[0x0]	89618	1			T1	2		T2	2		T3	60
all_pins[3]	values[0x1]	270	1			T11	3		T27	2		T18	8
all_pins[3]	transitions[0x0=>0x1]	227	1			T11	3		T27	2		T18	5
all_pins[3]	transitions[0x1=>0x0]	291	1			T11	13		T18	1		T34	2
all_pins[4]	values[0x0]	89554	1			T1	2		T2	2		T3	60
all_pins[4]	values[0x1]	334	1			T11	13		T18	4		T34	3
all_pins[4]	transitions[0x0=>0x1]	262	1			T11	12		T18	2		T34	2
all_pins[4]	transitions[0x1=>0x0]	138	1			T4	2		T11	2		T18	5
all_pins[5]	values[0x0]	89678	1			T1	2		T2	2		T3	60
all_pins[5]	values[0x1]	210	1			T4	2		T11	3		T18	7
all_pins[5]	transitions[0x0=>0x1]	161	1			T4	2		T11	3		T18	3
all_pins[5]	transitions[0x1=>0x0]	763	1			T11	2		T12	1		T20	1
all_pins[6]	values[0x0]	89076	1			T1	2		T2	2		T3	60
all_pins[6]	values[0x1]	812	1			T11	2		T12	1		T20	1
all_pins[6]	transitions[0x0=>0x1]	759	1			T11	1		T12	1		T20	1
all_pins[6]	transitions[0x1=>0x0]	286	1			T11	9		T20	2		T18	2
all_pins[7]	values[0x0]	89549	1			T1	2		T2	2		T3	60
all_pins[7]	values[0x1]	339	1			T11	10		T20	2		T18	4
all_pins[7]	transitions[0x0=>0x1]	194	1			T11	4		T20	2		T18	4
all_pins[7]	transitions[0x1=>0x0]	12705	1			T3	3		T4	19		T15	2
all_pins[8]	values[0x0]	77038	1			T1	2		T2	2		T3	57
all_pins[8]	values[0x1]	12850	1			T3	3		T4	19		T15	2
all_pins[8]	transitions[0x0=>0x1]	6450	1			T3	2		T4	18		T15	1
all_pins[8]	transitions[0x1=>0x0]	11158	1			T3	40		T11	24		T16	9