Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6407503	1			T3	22		T4	9		T15	10
all_levels[1]	1782358	1			T3	73		T15	4		T11	316
all_levels[2]	429273	1			T3	2		T11	102		T16	5
all_levels[3]	280300	1			T15	2		T18	17		T43	17
all_levels[4]	245491	1			T18	15		T24	1		T44	10
all_levels[5]	206853	1			T16	2		T48	78		T18	16
all_levels[6]	217239	1			T19	1		T18	18		T44	5
all_levels[7]	238135	1			T381	3		T18	17		T44	2
all_levels[8]	329846	1			T12	3		T18	14		T44	5
all_levels[9]	406431	1			T16	1		T18	17		T44	7
all_levels[10]	251693	1			T16	4		T20	2		T18	16
all_levels[11]	576259	1			T12	2		T20	1		T48	1
all_levels[12]	157058	1			T16	1		T20	3		T48	33
all_levels[13]	254334	1			T18	19		T110	2		T96	4
all_levels[14]	160893	1			T12	6		T20	2		T18	17
all_levels[15]	160530	1			T11	28		T257	11		T18	16
all_levels[16]	273430	1			T15	5		T11	234		T19	2
all_levels[17]	535265	1			T16	1		T48	1		T27	1
all_levels[18]	247983	1			T18	25		T111	2		T25	106
all_levels[19]	281445	1			T19	3		T18	28		T111	1
all_levels[20]	153252	1			T16	2		T48	3		T18	31
all_levels[21]	514573	1			T20	5		T18	27		T111	1
all_levels[22]	167938	1			T16	5		T20	1		T48	2
all_levels[23]	391235	1			T19	4		T48	2		T18	34
all_levels[24]	149224	1			T18	31		T111	26		T25	363
all_levels[25]	417745	1			T48	44		T18	28		T111	9
all_levels[26]	553407	1			T18	32		T110	1		T25	448
all_levels[27]	130802	1			T18	26		T110	6		T25	490
all_levels[28]	123424	1			T18	28		T111	4		T25	392
all_levels[29]	203631	1			T27	2		T18	32		T110	1
all_levels[30]	132088	1			T16	1		T18	33		T25	434
all_levels[31]	577084	1			T27	1		T18	95		T115	4
all_levels[32]	9970089	1			T20	3		T27	14		T18	2478

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26923197

1

T3

97

T15

20

T11

655

auto[1]

3614

1

T4

9

T15

1

T11

36

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6405578	1			T3	22		T15	10		T11	3
all_levels[0]	auto[1]	1925	1			T4	9		T11	8		T12	2
all_levels[1]	auto[0]	1782142	1			T3	73		T15	4		T11	313
all_levels[1]	auto[1]	216	1			T11	3		T16	1		T18	2
all_levels[2]	auto[0]	429238	1			T3	2		T11	102		T16	3
all_levels[2]	auto[1]	35	1			T16	2		T207	2		T218	1
all_levels[3]	auto[0]	280247	1			T15	2		T18	17		T43	17
all_levels[3]	auto[1]	53	1			T260	18		T292	3		T134	2
all_levels[4]	auto[0]	245465	1			T18	15		T24	1		T44	10
all_levels[4]	auto[1]	26	1			T152	1		T191	2		T385	1
all_levels[5]	auto[0]	206827	1			T16	2		T48	77		T18	16
all_levels[5]	auto[1]	26	1			T48	1		T386	1		T387	1
all_levels[6]	auto[0]	217209	1			T19	1		T18	18		T44	5
all_levels[6]	auto[1]	30	1			T136	2		T388	1		T389	1
all_levels[7]	auto[0]	238013	1			T381	2		T18	17		T44	2
all_levels[7]	auto[1]	122	1			T381	1		T373	8		T292	8
all_levels[8]	auto[0]	329825	1			T12	2		T18	14		T44	5
all_levels[8]	auto[1]	21	1			T12	1		T46	1		T294	1
all_levels[9]	auto[0]	406408	1			T16	1		T18	17		T44	7
all_levels[9]	auto[1]	23	1			T125	1		T135	1		T350	1
all_levels[10]	auto[0]	251676	1			T16	2		T20	2		T18	16
all_levels[10]	auto[1]	17	1			T16	2		T336	1		T207	1
all_levels[11]	auto[0]	576240	1			T12	2		T20	1		T48	1
all_levels[11]	auto[1]	19	1			T346	1		T390	1		T389	2
all_levels[12]	auto[0]	157039	1			T16	1		T20	3		T48	33
all_levels[12]	auto[1]	19	1			T43	1		T272	1		T391	1
all_levels[13]	auto[0]	254314	1			T18	19		T110	2		T96	4
all_levels[13]	auto[1]	20	1			T93	1		T186	1		T180	1
all_levels[14]	auto[0]	160867	1			T12	3		T20	2		T18	17
all_levels[14]	auto[1]	26	1			T12	3		T186	1		T135	1
all_levels[15]	auto[0]	160362	1			T11	3		T257	2		T18	16
all_levels[15]	auto[1]	168	1			T11	25		T257	9		T111	1
all_levels[16]	auto[0]	273401	1			T15	4		T11	234		T19	2
all_levels[16]	auto[1]	29	1			T15	1		T125	1		T279	1
all_levels[17]	auto[0]	535238	1			T16	1		T48	1		T27	1
all_levels[17]	auto[1]	27	1			T306	1		T218	1		T182	1
all_levels[18]	auto[0]	247964	1			T18	25		T111	2		T25	106
all_levels[18]	auto[1]	19	1			T227	1		T392	1		T393	1
all_levels[19]	auto[0]	281423	1			T19	3		T18	28		T111	1
all_levels[19]	auto[1]	22	1			T269	1		T283	1		T179	1
all_levels[20]	auto[0]	153232	1			T16	1		T48	3		T18	31
all_levels[20]	auto[1]	20	1			T16	1		T227	2		T394	1
all_levels[21]	auto[0]	514554	1			T20	5		T18	27		T111	1
all_levels[21]	auto[1]	19	1			T128	1		T312	1		T395	1
all_levels[22]	auto[0]	167920	1			T16	4		T20	1		T48	2
all_levels[22]	auto[1]	18	1			T16	1		T106	1		T396	2
all_levels[23]	auto[0]	391219	1			T19	4		T48	2		T18	34
all_levels[23]	auto[1]	16	1			T397	1		T398	2		T399	1
all_levels[24]	auto[0]	149206	1			T18	31		T111	26		T25	363
all_levels[24]	auto[1]	18	1			T180	1		T400	1		T379	1
all_levels[25]	auto[0]	417732	1			T48	44		T18	28		T111	9
all_levels[25]	auto[1]	13	1			T401	1		T402	2		T188	1
all_levels[26]	auto[0]	553393	1			T18	32		T110	1		T25	448
all_levels[26]	auto[1]	14	1			T93	1		T268	1		T214	1
all_levels[27]	auto[0]	130780	1			T18	26		T110	4		T25	490
all_levels[27]	auto[1]	22	1			T110	2		T269	1		T186	1
all_levels[28]	auto[0]	123412	1			T18	28		T111	4		T25	392
all_levels[28]	auto[1]	12	1			T303	1		T186	1		T133	1
all_levels[29]	auto[0]	203611	1			T27	2		T18	32		T110	1
all_levels[29]	auto[1]	20	1			T369	1		T403	1		T404	1
all_levels[30]	auto[0]	132070	1			T16	1		T18	33		T25	434
all_levels[30]	auto[1]	18	1			T124	1		T178	1		T320	1
all_levels[31]	auto[0]	577067	1			T27	1		T18	95		T115	4
all_levels[31]	auto[1]	17	1			T127	1		T227	2		T405	1
all_levels[32]	auto[0]	9969525	1			T20	3		T27	14		T18	2478
all_levels[32]	auto[1]	564	1			T45	2		T110	2		T259	1